Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a first wafer which comprises a substrate, a stacking structure, a first stop layer, and a first protection layer; performing graphical processing on the first wafer to form an interconnection through hole; after the interconnection through holes are formed, the first protection layer is removed, so that the first stop layer is exposed; after the first protection layer is removed, forming a conductive layer in the interconnection through hole and on one side, deviating from the stacking structure, of the first stop layer; planarization processing is carried out on the conductive layer until the stacking structure is exposed, an interconnection structure is formed in the interconnection through hole, and the removal rate of planarization processing on the first stop layer is smaller than a preset value. According to the method, the polishing end point can be controlled, the surface uniformity of the planarized process window and the wafer is improved so as to improve the surface flatness of the mixed bonding interface, and the bonding strength and the product yield of mixed bonding are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As integrated circuits evolve towards higher performance, lower power consumption, and higher bandwidth, three-dimensional integrated circuits (3DIC) are gradually becoming an important technological approach. Among them, hybrid bonding (HB) can achieve ultra-high density and low power interconnection in three-dimensional integration, and has become an important candidate solution for advanced packaging.

[0003] However, when forming copper interconnect structures at hybrid bonding interfaces, the continuous increase in interconnect via density and aspect ratio introduces significant unevenness on the wafer surface. As these surface morphology differences accumulate and amplify, it becomes difficult for the upper and lower wafer surfaces to achieve sufficient contact during hybrid bonding, easily leading to local gaps at the interface, resulting in bubble residue and voids, which in turn reduces bonding strength and deteriorates product yield. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which aims to improve the surface flatness of the hybrid bonding interface and increase the bonding strength of the hybrid bonding.

[0005] To achieve the above objectives, according to a first aspect of this application, a method for forming a semiconductor structure is provided, comprising: A first wafer is provided, the first wafer including a substrate, a stacked structure on the substrate, a first stop layer on the stacked structure, and a first protective layer on the first stop layer; The first wafer is patterned to form interconnect vias that penetrate the first protective layer, the first stop layer, and the stacked structure. After forming the interconnect vias, the first protective layer is removed to expose the first stop layer; After removing the first protective layer, a conductive layer is formed in the interconnect vias and on the side of the first stop layer opposite to the stacked structure. The conductive layer is planarized until the stacked structure is exposed, and an interconnect structure is formed in the interconnect via. The planarization process removes the first stop layer at a rate less than a preset value.

[0006] Optionally, the planarization process removes the first stop layer at a rate greater than that of silicon oxide but less than that of copper.

[0007] Optionally, the material of the first stop layer includes titanium nitride, the material of the first protective layer includes silicon oxynitride, and the material of the conductive layer includes copper.

[0008] Optionally, the thickness of the first stop layer ranges from [400, 500] angstroms.

[0009] Optionally, the first wafer further includes an electrical interconnect layer disposed between the substrate and the stacked structure; After the interconnect vias are formed, the electrical interconnect layer is exposed from the interconnect vias.

[0010] Optionally, the stacked structure includes a barrier layer on the substrate, a second protective layer on the barrier layer, a first dielectric layer on the second protective layer, a second stop layer on the first dielectric layer, a second dielectric layer on the second stop layer, and a third dielectric layer on the second dielectric layer.

[0011] Optionally, the barrier layer is made of titanium nitride, the second protective layer is made of silicon oxynitride, the second stop layer is made of silicon nitride, the first dielectric layer and the second dielectric layer are both made of silicon oxide, and the third dielectric layer is made of nitrogen-doped carbon.

[0012] Optionally, before patterning the first wafer to form interconnect vias, the forming method further includes: The first wafer is pre-patterned to form pre-interconnect vias, which penetrate the first protective layer and the first stop layer and extend into a portion of the stacked structure. An anti-reflective layer is formed within the pre-interconnect via and on the side of the first protective layer opposite to the first stop layer.

[0013] Optionally, after forming the anti-reflective layer, the patterning process of the first wafer to form interconnect vias includes: A photoresist layer is formed on the anti-reflection layer, the photoresist layer has a patterned opening, the patterned opening has a first projected pattern projected onto the substrate surface, the pre-interconnect via has a second projected pattern projected onto the substrate surface, the second projected pattern being within the range of the first projected pattern; Using the photoresist layer as a mask, the anti-reflection layer, the first protective layer, the first stop layer, and the stacked structure are etched to form the interconnect vias. The interconnect vias include a first segment and a second segment that are connected. The diameter of the first segment is larger than the diameter of the second segment, and the first segment is farther away from the substrate than the second segment.

[0014] Optionally, after removing the first protective layer and before forming the conductive layer, the formation method further includes: A barrier diffusion layer is formed on the inner wall of the interconnecting via and on the side of the first stop layer opposite to the stacked structure; After the barrier diffusion layer is formed, the conductive layer is formed on the barrier diffusion layer.

[0015] Optionally, the material of the barrier diffusion layer includes tantalum nitride, and the thickness of the barrier diffusion layer is [25, 35] nanometers.

[0016] Optionally, it also includes: Provide a second wafer; After planarizing the conductive layer, the second wafer is bonded to the first wafer, and the surface of the stacked structure and the surface of the interconnect structure are in contact with the second wafer.

[0017] According to a second aspect of this application, a semiconductor structure is provided, formed by the method for forming a semiconductor structure described in any one of the preceding claims, the semiconductor structure comprising: A substrate, an electrical interconnect layer, and a stacked structure are arranged in sequence. An interconnect structure located in the stacked structure and in contact with the electrical interconnect layer, wherein the end face of the interconnect structure facing away from the electrical interconnect layer is exposed on the side of the stacked structure facing away from the electrical interconnect layer.

[0018] In this application, by sequentially setting a first stop layer and a first protective layer on the stacked structure, the first protective layer can effectively block direct erosion of the first stop layer by processes such as etching and plasma treatment during the formation of interconnect vias and subsequent removal of photoresist and anti-reflective layers, thereby maintaining the interface integrity of the first stop layer and providing a complete process interface for subsequent planarization. Furthermore, during the planarization process, making the removal rate of the first stop layer lower than a preset value ensures that the removal rate of the first stop layer is lower than or close to the removal rate of the conductive layer. When the conductive layer still has surface undulations that need to be removed, the first stop layer will not be prematurely polished through, thus effectively avoiding the situation where the interconnect structure has not reached the target flatness and the first stop layer has completely failed. With this configuration, the embodiments of this application can not only control the polishing endpoint, improve the planarization process window and wafer surface uniformity, but also significantly improve the surface flatness of the hybrid bonding interface, reduce interface residual gaps and defects such as bubbles and voids, and improve the bonding strength and product yield of the hybrid bonding.

[0019] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0022] Figure 1 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this application; Figures 2 to 8 A cross-sectional view of the semiconductor structure provided in the embodiments of this application during its formation process.

[0023] Explanation of reference numerals in the attached figures: 10. First wafer 110. Substrate; 120. Stacked structure; 121. Barrier layer; 122. Second protective layer; 123. First dielectric layer; 124. Second stop layer; 125. Second dielectric layer; 126. Third dielectric layer; 130. First Stop Layer; 140. First protective layer; 150. Pre-interconnect via; 151. Interconnect via; 1511. First hole segment; 1512. Second hole segment; 160. Conductive layer; 161. Interconnect structure; 162. Barrier diffusion layer; 170. Electrical interconnect layer; 180. Anti-reflective layer; 190. Photoresist layer; 191. Pattern opening. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0025] It should be understood that although the terms first, second, etc., may be used herein to describe various components, these components should not be limited to these terms. These terms are used to distinguish one component from another. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component, without departing from the scope of this application.

[0026] It should be understood that when a component is said to be "on" or "connected" to another component, it can be directly on or connected to the other component, or there may be an inserted component. Other terms used to describe relationships between components should be interpreted in a similar manner.

[0027] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a range smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive layers and contact layers, as well as one or more dielectric layers.

[0028] It should be noted that the illustrations provided in the embodiments of this application are only schematic representations of the basic concept of this application. Although the illustrations only show the components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0029] As described in the background section, in hybrid bonding processes, if the surfaces of the two wafers involved in bonding are not uniform, it is difficult to achieve sufficient contact across the entire interface during bonding. This can easily lead to gaps forming in localized areas, resulting in defects such as residual bubbles or voids at the interface. These defects weaken the mechanical strength and electrical connection reliability of the hybrid bonding interface, thereby causing a decrease in the overall bonding strength of the product and a deterioration in manufacturing yield.

[0030] Specifically, in some embodiments, taking one of the wafers involved in bonding as an example, this wafer needs to form an interconnect structure at the interface before hybrid bonding. The interconnect structure is used to realize electrical connection and signal and power transmission between the upper and lower wafers. As the density of interconnect vias and the aspect ratio of vias increase, a large difference in height and unevenness will gradually accumulate on the wafer surface during processes such as via etching, metal filling, and chemical mechanical polishing. The continuous amplification of surface morphology differences will lead to a significant decrease in wafer flatness, making it difficult to achieve sufficient and tight contact between the upper and lower wafer surfaces during hybrid bonding, easily generating local gaps, inducing interface bubbles and void defects, thereby reducing bonding strength and product yield.

[0031] Therefore, in order to improve the surface flatness of the hybrid bonding interface and increase the bonding strength of the hybrid bonding, this application discloses a method for forming a semiconductor structure.

[0032] Reference Figure 1 , Figure 1 A schematic flowchart of a method for forming a semiconductor structure provided in this application embodiment includes: Step S100: A first wafer is provided, the first wafer including a stacked structure on the substrate, a first stop layer on the stacked structure, and a first protective layer on the first stop layer; Step S200: The first wafer is patterned to form interconnect vias, which penetrate the first protective layer, the first stop layer and the stacked structure. Step S300: After forming the interconnect via, remove the first protective layer to expose the first stop layer; Step S400: After removing the first protective layer, a conductive layer is formed in the interconnect via and on the side of the first stop layer opposite to the stacked structure. Step S500: The conductive layer is planarized until the stacked structure is exposed, and an interconnect structure is formed in the interconnect via. The removal rate of the first stop layer by the planarization process is less than a preset value.

[0033] In this embodiment, by sequentially providing a first stop layer 130 and a first protective layer 140 on the stacked structure 120, during the formation of the interconnect via 151 and subsequent processes such as removing photoresist and anti-reflective layer 180, the first protective layer 140 can effectively block direct erosion of the first stop layer 130 by etching or plasma treatment, thereby maintaining the interface integrity of the first stop layer 130 and providing a complete process interface for subsequent planarization. Furthermore, during the planarization process, by reducing the removal rate of the first stop layer 130 to a preset value, the removal rate of the first stop layer 130 can be lower than or close to the removal rate of the conductive layer 160. When the conductive layer 160 still has surface undulations that need to be removed, the first stop layer 130 will not be prematurely polished through, thereby effectively preventing the first stop layer 130 from completely failing before the interconnect structure 161 reaches the target flatness. With this configuration, the embodiments of this application can not only control the polishing endpoint, improve the planarization process window and wafer surface uniformity, but also significantly improve the surface flatness of the hybrid bonding interface, reduce interface residual gaps and defects such as bubbles and voids, and improve the bonding strength and product yield of the hybrid bonding.

[0034] refer to Figures 2 to 8 , Figures 2 to 8This is a cross-sectional view of the semiconductor structure provided in the embodiment of this application during its formation process. The following will be combined with… Figure 1 and Figures 2 to 8 The formation process of the semiconductor structure provided in the embodiments of this application is described in detail.

[0035] Please refer to Figure 2 In this embodiment, the first wafer 10 provided in step S100 is any wafer that participates in bonding in the hybrid bonding process. The first wafer 10 includes a substrate 110, a stacked structure 120 on the substrate 110, a first stop layer 130 on the stacked structure 120, and a first protective layer 140 on the first stop layer 130.

[0036] In some embodiments, the substrate 110 includes, but is not limited to: single-crystal silicon (Si), silicon-on-insulator (SOI), and silicon-on-oxide (SiO2). x (Si) and other semiconductor materials suitable for integrated circuit manufacturing. The substrate 110 is used to support the stacked structure 120 and interconnect structure 161 located on the substrate 110, and is the basic support carrier.

[0037] In some embodiments, the first wafer 10 further includes an electrical interconnect layer 170 located between the substrate 110 and the stacked structure 120. The electrical interconnect layer 170 is used to realize electrical connections between devices within the first wafer 10, and, after hybrid bonding, to realize signal transmission, power distribution, and grounding paths with another wafer. The electrical interconnect layer 170 may include one or more metal interconnect layers. In some embodiments, the material of the electrical interconnect layer 170 includes aluminum or an aluminum alloy; in some other embodiments, the material of the electrical interconnect layer 170 includes other conductive materials such as copper or tungsten.

[0038] In some embodiments, the stacked structure 120 includes a barrier layer 121 on the substrate 110, a second protective layer 122 on the barrier layer 121, a first dielectric layer 123 on the second protective layer 122, a second stop layer 124 on the first dielectric layer 123, a second dielectric layer 125 on the second stop layer 124, and a third dielectric layer 126 on the second dielectric layer 125.

[0039] Reference Figure 2In one specific embodiment, the electrical interconnect layer 170 is located between the barrier layer 121 and the substrate 110. In some embodiments, the barrier layer 121 is titanium nitride (TiN). The barrier layer 121 covers the electrical interconnect layer 170 and can prevent the metal material in the electrical interconnect layer 170 from diffusing into the surrounding dielectric layer or device region due to damage during subsequent semiconductor structure fabrication processes, thereby improving the reliability of the semiconductor structure. If the barrier layer 121 is not provided, the metal material (e.g., copper, aluminum, etc.) is prone to diffuse along interface defects or dielectric micropores during high temperature or etching processes, leading to dielectric layer insulation failure, increased electromigration, and even short circuits or device performance degradation. Titanium nitride has a dense structure and high chemical stability. It has fewer lattice defects and limited diffusion channels, and has good barrier ability against metal atoms, making it suitable as a diffusion barrier layer 121 between the electrical interconnect layer 170 and the surrounding dielectric to ensure the structural stability and electrical performance reliability of the semiconductor structure.

[0040] In some embodiments, the material of the second protective layer 122 includes silicon oxynitride. By disposing of the silicon oxynitride layer on top of the barrier layer 121, the lower barrier layer 121 can be effectively protected during the etching and subsequent plasma processing steps of the upper structure to form interconnect vias 151 in stages, preventing the barrier layer 121 from being eroded.

[0041] In some embodiments, the second stop layer 124 is made of silicon nitride, which serves as an etching stop layer during the etching process of the pre-interconnect via 150 before the subsequent formation of interconnect via 151, preventing the underlying structure from being over-etched. Because silicon nitride and the second protective layer 122 (silicon oxynitride) differ in mechanical stress and process characteristics, if they are directly stacked, interface stress concentration is likely to occur during subsequent heat treatment or chemical mechanical polishing, leading to interface cracking or peeling. Therefore, a first dielectric layer 123 is provided between the second stop layer 124 and the second protective layer 122. The first dielectric layer 123 is made of silicon oxide and serves as a stress buffer and dielectric isolation layer.

[0042] In some embodiments, the material of the third dielectric layer 126 includes nitrogen-doped carbon (NDC). ） NDC has a low dielectric constant and sufficient interfacial adhesion properties. As an interface layer for hybrid bonding, it can reduce interconnect parasitic capacitance and improve signal transmission performance. At the same time, its material structure can alleviate interfacial stress and reduce the generation of bubbles and voids during hybrid bonding, thereby improving the reliability of the bonding interface and the product yield.

[0043] In some embodiments, a second dielectric layer 125 is disposed between the third dielectric layer 126 and the second stop layer 124, the material of the second dielectric layer 125 including silicon oxide. Since NDC material has a porous structure and relatively low mechanical strength, while silicon nitride material has high built-in stress and high hardness, if the two are in direct contact, stress concentration is likely to occur at the interface during subsequent heat treatment or chemical mechanical polishing processes, leading to cracking, delamination, or void defects in the dielectric layer. Therefore, by introducing a silicon oxide layer between the two, it can serve as a stress buffer and structural transition layer, improving the interface stress distribution and reducing the risk of structural damage. Furthermore, due to the hygroscopic and porous structure of NDC material, direct contact with silicon nitride may cause moisture or impurities to diffuse along the interface. Silicon oxide, being a dense dielectric layer, can effectively block the penetration of moisture and impurities, improving the electrical stability and reliability of the dielectric layer. It should also be noted that in some embodiments, the electrical interconnect layers 170 are spaced apart on the substrate 110. The electrical interconnect layers 170 are present in some areas between the stacked structure 120 and the substrate 110, while they are absent in others. This can easily lead to localized height differences in the second stop layer 124, which faces away from the surface of the substrate 110. By providing a second dielectric layer 125 between the second stop layer 124 and the third dielectric layer 126, the excellent deposition and filling capabilities and morphology coverage of silicon oxide can be utilized to fill the height difference between the areas containing the electrical interconnect layers 170 and those without, thereby further improving the wafer surface flatness and providing a more stable and flat foundation for subsequent hybrid bonding interfaces.

[0044] Reference Figure 6 In step S200, the first wafer 10 is patterned to form interconnect vias 151, which penetrate the first protective layer 140, the first stop layer 130, and the stacked structure 120. After the interconnect vias 151 are formed, the electrical interconnect layer 170 is exposed from the interconnect vias 151.

[0045] Specifically, in some embodiments, before patterning the first wafer 10 to form the interconnect via 151, the forming method further includes: Reference Figure 2 The first wafer 10 is pre-patterned to form pre-interconnect vias 150. These pre-interconnect vias 150 penetrate the first protective layer 140 and the first stop layer 130, and extend into a portion of the stacked structure 120. The pre-interconnect vias 150 effectively reduce the aspect ratio of the interconnect vias 151 during subsequent etching, improve the etching morphology, and enhance the etching directionality and perpendicularity of the vias. This avoids problems such as hole wall diffusion, sidewall damage, and etching residue during deep etching, thus helping to ensure the dimensional accuracy and morphological quality of the subsequent interconnect vias 151.

[0046] The formation method also includes: referring to Figure 3 An anti-reflection layer 180 is formed within the pre-interconnect via 150 and on the side of the first protective layer 140 opposite to the first stop layer 130. The anti-reflection layer 180 can suppress interference caused by light reflection in subsequent patterning steps, improving the optical contrast and pattern transfer accuracy of the exposed pattern. Simultaneously, it can shield against bottom reflection effects caused by light reflection from the sidewalls of the pre-interconnect via 150, thereby improving the consistency of the interconnect via 151. Furthermore, the anti-reflection layer 180, filling the pre-interconnect via 150, prevents etching gas from directly entering the lower layer region during subsequent patterning, preventing the interconnect via 151 from prematurely completing before reaching the set etching depth, ensuring the quality of the etching morphology and the controllability of the etching depth. In summary, forming the pre-interconnect via 150 and the anti-reflection layer 180 before patterning improves the deep-hole etching process window, ensures the dimensional accuracy, perpendicularity, and interface quality of the interconnect via 151, and provides a reliable structural foundation for subsequent metal filling and hybrid bonding interconnects. In some embodiments, the material of the antireflective layer 180 includes spin-on carbon or a bottom antireflective coating material.

[0047] In some embodiments, after forming the antireflective layer 180, the specific steps for patterning the first wafer 10 to form the interconnect vias 151 are as follows: Reference Figure 4 A photoresist layer 190 is formed on the anti-reflection layer 180. The photoresist layer 190 has a patterned opening 191. The patterned opening 191 has a first projection pattern projected onto the surface of the substrate 110. The pre-interconnect via 150 has a second projection pattern projected onto the surface of the substrate 110. The second projection pattern is within the range of the first projection pattern. Using the photoresist layer 190 as a mask, the anti-reflective layer 180, the first protective layer 140, the first stop layer 130, and the stacked structure 120 are etched to form interconnect vias 151. The interconnect vias 151 include a first via segment 1511 and a second via segment 1512 that are connected. The diameter of the first via segment 1511 is larger than the diameter of the second via segment 1512. The first via segment 1511 is farther away from the substrate 110 than the second via segment 1512.

[0048] By first forming pre-interconnect vias 150 and then using a larger-sized patterned opening 191 for deep etching, the effective aspect ratio of the interconnect vias 151 during etching is smaller, which helps improve the directionality and uniformity of the etching. This method of forming the interconnect vias 151 avoids problems such as morphological shrinkage, sidewall chamfering, over-etching, or etching residue caused by high aspect ratios during deep etching, effectively improving the perpendicularity and dimensional consistency of the interconnect vias 151. Simultaneously, this patterning method makes the structural transition of the interconnect vias 151, which is larger at the top and smaller at the bottom, more natural, facilitating subsequent metal filling and coverage, and reducing the risk of metal voids, bubbles, and filling failure.

[0049] In some embodiments, such as Figure 5 As shown, after forming the interconnect vias 151, the first wafer 10 undergoes processes to remove the photoresist layer 190 and the anti-reflective layer 180, thereby exposing the first protective layer 140. The removal of the anti-reflective layer 180 and the photoresist layer 190 can be achieved through processes such as dry etching or wet etching. During these removal processes, the first protective layer 140 acts as a protective layer, effectively preventing direct damage to the first stop layer 130 caused by etching or plasma treatment, thus ensuring the integrity of the interface of the first stop layer 130 and providing a stable interface foundation for subsequent planarization and further process steps. It should be noted that in some embodiments, the material of the first protective layer 140 includes silicon oxynitride.

[0050] Continue to refer to Figure 6 In step S300, after forming the interconnect via 151 and before forming the conductive layer 160, the first protective layer 140 is removed, exposing the first stop layer 130.

[0051] Reference Figure 7 In step S400, after removing the first protective layer 140, a conductive layer 160 is formed within the interconnect via 151 and on the side of the first stop layer 130 facing away from the stacked structure 120. In some embodiments, the conductive layer 160 is made of copper, and the conductive material filling the interconnect via 151 covers the exposed electrical interconnect layer 170 within the interconnect via 151 to achieve continuity of the metal structure within the interconnect via 151. In some embodiments, the conductive layer 160 is made of copper, which can provide a low-resistance interconnect path and improve signal transmission performance.

[0052] In some embodiments, to further enhance the diffusion barrier capability and interface reliability of the interconnect structure 161, after removing the first protective layer 140 and before forming the conductive layer 160, a diffusion barrier layer 162 is formed on the inner wall of the interconnect via 151 and on the side of the first stop layer 130 facing away from the stacked structure 120. The diffusion barrier layer 162 can suppress the diffusion of metals such as copper into the surrounding dielectric and interlayer structure during electroplating and subsequent heat treatment, thereby avoiding problems such as dielectric insulation failure and accelerated electromigration, and improving the long-term reliability of the interconnect structure 161. In some embodiments, the material of the diffusion barrier layer 162 includes tantalum nitride (TaN), and its thickness can be 25 nm to 35 nm. Those skilled in the art will understand that the diffusion barrier layer 162 can also be made of other materials with metal diffusion barrier capabilities, such as tantalum and titanium nitride.

[0053] Reference Figure 8 In step S500, the conductive layer 160 is planarized until the stacked structure 120 is exposed, and the interconnect structure 161 is formed in the interconnect via 151. The removal rate of the first stop layer 130 by the planarization process is less than a preset value.

[0054] Specifically, the planarization process may include a chemical mechanical polishing (CMP) process. During the planarization process, it is preferable that the removal rate of the polishing slurry on the first stop layer 130 is greater than the removal rate on silicon oxide (SiO2) and less than the removal rate on copper. In one specific embodiment, the preset value can be 100 angstroms per second, meaning that in the CMP process, the removal rate of the first stop layer 130 does not exceed 100 angstroms per second, so that the first stop layer 130 is not prematurely polished through before the conductive layer 160 and the surrounding dielectric layer achieve the target planarity.

[0055] In some embodiments, the first stop layer 130 is made of titanium nitride (TiN), and the conductive layer 160 is made of copper. For a polishing slurry adapted for copper polishing, the difference in removal rates between copper and titanium nitride is smaller than the difference in removal rates between copper and silicon oxide. For example, in some embodiments, the removal rate of copper is approximately 100 angstroms per second, the removal rate of titanium nitride is approximately 60 angstroms per second, the removal rate of silicon oxide is approximately 20 angstroms per second, and the removal rate of nitrogen-doped carbon is 10 angstroms per second. Compared to using silicon oxide as the stop layer, using titanium nitride as the first stop layer 130 provides a wider process control window for the planarization process, making the planarization process easier to control precisely, reducing surface height fluctuations caused by differences in polishing amounts in different areas, and improving the flatness of the bonding interface and the uniformity of the entire wafer.

[0056] In some embodiments, the thickness of the first stop layer 130 ranges from 400 angstroms to 500 angstroms. This thickness range provides sufficient safety margin when chemical mechanical polishing approaches the stop stage, maintaining the blocking effect of the first stop layer 130 even if there is slight local over-polishing; on the other hand, it does not significantly increase the effective depth of the interconnect via 151 due to excessive thickness of the first stop layer 130, thus avoiding adverse effects on the formation of the interconnect via 151 and the conductive layer 160.

[0057] In some embodiments, the method for forming a semiconductor structure further includes: Provide a second wafer; After planarizing the conductive layer 160, the second wafer is bonded to the first wafer 10, and the surfaces of the stacked structure 120 and the interconnect structure 161 are in contact with the second wafer.

[0058] Specifically, the second wafer can be another wafer with interconnect structure 161, or it can be a wafer carrying device structure. Its structure and fabrication method can be determined according to actual application requirements and are not particularly limited.

[0059] This application also discloses a semiconductor structure, as shown in the embodiments. Figure 8 The semiconductor structure is formed by any of the above semiconductor structure forming methods. The semiconductor structure includes: a substrate, an electrical interconnect layer 170, and a stacked structure 120 stacked sequentially; an interconnect structure 161 located in the stacked structure 120 and in contact with the electrical interconnect layer 170, and the end face of the interconnect structure 161 facing away from the electrical interconnect layer 170 is exposed on the side of the stacked structure 120 facing away from the electrical interconnect layer 170.

[0060] It should be noted that the morphological features and formation processes of the substrate, electrical interconnect layer 170, stacked structure 120 and interconnect structure 161 can be referred to the description in the aforementioned semiconductor structure formation method embodiments, and will not be repeated here.

[0061] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0062] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0063] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0064] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A first wafer is provided, the first wafer including a substrate, a stacked structure on the substrate, a first stop layer on the stacked structure, and a first protective layer on the first stop layer; The first wafer is patterned to form interconnect vias that penetrate the first protective layer, the first stop layer, and the stacked structure. After forming the interconnect vias, the first protective layer is removed to expose the first stop layer; After removing the first protective layer, a conductive layer is formed in the interconnect vias and on the side of the first stop layer opposite to the stacked structure. The conductive layer is planarized until the stacked structure is exposed, and an interconnect structure is formed in the interconnect via. The planarization process removes the first stop layer at a rate less than a preset value.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, The planarization process removes the first stop layer at a rate greater than that of silicon oxide but less than that of copper.

3. The method for forming a semiconductor structure according to claim 1, characterized in that, The material of the first stop layer includes titanium nitride, the material of the first protective layer includes silicon oxynitride, and the material of the conductive layer includes copper.

4. The method for forming a semiconductor structure according to claim 1, characterized in that, The thickness of the first stop layer ranges from [400, 500] angstroms.

5. The method for forming a semiconductor structure according to claim 1, characterized in that, The first wafer further includes an electrical interconnect layer disposed between the substrate and the stacked structure; After the interconnect vias are formed, the electrical interconnect layer is exposed from the interconnect vias.

6. The method for forming a semiconductor structure according to claim 1, characterized in that, The stacked structure includes a barrier layer on the substrate, a second protective layer on the barrier layer, a first dielectric layer on the second protective layer, a second stop layer on the first dielectric layer, a second dielectric layer on the second stop layer, and a third dielectric layer on the second dielectric layer.

7. The method for forming a semiconductor structure according to claim 6, characterized in that, The barrier layer is made of titanium nitride, the second protective layer is made of silicon oxynitride, the second stop layer is made of silicon nitride, the first dielectric layer and the second dielectric layer are both made of silicon oxide, and the third dielectric layer is made of nitrogen-doped carbon.

8. The method for forming a semiconductor structure according to claim 1, characterized in that, Before patterning the first wafer to form interconnect vias, the forming method further includes: The first wafer is pre-patterned to form pre-interconnect vias, which penetrate the first protective layer and the first stop layer and extend into a portion of the stacked structure. An anti-reflective layer is formed within the pre-interconnect via and on the side of the first protective layer opposite to the first stop layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, After forming the anti-reflective layer, the patterning process of the first wafer to form interconnect vias includes: A photoresist layer is formed on the anti-reflection layer, the photoresist layer has a patterned opening, the patterned opening has a first projected pattern projected onto the substrate surface, the pre-interconnect via has a second projected pattern projected onto the substrate surface, the second projected pattern being within the range of the first projected pattern; Using the photoresist layer as a mask, the anti-reflection layer, the first protective layer, the first stop layer, and the stacked structure are etched to form the interconnect vias. The interconnect vias include a first segment and a second segment that are connected. The diameter of the first segment is larger than the diameter of the second segment, and the first segment is farther away from the substrate than the second segment.

10. The method for forming a semiconductor structure according to claim 1, characterized in that, After removing the first protective layer and before forming the conductive layer, the forming method further includes: A barrier diffusion layer is formed on the inner wall of the interconnecting via and on the side of the first stop layer opposite to the stacked structure; After the barrier diffusion layer is formed, the conductive layer is formed on the barrier diffusion layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The material of the barrier diffusion layer includes tantalum nitride, and the thickness of the barrier diffusion layer is [25, 35] nanometers.

12. The method for forming a semiconductor structure according to claim 1, characterized in that, Also includes: Provide a second wafer; After planarizing the conductive layer, the second wafer is bonded to the first wafer, and the surface of the stacked structure and the surface of the interconnect structure are in contact with the second wafer.

13. A semiconductor structure, characterized in that, The semiconductor structure is formed by the method of forming the semiconductor structure according to any one of claims 1 to 12, wherein the semiconductor structure comprises: A substrate, an electrical interconnect layer, and a stacked structure are arranged in sequence. An interconnect structure located in the stacked structure and in contact with the electrical interconnect layer, wherein the end face of the interconnect structure facing away from the electrical interconnect layer is exposed on the side of the stacked structure facing away from the electrical interconnect layer.

Images