Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; an annular barrier layer structure on or in the substrate; the first doped region is located in the substrate on one side of the interior of the annular barrier layer structure, the annular barrier layer structure surrounds the first doped region, and the first doped region is provided with first type doped ions; the second doped region is located in the substrate on one side outside the annular barrier layer structure, the second doped region surrounds the annular barrier layer structure, the second doped region is provided with second type doped ions, and the first type doped ions and the second type doped ions are different in conductive type. In the embodiment, the annular barrier layer structure and the second doped region sequentially surround the periphery of the first doped region, so that the area utilization rate of the semiconductor structure is improved, and the production cost is reduced; meanwhile, the semiconductor structure can be placed in a small space region, so that the area utilization rate of the semiconductor structure can be further improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] Integrated circuits are susceptible to damage from electrostatic discharge (ESD). Protection circuits are typically designed at the input / output terminals or in power supply protection devices to prevent damage to internal circuitry caused by ESD. In current integrated circuit designs, diodes are commonly used as ESD protection devices to reduce ESD damage.

[0003] However, with the rapid growth of the integrated circuit (IC) industry, ESD protection technology continues to advance towards smaller process nodes under the drive of Moore's Law, making integrated circuits develop towards smaller size, higher circuit precision, and higher circuit complexity.

[0004] Therefore, the performance of existing electrostatic protection structures needs to be improved. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the area utilization rate of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; an annular barrier layer structure located on or within the substrate; a first doped region located in the substrate on an inner side of the annular barrier layer structure, the annular barrier layer structure surrounding the first doped region, and the first doped region having a first type of doped ion; and a second doped region located in the substrate on an outer side of the annular barrier layer structure, the second doped region surrounding the annular barrier layer structure, the second doped region having a second type of doped ion, and the first type of doped ion and the second type of doped ion having different conductivity types.

[0007] Accordingly, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate; forming an annular barrier layer structure on or in the substrate; and forming a first doped region and a second doped region spaced apart in the substrate, the second doped region surrounding the first doped region, the barrier layer structure being located between the first doped region and the second doped region and surrounding the first doped region; wherein the first doped region has a first type of dopant ion, the second doped region has a second type of dopant ion, and the first type of dopant ion and the second type of dopant ion have different conductivity types.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure, comprising: a substrate; a ring-shaped barrier layer structure located on or within the substrate; a first doped region located in the substrate on the inner side of the ring-shaped barrier layer structure, the ring-shaped barrier layer structure surrounding the first doped region, and the first doped region having a first type of doped ion; and a second doped region located in the substrate on the outer side of the ring-shaped barrier layer structure, the second doped region surrounding the ring-shaped barrier layer structure, the second doped region having a second type of doped ion, and the first type of doped ion and the second type of doped ion having different conductivity types. In this embodiment, since the ring-shaped barrier layer structure and the second doped region sequentially surround the first doped region, it is beneficial to improve the area utilization rate of the semiconductor structure and reduce production costs; at the same time, the semiconductor structure can be placed in a smaller space area, thereby further improving the area utilization rate of the semiconductor structure.

[0010] In an alternative embodiment, the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all polygonal along a direction perpendicular to the normal to the substrate surface. Compared with the interdigitated structure, this improves the problems of parasitic capacitance and corner effects, thereby enhancing the robustness of the semiconductor structure.

[0011] In an alternative embodiment, the outlines of the annular barrier layer structure, the first doped region, and the second doped region, along a direction perpendicular to the normal to the substrate surface, all include rectangles or regular polygons. Because rectangles and regular polygons have regular geometric shapes, the semiconductor structure is easier to arrange and align on the chip, thereby improving the area utilization of the semiconductor structure.

[0012] This invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming an annular barrier layer structure on or in the substrate; and forming a first doped region and a second doped region spaced apart in the substrate, the second doped region surrounding the first doped region, and the barrier layer structure located between and surrounding the first doped region; wherein the first doped region has a first type of dopant ion, the second doped region has a second type of dopant ion, and the first type of dopant ion and the second type of dopant ion have different conductivity types. In this embodiment, since the annular barrier layer structure and the second doped region sequentially surround the first doped region, it is beneficial to improve the area utilization rate of the semiconductor structure and reduce production costs; at the same time, the semiconductor structure can be placed in a smaller space area, thereby further improving the area utilization rate of the semiconductor structure. Attached Figure Description

[0013] Figure 1 This is a top view schematic diagram of the first embodiment of the semiconductor structure of the present invention;

[0014] Figure 2 yes Figure 1 Cross-sectional view along the AA1 direction;

[0015] Figure 3(a) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all circular.

[0016] Figure 3(b) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all hexagonal;

[0017] Figure 3(c) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all octagonal.

[0018] Figure 3(d) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all decagonal.

[0019] Figure 4 This is a top view of the second embodiment of the semiconductor structure of the present invention;

[0020] Figure 5 yes Figure 4 Cross-sectional view along the BB1 ​​direction;

[0021] Figure 6 This is a top view of the third embodiment of the semiconductor structure of the present invention;

[0022] Figure 7 yes Figure 6 Cross-sectional view along the CC1 direction;

[0023] Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention;

[0024] Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention;

[0025] Figures 17 to 18 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0026] Currently, the area utilization rate of semiconductor structures still needs to be improved.

[0027] Specifically, in the prior art, the electrostatic protection structure formed on silicon-on-insulator (SOI) substrates is mainly a multi-finger structure, which occupies a large area.

[0028] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate; an annular barrier layer structure located on or within the substrate; a first doped region located in the substrate on an inner side of the annular barrier layer structure, the annular barrier layer structure surrounding the first doped region, and the first doped region having a first type of doped ion; and a second doped region located in the substrate on an outer side of the annular barrier layer structure, the second doped region surrounding the annular barrier layer structure, the second doped region having a second type of doped ion, and the first type of doped ion and the second type of doped ion having different conductivity types.

[0029] In the embodiments of the present invention, since the annular barrier layer structure and the second doped region are sequentially surrounded by the first doped region, it is beneficial to improve the area utilization rate of the semiconductor structure and reduce the production cost; at the same time, the semiconductor structure can be placed in a smaller space area, which is beneficial to further improve the area utilization rate of the semiconductor structure.

[0030] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a top view schematic diagram of the first embodiment of the semiconductor structure of the present invention. Figure 2 yes Figure 1 Cross-sectional views along the AA1 direction: Figure 3(a) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all circular; Figure 3(b) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all hexagonal; Figure 3(c) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all octagonal; and Figure 3(d) shows the case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all decagonal.

[0032] refer to Figures 1 to 2The semiconductor structure includes: a substrate 100; an annular barrier layer structure 101 located on the substrate 100; a first doped region 102 located in the substrate 100 on the inner side of the annular barrier layer structure 101, the annular barrier layer structure 101 surrounding the first doped region 102, and the first doped region 102 having a first type of doped ion; and a second doped region 103 located in the substrate 100 on the outer side of the annular barrier layer structure 101, the second doped region 103 surrounding the annular barrier layer structure 101, the second doped region 103 having a second type of doped ion, and the first type of doped ion and the second type of doped ion having different conductivity types.

[0033] It should be noted that, since the annular barrier layer structure 101 and the second doped region 103 are sequentially surrounded around the first doped region 102, it is beneficial to improve the area utilization rate of the semiconductor structure and reduce the production cost; at the same time, the semiconductor structure can be placed in a smaller space area, which is beneficial to further improve the area utilization rate of the semiconductor structure.

[0034] The substrate 100 is used to provide a process platform for the semiconductor structure.

[0035] The substrate 100 includes a substrate (not indicated), which may be made of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), indium gallium arsenide (InAs), or other materials such as group III-V semiconductor materials. The substrate may also be other types of substrates such as silicon on insulator (SSOI), silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), silicon on insulator (SOI), or germanium on insulator (GOI).

[0036] In this embodiment, the substrate 100 includes, from bottom to top, a bottom semiconductor layer 120, an insulating material layer 122, and a top semiconductor layer (not shown).

[0037] Specifically, the insulating material layer 122 is a buried oxide (BOX) layer, which can be made of silicon dioxide. The bottom semiconductor layer 120 can be made of silicon, germanium, or germanium-silicon, and the top semiconductor layer can be made of undoped silicon, doped silicon, undoped germanium, or doped germanium. When the top semiconductor layer is made of undoped silicon or doped silicon, the substrate 100 is a silicon-on-insulator (GOI) substrate. When the top semiconductor layer is made of undoped germanium or doped germanium, the substrate 100 is a germanium-on-insulator (GOI) substrate. In this embodiment, the substrate on the insulator is a silicon-on-insulator substrate.

[0038] In this embodiment, the semiconductor structure further includes a well region 104 located in the substrate 100, the well region 104 having the first type of doped ions or the second type of doped ions.

[0039] It should be noted that the first type of dopant ion is an N-type ion, and the second type of dopant ion is a P-type ion. As an example, N-type ions include B, Ga, or In, and P-type ions include P, As, or Sb. In a specific embodiment, the well region 104 contains N-type ions.

[0040] Specifically, the well region 104 is located in the top semiconductor layer, and the bottom of the well region 104 is in contact with the top of the insulating material layer 122. Alternatively, the bottom of the well region 104 is located in the insulating material layer 122. This makes it easy to have a larger longitudinal cross-sectional area of ​​the PN junction in the semiconductor structure, which makes it easier for the electrostatic protection structure to have lower parasitic noise and current leakage. It has a wide range of applications and can be used in the field of radio frequency (RF) devices. It also helps to improve the stability of electrostatic protection devices.

[0041] Correspondingly, the first doped region 102 and the second doped region 103 are both located in the well region 104.

[0042] It should be noted that, for ease of illustration, Figure 2 The trap area in some regions has been omitted.

[0043] In this embodiment, the semiconductor structure further includes a second isolation structure 105, located in the substrate 100 and surrounding the second doped region 103.

[0044] The second isolation structure 105 is a shallow trench isolation structure (STI).

[0045] The second isolation structure 105 is used to isolate the various semiconductor devices to prevent leakage current between them.

[0046] Specifically, the bottom of the second isolation structure 105 is in contact with the top of the insulating material layer 122, or the bottom of the second isolation structure 105 is located in the insulating material layer 122, which can improve the isolation performance of the second isolation structure 105.

[0047] It should be noted that the material of the second isolation structure 105 is an insulating material. As an example, the material of the second isolation structure 105 is silicon oxide.

[0048] The second isolation structure 105 surrounds the second doped region 103, which helps to better isolate adjacent semiconductor devices.

[0049] refer to Figure 2 In this embodiment, along the normal direction of the top surface of the substrate 100, the thickness h1 of the second isolation structure 105 (e.g., ...) Figure 2 The thickness h1 of the second isolation structure 105 (as shown) should not be too small. If the thickness h1 of the second isolation structure 105 is too small, the isolation effect of the second isolation structure 105 on the various semiconductor devices will be poor. Therefore, in this embodiment, the thickness h1 of the second isolation structure 105 along the normal direction of the top surface of the substrate 100 is greater than or equal to 30 nanometers.

[0050] In one specific embodiment, the thickness h1 of the second isolation structure 105 is 30 nanometers to 200 nanometers.

[0051] In this embodiment, along the normal direction perpendicular to the top surface of the base 100, the width w1 of the second isolation structure 105 (e.g., ...) Figure 2 The width w1 of the second isolation structure 105 (as shown) should not be too small. If the width w1 of the second isolation structure 105 is too small, the isolation effect of the second isolation structure 105 on the various semiconductor devices will be poor. Therefore, in this embodiment, the width w1 of the second isolation structure 105 along the normal direction perpendicular to the top surface of the substrate 100 is greater than 0.1 micrometers.

[0052] In this embodiment, the annular barrier layer structure 101 is a gate structure located on the substrate 100.

[0053] The annular barrier layer structure 101 is used to define the positions of the first doped region 102 and the second doped region 103, and is also used to control the opening or pinching off of the conductive channel.

[0054] In this embodiment, the gate structure includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0055] Specifically, the gate dielectric layer is made of silicon oxide or silicon oxynitride, and the gate electrode layer is made of polycrystalline silicon, amorphous silicon, or amorphous carbon. In this embodiment, the gate structure is a polycrystalline silicon gate structure.

[0056] In other embodiments, the gate structure may also be a metal gate structure. Accordingly, the material of the gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, or La2O3, and the material of the gate electrode layer includes TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, or TiAlC.

[0057] In this embodiment, the annular barrier layer structure 101 is located on the substrate 100 of the well region 104, which is beneficial to improving the gate structure's control over the conductive channel, thereby improving the electrical performance of the semiconductor structure.

[0058] In this embodiment, along a direction perpendicular to the surface normal of the substrate 100, the distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 (e.g., ...) Figure 1 The distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 should not be too large or too small. If the distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 is too large, the area of ​​the semiconductor structure will be too large, thereby reducing the integration density. If the distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 is too small, the process difficulty of forming the annular barrier layer structure 101 will be increased, and the robustness of the semiconductor structure will be reduced. Therefore, in this embodiment, the distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 is 0.3 micrometers to 2 micrometers.

[0059] It should be noted that, in one embodiment, the second doped region 103 is located between the annular barrier layer structure 101 and the adjacent second isolation structure 105. Therefore, the distance w2 between the annular barrier layer structure 101 and the adjacent second isolation structure 105 is the lateral dimension of the second doped region 103 along the direction perpendicular to the surface normal of the substrate 100.

[0060] In this embodiment, along the direction perpendicular to the surface normal of the substrate 100, the width w3 of the annular barrier layer structure 101 (e.g., ...) Figure 1The width w3 of the annular barrier layer structure 101 should not be too large or too small. If the width w3 of the annular barrier layer structure 101 is too large, it can easily lead to an increase in the parasitic capacitance between the annular barrier layer structure 101 and the first doped region 102, and between the annular barrier layer structure 101 and the second doped region 103, thereby reducing the electrostatic protection capability of the semiconductor structure. If the width w3 of the annular barrier layer structure 101 is too small, it can easily increase the difficulty of forming the annular barrier layer structure 101. Therefore, along the direction perpendicular to the surface normal of the substrate 100, the width w3 of the annular barrier layer structure 101 is 0.2 micrometers to 2 micrometers.

[0061] It should be noted that the width w3 of the annular barrier layer structure 101 represents the distance between the first doped region 102 and the second doped region 103.

[0062] It should also be noted that in this embodiment, the barrier layer structure 101 is located on the substrate 100. In other embodiments, the barrier layer structure may also be located within the substrate. Accordingly, when the barrier layer structure may also be located within the substrate, the annular barrier layer structure is located within the substrate of the well region.

[0063] like Figure 2 As shown in the illustration, in this embodiment, the semiconductor structure may further include: a sidewall (not shown), located on the sidewall of the gate structure. It should be noted that, for ease of illustration, Figure 1 The side walls are not shown in the diagram.

[0064] The first doped region 102 serves as the cathode or anode of the electrostatic protection structure and is used for electrical connection with the cathode electrode or anode electrode.

[0065] In this embodiment, along a direction perpendicular to the surface normal of the substrate 100 and perpendicular to the sidewall of the first doped region 102, the lateral dimension w4 of the first doped region 102 (e.g., ...) is... Figure 1 The lateral dimension w4 of the first doped region 102 (as shown) should not be too large or too small. If the lateral dimension w4 of the first doped region 102 is too large, the area of ​​the semiconductor structure will be too large, thereby reducing the integration density; if the lateral dimension w4 of the first doped region 102 is too small, it will increase the difficulty of forming the first doped region 102 and reduce the robustness of the semiconductor structure. Therefore, in this embodiment, the lateral dimension w4 of the first doped region 102 is 0.5 micrometers to 40 micrometers along the direction perpendicular to the surface normal of the substrate 100 and perpendicular to the sidewall of the first doped region 102.

[0066] It should be noted that when the first doped region 102 is rectangular, the lateral dimension w4 of the first doped region 102 refers to the length or width of the rectangle along the direction perpendicular to the surface normal of the substrate 100 and perpendicular to the sidewall of the first doped region 102; when the first doped region 102 is circular, the lateral dimension w4 of the first doped region 102 refers to the diameter of the circle along the direction perpendicular to the surface normal of the substrate 100 and perpendicular to the sidewall of the first doped region 102.

[0067] In this embodiment, along the normal direction of the top surface of the substrate 100, the depth d1 of the first doped region 102 (e.g., ...) Figure 2 The depth d1 of the first doped region 102 (as shown) should not be too large or too small. If the depth d1 of the first doped region 102 is too small, it will easily increase the contact resistance of the first doped region 102, resulting in poor conductivity. It will also easily make the depth of the PN junction too small, thus making it difficult to improve the breakdown current of the semiconductor structure. If the depth d1 of the first doped region 102 is too large, it will easily increase the degree of ion diffusion, which will correspondingly increase the probability that the well region 104 is affected by ion diffusion, thus making the depth of the well region 104 smaller, and thus affecting the stability of the semiconductor structure. Therefore, in this embodiment, the depth d1 of the first doped region 102 along the normal direction of the top surface of the substrate 100 is 30 nanometers to 200 nanometers.

[0068] It should be noted that during the fabrication of the semiconductor structure, the first doped region 102 is typically formed using an ion implantation process. Therefore, the barrier structure 101 with a width close to the first doped region 102 contains type I doped ions.

[0069] The second doped region 103 serves as the cathode or anode of the electrostatic protection structure and is used for electrical connection with the cathode electrode or anode electrode.

[0070] In this configuration, one of the first doped region 102 and the second doped region 103 serves as the cathode, and the other serves as the anode.

[0071] refer to Figure 2 In this embodiment, the depth d2 of the second doped region 103 along the normal direction of the top surface of the substrate 100 should not be too large or too small. The reason why the depth d2 of the second doped region 103 should not be too large or too small is similar to the reason why the depth d1 of the first doped region 102 should not be too large or too small, so it will not be repeated here. Therefore, in this embodiment, the depth d2 of the second doped region 103 along the normal direction of the top surface of the substrate 100 is 30 nanometers to 200 nanometers.

[0072] It should be noted that during the fabrication of the semiconductor structure, the second doped region 103 is typically formed using an ion implantation process. Therefore, the width barrier structure 101 on the side near the second doped region 103 contains type II doped ions.

[0073] It should also be noted that, along the direction perpendicular to the surface normal of the substrate 100, the outline shapes of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 all include circles or polygons [e.g., ...]. Figure 1 As shown in Figures 3(b) to (d).

[0074] For example, as shown in FIG3(a), the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all circular along the direction perpendicular to the surface normal of the substrate 100.

[0075] For example, such as Figure 1 , Figures 3(b) to 3(d) As shown, along the direction perpendicular to the surface normal of the substrate 100, the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all polygonal.

[0076] The parasitic capacitance and robustness of the multi-finger electrostatic discharge (ESD) protection structure are high, which affects the performance of the ESD protection structure. Compared with the multi-finger structure, the embodiments of the present invention improve the problems of parasitic capacitance and corner effect, thereby improving the robustness of the semiconductor structure.

[0077] In this embodiment, along the direction perpendicular to the surface normal of the substrate 100, the outline shapes of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 all include rectangles or regular polygons. Since rectangles and regular polygons have regular geometric shapes, the semiconductor structure is easier to arrange and align on the chip, thereby improving the area utilization of the semiconductor structure.

[0078] It should be noted that the regular polygons include: regular quadrilaterals, regular hexagons, regular octagons, or regular decagons.

[0079] like Figure 1 As shown, in this embodiment, the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all rectangular along the direction perpendicular to the surface normal of the substrate 100.

[0080] In other embodiments, for example, as shown in FIG3(b), the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all regular hexagons along the direction perpendicular to the surface normal of the substrate 100; as shown in FIG3(c), the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all regular octagons along the direction perpendicular to the surface normal of the substrate 100; as shown in FIG3(d), the outlines of the annular barrier layer structure 101, the first doped region 102, and the second doped region 103 are all regular decagons along the direction perpendicular to the surface normal of the substrate 100.

[0081] In this embodiment, the semiconductor structure further includes an interconnect structure (not shown) that is electrically connected to the first doped region 102 and the second doped region 103, respectively.

[0082] The interconnect structure is used to apply a ground potential (i.e., zero potential), a positive potential, or a negative potential to the first doped region 102 and the second doped region 103.

[0083] It should be noted that the interconnect structure can be a certain layer interconnect structure in the back-end process (e.g., the first metal interconnect layer M1).

[0084] In this embodiment, the annular barrier layer structure 101 is a gate structure.

[0085] Therefore, the interconnect structure is electrically connected to the gate structure, the first doped region 102, and the second doped region 103, respectively.

[0086] It should be noted that the interconnect structure is electrically connected to the gate structure, and applying a potential to the gate structure through the interconnect structure helps to reduce the difficulty of applying a potential to the gate structure.

[0087] Applying a potential to the first doped region 102 through the interconnect structure electrically connected to the first doped region 102 helps reduce the difficulty of applying a potential to the first doped region 102. Similarly, applying a potential to the second doped region 103 through the interconnect structure electrically connected to the second doped region 103 helps reduce the difficulty of applying a potential to the second doped region 103.

[0088] In this embodiment, the material of the interconnect structure includes one or more of copper, tantalum, and tantalum nitride.

[0089] Copper, tantalum, and tantalum nitride have high conductivity and low resistivity, which helps reduce the resistance of electrostatic discharge (ESD) protection devices, thereby improving their heat dissipation. In other embodiments, the interconnect structure can also be made of other conductive materials.

[0090] Specifically, the interconnect structure includes a barrier layer (not shown) and a conductive layer (not shown) located on the barrier layer. The barrier layer is made of tantalum or tantalum nitride, and the conductive layer is made of copper.

[0091] In this embodiment, the semiconductor structure further includes a first plug (not shown) located between the interconnect structure and the gate structure, wherein the first plug is located on the gate structure and electrically connected to the gate structure.

[0092] The first plug is used to bring out the electrical properties of the gate structure.

[0093] Providing a first plug between the interconnect structure and the gate structure helps reduce the difficulty of forming an interconnect structure that electrically connects the gate structure.

[0094] Specifically, the material of the first plug includes one or more of tungsten, cobalt, and ruthenium. Tungsten, cobalt, and ruthenium have good electrical conductivity, which is beneficial for improving the electrical connection performance between the gate structure and the interconnect structure.

[0095] In this embodiment, the semiconductor structure further includes a second plug 109, which is located between the interconnect structure and the first doped region 102 and between the interconnect structure and the second doped region 103, respectively. The second plug 109 is located on the first doped region 102 and the second doped region 103, respectively, and is electrically connected to the first doped region 102 and the second doped region 103, respectively.

[0096] The second plug 109 is used to draw out the electrical properties of the first doped region 102 and the second doped region 103.

[0097] By providing second plugs 109 between the interconnect structure and the first doped region 102, and between the interconnect structure and the second doped region 103, it is beneficial to reduce the difficulty of forming the interconnect structure that electrically connects the first doped region 102 and the interconnect structure that electrically connects the second doped region 103.

[0098] Specifically, the material of the second plug 109 includes one or more of tungsten, cobalt, and ruthenium. Tungsten, cobalt, and ruthenium have good electrical conductivity, which is beneficial to improving the electrical connection performance between the interconnect structure and the first doped region 102, and between the interconnect structure and the second doped region 103.

[0099] It should be noted that, along the direction perpendicular to the surface normal of the substrate 100, the distance w5 between the second plug 109 and the adjacent annular barrier layer structure 101 (e.g., ...) Figure 1The distance w5 between the second plug 109 and the adjacent annular barrier layer structure 101 should not be too small or too large. If the distance w5 between the second plug 109 and the adjacent barrier layer structure 101 is too small, the parasitic capacitance between the second plug 109 and the adjacent barrier structure 101 will be too large, which will also increase the difficulty of forming the second plug 109. If the distance w5 between the second plug 109 and the adjacent annular barrier layer structure 101 is too large, the area of ​​the semiconductor structure will be too large. Therefore, in this embodiment, the distance w5 between the second plug 109 and the adjacent annular barrier layer structure 101 is 0.1 micrometers to 2 micrometers along the direction perpendicular to the surface normal of the substrate 100.

[0100] In this embodiment, the semiconductor structure further includes a metal silicide layer 110, which covers the top of the first doped region 101 and the second doped region 102.

[0101] The metal silicide layer 110 can reduce the contact resistance between the first doped region 102 and the external electrical connection structure, and between the second doped region 103 and the external electrical connection structure.

[0102] Specifically, the material of the metal silicide layer 110 includes one or more of titanium silicon compounds, cobalt silicon compounds, or nickel silicon compounds.

[0103] As an example, the metal silicide layer 110 may also be formed on top of the barrier structure 101. Figure 2 (Not shown in the image).

[0104] refer to Figures 4 to 5 , Figure 4 This is a schematic diagram of the second embodiment of the semiconductor structure of the present invention. Figure 5 yes Figure 4 Cross-sectional view along the BB1 ​​direction.

[0105] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the annular barrier layer structure 201 is an insulating barrier structure, and the insulating barrier structure is a silicide barrier (SAB) structure.

[0106] In this embodiment, the insulating barrier structure is located on the substrate 200.

[0107] Specifically, the annular barrier layer structure 201 is an insulating barrier structure, meaning the semiconductor structure is a gateless device. When a high voltage is applied, compared to a gate-structured annular barrier layer structure, it is easier to reduce the probability of gate breakdown in the semiconductor structure. At the same time, in the process of forming the semiconductor structure, since there is no need to form a gate structure, the photomask can be reduced, thereby reducing the process cost.

[0108] In this embodiment, the annular barrier layer structure 201 is a silicide barrier structure.

[0109] Silicide barrier structures are used to prevent metal silicide layers from forming in areas where they are not desired.

[0110] The material of the silicide barrier structure may include one or more of oxide materials, nitride materials, and oxynitride materials. For example, oxide materials may include silicon oxide, nitride materials may include silicon nitride, and oxynitride materials may include silicon oxynitride.

[0111] It should be noted that the annular barrier layer structure 201 is a silicide barrier structure, which is used to isolate the first doped region 202 and the second doped region 203, so that the silicide barrier structure, the first doped region 202 and the second doped region 203 form a high-resistivity region, thereby controlling the magnitude of the current.

[0112] Therefore, the semiconductor structure includes: an interconnect structure (not shown) electrically connected to the first doped region 202 and the second doped region 203 respectively; and a second plug 209 located between the interconnect structure and the first doped region 202 and between the interconnect structure and the second doped region 203 respectively.

[0113] For a description of the interconnection structure and the second plug 209, please refer to the relevant content in the foregoing embodiments, and it will not be repeated here.

[0114] refer to Figures 6 to 7 , Figure 6 This is a schematic diagram of the third embodiment of the semiconductor structure of the present invention. Figure 7 yes Figure 6 Cross-sectional view along the CC1 direction.

[0115] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the annular barrier layer structure 301 is an insulating barrier structure, and the insulating barrier structure is located in the substrate 300.

[0116] In this embodiment, the insulating barrier structure is a first isolation structure, and the first isolation structure is located in the substrate 300.

[0117] Specifically, the annular barrier layer structure 301 is an insulating barrier structure, meaning the semiconductor structure is a gateless device. When a high voltage is applied, compared to a gate-structured annular barrier layer structure, it is easier to reduce the probability of gate breakdown in the semiconductor structure. At the same time, in the process of forming the semiconductor structure, since there is no need to form a gate structure, the photomask can be reduced, thereby reducing the process cost.

[0118] The first isolation structure is a shallow trench isolation structure.

[0119] It should be noted that the annular barrier layer structure 301 is a first isolation structure used to isolate the first doped region 302 and the second doped region 303, and the thickness of the first isolation structure is less than the thickness of the second isolation structure 305.

[0120] In this embodiment, the annular barrier layer structure 301 is a first isolation structure.

[0121] Therefore, the semiconductor structure includes: an interconnect structure (not shown) electrically connected to the first doped region 302 and the second doped region 303 respectively; and a second plug 309 located between the interconnect structure and the first doped region 302 and between the interconnect structure and the second doped region 303 respectively.

[0122] For a description of the interconnection structure and the second plug 309, please refer to the relevant content in the foregoing embodiments, and it will not be repeated here.

[0123] Accordingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 14 This is a schematic diagram of the structure corresponding to each step in the first embodiment of the semiconductor structure formation method of the present invention.

[0124] refer to Figure 8 Provides a 500 base.

[0125] The substrate 500 is used to provide a process platform for the semiconductor structure.

[0126] The substrate 500 includes a substrate (not indicated), which may be made of silicon, germanium, silicon germanide, silicon carbide, silicon germanium carbon, indium arsenide, gallium arsenide, indium phosphide, indium gallium phosphate, or other materials such as group III-V semiconductor materials. The substrate may also be other types of substrates such as a multilayer silicon substrate on an insulator, a multilayer silicon germanide substrate on an insulator, a silicon substrate on an insulator, or a germanium substrate on an insulator.

[0127] In this embodiment, the substrate 500 includes, from bottom to top, a bottom semiconductor layer 520, an insulating material layer 522, and a top semiconductor layer (not shown).

[0128] Specifically, the insulating material layer 522 is an oxide buried layer, and the material of the oxide buried layer can be silicon dioxide. The material of the bottom semiconductor layer 520 can be silicon, germanium, or germanium-silicon. The material of the top semiconductor layer can be undoped silicon, doped silicon, undoped germanium, or doped germanium. When the material of the top semiconductor layer is undoped silicon or doped silicon, the substrate 500 is a silicon substrate on an insulator; when the material of the top semiconductor layer is undoped germanium or doped germanium, the substrate 500 is a germanium substrate on an insulator. In this embodiment, the substrate on an insulator is a silicon substrate on an insulator.

[0129] In this embodiment, a well region 504 is formed in the substrate 500, and the well region 504 has the first type doped ion or the second type doped ion.

[0130] It should be noted that the first type of dopant ion is an N-type ion, and the second type of dopant ion is a P-type ion. As an example, N-type ions include B, Ga, or In, and P-type ions include P, As, or Sb.

[0131] In one specific embodiment, the well region 504 contains N-type ions.

[0132] Specifically, the well region 504 is located in the top semiconductor layer, and the bottom of the well region 504 is in contact with the top of the insulating material layer 522. Alternatively, the bottom of the well region 504 is located in the insulating material layer 522. This makes it easy to have a larger longitudinal cross-sectional area of ​​the PN junction of the semiconductor structure, which makes it easier to have lower parasitic noise and current leakage in the electrostatic protection structure. It has a wide range of applications and can be used in the field of radio frequency devices. It also helps to improve the stability of electrostatic protection devices.

[0133] In this embodiment, the process for forming the well region 504 includes an ion implantation process. The process parameters for the ion implantation process include: the implanted ions are N-type ions or P-type ions, the implantation energy ranges from 5 keV to 100 keV, and the implantation dose ranges from 1 E12 atom / cm². 2 Up to 1E14 atom / cm 2 The energy and dose of the injected ions are within the range described above, so that the bottom of the trap region 504 is in contact with the top of the insulating material layer 522, or is located within the insulating material layer 522.

[0134] Continue to refer to Figure 8 After providing the substrate 500 and before forming the annular barrier structure, the forming method further includes forming a second isolation structure 505 in the substrate 500.

[0135] The second isolation structure 505 is a shallow trench isolation structure.

[0136] The second isolation structure 505 is used to isolate the various semiconductor devices to prevent leakage current between them.

[0137] Specifically, the bottom of the second isolation structure 505 is in contact with the top of the insulating material layer 522, or the bottom of the second isolation structure 505 is located in the insulating material layer 522, which can improve the isolation performance of the second isolation structure 505.

[0138] It should be noted that the material of the second isolation structure 505 is an insulating material. As an example, the material of the second isolation structure 505 is silicon oxide.

[0139] In this embodiment, the thickness H1 of the second isolation structure 505 along the normal direction of the top surface of the substrate 500 should not be too small. If the thickness H1 of the second isolation structure 505 is too small, the isolation effect of the second isolation structure 505 on the various semiconductor devices may be poor. Therefore, in this embodiment, the thickness H1 of the second isolation structure 505 along the normal direction of the top surface of the substrate 500 is greater than or equal to 30 nanometers.

[0140] In one specific embodiment, the thickness H1 of the second isolation structure 505 is 30 nanometers to 200 nanometers.

[0141] In this embodiment, the width W1 of the second isolation structure 505 along the normal direction perpendicular to the top surface of the substrate 500 should not be too small. If the width W1 of the second isolation structure 505 is too small, the isolation effect of the second isolation structure 505 on the various semiconductor devices may be poor. Therefore, in this embodiment, the width W1 of the second isolation structure 505 along the normal direction perpendicular to the top surface of the substrate 500 is greater than 0.1 micrometers.

[0142] It should also be noted that the isolation structure 505 can be formed after the formation of the well region 504, or it can be formed before the formation of the well region 504.

[0143] refer to Figures 9 to 1 3. An annular barrier layer structure 501 is formed on the substrate 500, and a first doped region 502 and a second doped region 503 are formed in the substrate 500 at intervals, the second doped region 503 surrounds the first doped region 502, and the barrier layer structure 501 is located between the first doped region 502 and the second doped region 503 and surrounds the first doped region 502.

[0144] in, Figure 9 This is a top view after an annular barrier layer structure has been formed on the substrate. Figure 10 yes Figure 9 Cross-sectional view along the EE1 direction. Figure 11 This is a top view of a first doped region and a second doped region spaced apart in the substrate. Figure 12 yes Figure 11 A cross-sectional view along the EE1 direction, Figure 13(a) is Figure 11 The case where the ring-shaped barrier layer structure, the first doped region, and the second doped region all have circular outlines is shown in Figure 13(b). Figure 11 The case where the ring-shaped barrier layer structure, the first doped region, and the second doped region all have hexagonal outlines is shown in Figure 13(c). Figure 11 The case where the ring-shaped barrier layer structure, the first doped region, and the second doped region all have octagonal outlines is shown in Figure 13(d). Figure 11 The case where the outlines of the annular barrier layer structure, the first doped region, and the second doped region are all decagonal.

[0145] In this embodiment, the annular blocking structure 501 is an annular gate structure, and the annular gate structure is located on the substrate 500.

[0146] Therefore, refer to Figures 9 to 10 Before forming the first doped region and the second doped region, an annular gate structure is formed on the substrate 500 to serve as an annular barrier structure 501.

[0147] The annular barrier structure 501 is used to define the positions of the first doped region 502 and the second doped region 503, and also to control the opening or pinching off of the conductive channel.

[0148] In this embodiment, the gate structure includes a gate dielectric layer (not shown) and a gate electrode layer (not shown) located on the gate dielectric layer.

[0149] Specifically, the gate dielectric layer is made of silicon oxide or silicon oxynitride, and the gate electrode layer is made of polycrystalline silicon, amorphous silicon, or amorphous carbon. In this embodiment, the gate structure is a polycrystalline silicon gate structure.

[0150] In other embodiments, the gate structure may also be a metal gate structure. Accordingly, the material of the gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, or La2O3, and the material of the gate electrode layer includes TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, or TiAlC.

[0151] In this embodiment, the annular barrier structure 501 is located on the well region 504, which helps to improve the gate structure's control over the conductive channel, thereby improving the electrical performance of the semiconductor structure.

[0152] In this embodiment, along a direction perpendicular to the surface normal of the substrate 500, the distance W2 between the annular barrier layer structure 501 and the adjacent second isolation structure 505 (e.g., ...) Figure 9 The distance W2 between the annular barrier layer structure 501 and the adjacent second isolation structure 505 should not be too large or too small. If the distance W2 is too large, the area of ​​the semiconductor structure will be too large, thereby reducing the integration density. If the distance W2 between the annular barrier layer structure 501 and the adjacent second isolation structure 505 is too small, it will increase the difficulty of forming the annular barrier layer structure 501 and reduce the robustness of the semiconductor structure. Therefore, in this embodiment, the distance W2 between the annular barrier layer structure 501 and the adjacent second isolation structure 505 is 0.3 micrometers to 2 micrometers.

[0153] It should be noted that, in one embodiment, the second doped region 503 is located between the annular barrier layer structure 501 and the adjacent second isolation structure 505. Therefore, the distance W2 between the annular barrier layer structure 501 and the adjacent second isolation structure 505 is the lateral dimension of the second doped region 503 along the direction perpendicular to the surface normal of the substrate 500.

[0154] In this embodiment, along the direction perpendicular to the surface normal of the substrate 500, the width W3 of the annular barrier layer structure 501 (e.g., Figure 9 The width W3 of the annular barrier layer structure 501 should not be too large or too small. If the width W3 of the annular barrier layer structure 501 is too large, it can easily lead to an increase in the parasitic capacitance between the annular barrier layer structure 501 and the first doped region 502, and between the annular barrier layer structure 501 and the second doped region 503, thereby reducing the electrostatic protection capability of the semiconductor structure. If the width W3 of the annular barrier layer structure 501 is too small, it can easily increase the difficulty of forming the annular barrier layer structure 501. Therefore, along the direction perpendicular to the surface normal of the substrate 500, the width w3 of the annular barrier layer structure 501 is 0.2 micrometers to 2 micrometers.

[0155] It should be noted that the width W3 of the annular barrier layer structure 501 represents the distance between the first doped region 502 and the second doped region 503.

[0156] It should also be noted that in this embodiment, the barrier layer structure 501 is located on the substrate 500. In other embodiments, the barrier layer structure may also be located within the substrate. Accordingly, when the barrier layer structure may also be located within the substrate, the annular barrier layer structure is located within the substrate of the well region.

[0157] like Figure 10 As shown, after forming the gate structure and before forming the first doped region 502 and the second doped region 503, the process further includes: forming sidewalls (not shown) on the sidewalls of the gate structure. It should be noted that, for ease of illustration, Figure 9 , Figure 11 Figure 13 and Figure 14 The side walls are not shown in the diagram.

[0158] refer to Figures 11 to 12 The step of forming a first doped region 502 and a second doped region 503 spaced apart in the substrate 500 includes: forming a first doped region 502 in the substrate 500 on the inner side of the annular gate structure, and the annular gate structure surrounding the first doped region 502; forming a second doped region 503 in the substrate 500 on the outer side of the annular gate structure, and the second doped region 503 surrounding the annular gate structure.

[0159] The first doped region 502 has a first type of doped ion, the second doped region 503 has a second type of doped ion, and the first type of doped ion and the second type of doped ion have different conductivity types.

[0160] The first doped region 502 serves as the cathode or anode of the electrostatic protection structure and is used for electrical connection with the cathode electrode or anode electrode.

[0161] In this configuration, one of the first doped region 502 and the second doped region 503 serves as the cathode, and the other serves as the anode.

[0162] In this embodiment, along a direction perpendicular to the surface normal of the substrate 500 and perpendicular to the sidewall of the first doped region 502, the lateral dimension W4 of the first doped region 502 (e.g., ...) is... Figure 11 The lateral dimension W4 of the first doped region 502 (as shown) should not be too large or too small. If the lateral dimension W4 of the first doped region 502 is too large, the area of ​​the semiconductor structure will be too large, thereby reducing the integration density; if the lateral dimension W4 of the first doped region 502 is too small, the process difficulty of forming the first doped region 502 will be increased, and the robustness of the semiconductor structure will be reduced. Therefore, in this embodiment, the lateral dimension W4 of the first doped region 502 is 0.5 micrometers to 40 micrometers along the direction perpendicular to the surface normal of the substrate 500 and perpendicular to the sidewall of the first doped region 502.

[0163] It should also be noted that when the first doped region 502 is rectangular, the lateral dimension W4 of the first doped region 502 refers to the length or width of the rectangle along the direction perpendicular to the surface normal of the substrate 500 and perpendicular to the sidewall of the first doped region 502; when the first doped region 502 is circular, the lateral dimension W4 of the first doped region 502 refers to the diameter of the circle along the direction perpendicular to the surface normal of the substrate 500 and perpendicular to the sidewall of the first doped region 502.

[0164] In this embodiment, along the normal direction of the top surface of the substrate 500, the depth D1 of the first doped region 502 (e.g., ...) Figure 12 The depth D1 of the first doped region 502 (as shown) should not be too large or too small. If the depth D1 of the first doped region 502 is too small, it will easily increase the contact resistance of the first doped region 502, resulting in poor conductivity. It will also easily make the depth of the PN junction too small, thus making it difficult to improve the breakdown current of the semiconductor structure. If the depth D1 of the first doped region 502 is too large, it will easily increase the degree of ion diffusion, which will correspondingly increase the probability that the well region 504 is affected by ion diffusion, thus making the depth of the well region 504 smaller, and thus affecting the stability of the semiconductor structure. Therefore, in this embodiment, the depth D1 of the first doped region 502 along the normal direction of the top surface of the substrate 500 is 30 nanometers to 200 nanometers.

[0165] The process for forming the first doped region 502 includes an ion implantation process. The process parameters for the ion implantation process include: the implanted ions are P-type ions, the implantation energy ranges from 5 keV to 100 keV, and the implantation dose ranges from 1E14 atom / cm². 2 Up to 9E15atom / cm 2 This is beneficial to ensure that the depth D1 of the first doped region 502 is within the aforementioned range.

[0166] The first doped region 502 is usually formed by ion implantation. Therefore, in order to increase the process window of photolithography, the barrier structure 501 with a width of a certain width near the first doped region 502 contains type I doped ions.

[0167] The second doped region 503 serves as the cathode or anode of the electrostatic protection structure and is used for electrical connection with the cathode electrode or anode electrode.

[0168] In this embodiment, along the normal direction of the top surface of the substrate 500, the depth D2 of the second doped region 503 (e.g., ...) Figure 12The depth D2 of the second doped region 503 (as shown) should not be too large or too small. The reasons for this are similar to those for the first doped region 502's depth D1, and therefore will not be repeated here. Therefore, in this embodiment, along the normal direction of the top surface of the substrate 500, the depth D2 of the second doped region 503 is 30 nanometers to 200 nanometers.

[0169] The process for forming the second doped region 503 includes an ion implantation process. The process parameters for the ion implantation process include: the implanted ions are N-type ions, the implantation energy ranges from 5 keV to 100 keV, and the implantation dose ranges from 1E14 atom / cm². 2 Up to 9E15atom / cm 2 This is beneficial to ensure that the depth D2 of the second doped region 503 is within the aforementioned range.

[0170] The second doped region 503 is usually formed by ion implantation. Therefore, in order to increase the process window of photolithography, the barrier structure 501 near the second doped region 503 contains type I or type II doped ions.

[0171] In this embodiment, along a direction perpendicular to the surface normal of the substrate 500, the outline shapes of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 all include circles or polygons [e.g., ...]. Figure 11 As shown in Figures 13(b) to (d).

[0172] For example, as shown in FIG13(a), the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all circular along the direction perpendicular to the surface normal of the substrate 500.

[0173] For example, such as Figure 11 , Figures 13(b) to 13(d) As shown, along the direction perpendicular to the surface normal of the substrate 500, the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all polygonal.

[0174] The parasitic capacitance and robustness of the multi-finger electrostatic discharge (ESD) protection structure are high, which affects the performance of the ESD protection structure. Compared with the multi-finger structure, the embodiments of the present invention improve the problems of parasitic capacitance and corner effect, thereby improving the robustness of the semiconductor structure.

[0175] In this embodiment, along the direction perpendicular to the surface normal of the substrate 500, the outline shapes of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 all include rectangles or regular polygons. Since rectangles and regular polygons have regular geometric shapes, the semiconductor structure is easier to arrange and align on the chip, thereby improving the area utilization of the semiconductor structure.

[0176] It should be noted that the regular polygons include: regular quadrilaterals, regular hexagons, regular octagons, or regular decagons.

[0177] like Figure 11 As shown, in this embodiment, the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all rectangular along the direction perpendicular to the surface normal of the substrate 500.

[0178] In other embodiments, for example, as shown in FIG13(b), the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all regular hexagons along the direction perpendicular to the surface normal of the substrate 500; as shown in FIG13(c), the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all regular octagons along the direction perpendicular to the surface normal of the substrate 500; as shown in FIG13(d), the outlines of the annular barrier layer structure 501, the first doped region 502, and the second doped region 503 are all regular decagons along the direction perpendicular to the surface normal of the substrate 500.

[0179] refer to Figure 14 , Figure 14 for Figure 11 A top view after the formation of the second plug. In this embodiment, after forming the first doped region 502 and the second doped region 503 and before forming the interconnect structure, the formation method further includes: forming a second plug 509 on the first doped region 502 and the second doped region 503 respectively, the second plug 509 being located on the first doped region 502 and the second doped region 503 respectively, and electrically connected to the first doped region 502 and the second doped region 503 respectively; forming a first plug (not shown) on the annular gate structure, the first plug being located on the gate structure and electrically connected to the gate structure.

[0180] The first plug is used to annularly bring out the electrical components of the gate structure.

[0181] Forming a first plug on the annular gate structure helps reduce the difficulty of subsequently forming an interconnect structure that electrically connects the gate structure.

[0182] Specifically, the material of the first plug includes one or more of tungsten, cobalt, and ruthenium. Tungsten, cobalt, and ruthenium have good electrical conductivity, which is beneficial for improving the electrical connection performance between the gate structure and the interconnect structure.

[0183] The second plug 509 is used to draw out the electrical properties of the first doped region 502 and the second doped region 503.

[0184] Forming a second plug 509 that is electrically connected to the first doped region 502 and the second doped region 503 respectively helps to reduce the difficulty of subsequently forming an interconnect structure electrically connected to the first doped region 502 and an interconnect structure electrically connected to the second doped region 503.

[0185] Specifically, the material of the second plug 509 includes one or more of tungsten, cobalt, and ruthenium. Tungsten, cobalt, and ruthenium have good electrical conductivity, which is beneficial to improving the electrical connection performance between the interconnect structure and the first doped region 502, and between the interconnect structure and the second doped region 503.

[0186] It should be noted that, along the direction perpendicular to the surface normal of the substrate 500, the distance W5 between the second plug 509 and the adjacent annular barrier layer structure 501 (e.g., ...) Figure 14 The distance W5 between the second plug 509 and the adjacent annular barrier layer structure 501 should not be too small or too large. If the distance W5 between the second plug 509 and the adjacent barrier layer structure 501 is too small, the parasitic capacitance between the second plug 509 and the adjacent barrier structure 501 will be too large, which will also increase the difficulty of forming the second plug 509. If the distance W5 between the second plug 509 and the adjacent annular barrier layer structure 501 is too large, the area of ​​the semiconductor structure will be too large. Therefore, in this embodiment, the distance W5 between the second plug 509 and the adjacent annular barrier layer structure 501 is 0.1 micrometers to 2 micrometers along the direction perpendicular to the surface normal of the substrate 500.

[0187] In this embodiment, after forming the first doped region 502 and the second doped region 503 and before forming the first plug and the second plug, the formation method further includes: forming a metal silicide 508, wherein the metal silicide 508 covers the top of the first doped region 502 and the second doped region 503 (e.g., Figure 12 (As shown).

[0188] It should be noted that, for ease of illustration, Figure 11 Figure 13 and Figure 14 Neither of them indicated metal silicides.

[0189] The metal silicide layer 508 can reduce the contact resistance between the first doped region 502 and the external electrical connection structure, as well as the contact resistance between the second doped region 503 and the external electrical connection structure.

[0190] Specifically, the material of the metal silicide layer 508 includes one or more of titanium silicon compounds, cobalt silicon compounds, or nickel silicon compounds.

[0191] As an example, the metal silicide layer 508 may also be formed on top of the annular gate structure. Figure 12 (Not shown in the image).

[0192] In this embodiment, after forming the first plug and the second plug 509, the forming method further includes: forming an interconnect structure (not shown), wherein the interconnect structure is electrically connected to the first doped region 502 and the second doped region 503 respectively.

[0193] The interconnect structure is used to apply a ground potential (i.e., zero potential), a positive potential, or a negative potential to the first doped region 502 and the second doped region 503.

[0194] It should be noted that the interconnect structure can be a certain layer interconnect structure in the back-end process (e.g., the first metal interconnect layer M1).

[0195] In this embodiment, the annular barrier layer structure 501 is an annular gate structure.

[0196] Therefore, the interconnect structure is electrically connected to the annular gate structure, the first doped region 502, and the second doped region 503, respectively.

[0197] It should be noted that the interconnect structure is electrically connected to the annular gate structure. Applying a potential to the annular gate structure through the interconnect structure helps to reduce the difficulty of applying a potential to the annular gate structure.

[0198] Applying a potential to the first doped region 502 through the interconnect structure electrically connected to the first doped region 502 helps reduce the difficulty of applying a potential to the first doped region 502. Similarly, applying a potential to the second doped region 503 through the interconnect structure electrically connected to the second doped region 503 helps reduce the difficulty of applying a potential to the second doped region 503.

[0199] In this embodiment, the material of the interconnect structure includes one or more of copper, tantalum, and tantalum nitride.

[0200] Copper, tantalum, and tantalum nitride have high conductivity and low resistivity, which helps reduce the resistance of electrostatic discharge (ESD) protection devices, thereby improving their heat dissipation. In other embodiments, the interconnect structure can also be made of other conductive materials.

[0201] Specifically, the interconnect structure includes a barrier layer (not shown) and a conductive layer (not shown) located on the barrier layer. The barrier layer is made of tantalum or tantalum nitride, and the conductive layer is made of copper.

[0202] Accordingly, in this embodiment, during the step of forming the interconnect structure, an interconnect structure is formed on the first plug and the second plug 509, and the interconnect structure is electrically connected to the first plug and the second plug 509, respectively.

[0203] refer to Figures 15 to 16 , Figures 15 to 16 This is a schematic diagram of the structure corresponding to each step in the second embodiment of the semiconductor structure formation method of the present invention; wherein, Figure 15 This is a top view after an annular barrier layer structure has been formed on the substrate. Figure 16 yes Figure 15 A sectional view along the EE3 direction.

[0204] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that the barrier structure is an insulating barrier structure formed on the substrate.

[0205] Specifically, the annular barrier layer structure 601 is a silicide barrier structure, and the silicide barrier structure is located on the substrate 600.

[0206] Silicide barrier structures are used to prevent metal silicide layers from forming in areas where they are not desired.

[0207] The material of the silicide barrier structure may include one or more of oxide materials, nitride materials, and oxynitride materials. For example, oxide materials may include silicon oxide, nitride materials may include silicon nitride, and oxynitride materials may include silicon oxynitride.

[0208] refer to Figures 15 to 16 The step of forming an annular barrier layer structure 601 on the substrate 600 includes: after forming the first doped region 602 and the second doped region 603, forming an annular silicide barrier structure on the substrate 600 between the first doped region 602 and the second doped region 603, the annular silicide barrier structure surrounding the first doped region 602, and the second doped region 603 surrounding the annular silicide barrier structure.

[0209] It should be noted that the type of the barrier structure 601 is a silicide barrier structure. The silicide barrier structure can isolate the first doped region 602 and the second doped region 603, thereby forming a high-resistivity region with the silicide barrier structure, the first doped region 602 and the second doped region 603, which can then control the magnitude of the current.

[0210] Specifically, the annular barrier layer structure 601 is an annular silicide barrier structure, meaning the semiconductor structure is a gateless device. When a high voltage is applied, compared to a gate-structured annular barrier layer structure, it is easier to reduce the probability of gate breakdown in the semiconductor structure. At the same time, in the process of forming the semiconductor structure, since there is no need to form a gate structure, the photomask can be reduced, thereby reducing the process cost.

[0211] In this embodiment, the annular barrier layer structure 601 is a silicide barrier structure.

[0212] Therefore, after forming the annular barrier layer structure 601, the process further includes forming: forming second plugs 609 located between the interconnect structure and the first doped region 602, and between the interconnect structure and the second doped region 603; after forming the second plugs 609, forming interconnect structures electrically connected to the first doped region 602 and the second doped region 603 respectively.

[0213] For a description of the interconnection structure and the second plug 609, please refer to the relevant content in the foregoing embodiments, and it will not be repeated here.

[0214] refer to Figures 17 to 18 , Figures 17 to 18 This is a schematic diagram of the structure corresponding to each step in the third embodiment of the semiconductor structure formation method of the present invention; wherein, Figure 17 This is a top view after an annular barrier layer structure has been formed on the substrate. Figure 18 yes Figure 17 A sectional view along the EE4 direction.

[0215] The similarities between this embodiment and the previous embodiments will not be repeated here. The difference between this embodiment and the previous embodiments is that an annular barrier layer structure is formed in the substrate, and the barrier layer structure is an insulating barrier structure.

[0216] Specifically, the annular barrier layer structure 701 is of the type of a first isolation structure, and the first isolation structure is located in the substrate 700.

[0217] refer to Figures 17 to 18 The step of forming an annular barrier layer structure 701 on the substrate 700 includes: forming an annular first isolation structure in the substrate 700 before forming the first doped region 702 and the second doped region 703.

[0218] The first isolation structure is a shallow trench isolation structure.

[0219] It should be noted that the barrier structure 701 is a first isolation structure used to isolate the first doped region 702 from the second doped region 703, and the thickness of the first isolation structure is less than the thickness of the second isolation structure 705.

[0220] Specifically, in this embodiment, the first isolation structure is formed after the second isolation structure 705 is formed and before the first doped region 702 and the second doped region 703 are formed.

[0221] In this embodiment, the step of forming a first doped region 702 and a second doped region 703 spaced apart in the substrate 700 includes: forming a first doped region 702 in the substrate 700 on one side inside the annular first isolation structure, and the annular first isolation structure surrounding the first doped region 702; forming a second doped region 703 in the substrate 700 on one side outside the annular first isolation structure, and the second doped region 703 surrounding the annular first isolation structure.

[0222] For a description of the first doped region 702 and the second doped region 703, please refer to the relevant content in the foregoing embodiments, and it will not be repeated here.

[0223] It should be noted that the type of the annular barrier layer structure 701 is a first isolation structure, that is, the semiconductor structure is a gateless device. When a high voltage is applied, compared with the scheme of the annular barrier layer structure being a gate structure, it is easier to reduce the probability of gate breakdown of the semiconductor structure. At the same time, in the process of forming the semiconductor structure, since there is no need to form a gate structure, the photomask can be reduced, thereby reducing the process cost.

[0224] In this embodiment, after forming the first doped region 702 and the second doped region 703, the method further includes: forming a second plug 709 located between the interconnect structure and the first doped region 702 and between the interconnect structure and the second doped region 703, respectively; after forming the second plug 709, forming an interconnect structure electrically connected to the first doped region 702 and the second doped region 703, respectively.

[0225] For a description of the interconnection structure and the second plug 709, please refer to the relevant content in the foregoing embodiments, and it will not be repeated here.

[0226] It should be noted that the semiconductor structure described in this embodiment can be formed using the formation method described in the foregoing embodiments, or it can be formed using other formation methods. For a detailed description of the formation method of the semiconductor structure described in this embodiment, please refer to the corresponding description in the foregoing embodiments. This embodiment will not repeat the description here.

[0227] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A ring-shaped barrier layer structure is located on or within the substrate; A first doped region is located in the substrate on one side of the inner side of the annular barrier layer structure, the annular barrier layer structure surrounding the first doped region, and the first doped region has a first type doped ion; The second doped region is located in the substrate on the outer side of the annular barrier layer structure. The second doped region surrounds the annular barrier layer structure and has a second type of doped ion, wherein the first type of doped ion and the second type of doped ion have different conductivity types.

2. The semiconductor structure as described in claim 1, characterized in that, The annular barrier layer structure includes: a gate structure located on the substrate, or an insulating barrier structure located on or in the substrate; The insulating barrier structure includes: a silicide barrier structure located on the substrate or a first isolation structure located in the substrate.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure includes an interconnect structure electrically connected to the first doped region and the second doped region, respectively.

4. The semiconductor structure as described in claim 3, characterized in that, The annular barrier layer structure is a gate structure, and the interconnect structure is electrically connected to the gate structure, the first doped region, and the second doped region, respectively.

5. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes a first plug located between the interconnect structure and the gate structure, wherein the first plug is located on the gate structure and electrically connected to the gate structure.

6. The semiconductor structure according to any one of claims 3 to 5, characterized in that, The semiconductor structure further includes: a second plug, located between the interconnect structure and the first doped region and between the interconnect structure and the second doped region, respectively. The second plug is located on the first doped region and the second doped region and is electrically connected to the first doped region and the second doped region, respectively.

7. The semiconductor structure as described in claim 6, characterized in that, Along a direction perpendicular to the normal to the substrate surface, the distance between the second plug and the adjacent annular barrier layer structure is 0.1 micrometers to 2 micrometers.

8. The semiconductor structure as described in claim 1, characterized in that, The substrate includes: a bottom semiconductor layer, an insulating material layer, and a top semiconductor layer; The semiconductor structure further includes: a well region located in the substrate, the well region having a first type doped ion or a second type doped ion, and the bottom of the well region being in contact with the top of the insulating material layer, or the bottom of the well region being located in the insulating material layer; The annular barrier layer structure is located on the substrate of the well region, or the annular barrier layer structure is located in the substrate of the well region; both the first doped region and the second doped region are located in the well region.

9. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a second isolation structure located in the substrate and surrounding the second doped region.

10. The semiconductor structure as described in claim 9, characterized in that, Along the normal direction of the top surface of the substrate, the thickness of the second isolation structure is 30 nanometers to 200 nanometers; Along the normal direction perpendicular to the top surface of the substrate, the width of the second isolation structure is greater than 0.1 micrometers.

11. The semiconductor structure as described in claim 9, characterized in that, Along a direction perpendicular to the normal to the substrate surface, the distance between the annular barrier layer structure and the adjacent second isolation structure is 0.3 micrometers to 2 micrometers.

12. The semiconductor structure as claimed in claim 1, characterized in that, Along a direction perpendicular to the normal to the substrate surface and perpendicular to the sidewall of the first doped region, the lateral dimension of the first doped region is 0.5 micrometers to 40 micrometers.

13. The semiconductor structure as claimed in claim 1, characterized in that, Along a direction perpendicular to the normal to the substrate surface, the width of the annular barrier layer structure is 0.2 micrometers to 2 micrometers.

14. The semiconductor structure as claimed in claim 1, characterized in that, Along the normal direction of the top surface of the substrate, the depth of the first doped region is 30 nanometers to 200 nanometers; Along the normal direction of the top surface of the substrate, the depth of the second doped region is 30 nanometers to 200 nanometers.

15. The semiconductor structure as claimed in claim 1, characterized in that, Along a direction perpendicular to the normal to the substrate surface, the outlines of the annular barrier layer structure, the first doped region, and the second doped region all include circles or polygons.

16. The semiconductor structure as claimed in claim 1, characterized in that, Along a direction perpendicular to the normal to the substrate surface, the outline shapes of the annular barrier layer structure, the first doped region, and the second doped region all include: rectangles or regular polygons.

17. The semiconductor structure as claimed in claim 1, characterized in that, The semiconductor structure further includes a metal silicide layer covering the top of the first doped region and the second doped region.

18. A method for forming a semiconductor structure, characterized in that, include: Provide a base; An annular barrier layer structure is formed on or in the substrate, and a first doped region and a second doped region are formed in the substrate at intervals, the second doped region surrounding the first doped region, and the barrier layer structure is located between the first doped region and the second doped region and surrounding the first doped region. The first doped region has a first type of doped ion, the second doped region has a second type of doped ion, and the first type of doped ion and the second type of doped ion have different conductivity types.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The step of forming the annular barrier layer structure includes: forming an annular gate structure on the substrate before forming the first doped region and the second doped region; The step of forming a first doped region and a second doped region spaced apart in the substrate includes: forming a first doped region in the substrate on one side inside the annular gate structure, and the annular gate structure surrounding the first doped region; forming a second doped region in the substrate on one side outside the annular gate structure, and the second doped region surrounding the annular gate structure. or, The step of forming the annular barrier layer structure includes: after forming the first doped region and the second doped region, forming an annular silicide barrier structure on a substrate between the first doped region and the second doped region, the annular silicide barrier structure surrounding the first doped region and the second doped region surrounding the annular silicide barrier structure. or, The step of forming the annular barrier layer structure includes: forming an annular first isolation structure in the substrate before forming the first doped region and the second doped region; The step of forming a first doped region and a second doped region spaced apart in the substrate includes: forming a first doped region in the substrate on one side inside the annular first isolation structure, with the annular first isolation structure surrounding the first doped region; and forming a second doped region in the substrate on one side outside the annular first isolation structure, with the second doped region surrounding the annular first isolation structure.

20. The method for forming a semiconductor structure as described in claim 18, characterized in that, The process for forming the second doped region includes an ion implantation process, the process parameters of which include: the implanted ions are N-type ions, the implantation energy ranges from 5 keV to 100 keV, and the implantation dose ranges from 1E14 atom / cm². 2 Up to 9E15atom / cm 2 ; The process for forming the first doped region includes an ion implantation process, the process parameters of which include: the implanted ions are p-type ions, the implantation energy ranges from 5 keV to 100 keV, and the implantation dose ranges from 1E14 atom / cm². 2 Up to 9E15atom / cm 2 .

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