Multi-power domain chip timing sequence adaptive test system and test method
By using a multi-power-domain chip timing adaptive testing system, multiple timing testing devices work in conjunction with the processor to solve the problems of deviation in timing parameter acquisition and low testing efficiency of GPU chips. This enables more efficient and accurate timing parameter detection and analysis, and forms a timing failure database.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-24
- Publication Date
- 2026-03-17
AI Technical Summary
Existing methods for obtaining timing parameters of GPU chips suffer from several problems: discrepancies between simulation and actual conditions, inaccurate reflection of normal operating conditions under test modes, and low efficiency and insufficient reliability of manual testing.
A multi-power-domain chip timing adaptive test system is adopted. Through the collaborative work of multiple timing test devices and the processor, a test plan is formulated, and the power-on sequence and rise delay of each power domain of the GPU chip are automatically controlled to perform comprehensive timing parameter detection and analysis.
It improves the efficiency and accuracy of timing tests for GPU chips, can more comprehensively reflect the timing parameters of chips in real-world application scenarios, forms a timing failure database, and improves the reliability of test results.
Smart Images
Figure CN121679293A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of chip testing, and more particularly, to a multi-power-domain chip timing adaptive testing system and method. BACKGROUND
[0002] GPU (Graphic Processing Unit) as a display core chip, contains internal memory, image display, PCIe and other high-speed interconnection interface, chip design in order to be able to compatible with multiple interfaces, often need to design multiple voltage domains, the timing control between each voltage domain is directly related to whether the chip can work normally.
[0003] At present, GPU chip timing control requirements according to the following three ways to confirm:
[0004] (1) GPU chip internal interface module if there is power-on timing requirements, in the back-end design stage through simulation method to simulate the timing parameters of the whole chip.
[0005] (2) GPU chip in test mode through the special test machine timing parameters.
[0006] (3) GPU chip in the application stage, through the hardware circuit to control the timing of different power domains, through the continuous adjustment of the timing control of the empirical value.
[0007] For the above implementation (1), GPU chip internal module is more, each module only has the timing requirements of the module itself, the back-end stage chip designers through simulation means to simulate the timing parameters of the whole chip, there is a difference with the actual timing parameters of the chip.
[0008] For the above implementation (2), the test mode of GPU chip internal only part of the module is in working condition, there is a big difference with the normal working mode, the timing parameters in the test mode can not be used as the basis for the normal working mode of the chip.
[0009] For the above implementation (3), timing adjustment needs to be verified by multiple test boards to determine the consistency of the results, the testing process needs to be adjusted and confirmed manually, which is very tedious, and the sample size is small, and the reliability is low.
[0010] The above-mentioned GPU chip timing determination method can obtain the timing parameters of the chip to some extent, but in order to further obtain the timing parameters of the chip more accurately, it is necessary to study a more accurate and efficient chip timing adaptive testing method. SUMMARY
[0011] This invention addresses the technical problems existing in the prior art by providing a multi-power domain chip timing adaptive testing system and method. It solves the problems of discrepancies between timing parameters obtained by simulation and actual conditions, the inability of timing parameters in test modes to accurately reflect the timing parameters under normal working conditions of GPU chips, and the low testing efficiency and reliability caused by relying on manual testing experience.
[0012] According to a first aspect of the present invention, a multi-power domain chip timing adaptive test system is provided, comprising multiple timing test devices and a processor, each timing test device being connected to a GPU chip, all GPU chips being of the same model, and each timing test device comprising a timing control module, a timing detection module and a result analysis module.
[0013] The timing control module is used to formulate a current test plan based on the current test status of this timing test device and other timing test devices under the same test; and based on the current test plan, output a first set of control signals to the enable ports of each power domain of the GPU chip to control the power-on sequence of each power domain, and output a second set of control signals to the rise delay selector of each power domain to control the rise delay of each power domain; it is also used to output a start test signal to the timing detection module for timing detection;
[0014] The timing detection module is used to detect the power-on time and rise delay of each power domain of the GPU chip under the current test scheme, and to determine whether the power-on time and rise delay of each power domain meet the conditions of the current test scheme, and to transmit the determination result to the result analysis module.
[0015] The result analysis module is used to detect whether the GPU chip can be recognized normally when the judgment result is yes; if yes, load stress test cases onto the GPU chip and obtain test results, and save the test results of the current test scheme; iterate through each test scheme and save the test results corresponding to all test schemes tested by this timing test device.
[0016] The processor is used to analyze the timing parameters of the GPU chip based on the test results of all test schemes tested by all timing test devices.
[0017] According to a second aspect of the present invention, a timing adaptive testing method for multi-power domain chips is provided, comprising:
[0018] Step 1: Develop the current test plan based on the test status of the current timing test device and other timing test devices;
[0019] Step 2: Based on the current test scheme, output the first set of control signals to the enable ports of each power domain of the GPU chip to control the power-on sequence of each power domain, and output the second set of control signals to the rise delay selector of each power domain to control the rise delay of each power domain, and output the start test signal to perform timing detection.
[0020] Step 3: Detect the power-on time and rise time of each power domain of the GPU chip under the current test scheme, and determine whether the power-on time and rise time of each power domain meet the conditions of the current test scheme, and obtain the judgment result;
[0021] Step 4: If the result is yes, check if the GPU chip can recognize it normally. If yes, load the stress test case into the GPU chip and obtain the test result, and save the test result of the current test plan.
[0022] Step 5: Iterate through each test plan and save the test results corresponding to all test plans;
[0023] Step 6: Analyze the timing parameters of the GPU chip based on the test results of all test schemes tested by all timing test devices.
[0024] This invention provides a timing adaptive testing system and method for multi-power-domain chips. The system formulates a testing scheme based on the testing status of this timing testing device and other timing testing devices used in the same test. Multiple timing testing devices are employed to simultaneously test the GPU chip, thereby improving the timing testing efficiency of multi-power-domain GPU chips. During testing, the system evaluates the power-on sequence and rise time of the multi-power-domain GPU chip, providing a more comprehensive analysis of the GPU chip's timing parameters. Furthermore, testing is conducted under the normal operating conditions of the GPU chip, more accurately reflecting the chip's timing parameters in real-world application scenarios. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the structure of a multi-power domain chip timing adaptive test system provided in one embodiment of the present invention;
[0026] Figure 2 A flowchart of a multi-power-domain chip timing adaptive testing method provided in one embodiment of the present invention;
[0027] Figure 3 This is an overall flowchart of a multi-power-domain chip timing adaptive testing method provided in one embodiment of the present invention;
[0028] Figure 4 Develop a flowchart for the test plan. Detailed Implementation
[0029] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. In addition, the technical features of the various embodiments or individual embodiments provided by the present invention can be arbitrarily combined with each other to form feasible technical solutions. Such combinations are not constrained by the order of steps and / or structural composition patterns, but must be based on the ability of those skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed by the present invention.
[0030] Existing research lacks studies on the power-on timing issues of multiple power supplies. Regarding methods for obtaining timing parameters of GPU chips, existing methods suffer from problems such as deviations between timing parameters obtained through simulation and actual conditions, inconsistencies between timing parameters obtained through test modes and normal chip operation modes, and low reliability of test results due to the small sample size of test boards.
[0031] Therefore, to address the discrepancies between GPU chip timing parameter testing methods and actual applications, as well as the low efficiency and unreliability of manual testing, a more accurate and efficient adaptive timing testing method is needed to obtain more accurate chip timing parameters and improve product stability during application.
[0032] Figure 1 This invention illustrates a multi-power-domain chip timing adaptive test system according to an embodiment of the present invention, such as... Figure 1 As shown, the test system includes multiple timing test devices and processors. Each timing test device is connected to a GPU chip. All GPU chips are of the same model. Each timing test device includes a timing control module, a timing detection module, and a result analysis module.
[0033] It is understood that the multi-power-domain chip timing adaptive test system in this embodiment of the invention includes multiple identical timing test devices, each connected to a GPU chip. Each timing test device connects the GPU chip to its own circuit board via a detachable metal fixture, and the timing test devices are connected to each other via a communication bus. The GPU chips connected to the multiple timing test devices are of the same model.
[0034] like Figure 1As shown, each timing test device includes a timing control module, a timing detection module, and a result analysis module. Its working principle is as follows:
[0035] The timing control module is used to determine whether the current test plan needs to be tested based on the test status of this timing test device and other timing test devices under the same test; and if the current test plan needs to be tested, based on the current test plan, outputting a first set of control signals to the enable ports of each power domain of the GPU chip to control the power-on sequence of each power domain, and outputting a second set of control signals to the rise delay selector of each power domain to control the rise delay of each power domain; it is also used to output a start test signal to the timing detection module for timing detection;
[0036] The timing detection module is used to detect the power-on time and rise delay of each power domain of the GPU chip under the current test scheme, and to determine whether the power-on time and rise delay of each power domain meet the requirements of the current test scheme, and to transmit the determination result to the result analysis module.
[0037] The result analysis module is used to detect whether the GPU chip can be recognized normally when the judgment result is yes. If it can be recognized normally, load stress test cases onto the GPU chip and obtain test results, and save the test results of the current test plan; iterates through each test plan and saves the test results corresponding to all test plans tested by this timing test device.
[0038] The processor is used to analyze the timing parameters of the GPU chip based on the test results of all test schemes tested by all timing test devices.
[0039] Each test scheme includes parameters such as the initial step size, step unit, number of steps, number of repetitions of a single test scheme, and pass rate of a single test scheme for each power domain.
[0040] The test modes include sequential mode and delay mode. In sequential mode, the rise delay selectors for each power domain use default settings, focusing on testing the power-on sequence of each power domain. In delay mode, the power-on sequence of each power domain uses default settings, focusing on testing the rise time of each power domain. During testing, the test mode starts by default in sequential mode. After all test schemes of all timing test devices are completed in sequential mode, the test mode transitions to delay mode.
[0041] During the testing of the current test scheme, when entering the power-on timing detection phase, the voltage comparator of the timing detection module captures the low-to-high level changes in voltage signals at the 10% and 90% voltage points of each power domain. Simultaneously, the internal timer of the timing detection module records the time at the 10% and 90% voltage change points of each power domain. This allows for the acquisition of the power-on time and rise delay of each power domain, determining whether the power-on time and rise delay of each power domain meet the requirements of the current test scheme.
[0042] The results analysis module detects whether the GPU chip can be recognized normally, runs stress test cases to ensure that the internal modules of the GPU chip work properly, determines whether the GPU chip is functioning correctly, then closes the stress test cases, calculates and updates the success rate and number of repetitions for the current test plan, and records the test results. The stress test cases include PCIe link testing, DDR read / write testing, firmware consistency testing, video decoding testing, 2D testing, and 3D testing, which can quickly evaluate whether the GPU chip modules are functioning correctly and output test results.
[0043] The above describes the testing method for all test schemes on a timing test setup, obtaining the test results for all test schemes. After all timing test setups have completed testing all test schemes, the processor summarizes the test results obtained from all timing test setups for all test schemes. By analyzing these test results, the timing parameters of the GPU chip are obtained.
[0044] See Figure 2 This illustration shows a timing adaptive testing method for multi-power domain chips according to an embodiment of the present invention, applied in a timing adaptive testing system for multi-power domain chips. See also... Figure 2 and Figure 3 As shown, the test method includes the following steps:
[0045] Step 1: Determine whether the current test plan needs to be tested based on the test status of this timing test device and other timing test devices being tested.
[0046] Understandably, firstly, the total number of test schemes for the GPU chip is generated, and the system enters the initialization state S0 to obtain the default test scheme parameters, including the test mode selection, the limit of the number of steps for each power domain, the starting number of steps and the step unit, the number of repeated tests for the test scheme and the success rate of the scheme, the total number of timing test devices, and the default test scheme parameters are synchronously sent to all other timing test devices. After receiving the test start signal, the system enters state S1: formulate the test scheme and execute the power-on control.
[0047] In embodiments of the present invention, the test modes are divided into sequential mode and delay mode. In sequential mode, the rise delay selectors of each power domain are set to default settings, and the focus is on testing the power-on sequence of each power domain; in delay mode, the power-on sequence of each power domain is set to default settings, and the focus is on testing the rise time of each power domain. The test mode defaults to starting with sequential mode. After all test schemes of all timing test devices are completed in sequential mode, the test mode is entered.
[0048] See Figure 4 In state S1, the current test plan is obtained sequentially. It is determined whether the current test plan is the first test plan. If it is, the power-on enable time and rise delay selector configuration of each power domain are calculated according to the default test parameters to control the power-on of the GPU chip. If the current test plan is not the first test plan, it is determined whether to execute the current test plan based on the test status of this timing test device and other timing test devices.
[0049] In one embodiment of the present invention, step 1, determining whether the current test plan needs to be executed based on the test status of the timing test device and other timing test devices undergoing simultaneous testing, includes:
[0050] Step 11: This timing test device queries the test results of other timing test devices for the current test scheme. Other timing test devices that have tested the current test scheme act as judges and vote on the current test scheme.
[0051] Step 12: If the number of votes and the approval rate reach the set value, proceed to step 13; otherwise, proceed to step 14.
[0052] Step 13: This timing test device checks whether the number of power-on failures in the current test plan has not exceeded the set value, and checks whether the success rate of repeated tests calculated before the number of repeated tests in the current test plan reaches the set value has met the set requirements. If the number of power-on failures has not exceeded the set value and the success rate of repeated tests has met the set requirements, it is determined that the current test plan needs to be executed, and proceeds to step 14; otherwise, proceeds to step 15.
[0053] Step 15: Proceed to the next test plan and return to Step 11 to evaluate the next test plan.
[0054] Step 2: Under the current test plan, based on the current test plan, output the first set of control signals to the enable ports of each power domain of the GPU chip to control the power-on sequence of each power domain, and output the second set of control signals to the rise delay selector of each power domain to control the rise delay of each power domain, and output the start test signal to perform timing detection.
[0055] Understandably, when the current test plan needs to be executed as determined through steps 11-15 above, the corresponding test parameters are configured according to the current test plan. These test parameters include the initial step size, step unit, number of steps, number of repetitions of a single test plan, pass rate of a single test plan, and test mode for each power domain. Based on the test parameters and test mode of the current test plan, the enable time and delay selector configuration for each power domain are calculated, generating the first set of control signals and the second set of control signals to power on the GPU chip.
[0056] As mentioned above, the GPU chip's testing modes include sequential mode and latency mode. In sequential mode, based on the test parameters and test mode, the enable time and latency selector configuration for each power domain are calculated, generating the first set of control signals and the second set of control signals to control the GPU chip's power-on, including:
[0057] In sequential mode, each power domain uses the same timer as a reference for timing calculation to ensure consistency of timing control. The reference time is 1ms, and the step unit is an integer multiple of the reference time. The power-on enable time of each power domain is controlled by a timer counting method. The timer is started when the test plan is determined, and the counting method is as follows:
[0058] Power domain enable timer count = (starting step count + current step count) × step unit / reference time
[0059] When the timer counts reach the demand of each power domain, the first set of control signals is output to enable each power domain to power on and stop the timer. At the same time, the second set of control signals is output according to the default parameters of the rise delay selector to control the rise time of each power domain.
[0060] In this embodiment, in delay mode, each power domain configures a rise delay selector based on the current step count. The rise delay selector consists of a multi-stage parallel capacitor array. By selecting the number of parallel capacitors, the voltage rise time of each power domain is changed. Specifically, the number of capacitors selected by the rise delay selector is the current step count. After configuring the rise delay selector, the first set of control signals is output in the default power-on sequence to enable each power domain to power on, and the second set of signals is output to control the rise time of each power domain.
[0061] It should be noted that during the timing test of the GPU chip, for both sequential and latency modes, in sequential mode, all timing test devices complete all test schemes. Then, the pass rate of all test schemes for each test scheme is obtained. The test scheme with the highest pass rate is used as the default configuration for the power-on enable time of each power domain in latency mode. If the pass rates are the same, the test scheme with the smallest total number of steps for each power domain is selected as the default configuration for the power-on enable time of each power domain in latency mode. Then, the latency test mode is entered, and all test schemes are traversed.
[0062] Step 3: Detect the power-on time and rise time of each power domain of the GPU chip under the current test scheme, and determine whether the power-on time and rise time of each power domain meet the conditions of the current test scheme, and obtain the judgment result.
[0063] Understandably, based on the test parameters and test mode of the current test scheme, the power-on enable time and rise delay selector configuration of the current test scheme are calculated, and then the GPU chip is powered on.
[0064] In state S2, during the process of controlling the GPU to power on, the power-on time and rise delay of each power domain of the GPU chip are obtained. In this embodiment of the invention, the power-on time and rise delay are compared with the starting time based on the time points captured at the 10% and 90% voltage points of each power domain. The power-on time and rise delay are calculated to see if they meet the requirements of the current test scheme. If they do, the process proceeds to state S3; otherwise, it proceeds to state S1 to judge and test the next test scheme.
[0065] Step 4: If the judgment result is yes, check whether the GPU chip can recognize it normally. If it can recognize it normally, load the stress test case onto the GPU chip and obtain the test result, and save the test result of the current test plan.
[0066] Understandably, if the power-on time and rise time of each power domain of the GPU meet the requirements of the current test scheme, then in state S3, it is checked whether the GPU chip can be recognized normally. If it can be recognized normally, then it goes to state S4; otherwise, it goes to state S1.
[0067] In state S4, load stress test cases onto the GPU chip and obtain test results. If the test results are normal, proceed to state S5; otherwise, proceed to state S1.
[0068] In state S5, update and save the test results of the current test plan.
[0069] Step 5: Iterate through each test plan and save the test results corresponding to all test plans.
[0070] The timing test device judges and tests all test schemes in sequence to confirm whether all test schemes have been tested, until the timing test device has completed testing all test schemes.
[0071] In the final state S6, all test schemes of this timing test device are completed, the test scheme results are reported, and the device enters the initial state S0.
[0072] Step 6: Analyze the timing parameters of the GPU chip based on the test results of all test schemes tested by all timing test devices.
[0073] Each timing test unit's test report includes data such as step data for each test scheme, number of repeated tests, success rate of repeated tests, and reasons for test failures. After all timing test units have completed testing, the data is summarized and analyzed to determine the timing parameters of the GPU chip. The test failure results under different power-on sequences can further provide feedback on the impact of timing parameters on chip operation, forming a timing failure database. Once all units in the system have completed testing, the GPU chip is disassembled to replace the test sample, and multiple samples are tested to improve test reliability.
[0074] The timing adaptive testing system and method for multi-power domain chips provided in this invention have the following advantages compared with existing technical solutions:
[0075] (1) The present invention combines the test data of the same timing test device to determine the test scheme of each timing test device, which can greatly improve the timing test efficiency of multi-power GPU chips;
[0076] (2) The present invention evaluates the timing parameters of multi-power GPU chips in terms of power-on sequence and rise delay, and conducts tests in sequential mode and delay mode respectively, providing a more comprehensive analysis of the chip's timing parameters.
[0077] (3) The present invention is tested under the normal working condition of the GPU chip, which more accurately reflects the timing parameters of the chip in actual application scenarios. At the same time, the test failure results can form a timing failure fault library.
[0078] (4) The present invention uses automatic generation of timing test schemes, automatic completion of test process and automatic summarization of test results, which is more efficient.
[0079] It should be noted that the descriptions of each embodiment in the above embodiments have different focuses. For parts that are not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.
[0080] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.
[0081] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0082] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0083] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0084] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.
[0085] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.
Claims
1. A multi-power domain chip timing adaptive test system, characterized in that, The application comprises a plurality of same timing test devices and a processor, each of the timing test devices is connected with a GPU chip, all the GPU chips are of the same model, each of the timing test devices comprises a timing control module, a timing detection module and a result analysis module; The timing control module is configured to determine whether a current test scheme satisfies an execution condition according to a test state of the timing test device and other timing test devices; and in the case that the current test scheme satisfies the execution condition, output a first group of control signals to act on enable ports of each power domain of the GPU chip to control a power-on sequence of each power domain, and output a second group of control signals to act on rising delay selectors of each power domain to control rising delays of each power domain; and output a start test signal to the timing detection module for timing detection; The timing detection module is configured to detect power-on times and rising delays of each power domain of the GPU chip under the current test scheme, and determine whether the power-on times and the rising delays of each power domain satisfy requirements of the current test scheme, and transmit a determination result to the result analysis module; The result analysis module is configured to, in the case that the determination result is yes, detect whether the GPU chip can be normally recognized, if yes, load a stress test case to the GPU chip and obtain a test result, and save the test result of the current test scheme; Each test scheme is traversed, and test results corresponding to all test schemes tested by the timing test device are saved; The processor is configured to analyze timing parameters of the GPU chip according to the test results of all test schemes tested by all timing test devices.
2. A multi-power domain chip timing adaptive test method applied in the multi-power domain chip timing adaptive test system of claim 1, characterized in that, The method comprises: Step 1, determining whether a current test scheme satisfies an execution condition according to a test state of the timing test device and other timing test devices; Step 2, if the execution condition is satisfied, outputting a first group of control signals to act on enable ports of each power domain of the GPU chip to control a power-on sequence of each power domain, and outputting a second group of control signals to act on rising delay selectors of each power domain to control rising delays of each power domain, and outputting a start test signal for timing detection; Step 3, detecting power-on times and rising delays of each power domain of the GPU chip under the current test scheme, and determining whether the power-on times and the rising delays of each power domain satisfy conditions of the current test scheme, to obtain a determination result; Step 4, in the case that the determination result is yes, detecting whether the GPU chip can be normally recognized, if yes, loading a stress test case to the GPU chip and obtaining a test result, and saving the test result of the current test scheme; Step 5, traversing each test scheme, and saving test results corresponding to all test schemes tested by the timing test device; Step 6, analyzing timing parameters of the GPU chip according to the test results of all test schemes tested by all timing test devices.
3. The multi-power domain chip timing adaptive test method of claim 2, wherein, The step 1 comprises: Step 11, the timing test device queries the test result of the current test scheme from other timing test devices, and other timing test devices that have tested the current test scheme vote for the test scheme as a judge; Step 12, when the number of votes and the approval rate reach the set value, enter step 13, otherwise, enter step 14; Step 13, the timing test device queries whether the power-on process failure number of the current test scheme does not exceed the set value, and queries whether the repeated test success rate calculated before the repeated test number of the current test scheme reaches the set value reaches the set requirement, when the power-on process failure number does not exceed the set value, and the repeated test success rate reaches the set requirement, the current test scheme meets the execution condition, otherwise, enter step 14; Step 14, enter the next test scheme and return to step 11.
4. The multi-power-domain chip timing adaptive test method according to claim 2 or 3, characterized in that, The step 2, based on the current test scheme, outputs the first group of control signals to act on the enable ports of each power domain of the GPU chip to control the power-on sequence of each power domain, and outputs the second group of control signals to act on the rising time delay selector of each power domain to control the rising time delay of each power domain, and outputs the start test signal for timing detection, comprising: Based on the current test scheme, configure corresponding test parameters, the test parameters including the starting step number, step unit, step number, repeated test number of single test scheme, single test scheme pass rate and test mode of each power domain; Based on the test parameters and the test mode, calculate the power-on enable time and the delay selector configuration of each power domain, generate the first group of control signals and the second group of control signals, and control the power-on of the GPU chip.
5. The multi-power domain chip timing adaptive test method of claim 4, wherein, The test mode includes a sequence mode and a delay mode; based on the test parameters and the test mode, calculate the power-on enable time and the rising time delay selector configuration of each power domain, generate the first group of control signals and the second group of control signals, and control the power-on of the GPU chip, comprising: In the sequence mode, the rising time delay selector of each power domain adopts the default configuration, and the power-on enable time of each power domain is calculated according to the test parameters; In the delay mode, the power-on enable time of each power domain adopts the default configuration, and the rising time delay of each power domain is calculated according to the test parameters; In different modes, the first group of control signals and the second group of control signals are generated according to the enable time and the rising time delay selector configuration of each power domain, and the power-on of the GPU chip is controlled.
6. The multi-power domain chip timing adaptive test method of claim 5, wherein, In the sequence mode, the power-on enable time of each power domain is calculated according to the test parameters, comprising: Each power domain takes a same timer as a reference for time calculation, the step unit is an integer multiple of the reference time, the power-on enable time of each power domain is controlled in a timer counting mode, and the timer counting mode is as follows: Power domain enable timer count = (starting step number + current step number) × step unit / reference time; The in different modes, the first group of control signals and the second group of control signals are generated according to the power-on enable time and the delay selector configuration of each power domain, and the power-on of the GPU chip is controlled, comprising: When the timer counts to the respective power domain requirements, the first group of control signals is output to enable the respective power domains to power on and stop timing, and the second group of control signals is output according to the default parameters of the rising delay selector to control the rising delay of the respective power domains.
7. The multiple power domain chip timing adaptive test method of claim 5, wherein, In the delay mode, the rising delay of each power domain is calculated according to the test parameters, including: In the delay mode, each power domain configures the rising delay selector through the current step number, wherein the rising delay selector includes a plurality of parallel capacitor arrays, and the number of capacitor arrays of the rising delay selector is the current step number; After the configuration of the rising delay selector is completed, the first group of control signals is output in the default power-on sequence to enable each power domain to power on, and the second group of signals is output to control the rising time of each power domain.
8. The multiple power domain chip timing adaptive test method of claim 1, wherein, The step 3 includes: According to the power-on time of each power domain, the GPU chip is powered on, and when entering the power-on sequence detection, the voltage comparator captures the rising change signal from low level to high level of each power domain at 10% and 90% voltage points; At the same time, the internal timer records the time at the 10% and 90% change points of each power domain to obtain the rising delay.
9. The multiple power domain chip timing adaptive test method of claim 1, wherein, The step 4 includes: If the judgment result is yes, the GPU chip is detected whether it can be normally recognized, if yes, the stress test case is loaded to the GPU chip to obtain the test result, and the test result of the current test scheme is saved, including: The GPU chip is detected whether it can be normally recognized, if yes, the stress test case is run to make each module of the GPU chip work normally; 10. The multiple power domain chip timing adaptive test method of claim 9, wherein, The GPU chip is judged whether it works normally, if yes, the stress test case is closed, the success rate and the repeated test number of the current test scheme are calculated and updated, and the test result of the current test scheme is recorded. The stress test case includes PCIE link test, DDR read-write test, firmware consistency test, video decoding test, 2D test and 3D test.