A Reinforcement Learning-Based Topology Optimization Method for High-Temperature Driver Circuits

Abstract

This invention discloses a high-temperature resistant drive circuit topology optimization method based on reinforcement learning, belonging to the field of intelligent optimization control technology for power electronics. The method includes the following steps: In the drive circuit topology optimization stage, temperature change data, signal delay data, and command timing data of the drive circuit during operation are synchronously collected. Based on the collected data, a time distribution diagram of the topology switching process is reconstructed. Time segments with thermal mismatch characteristics in the time distribution diagram are analyzed, and a potential conflict information table is generated. This invention achieves adaptive rhythm reconstruction of the drive circuit under high temperatures by synchronously collecting temperature, signal delay, and command timing data, combined with time isolation and thermal disturbance protection mechanisms. This prevents command overlap and instantaneous short circuits, maintaining stable operation. Furthermore, through the coordinated adjustment of a reverse silent window and temperature compensation pulses, the safety, thermal stability, and reliability of the drive circuit under high-temperature environments are improved.

Description

Technical Field

[0001] This invention relates to the field of intelligent optimization control technology in power electronics, specifically to a method for optimizing the topology of high-temperature driving circuits based on reinforcement learning. Background Technology

[0002] Topology optimization of high-temperature resistant drive circuits based on reinforcement learning refers to the process of intelligently evolving and adaptively adjusting the topology of drive circuits under high-temperature operating conditions using reinforcement learning mechanisms. By establishing performance response models of the drive circuit under different temperatures, loads, and material parameters, and using indicators such as conduction loss, thermal stability, electromagnetic compatibility, and power density as reward signals for reinforcement learning, the drive agent continuously tries different topology connection methods and device configuration schemes in simulation or experimental environments. Through multiple rounds of interactive learning, the algorithm gradually identifies the optimal circuit topology combination under high-temperature stress, achieving coordinated optimization of the drive path, energy flow distribution, and heat dissipation structure, thereby obtaining a high-efficiency and highly reliable high-temperature resistant drive circuit design scheme.

[0003] The existing technology has the following shortcomings:

[0004] In existing technologies, during the topology optimization process of reinforcement learning-based driver circuits, the topology reconstruction stage often relies on multi-threaded parallel instruction execution to achieve rapid switching. However, when the circuit operates at high temperatures, thermal disturbances can cause signal sampling delays and control feedback misalignments, leading to contention and conflicts in the multi-threaded scheduling of the reinforcement learning control logic, which can easily result in overlapping control signal writes. At this point, topology switching commands may overlap within the execution buffer, and turn-on and turn-off instructions that should be executed sequentially may be triggered simultaneously, potentially causing adjacent power devices to conduct simultaneously under high voltage differentials, resulting in a momentary short circuit. Once this problem occurs, it can not only cause energy backflow into the drive path but also potentially burn out power devices and trigger system-level thermal instability, severely impacting the reliability and safety of the driver circuit under high-temperature conditions.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide a topology optimization method for high-temperature resistant driving circuits based on reinforcement learning, so as to solve the problems in the background art mentioned above.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a high-temperature resistant driving circuit topology optimization method based on reinforcement learning, comprising the following steps:

[0008] During the topology optimization stage of the drive circuit, temperature change data, signal delay data and command timing data of the drive circuit during operation are collected synchronously. Based on the collected data, the time distribution diagram of the topology switching process is reconstructed, the time segments with thermal mismatch characteristics in the time distribution diagram are analyzed, and a potential conflict information table containing the time segment is generated.

[0009] The timing sequence, signal response offset, and feedback lag of each switch action in the drive circuit are analyzed point by point using the potential conflict information table. Based on the analysis results, the trigger time of instruction overlap is determined, the running segments with instruction overlap are sorted out, and an overlap feature list containing abnormal response segments is output.

[0010] Based on the overlapping feature list, the operation trajectory of the driving circuit during the temperature surge stage is traced back. The starting position of the repeated write instruction and the source of competition for multi-threaded instructions are identified. Based on the identification results, the instruction execution interval boundary is extracted, and a time isolation scheme for separating competing threads is generated.

[0011] The execution order of the drive circuit control instructions is adjusted according to the time isolation scheme, and a duty-free area and a delay buffer are set. A unified execution timing is established according to the adjusted instruction execution order to generate a thermal disturbance protection instruction set that adapts to high temperature disturbance conditions.

[0012] Based on the thermal disturbance protection instruction set, the drive circuit is adjusted in real time. During the high temperature fluctuation stage, a reverse silence window is inserted, a rhythm yielding interval is set and a temperature drift compensation pulse is injected. The topology switching rhythm is continuously adjusted to prevent the risk of instantaneous short circuit during high temperature operation and maintain stable operation of the drive process.

[0013] Preferably, the steps for generating the potential conflict information table are as follows:

[0014] During the topology optimization stage of the drive circuit, temperature change data, signal delay data and command timing data of the drive circuit during operation are collected in a unified manner, and drive signals, sampling signals and control signals are recorded on the same time base through parallel sampling.

[0015] Based on the collected temperature change data, signal delay data, and command timing data, the topology switching events are arranged in chronological order using time index as the main line to generate a time distribution map that includes command actions, temperature changes, and signal delays.

[0016] Based on the time distribution diagram, analyze the combination relationship between the temperature change rate, signal delay change amplitude and instruction interval in each time segment to extract the risk segments that simultaneously have temperature surge, response lag and execution compression.

[0017] Based on the risk segment information, the start time, end time, temperature change rate, signal delay amplitude, and command trigger interval are recorded to generate a potential conflict information table containing all potential conflict intervals, providing a time reference basis for subsequent topology switching overlap analysis.

[0018] Preferably, the steps for outputting the overlapping feature list are as follows:

[0019] Based on the generated potential conflict information table, each potential conflict event is read and analyzed. The time dependency relationship of the drive circuit switching action is established with time as the main line, forming an action time sequence that includes the on and off states of each power switch unit.

[0020] Based on the action time series, the signal response offset corresponding to each switch action is analyzed. By aligning the action time series with the signal delay data in the potential conflict information table, action segments with response extension or compression are identified and offset mapping is formed.

[0021] Based on the correlation analysis of the feedback lag data in the offset mapping and potential conflict information table, extract the instruction overlap trigger time when the lag interval overlaps and generate an overlap event list.

[0022] Based on the list of overlapping events, the running segments with overlapping instructions are organized, and the number of instructions, duration, response offset direction and lag degree are recorded. The list of overlapping features containing the segments with abnormal responses is output.

[0023] Preferably, during the process of generating the list of overlapping features, the temperature change curves, signal delay curves, and action time curves of each abnormal response segment are compared and analyzed. Multiple command overlap phenomena within the same temperature segment are aggregated and processed. The abnormal response segments are sorted according to the heat load intensity, and the timing distribution correlation of the drive circuit in the high-temperature disturbance stage is established.

[0024] Preferably, the steps for generating the time isolation scheme are as follows:

[0025] Based on the resulting list of overlapping features, the abnormal response segments recorded therein are traced back, and the time information is matched with the temperature change curve of the drive circuit under high temperature operation to construct the operating trajectory of the temperature surge stage and form a continuous time series.

[0026] Based on the running trajectory, the execution sequence of control commands during the temperature surge phase is analyzed retrospectively to identify the starting position of the repeatedly written commands, record the temperature value and delay amplitude corresponding to the starting position, and form the command timing distribution.

[0027] Based on the instruction timing distribution, the sources of competition for multi-threaded instructions are analyzed and classified, and the threads triggered within the same time period are arranged in chronological order to form a competition thread distribution table;

[0028] Based on the distribution table of competing threads, the instruction execution interval boundary is extracted, non-overlapping time partitions are divided, and a time isolation scheme is generated so that each thread can complete instruction processing within an independent execution time period.

[0029] Preferably, during the generation of the time isolation scheme, the execution gap of competing threads is dynamically adjusted according to the time window of the temperature surge phase. By combining the temperature change rate and feedback delay characteristics to expand or shrink the time interval between threads, the control threads of the drive circuit remain time-independent under high temperature fluctuation conditions and prevent execution overlap.

[0030] Preferably, the steps for generating the thermal disturbance protection instruction set are as follows:

[0031] Based on the thread execution interval boundary defined in the time isolation scheme, the execution order of the drive circuit control instructions is adjusted, the original instruction stream is rearranged according to the time sequence, and a basic execution framework is formed by matching the temperature range and feedback lag characteristics.

[0032] The duty and yield zone is set according to the adjusted instruction execution order, and time intervals are inserted between adjacent control instructions to absorb signal propagation delays and maintain sequential execution.

[0033] The instruction execution path is delayed based on the duty and yield area, and a delay buffer is set to absorb the accumulated instruction delay caused by high temperature fluctuations, so that the control timing has the ability to resist disturbances.

[0034] Based on the adjusted instruction execution order and the set duty and delay buffer, a unified execution sequence is established to generate a thermal disturbance protection instruction set that includes the trigger time, execution duration, and temperature range.

[0035] Preferably, the thermal disturbance protection instruction set dynamically adjusts the time length of the duty-free zone and the delay buffer according to the temperature change rate during the operation of the drive circuit. When the temperature rises, the execution interval is extended to prevent instruction overlap, and when the temperature drops, the interval is compressed to improve the control response speed, thereby maintaining the continuity and stability of the topology switching rhythm during the high temperature fluctuation stage.

[0036] Preferably, the following steps are taken to continuously adjust the topology switching rhythm by adjusting the drive circuit in real time according to the thermal disturbance protection instruction set, inserting a reverse silence window during high temperature fluctuations, setting a rhythm yielding interval, and injecting temperature drift compensation pulses:

[0037] The control rhythm of the drive circuit is adjusted in real time according to the thermal disturbance protection instruction set. By reallocating the trigger time and execution duration of the control instructions, the topology switching action is coordinated with the temperature fluctuation trend.

[0038] Based on the operating status of the protection instruction set, a reverse silence window is inserted during the high temperature fluctuation phase. By suspending some conduction instructions, an intermittent operating path is formed to reduce the concentrated release of heat power.

[0039] Based on the insertion results of the reverse silent window, a rhythm yielding interval is set. At the end of the silent window, the execution priority is divided and a time yielding interval is formed to maintain the independence of multi-channel execution.

[0040] Temperature drift compensation pulses are injected according to the rhythmic yielding interval. By continuously adjusting the topology switching rhythm during the driving cycle, the junction temperature change of the conducting device is balanced, and stable operation of the driving process is achieved.

[0041] Preferably, the duration of the reverse silence window is dynamically matched according to the rate of temperature change and the degree of signal delay, the duration of the rhythm yielding interval is synchronously adjusted according to the delay buffer parameter, and the injection timing of the temperature drift compensation pulse is consistent with the boundary of the rhythm yielding interval, so as to ensure that the triggering and feedback process of the control command during the high temperature fluctuation stage remains synchronized in time and stable in rhythm.

[0042] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0043] This invention synchronously acquires temperature change data, signal delay data, and instruction timing data during the operation of the drive circuit. Combined with a time isolation scheme and dynamic adjustment of the thermal disturbance protection instruction set, the drive circuit can proactively identify and separate the competing relationships of multi-threaded instructions in high-temperature environments, thereby achieving adaptive reconfiguration of the instruction execution order. This technique effectively avoids overlapping execution of turn-on and turn-off instructions during topology switching, preventing instantaneous short circuits and energy backflow, ensuring continuous, controllable, and stable operation of the drive process under high-temperature stress, and improving overall operational safety and thermal stability.

[0044] This invention achieves real-time self-adjustment of the topology switching rhythm in response to temperature changes by inserting a reverse quiescent window and injecting temperature drift compensation pulses during high-temperature fluctuations. This method enables the control rhythm to form a dynamic yielding and delay buffering mechanism under thermal disturbance conditions, ensuring the continuous and effective time isolation between switching signals and reducing the impact of feedback misalignment caused by thermal mismatch on the control logic. Through the synergistic effect of continuous rhythm rearrangement and compensation pulses, the drive circuit maintains high efficiency and stable power output under high-temperature conditions, improving the system's reliability and resistance to thermal disturbances. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0046] Figure 1 This is a flowchart of the method for optimizing the topology of a high-temperature driving circuit based on reinforcement learning, as described in this invention. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0048] This invention provides, for example Figure 1 The high-temperature driving circuit topology optimization method based on reinforcement learning shown includes the following steps:

[0049] During the topology optimization stage of the drive circuit, temperature change data, signal delay data and command timing data of the drive circuit during operation are collected synchronously. Based on the collected data, the time distribution diagram of the topology switching process is reconstructed, the time segments with thermal mismatch characteristics in the time distribution diagram are analyzed, and a potential conflict information table containing the time segment is generated.

[0050] In order to accurately reconstruct the time distribution of the drive circuit topology switching process and ensure the simultaneous capture of full information on temperature changes, signal delays, and command timing under high-temperature conditions, so as to ensure the continuity and correlation of subsequent risk segment identification, the specific implementation steps are as follows:

[0051] Real-time temperature change data, signal delay data, and command timing data of the drive circuit at different operating stages are uniformly collected. During the acquisition process, the drive circuit operates under high-temperature dynamic conditions, and the drive signal, sampling signal, and switching control signal are all synchronously recorded at fixed time intervals. To ensure data time consistency, the temperature signal sampling channel, current and voltage detection channel, and control command triggering channel are sampled in parallel under the same time base. Time base control ensures that the three types of data have a one-to-one correspondence at the same time. Temperature change data is used to reflect the continuous changes in the junction temperature of the drive circuit, the heat conduction channel, and the ambient temperature; signal delay data is used to reflect the response lag of the control signal during propagation and execution; command timing data is used to record the entire process from the issuance of the control command to the completion of the action. All acquired data form a continuous sequence in the time dimension and correspond spatially to specific drive devices, power switching units, and their operating cycles, thereby achieving three-dimensional synchronous acquisition of temperature, signal, and timing, laying a complete data foundation for subsequent topology switching and reconstruction.

[0052] Based on the collected temperature change data, signal delay data, and command timing data, the topology switching process of the drive circuit is reconstructed in terms of time. In this process, the time index of the collected data is used as the main thread, and each topology switching event is arranged in chronological order. By comparing the time intervals between sampling points, the signal delay trend, and the command triggering sequence segment by segment, a continuous time distribution map can be generated. This time distribution map uses time as the horizontal axis and command actions, temperature changes, and signal response delays as vertical correlation elements, forming a dynamic mapping structure reflecting the entire topology switching process. By comparing the intersection segments of the temperature rise rate and signal response delay in the time distribution map, the specific time nodes that cause control signal feedback offset under thermal stress can be identified. Simultaneously, by marking the execution sequence of each command and the time difference between adjacent actions, preliminary signs of control overlap that may occur during high-temperature operation can be identified, thus establishing the global time evolution trajectory of the topology switching process. This time distribution map can fully display the dynamic timing relationship of the circuit under high-temperature conditions, providing a clear basis for identifying thermal mismatch characteristics.

[0053] After constructing the time distribution map, each time segment within the map is analyzed segment by segment to extract risk segments exhibiting thermal mismatch characteristics. Risk segments are identified based on abnormal combinations of temperature change rate, signal delay variation amplitude, and instruction execution interval. Specifically, by comparing the gradient changes in temperature curves with the signal delay variation trend over consecutive time periods, segments exhibiting rapid temperature changes and sudden increases in signal delay can be identified. Combined with the degree of compression between adjacent instruction intervals in the instruction timing data, potential command overlap intervals can be determined. At this point, the temperature, signal delay, and instruction timing sequence are time-aligned, and segments simultaneously satisfying temperature surges, response lags, and execution interval compression are extracted as risk segments exhibiting thermal mismatch characteristics. Each risk segment corresponds to high-temperature disturbance behavior occurring during one or more topology switching processes, reflecting time offsets caused by thermal coupling effects and multi-threaded scheduling differences in the drive circuit. By labeling and classifying these risk segments on the time axis, the duration, occurrence sequence, and corresponding control instruction sequences of each type of risk can be clearly defined, thus forming a complete risk distribution map.

[0054] Based on the extracted risk segment information, a potential conflict information table containing all potential conflict intervals under high-temperature operation is generated. During generation, the start time, end time, temperature change rate, signal delay amplitude, and command trigger interval of each risk segment are sequentially entered into the information table. Each risk segment is also appended with a corresponding topology switching number and control channel identifier, ensuring that the potential conflict information table not only includes time and temperature characteristics but also operational relationships corresponding to specific topology events. Each record in the information table represents a potential conflict event, including its occurrence conditions, time span, and corresponding signal delay status. To ensure continuity in subsequent analysis, the time intervals between each risk segment are supplemented in the information table, ensuring the time series of the entire driving process remains closed. After processing, the potential conflict information table can serve as input for subsequent overlap analysis and time isolation design. It can track the response characteristics of each topology switch under high-temperature influence, clarify the impact range of thermal disturbances on timing execution accuracy, and provide a complete time reference basis for subsequent overlap feature extraction and execution order adjustment.

[0055] The timing sequence, signal response offset, and feedback lag of each switch action in the drive circuit are analyzed point by point using the potential conflict information table. Based on the analysis results, the trigger time of instruction overlap is determined, the running segments with instruction overlap are sorted out, and an overlap feature list containing abnormal response segments is output.

[0056] To accurately utilize the potential conflict information table and comprehensively analyze the timing sequence, signal response offset, and feedback lag of each switch action in the drive circuit under high-temperature operation, so that overlapping trigger moments in the control timing can be accurately identified, and operating segments with abnormal response characteristics are organized and classified to form an overlapping feature list that can be used in subsequent steps, the specific implementation steps are as follows:

[0057] Based on the generated potential conflict information table, each potential conflict event recorded within it is sequentially read and parsed. The potential conflict information table contains information such as the temperature change range during high-temperature operation, signal delay amplitude, command execution interval, and topology switching time nodes. During the analysis, time is the primary focus, with the start and end times of each conflict event serving as segment boundaries to reconstruct the switching sequence of the drive circuit within that time interval. By comprehensively comparing the command trigger time, current conduction path changes, and temperature change rates, the time dependencies between each switching action are established, forming a complete action time sequence. This time sequence reflects the on-state, off-state, and switching intervals of each power switching unit during topology switching. At this point, combined with the delay data and feedback response data in the potential conflict information table, it can be determined whether the command execution sequence of different control channels has been misaligned within the same time period, providing a basic timing comparison for subsequent response offset analysis.

[0058] After obtaining the time sequence of each switch action, the signal response offset corresponding to each action is analyzed item by item. Signal response offset refers to the time lag between the issuance of the control command and the actual change in current or voltage. To ensure the continuity of the analysis process, the action time sequence formed in the previous sub-step is time-aligned with the signal delay data in the potential conflict information table. The signal response time corresponding to each switch action is compared, and the response time offset is calculated. By comparing the response offset trends between adjacent actions, it is possible to identify situations where the signal response is extended or compressed during periods of drastic temperature changes or sudden current surges. When a continuous response time offset is found, it indicates that the execution rhythm of the control signal is affected by thermal disturbances, resulting in command feedback misalignment. At this point, all action segments with response offsets are recorded in chronological order to form a preliminary offset map. This offset map can reflect the dynamic characteristics of the signal propagation path at high temperatures, ensuring that the execution behavior and feedback behavior of each command remain traceable on the time axis, thus providing an accurate timing identifier for determining the triggering time of command overlap.

[0059] After obtaining the signal response offset, the feedback hysteresis data recorded in the potential conflict information table is analyzed in depth and correlated with the response offset mapping to determine the trigger moment of command overlap. Feedback hysteresis manifests as the accumulation of delay in the signal closed-loop response process, which typically increases with the increase of device junction temperature under high temperature conditions. In this process, the feedback hysteresis amplitude of each switching action in the time series is sorted, and the hysteresis time is superimposed with the response offset for analysis. When the hysteresis intervals of two or more commands overlap on the time axis, it can be identified as the potential command overlap trigger moment. To accurately determine this moment, the start point, end point, and duration of the overlapping interval are extracted item by item, and these time parameters are matched with the corresponding control channel number and command type to generate a list of overlapping events containing trigger conditions and trigger times. In this process, each overlapping event maintains a one-to-one correspondence with the temperature segment, signal delay, and feedback hysteresis data in the potential conflict information table, ensuring that the overlap identification results maintain a consistent physical correlation with the actual operating state.

[0060] Based on the overlapping event list, the system systematically organizes the operational segments with overlapping commands and outputs an overlapping feature list including abnormal response segments. During this organization, all overlapping events identified in the previous step are categorized by time sequence and spatial location, and multiple overlapping commands occurring within the same temperature range are aggregated and analyzed. For each aggregated segment, the number of commands, duration, signal response offset direction, and feedback lag degree are recorded to form a multi-dimensional description of the operational segment. Subsequently, the temperature change curves, signal delay curves, and action time curves of each segment are compared, and the characteristic intervals where command conflicts occur during the high-temperature disturbance phase are marked as abnormal response segments. By sorting all abnormal response segments according to their occurrence time, duration, and heat load intensity, an overlapping feature list covering the entire drive process can be generated. This overlapping feature list not only includes the trigger time and response characteristics of overlapping commands but also records the corresponding temperature changes and signal lag characteristics, providing a continuous and traceable data source for subsequent time isolation design and protection command generation.

[0061] Based on the overlapping feature list, the operation trajectory of the driving circuit during the temperature surge stage is traced back. The starting position of the repeated write instruction and the source of competition for multi-threaded instructions are identified. Based on the identification results, the instruction execution interval boundary is extracted, and a time isolation scheme for separating competing threads is generated.

[0062] To enable backtracking analysis of the overlapping feature list, ensure accurate tracking of the drive circuit's trajectory during temperature surges, and identify the starting position of repeated write instructions and the source of contention for multi-threaded instructions, thereby extracting instruction execution interval boundaries and generating a time isolation scheme to separate competing threads, the specific implementation steps are as follows:

[0063] Based on the established list of overlapping features, each abnormal response segment recorded in the list is traced back sequentially to construct the operating trajectory of the drive circuit during the temperature surge phase. The core of this tracing lies in mapping the time information in the overlapping feature list to the temperature change curve of the drive circuit under high-temperature operation, thus reconstructing the temperature surge interval at the time of the overlapping event using a time index. During this process, the start time, end time, duration, and corresponding temperature change rate of each abnormal response segment are organized to form a continuous operating trajectory sequence with time as the main thread. This operating trajectory not only reflects the temperature dynamics of the drive circuit during topology switching but also records the triggering sequence and feedback response changes of each control channel. By analyzing the overlap between the temperature change curve and the instruction execution time, the delay trend of the signal propagation path under high temperature can be determined, and this can be used to define the time range of the temperature surge phase. At this point, the operating trajectory exhibits multi-dimensional characteristics, including both the continuous temperature change over time and the overlapping execution of signals and instructions within the same time window, providing a clear time mapping reference for subsequent identification of repeated write positions.

[0064] Based on the constructed operating trajectory, the execution sequence of control commands during the temperature surge phase is back-analyzed to identify the starting position of repeated write commands. Under high-temperature disturbance conditions, multi-threaded parallel scheduling causes some commands to be continuously overwritten or alternately written in the execution buffer, resulting in repeated write phenomena. To achieve this identification process, the time series in the operating trajectory is used as the main axis, and the command triggering time marked in the overlapping feature list is combined with the feedback response delay to reconstruct the command execution state in each time period. When the same control channel has two or more command triggering records in a short period of time, it can be determined as repeated write behavior. The starting position of each repeated write event is further marked, and its corresponding temperature value and delay amplitude are recorded. By sorting these starting positions along the time axis, the timing distribution of command writing in the drive circuit during the high-temperature surge phase can be obtained. This distribution reflects the execution competition relationship of multi-threaded scheduling under the influence of high temperature, and at the same time reveals the concentrated segment of repeated write behavior in time, providing a clear basis for identifying the source of competition.

[0065] After identifying the start position of repeated writes, the sources of contention for multi-threaded instructions are analyzed and categorized. Contention typically manifests as multiple threads attempting to access the same control channel or execute interdependent topology switching instructions within the same time window. To perform this analysis, the start positions of repeated writes marked in the previous sub-step are mapped to thread identifiers in the overlap feature list. Threads that conflict within the same time period are arranged according to their triggering order, and their corresponding execution paths are analyzed. Under high-temperature conditions, thread contention is often accompanied by signal response lag and control delays caused by temperature coupling; therefore, the temperature change trend in the running trajectory must also be considered during the categorization process. When the execution paths of two or more threads overlap within a temperature surge zone, and their control targets point to the same power switching unit, this set of threads can be identified as a contention source. By analyzing the triggering time, duration, and overlap ratio of each contention source, the distribution range and interference intensity of multi-threaded contention can be clarified. Subsequently, all contention sources are arranged in chronological order to form a contention thread distribution table, providing structured input information for subsequent extraction of execution interval boundaries.

[0066] Based on the distribution table of competing threads, instruction execution interval boundaries are extracted, and a time isolation scheme for separating competing threads is generated. In this process, the thread set corresponding to each source of competition is divided according to execution time, the minimum safe interval between adjacent threads is calculated, and this is used to determine the execution boundary of each thread. To ensure the integrity of time isolation, the time window of the temperature surge phase is divided into several continuous intervals, and the thread trigger start and end points are marked within each interval, forming non-overlapping time partitions. Subsequently, a time isolation scheme is established based on these time partitions, allowing each thread to complete instruction processing within an independent execution time period, thereby avoiding duplicate writes to the buffer. This time isolation scheme not only considers the thread trigger interval but also combines the temperature change rate and feedback delay characteristics to dynamically expand or shrink the execution interval of each thread, ensuring that there is no overlap in competition between threads under high-temperature fluctuation conditions. The final time isolation scheme includes thread identifiers, execution time start and end points, isolation interval values, and corresponding temperature intervals, enabling subsequent drive circuits to operate according to a unified timing rhythm when executing topology switching instructions, ensuring that the execution behavior of each thread is independent in time, fundamentally eliminating the impact of multi-threaded competition on control stability.

[0067] The execution order of the drive circuit control instructions is adjusted according to the time isolation scheme, and a duty-free area and a delay buffer are set. A unified execution timing is established according to the adjusted instruction execution order to generate a thermal disturbance protection instruction set that adapts to high temperature disturbance conditions.

[0068] To ensure a stable topology switching rhythm for the drive circuit during high-temperature operation and to achieve unified and orderly instruction execution logic after multi-threaded contention is isolated, the generated time isolation scheme is applied and extended. By adjusting the execution order of control instructions and setting duty-free and delay buffers, various control instructions can run according to a unified time pattern under high-temperature disturbance conditions, thereby generating a protective instruction set with thermal disturbance protection function. The specific implementation steps are as follows:

[0069] Based on the thread execution interval boundaries defined in the time isolation scheme, the execution order of the drive circuit control instructions is comprehensively adjusted. This adjustment is based on the execution start and end points in the time isolation scheme, reordering the original instruction stream according to chronological order. To ensure that there is no overlap or conflict between instructions, the trigger and termination times of each instruction are matched with its corresponding temperature range and feedback hysteresis characteristics. When a control instruction is in a temperature surge zone, its execution order is shifted backward according to the interval boundaries in the time isolation scheme, so that its execution period avoids the overlapping intervals of other control channels. At the same time, the execution priority of all instructions is rearranged, prioritizing instructions related to the stability of the current conduction path, while instructions related to heat dissipation path adjustment are executed sequentially. Through this order adjustment, all control instructions form a continuous and non-overlapping execution sequence on the time axis, ensuring that the execution process of each instruction is independent and complete, thereby constructing the basic execution framework under high-temperature conditions. The execution result of this step provides clear time limits and trigger nodes for subsequent setting of duty and yield zones.

[0070] After adjusting the instruction execution order, a duty-free zone is set based on the time isolation scheme and the new instruction sequence. The purpose of setting the duty-free zone is to reserve a safe execution gap between adjacent control instructions to prevent execution overlap caused by signal propagation delays due to temperature changes. During this process, the on-time and off-time of each instruction are analyzed to calculate its minimum response interval under the current temperature conditions. Based on the analysis results, a time interval is inserted between two adjacent instructions, ensuring that the start time of the subsequent instruction is fixedly delayed relative to the end time of the previous instruction, thus forming a duty-free zone with time buffering characteristics. This zone not only absorbs signal propagation delays but also balances the execution load between different control channels. When a rise in temperature causes a decrease in device response speed, the duty-free zone automatically extends, ensuring that control signals still execute sequentially without contention or overlap even at high temperatures. This dynamic time allocation method enables the control timing of the drive circuit to adapt to thermal disturbances, providing a time reference for setting the delay buffer.

[0071] Based on the pre-defined duty-free zone, the instruction execution path of the drive circuit is optimized for delay by setting a delay buffer. The delay buffer absorbs the accumulated instruction execution delay caused by thermal stress during high-temperature fluctuations, preventing excessive accumulation of feedback lag due to sudden temperature changes. In this process, the execution start point of each control instruction is compared with its feedback response end point to calculate the delay interval length, and a delay buffer is inserted at the end of instruction execution. The length of the delay buffer is determined based on the temperature change rate and the feedback lag time difference, ensuring the buffer completely covers the delay interval during high-temperature periods. In this way, when high-temperature fluctuations cause instruction response delays, the delay buffer automatically absorbs the offset, ensuring that subsequent instructions still follow a consistent timing rhythm. Simultaneously, the delay buffer and the duty-free zone complement each other: the duty-free zone handles time isolation between instructions, while the delay buffer absorbs responses within instructions. Through their coordinated setup, the control timing of the drive circuit under high temperatures possesses anti-disturbance capabilities, ensuring stable execution logic for various instructions under different thermal load conditions. This step provides a precise time allocation basis for establishing a unified execution timing.

[0072] Based on the adjusted instruction execution order and the set duty-free and delay buffers, a unified execution timing is established, and a thermal disturbance protection instruction set adapted to high-temperature disturbance conditions is generated. During the establishment of the unified execution timing, all control instructions are arranged according to the adjusted time sequence, ensuring a strict sequential relationship between instruction triggering, execution, and feedback on the timeline. To prevent instruction rhythm drift caused by high temperatures, a reference time node is set in the unified execution timing, ensuring that the trigger signals of all instructions proceed synchronously with reference to this reference. Subsequently, the unified execution timing is mapped to a thermal disturbance protection instruction set, which includes the trigger time, execution duration, duty-free and delay buffer length, and corresponding temperature range for each control instruction. As the scheduling basis for control execution, the thermal disturbance protection instruction set can proactively adjust the execution rhythm of each instruction during high-temperature fluctuations, ensuring that the topology switching process remains within a safe time isolation range. When the temperature suddenly rises, the protection instruction set automatically calls the delay buffer to extend the rhythm; when the temperature drops, the protection instruction set automatically compresses the duty-free and delay buffer to improve control response speed. Through this continuous self-coordinated time control method, the instruction execution process of the drive circuit maintains a stable sequence and rhythm under high temperature interference, thereby achieving active protection against thermal disturbances.

[0073] Based on the thermal disturbance protection instruction set, the drive circuit is adjusted in real time. During the high temperature fluctuation stage, a reverse silence window is inserted, a rhythm yielding interval is set and a temperature drift compensation pulse is injected. The topology switching rhythm is continuously adjusted to prevent the risk of instantaneous short circuit during high temperature operation and maintain stable operation of the drive process.

[0074] To ensure the drive circuit can adjust its rhythm in real time according to the thermal disturbance protection command set during high-temperature fluctuations, maintaining continuity and stability in the topology switching process under different temperature conditions, effectively preventing instantaneous short-circuit risks, and maintaining energy flow balance in the drive path, a dynamically adjustable control rhythm structure is established by executing each protection command set. This achieves synchronous coordination of time, temperature, and signal when the circuit is subjected to thermal stress disturbances. The specific implementation steps are as follows:

[0075] The control rhythm of the drive circuit is adjusted in real time based on the thermal disturbance protection instruction set to ensure that various control instructions maintain a consistent timing order under high-temperature conditions. This adjustment is centered on the time parameters in the protection instruction set, including the trigger time, execution duration, duty cycle length, and delay buffer length for each control instruction. During execution, the instruction rhythm within each control cycle is redistributed to align its trigger time with temperature fluctuation trends. When the temperature rises rapidly, the control cycle is appropriately extended on the time axis to lengthen the interval between topology switching actions, absorbing signal response offsets caused by thermal expansion and junction temperature rise. When the temperature change stabilizes, the instruction rhythm returns to its original interval to maintain system operating efficiency. This continuous fine-tuning of the timing rhythm balances conduction losses and thermal stability under thermal stress, avoiding the superposition of instruction execution frequency and heat accumulation rate, thus achieving real-time rhythm self-adjustment control under thermal disturbances.

[0076] After real-time rhythm adjustment, a reverse silence window is dynamically inserted during high-temperature fluctuations based on the operating status of the protection command set. The reverse silence window temporarily suspends some conduction commands when the drive circuit experiences a sudden temperature rise, blocking energy backflow and eliminating transient overcurrent caused by signal superposition. The insertion process is based on the time stamp of the thermal disturbance protection command set. When the system detects that the rate of temperature change exceeds a preset threshold, a silence window is automatically set within the corresponding time period, delaying the originally scheduled command trigger action until after the silence zone ends. The duration of the silence window is dynamically matched based on the temperature rise rate and signal delay, ensuring that the conduction path of the drive circuit remains discontinuous during the temperature surge phase, thereby reducing the concentrated release of heat power. Furthermore, the reverse silence window applies not only to the main switch arm but also to the auxiliary drive channel, forming a dual-channel synchronous silence zone. This temporarily separates the current path in the high-temperature range, preventing short-circuit risks caused by timing overlap between adjacent power devices. Through this reverse quiescent mechanism, the drive circuit can form a dynamic rest zone during the thermal shock phase, which divides the energy flow in time, achieves a balanced distribution of instantaneous thermal load, and provides a safe buffer for setting the subsequent rhythm yielding interval.

[0077] Based on the insertion results of the reverse silent window, a rhythmic yielding interval is set to enable the drive circuit to have a hierarchical execution rhythm when restarting the conduction sequence. The rhythmic yielding interval is set starting from the end time of the silent window, dividing the execution priority sequence among various control channels so that related switching instructions are started in staggered order. Specifically, the main turn-on instruction is set as the rhythmic start point, and the triggering time of the auxiliary drive instruction is delayed to form a time yielding zone. The duration of the rhythmic yielding interval is matched according to the delay buffer parameters in the protection instruction set, so that the execution interval between different channels is sufficient to offset the signal propagation offset caused by high temperature. This interval is periodically distributed in time structure and is updated synchronously with the drive cycle, thus forming a sustainable timing yielding mechanism. When the system is in the thermal stable stage, the rhythmic yielding interval maintains a fixed length; when temperature fluctuations intensify, the rhythmic yielding interval automatically expands, further separating adjacent control instructions in time. Through this time-based yielding control, overlapping writes of control signals can be effectively avoided during high-temperature operation, ensuring that no cross-conduction occurs during the turn-on and turn-off processes of each switching unit. The setting of the rhythm yield interval not only ensures the independence of multi-channel command execution, but also provides a stable time window for the injection of temperature drift compensation pulses.

[0078] After the rhythm yielding interval is formed, a temperature drift compensation pulse is injected based on the temperature response parameters in the thermal disturbance protection command set, and the topology switching rhythm is continuously adjusted throughout the entire drive cycle. The function of the temperature drift compensation pulse is to offset the signal amplitude shift and delay accumulation caused by temperature fluctuations, ensuring that the control command maintains its original trigger amplitude and response synchronization during thermal changes. The timing of the compensation pulse injection is consistent with the boundary of the rhythm yielding interval to ensure that it does not overlap with the main control command. During the high-temperature fluctuation phase, the amplitude of the compensation pulse is dynamically adjusted according to the junction temperature change rate to form a short-term reverse potential in the energy output path, thereby balancing the junction temperature rise of the conducting devices. When the temperature begins to drop, the compensation pulse gradually contracts, and the system returns to the normal operating rhythm. By continuously injecting temperature drift compensation pulses during the drive cycle, the impact of thermal disturbances on signal timing is offset in real time, thereby achieving continuous adjustment of the topology switching rhythm. Ultimately, the control rhythm of the drive circuit forms a dynamic closed loop throughout the high-temperature phase: rhythm adjustment is responsible for balancing the time base, the reverse silence window is responsible for isolating the thermal load, the rhythm yielding interval is responsible for staggered execution of timing, and the temperature drift compensation pulse is responsible for restoring the signal amplitude. The interaction of these four elements enables the drive circuit to have continuous self-adjustment and dynamic repair capabilities during topology switching under high-temperature fluctuation conditions, preventing the occurrence of instantaneous short-circuit risks and maintaining the continuous operation of the system.

[0079] This invention synchronously acquires temperature change data, signal delay data, and instruction timing data during the operation of the drive circuit. Combined with a time isolation scheme and dynamic adjustment of the thermal disturbance protection instruction set, the drive circuit can proactively identify and separate the competing relationships of multi-threaded instructions in high-temperature environments, thereby achieving adaptive reconfiguration of the instruction execution order. This technique effectively avoids overlapping execution of turn-on and turn-off instructions during topology switching, preventing instantaneous short circuits and energy backflow, ensuring continuous, controllable, and stable operation of the drive process under high-temperature stress, and improving overall operational safety and thermal stability.

[0080] This invention achieves real-time self-adjustment of the topology switching rhythm in response to temperature changes by inserting a reverse quiescent window and injecting temperature drift compensation pulses during high-temperature fluctuations. This method enables the control rhythm to form a dynamic yielding and delay buffering mechanism under thermal disturbance conditions, ensuring the continuous and effective time isolation between switching signals and reducing the impact of feedback misalignment caused by thermal mismatch on the control logic. Through the synergistic effect of continuous rhythm rearrangement and compensation pulses, the drive circuit maintains high efficiency and stable power output under high-temperature conditions, improving the system's reliability and resistance to thermal disturbances.

[0081] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning, characterized in that, Includes the following steps: During the topology optimization stage of the drive circuit, temperature change data, signal delay data, and command timing data of the drive circuit during operation are collected synchronously. Based on the collected data, the time distribution diagram of the topology switching process is reconstructed, the time segments with thermal mismatch characteristics in the time distribution diagram are analyzed, and a potential conflict information table is generated. The timing sequence, signal response offset, and feedback lag of each switch action in the drive circuit are analyzed point by point using a potential conflict information table. Based on the analysis results, the trigger time of instruction overlap is determined, the running segments with instruction overlap are sorted out, and an overlap feature list is output. Based on the overlapping feature list, the operation trajectory of the driving circuit during the temperature surge stage is traced back, the starting position of repeated write instructions and the source of competition for multi-threaded instructions are identified, the instruction execution interval boundary is extracted based on the identification results, and a time isolation scheme is generated. The execution order of the drive circuit control instructions is adjusted according to the time isolation scheme, a duty-free area and a delay buffer are set, a unified execution timing is established according to the adjusted instruction execution order, and a thermal disturbance protection instruction set is generated. The steps are as follows: Based on the thread execution interval boundary defined in the time isolation scheme, the execution order of the drive circuit control instructions is adjusted, the original instruction stream is rearranged according to the time sequence, and a basic execution framework is formed by matching the temperature range and feedback lag characteristics. The duty and yield zone is set according to the adjusted instruction execution order, and time intervals are inserted between adjacent control instructions to absorb signal propagation delays and maintain sequential execution. The instruction execution path is delayed based on the duty and yield area, and a delay buffer is set to absorb the accumulated instruction delay caused by high temperature fluctuations, so that the control timing has the ability to resist disturbances. A unified execution sequence is established based on the adjusted instruction execution order and the set duty and delay buffer areas to generate a thermal disturbance protection instruction set; Based on the thermal disturbance protection instruction set, the drive circuit is adjusted in real time. During the high temperature fluctuation stage, a reverse silence window is inserted, a rhythm yielding interval is set and a temperature drift compensation pulse is injected to continuously adjust the topology switching rhythm. The steps are as follows: The control rhythm of the drive circuit is adjusted in real time according to the thermal disturbance protection instruction set. By reallocating the trigger time and execution duration of the control instructions, the topology switching action is coordinated with the temperature fluctuation trend. Based on the operating status of the protection instruction set, a reverse silence window is inserted during the high temperature fluctuation phase, forming an intermittent operating path by pausing some conduction instructions; Based on the insertion results of the reverse silent window, a rhythm yielding interval is set. At the end of the silent window, the execution priority is divided and a time yielding interval is formed to maintain the independence of multi-channel execution. Temperature drift compensation pulses are injected according to the rhythmic yielding interval to balance the junction temperature change of the conducting device by continuously adjusting the topology switching rhythm during the driving cycle.

2. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 1, characterized in that, The steps for generating the potential conflict information table are as follows: During the topology optimization stage of the drive circuit, temperature change data, signal delay data and command timing data of the drive circuit during operation are collected in a unified manner, and drive signals, sampling signals and control signals are recorded on the same time base through parallel sampling. Based on the collected temperature change data, signal delay data, and command timing data, the topology switching events are arranged in chronological order using time index as the main line to generate a time distribution map. Based on the time distribution diagram, analyze the combination relationship between the temperature change rate, signal delay change amplitude and instruction interval in each time segment to extract the risk segments that simultaneously have temperature surge, response lag and execution compression. Based on the risk segment information, the start time, end time, temperature change rate, signal delay amplitude, and command trigger interval are recorded to generate a potential conflict information table.

3. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 2, characterized in that, The steps for outputting the overlapping feature list are as follows: Based on the generated potential conflict information table, each potential conflict event is read and analyzed, and the time dependency relationship of the driving circuit switching action is established with time as the main line to form an action time sequence; Based on the action time series, the signal response offset corresponding to each switch action is analyzed. By aligning the action time series with the signal delay data in the potential conflict information table, action segments with response extension or compression are identified and offset mapping is formed. Based on the correlation analysis of the feedback lag data in the offset mapping and potential conflict information table, extract the instruction overlap trigger time when the lag interval overlaps and generate an overlap event list. Based on the list of overlapping events, the running segments with overlapping instructions are organized, and the number of instructions, duration, response offset direction and lag degree are recorded, and the list of overlapping features is output.

4. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 3, characterized in that, During the process of generating the list of overlapping features, the temperature change curves, signal delay curves and action time curves of each abnormal response segment are compared and analyzed. Multiple command overlap phenomena within the same temperature segment are aggregated and processed. The abnormal response segments are sorted according to the heat load intensity, and the timing distribution correlation of the drive circuit in the high temperature disturbance stage is established.

5. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 3, characterized in that, The steps to generate a time isolation scheme are as follows: Based on the resulting list of overlapping features, the abnormal response segments recorded therein are traced back, and the time information is matched with the temperature change curve of the drive circuit under high temperature operation to construct the operating trajectory of the temperature surge stage and form a continuous time series. Based on the running trajectory, the execution sequence of control commands during the temperature surge phase is analyzed retrospectively to identify the starting position of the repeatedly written commands, record the temperature value and delay amplitude corresponding to the starting position, and form the command timing distribution. Based on the instruction timing distribution, the sources of competition for multi-threaded instructions are analyzed and classified, and the threads triggered within the same time period are arranged in chronological order to form a competition thread distribution table; Based on the distribution table of competing threads, the instruction execution interval boundaries are extracted, non-overlapping time partitions are divided, and a time isolation scheme is generated.

6. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 5, characterized in that, During the generation of the time isolation scheme, the execution gap of competing threads is dynamically adjusted according to the time window of the temperature surge phase. By combining the temperature change rate and feedback delay characteristics to expand or shrink the time interval between threads, the control threads of the drive circuit remain time-independent under high temperature fluctuation conditions and prevent execution overlap.

7. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 1, characterized in that, The thermal disturbance protection instruction set dynamically adjusts the time length of the duty-free zone and the delay buffer according to the temperature change rate during the operation of the drive circuit. When the temperature rises, the execution interval is extended to prevent instruction overlap, and when the temperature drops, the interval is compressed to improve the control response speed.

8. The method for topology optimization of high-temperature resistant driving circuits based on reinforcement learning according to claim 1, characterized in that, The duration of the reverse silence window is dynamically matched based on the rate of temperature change and the degree of signal delay. The duration of the rhythm yielding interval is synchronously adjusted based on the delay buffer parameters. The injection timing of the temperature drift compensation pulse is consistent with the boundary of the rhythm yielding interval.

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