A driving voltage generation circuit

Abstract

This invention discloses a driving voltage generation circuit, relating to the field of driving voltage technology. It includes: the drains of a second NMOS transistor and a third NMOS transistor, and one end of a current source, all connected to an input voltage source; the gate of the second NMOS transistor is connected to the gate of a first PMOS transistor, one end of a first resistor, and the other end of the current source; the source of the second NMOS transistor is connected to the source of the first PMOS transistor, and its first connection node is connected to a first output node, outputting a low-side driving voltage; the second connection node between the gate of the second NMOS transistor and the other end of the current source is connected to the gate of the third NMOS transistor to form a third connection node; the third connection node is connected to the gate of a fourth NMOS transistor; the fourth connection node formed by the connection of the source of the third NMOS transistor and the source of the second PMOS transistor is connected to the drain of the fourth NMOS transistor; the source of the fourth NMOS transistor is connected to a second output node, outputting a high-side driving voltage. This circuit can generate a more accurate gate driving voltage for power NMOS transistors, thereby improving energy conversion efficiency and reducing chip area.

Description

Technical Field

[0001] This invention relates to the field of driving voltage technology, and more specifically to a driving voltage generating circuit. Background Technology

[0002] Currently, DC-DC converters are widely used in various fields that require high energy conversion efficiency. Many existing DC-DC converters use NMOS as the power transistor. However, the gate drive voltage of the power NMOS in existing DC-DC converters is inaccurate, and due to its complex structure, it occupies a large chip area.

[0003] The implementation methods of existing technologies are as follows Figure 1 As shown. Figure 1 The circuit includes a loop control circuit (Loop1), a voltage regulator (LDO) (generating approximately 5V), a high-side driver (DRVH), a low-side driver (DRVL), capacitors Cbs and C1, an inductor (L1), feedback resistors (Rf1 and Rf2), and a diode (D1). Typically, the LDO requires a fast dynamic response and a complex structure, occupying a large chip area. Additionally, diode D1 is prone to latch-up due to its forward conduction, necessitating auxiliary circuitry for risk control. Furthermore, the forward conduction voltage of diode D1 varies significantly with the process corner, leading to inaccurate high-level voltage at the PSH.

[0004] Therefore, how to generate a more accurate gate drive voltage for power NMOS, thereby improving energy conversion efficiency and reducing chip area, is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] In view of the above problems, the present invention is proposed to provide a drive voltage generation circuit that overcomes or at least partially solves the above problems, and is capable of generating a more accurate gate drive voltage for power NMOS, thereby improving energy conversion efficiency and reducing chip area.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] In a first aspect, embodiments of the present invention provide a driving voltage generating circuit, comprising: a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a current source, a first PMOS transistor, a second PMOS transistor, and a first resistor;

[0008] The drain of the second NMOS transistor, the drain of the third NMOS transistor, and one end of the current source are all connected to the input voltage source;

[0009] The gate of the second NMOS transistor is connected to the gate of the first PMOS transistor, one end of the first resistor, and the other end of the current source, respectively.

[0010] The source of the second NMOS transistor is connected to the source of the first PMOS transistor, and the first connection node formed therebetween is connected to the first output node, which outputs a low-side drive voltage.

[0011] The gate of the second NMOS transistor and the second connection node at the other end of the current source are connected to the gate of the third NMOS transistor, forming a third connection node;

[0012] The third connection node is connected to the gate of the fourth NMOS transistor;

[0013] The source of the third NMOS transistor is connected to the source of the second PMOS transistor, and the fourth connection node formed is connected to the drain of the fourth NMOS transistor.

[0014] The source of the fourth NMOS transistor is connected to the second output node, and it outputs a high-side drive voltage.

[0015] The gate of the second NMOS transistor is connected to the fifth connection node at one end of the first resistor and the gate of the second PMOS transistor;

[0016] The other end of the first resistor is connected to the gate and drain of the first NMOS transistor, respectively;

[0017] The drain of the first PMOS transistor, the source of the first NMOS transistor, and the drain of the second PMOS transistor are all grounded.

[0018] In one embodiment, it further includes: a first capacitor;

[0019] The second connection node connects with the third connection node to form a sixth connection node;

[0020] The first capacitor is connected to the sixth connection node and ground respectively, and is used to stabilize the output voltage of the second connection node.

[0021] In one embodiment, it further includes: a second capacitor;

[0022] The two ends of the second capacitor are connected to the first output node and ground, respectively, to stabilize the low-side drive voltage of the output.

[0023] In one embodiment, the current I1 output by the current source is set as follows:

[0024] I1 = VR1 / Rg;

[0025] Where VR1 represents the reference voltage based on the bandgap reference voltage, and Rg represents a resistance value.

[0026] In one embodiment, Rg and the first resistor are of the same type, with equal width, proportional length, and the same current direction.

[0027] In one embodiment, the current output from the current source passes through the first resistor and the first NMOS transistor to generate an NG1 voltage V. NG1 :

[0028] V NG1 =I1·Ra+Vth_MNH1;

[0029] Where Ra represents the first resistor and Vth_MNH1 represents the threshold voltage of the first NMOS transistor.

[0030] In one embodiment, the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all device types capable of withstanding the maximum output voltage of the input voltage source, and their channel lengths are equal, their channel widths are proportional, their geometric centers overlap, and their current directions are consistent.

[0031] In one embodiment, the first PMOS transistor is used to clamp the low-side drive voltage and is turned on when the low-side drive voltage is higher than a first threshold to prevent the low-side drive voltage from being coupled too high by switching noise.

[0032] The second PMOS transistor is used to clamp the fourth node voltage output by the fourth connection node. When the fourth node voltage exceeds the second threshold, it is turned on to discharge the charge.

[0033] In one embodiment, a second resistor is also included;

[0034] The second connection node connects with the fifth connection node to form the seventh connection node;

[0035] The two ends of the second resistor are connected to the seventh connection node and the fifth connection node respectively, and the output voltage GPH2 of the fifth connection node is input to the gate of the second PMOS transistor.

[0036] In one embodiment, it further includes: a first diode, a second diode, and a third diode;

[0037] The third connection node is connected to the sixth connection node to form the eighth connection node;

[0038] The fourth connection node is connected to the source of the second PMOS transistor to form the ninth connection node;

[0039] The eighth connection node is connected to the positive terminal of the first diode;

[0040] The negative terminal of the first diode is connected to the positive terminal of the second diode;

[0041] The negative terminal of the second diode is connected to the positive terminal of the third diode;

[0042] The negative terminal of the third diode is connected to the ninth connection node.

[0043] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a driving voltage generation circuit. By generating an accurate gate driving voltage, i.e. DRVPS output voltage, the present invention helps to design with a higher driving voltage value while ensuring that the chip has no overvoltage risk, and can significantly reduce the area of ​​MNH and MNL. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0045] Figure 1 This is a structural diagram of a conventional DC-DC converter provided in an embodiment of the present invention.

[0046] Figure 2 This is a schematic diagram of a driving voltage generation circuit DRVPS provided in Embodiment 1 of the present invention.

[0047] Figure 3 This is a schematic diagram of a step-down DC-DC converter structure using the driving voltage generation circuit DRVPS of the present invention, as provided in Embodiment 1 of the present invention.

[0048] Figure 4 This is a schematic diagram of a driving voltage generation circuit DRVPS provided in Embodiment 2 of the present invention.

[0049] Figure 5 This is a schematic diagram of a driving voltage generation circuit DRVPS provided in Embodiment 3 of the present invention. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0051] Example 1

[0052] In the existing technology, due to process deviations, the driving voltage varies greatly between chips during mass production. If the driving voltage is too high, the chip will be damaged due to overvoltage. If the driving voltage is too low, the on-resistance of the driven transistor (MNH or MNL) will be too high. If the on-resistance of MNH or MNL is to be kept low when the driving voltage is low, the area of ​​MNH or MNL needs to be increased significantly, which is costly.

[0053] Based on this, the present invention generates an accurate gate drive voltage, i.e., the DRVPS output voltage, which helps to design with a higher drive voltage value while ensuring that the chip is free from overvoltage risk, and can significantly reduce the area of ​​MNH and MNL.

[0054] like Figure 2 As shown, an embodiment of the present invention discloses a driving voltage generation circuit DRVPS, including: a first NMOS transistor MNH1, a second NMOS transistor MNH2, a third NMOS transistor MNH3, a fourth NMOS transistor MNH4, a current source, a first PMOS transistor MPH1, a second PMOS transistor MPH2, and a first resistor Ra;

[0055] The drains of the second NMOS transistor MNH2 and the third NMOS transistor MNH3, as well as one end of the current source, are all connected to the input voltage source VIN.

[0056] The gate of the second NMOS transistor MNH2 is connected to the gate of the first PMOS transistor MPH1, one end of the first resistor Ra, and the other end of the current source, respectively.

[0057] The source of the second NMOS transistor MNH2 is connected to the source of the first PMOS transistor MPH1, and the first connection node 1 formed by them is connected to the first output node PSL, outputting the low-side drive voltage.

[0058] The gate of the second NMOS transistor MNH1 is connected to the second connection node 2 at the other end of the current source and the gate of the third NMOS transistor MNH3, forming the third connection node 3;

[0059] The third connection node 3 is connected to the gate of the fourth NMOS transistor MNH4;

[0060] The source of the third NMOS transistor MNH3 is connected to the source of the second PMOS transistor MPH2, and the fourth connection node 4 formed is connected to the drain of the fourth NMOS transistor MNH4.

[0061] The source of the fourth NMOS transistor MNH4 is connected to the second output node PSH, and it outputs the high-side drive voltage.

[0062] The gate of the second NMOS transistor MNH2 is connected to the fifth connection node at one end of the first resistor Ra and the gate of the second PMOS transistor MPH2.

[0063] The other end of the first resistor Ra is connected to the gate and drain of the first NMOS transistor MNH1, respectively.

[0064] The drain of the first PMOS transistor MPH1, the source of the first NMOS transistor MNH1, and the drain of the second PMOS transistor MPH2 are all grounded.

[0065] Furthermore, it also includes: a first capacitor Ca;

[0066] The second connecting node 2 and the third connecting node 3 are connected to form the sixth connecting node 6;

[0067] The first capacitor Ca is connected to the sixth connection node 6 and ground respectively, and is used to stabilize the output voltage of the second connection node 2.

[0068] Furthermore, it also includes: a second capacitor Cb;

[0069] The second capacitor Cb is connected to the first output node and ground respectively, and is used to stabilize the low-side drive voltage PSL of the output.

[0070] Furthermore, the current I1 output by the current source is set as follows:

[0071] I1 = VR1 / Rg;

[0072] Where VR1 represents the reference voltage based on the bandgap reference voltage, and Rg represents a resistance value.

[0073] Furthermore, Rg and the first resistor Ra are the same type of resistor, with equal width and proportional length. In the layout design, the current direction of Rg and the first resistor Ra is the same.

[0074] Furthermore, the current I1 output by the current source passes through the first resistor Ra and the first NMOS transistor MNH1 to generate the voltage V of NG1. NG1 :

[0075] V NG1 =I1·Ra+Vth_MNH1;

[0076] Where Ra represents the first resistor and Vth_MNH1 represents the threshold voltage of the first NMOS transistor MNH1.

[0077] Furthermore, the first NMOS transistor MNH1, the second NMOS transistor MNH2, and the third NMOS transistor MNH3 are all device types capable of withstanding the maximum output voltage of the input voltage source. Their channel lengths are equal, their channel widths are proportional, and they are designed to have overlapping geometric centers and consistent current directions in the layout design.

[0078] Furthermore, the first PMOS transistor MPH1 is used to clamp the low-side drive voltage. It is turned on when the low-side drive voltage is higher than the first threshold to prevent the low-side drive voltage from being coupled too high by switching noise.

[0079] The second PMOS transistor MPH2 is used to clamp the fourth node voltage output of the fourth connection node. When the fourth node voltage exceeds the second threshold, it is turned on to discharge the charge.

[0080] Furthermore, in this embodiment, the first threshold is set to V. NG1 +|Vth_MPH1|, where |Vth_MPH1| represents the absolute value of the threshold voltage of the first PMOS transistor MPH1;

[0081] The second threshold is set to V. NG1 +|Vth_MPH2|, where |Vth_MPH2| represents the absolute value of the threshold voltage of the second PMOS transistor MPH2.

[0082] Furthermore, in this embodiment, the first PMOS transistor MPH1 is a low-voltage PMOS transistor with a withstand voltage of 5V, and the second PMOS transistor MPH2 is a PMOS transistor with a withstand voltage greater than 5V. In this embodiment, a 10V PMOS transistor is used.

[0083] Furthermore, the second NMOS transistor MNH2 functions as a voltage follower (with a common-drain connection), ensuring that its source voltage (i.e., the PSL voltage at the first output node) equals V. NG1 Subtracting the threshold voltage of the second NMOS transistor MNH2, since the second NMOS transistor MNH2 and the first NMOS transistor MNH1 are matched, their threshold voltages are equal and can cancel each other out. Therefore, the low-side drive voltage V output by the first output node PSL is... PSL for:

[0084] V PSL =I1·Ra+Vth_MNH1-Vth_MNH2=I1·Ra;

[0085] Where Vth_MNH1 represents the threshold voltage of MNH1, and Vth_MNH2 represents the threshold voltage of MNH2;

[0086] If I1 = VR1 / Rg, then the low-side drive voltage V PSL It is equal to VR1.Ra / Rg. Since the first resistor Ra and Rg are designed to be matched, their resistance ratio is a constant value. Therefore, VR1.Ra / Rg is less than the preset value due to the process angle deviation, and can be used as an accurate value.

[0087] Furthermore, such as Figure 3As shown, a step-down DC-DC converter using the driving voltage generation circuit DRVPS of the present invention is shown. The operating range of the VIN voltage is 7V~50V, and the output voltage OUTD of the DC-DC converter is 0.5V~5V. The specific value can be set by the feedback resistors Rf1 and Rf2.

[0088] The present invention provides a driving voltage generation circuit DRVPS for generating a high-side driving voltage V. PSH Powering the high-side driver DRVH simultaneously generates the low-side drive voltage V. PSL Power the low-side driver DRVL;

[0089] V PSL For any value between 4.5V and 7V, V PSH The voltage relative to SW can be any value between 4.5V and 7V, meaning the voltage of the PSH-SW can be designed to be any value between 4.5V and 7V.

[0090] Voltage divider resistors Rf1 and Rf2 divide OUTD to generate FB1, which is input to the loop controller Loop1. Loop1 compares the FB1 voltage with the built-in reference voltage (e.g., 1V). When the FB1 voltage is lower than the built-in reference voltage, Loop1 adjusts by increasing the duty cycle of DH1 and decreasing the duty cycle of DL1. This increases the on-time of the upper N-channel MOSFET MNH and decreases the on-time of the lower N-channel MOSFET MNL, resulting in a larger duty cycle at the SWD node and a larger OUTD voltage after filtering by L1 and C1. Conversely, when the FB1 voltage is higher than the built-in reference voltage, Loop1 adjusts by decreasing the duty cycle of DH1 and increasing the duty cycle of DL1. This decreases the on-time of MNH and increases the on-time of MNL, resulting in a smaller duty cycle at the SWD node and a smaller OUTD voltage after filtering by L1 and C1. This forms a negative feedback loop. When the negative feedback loop is stable, the FB1 voltage equals the built-in reference voltage, and OUTD is also a stable output voltage.

[0091] Generally, DHI and DLI are inverted signals; that is, when DHI is high, DLI is low, and when DHI is low, DLI is high.

[0092] Furthermore, when the SWD node is pulled low by MNL (approximately equal to ground voltage), the drive voltage generation circuit DRVPS outputs a high-side drive voltage V. PSH The capacitor Cbs is charged until its voltage reaches a preset voltage (5V in this embodiment, but can be between 4.5V and 7V in actual design). When the SWD node is turned on by MNH and pulled high to VIN, the voltage on capacitor Cbs remains constant, and the high-side drive voltage V... PSHThe voltage increases as the SWD node voltage increases, maintaining PSH-SW at 5V.

[0093] Furthermore, when the SWD node is low, the third NMOS transistor MNH3 and the fourth NMOS transistor MNH4 are turned on, which turns on the fourth node voltage V of the fourth connection node SNH3. SNH3 Charge to equal V NG1 -Vth_MNH3, where Vth_MNH3 represents the threshold voltage of MNH3. Since the fourth NMOS transistor MNH4 is turned on as a switch, the high-side drive voltage V is... PSH equals V SNH3 Because of V NG1 =I1·Ra+Vth_MNH1,V SNH3 = I1·Ra + Vth_MNH1 - Vth_MNH3, where MNH1 and MNH3 are designed with matching, so their threshold voltages are equal. The above equation is simplified to I1·Ra, which is the high-side drive voltage V. PSH =I1·Ra, when I1=VR1 / Rg, then substituting into the formula, we get V. PSH VR1·Ra / Rg: Ra and Rg are designed to be matched, and their resistance ratio is a constant value. Therefore, VR1.Ra / Rg can achieve a more accurate value than existing technologies by adjusting the preset value according to the process angle deviation.

[0094] Furthermore, when the SWD node voltage increases (corresponding to...) Figure 2 When MNH is on, since the voltage across capacitor Cbs will not change abruptly, the high-side drive voltage V PSH When the voltage is pulled up, maintaining PSH-SW at a constant value (e.g., 5V), MNH4 is cut off and does not conduct. Due to the presence of the parasitic capacitance Cds (the parasitic capacitance between the drain and source of MNH4), the fourth node voltage V... SNH3 The voltage at the SNH3 node will be highly coupled, therefore MPH2 is needed to clamp the voltage at the SNH3 node to prevent it from becoming too high and damaging MNH3 and MPH2. When the voltage at the fourth node V... SNH3 When the second threshold is exceeded, MPH2 will conduct to discharge the charge.

[0095] Example 2

[0096] Based on the same inventive concept, such as Figure 4 As shown, this embodiment of the invention discloses another driving voltage generation circuit DRVPS, which, based on the driving voltage generation circuit DRVPS in embodiment 1, adds a second resistor Rb.

[0097] The second connecting node 2 and the fifth connecting node 5 are connected to form the seventh connecting node 7;

[0098] The two ends of the second resistor Rb are connected to the seventh connection node 7 and the fifth connection node 5 respectively. The output voltage GPH2 of the fifth connection node 5 is input to the gate of the second PMOS transistor.

[0099] Furthermore, since the output voltage GPH2 is greater than V NG1 The low voltage I1·Rb allows for a reduction in the clamping voltage of the fourth node, SNH3, thus more reliably preventing overvoltage and making the implementation safer. The operating principle of the other parts of the circuit is the same as in Example 1, and will not be repeated here.

[0100] Example 3

[0101] Based on the same inventive concept, such as Figure 5 As shown, this embodiment of the invention also provides another driving voltage generating circuit DRVPS, which, based on the driving voltage generating circuit DRVPS in embodiment 2, adds a first diode D1, a second diode D2, and a third diode D3;

[0102] The third connecting node 3 and the sixth connecting node 6 are connected to form the eighth connecting node 8;

[0103] The fourth connection node 4 is connected to the source of the second PMOS transistor MPH2, forming the ninth connection node 9;

[0104] The eighth connection node 8 is connected to the positive terminal of the first diode D1;

[0105] The negative terminal of the first diode D1 is connected to the positive terminal of the second diode D2;

[0106] The negative terminal of the second diode D2 is connected to the positive terminal of the third diode D3;

[0107] The negative terminal of the third diode D3 is connected to the ninth connection node 9.

[0108] Furthermore, by adding clamping diodes D1, D2, and D3 to the DRVPS circuit disclosed in Embodiment 2, the gate of MNH3 can be effectively protected, preventing damage to MNH3 due to excessively high gate-source voltage. This is because the voltage of SNH3 fluctuates drastically during the switching process of the power transistor in the DC-DC converter (due to the influence of parasitic capacitance). When the gate-source voltage of MNH3 exceeds three times the forward conduction voltage of the diode, voltage clamping will be performed to achieve the protection effect.

[0109] The working principle of the other parts of the circuit is the same as that of Example 1, and will not be repeated here.

[0110] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to the method section.

[0111] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A driving voltage generating circuit, characterized in that, include: First NMOS transistor, second NMOS transistor, third NMOS transistor, fourth NMOS transistor, current source, first PMOS transistor, second PMOS transistor and first resistor; The drain of the second NMOS transistor, the drain of the third NMOS transistor, and one end of the current source are all connected to the input voltage source; The gate of the second NMOS transistor is connected to the gate of the first PMOS transistor, one end of the first resistor, and the other end of the current source, respectively. The source of the second NMOS transistor is connected to the source of the first PMOS transistor, and the first connection node formed therebetween is connected to the first output node, which outputs a low-side drive voltage. The gate of the second NMOS transistor and the second connection node at the other end of the current source are connected to the gate of the third NMOS transistor, forming a third connection node; The third connection node is connected to the gate of the fourth NMOS transistor; The source of the third NMOS transistor is connected to the source of the second PMOS transistor, and the fourth connection node formed is connected to the drain of the fourth NMOS transistor. The source of the fourth NMOS transistor is connected to the second output node, and it outputs a high-side drive voltage. The gate of the second NMOS transistor is connected to the fifth connection node at one end of the first resistor and the gate of the second PMOS transistor; The other end of the first resistor is connected to the gate and drain of the first NMOS transistor, respectively; The drain of the first PMOS transistor, the source of the first NMOS transistor, and the drain of the second PMOS transistor are all grounded.

2. The driving voltage generating circuit according to claim 1, characterized in that, It also includes: the first capacitor; The second connection node connects with the third connection node to form a sixth connection node; The first capacitor is connected to the sixth connection node and ground respectively, and is used to stabilize the output voltage of the second connection node.

3. The driving voltage generating circuit according to claim 1, characterized in that, Also includes: Second capacitor; The two ends of the second capacitor are connected to the first output node and ground, respectively, to stabilize the low-side drive voltage of the output.

4. The driving voltage generating circuit according to claim 1, characterized in that, The current I1 output by the current source is set as follows: I1 = VR1 / Rg; Where VR1 represents the reference voltage based on the bandgap reference voltage, and Rg represents a resistance value.

5. A driving voltage generating circuit according to claim 4, characterized in that, Rg and the first resistor are of the same type, with equal width, proportional length, and the same current direction.

6. A driving voltage generating circuit according to claim 4, characterized in that, The current output from the current source passes through the first resistor and the first NMOS transistor to generate NG1 voltage V. NG1 : In NG1 =I1·Ra+Vth_MNH1; Where Ra represents the first resistor and Vth_MNH1 represents the threshold voltage of the first NMOS transistor.

7. The driving voltage generating circuit according to claim 1, characterized in that, The first NMOS transistor, the second NMOS transistor, and the third NMOS transistor are all device types capable of withstanding the maximum output voltage of the input voltage source. They have equal channel lengths, proportional channel widths, overlapping geometric centers, and consistent current directions.

8. A driving voltage generating circuit according to claim 1, characterized in that, The first PMOS transistor is used to clamp the low-side drive voltage. It is turned on when the low-side drive voltage is higher than the first threshold to prevent the low-side drive voltage from being coupled too high by switching noise. The second PMOS transistor is used to clamp the fourth node voltage output by the fourth connection node. When the fourth node voltage exceeds the second threshold, it is turned on to discharge the charge.

9. A driving voltage generating circuit according to claim 1, characterized in that, It also includes a second resistor; The second connection node connects with the fifth connection node to form the seventh connection node; The two ends of the second resistor are connected to the seventh connection node and the fifth connection node respectively, and the output voltage GPH2 of the fifth connection node is input to the gate of the second PMOS transistor.

10. A driving voltage generating circuit according to claim 2, characterized in that, Also includes: First diode, second diode, and third diode; The third connection node is connected to the sixth connection node to form the eighth connection node; The fourth connection node is connected to the source of the second PMOS transistor to form the ninth connection node; The eighth connection node is connected to the positive terminal of the first diode; The negative terminal of the first diode is connected to the positive terminal of the second diode; The negative terminal of the second diode is connected to the positive terminal of the third diode; The negative terminal of the third diode is connected to the ninth connection node.

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