Wireless dynamic updating system based on ultra wide band wireless

Abstract

A wireless dynamic updating system based on ultra wide band wireless is realized based on ZYNQ and comprises a ZYNQ master control module, a power supply module, a FLASH storage module, a DDR3 cache module, an SPI interface module and a UWB wireless module. When the UWB wireless module receives bin file data needing to be updated and sent by an upper computer, the bin file data are transmitted to the SPI interface module; the SPI interface module adopts double pointers to continuously send bin file data to the ZYNQ main control module; the ZYNQ main control module packages bin file data and then transmits the bin file data to the DDR3 cache module for framing, the whole bin file data is restored, and then formed data framing is extracted and sent to the FLASH storage module; when dynamic updating is executed, the ZYNQ main control module reads a data set frame from the FLASH storage module, puts the data set frame into a specified space of the DDR3 cache module and provides the data set frame for a PL end to download, and configuration updating is completed; the power module supplies power to the system. According to the method, the ultra-wideband wireless technology and split mirror image partition are adopted, cooperative work of the wireless updating function and the dynamic loading function is achieved, and the online updating and dynamic loading modes are enriched.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded wireless communication technology, and particularly relates to a wireless dynamic updating system based on ultra-wideband wireless. BACKGROUND

[0002] ZYNQ is a new generation of all programmable system on chip launched by Xilinx, which perfectly combines the software programmability of the processor and the hardware programmability of the FPGA to provide unparalleled system performance, flexibility and scalability.

[0003] Online updating refers to transmitting binary files containing system programs into on-chip or off-chip FLASH of the chip by some communication interfaces, without the need of program burning through the official debugging interface.

[0004] The current ZYNQ online updating technology is relatively mature, and the general online updating ZYNQ system hardware includes an upper computer, a network physical layer interaction PHY chip, a ZYNQ board card, a QSPI controller, a QSPI FLASH chip, a DDR3 memory, an EEPROM storage chip and a lower computer; the upper computer initiates an online updating command and sends binary data of the online updating firmware; the network physical layer interaction PHY chip is used for realizing physical layer conversion of network data protocol communication between the upper computer and the ZYNQ board card. After the data transmission is completed, the data is stored in the DDR3, then the partition header file data of the file is extracted, the partition header file data and the program data are framed to generate updating program data, and finally the updating program data is written into the QSPI FLASH.

[0005] Using this method for online updating needs to use wired connection, such as network port, serial port and other physical connections. And after online updating, the whole system needs to be restarted to make the program run again, which is relatively troublesome in the system with a large number of hardware initialization functions.

[0006] As disclosed in the patent document CN115454469A, a mirror image updating method, device, chip, electronic equipment and storage medium are specifically disclosed, which belong to the technical field of wireless communication, and include: receiving an updating mirror image request; in response to the updating mirror image request, updating the initial mirror image file according to the updating parameter, generating a first mirror image file and a configuration file of FLASH; based on the configuration file, verifying the target file in the first mirror image file to write the target file into the update partition of FLASH, and generating an update completion prompt. The mirror image updating method, device, chip, electronic equipment and storage medium provided by the present application can ensure the correctness of the upgrade mirror image by verifying the updated mirror image file, thereby ensuring the safe and reliable updating and upgrading of the mirror image file of ZYNQ without the limitation of external product environment and without affecting the original design work of ZYNQ, and without relying on JTAG tools.

[0007] Therefore, in order to meet the online updating needs of users at the present stage, a technical solution is needed to realize ultra-wideband wireless updating, and after online updating, the entire system does not need to be restarted, and software updating can be dynamically completed. SUMMARY

[0008] In order to solve the technical problems of the prior art that online updating needs to use wired connection, the entire system needs to be restarted after online updating to make the program run again, and it is not suitable for ultra-wideband wireless updating, a wireless dynamic updating system based on ultra-wideband wireless is provided, which is realized based on ZYNQ and includes a ZYNQ master module, a power module, a FLASH storage module, a DDR3 cache module, an SPI interface module and a UWB wireless module. The UWB wireless module is used to receive bin file data that needs to be updated sent by a host computer, and transmit the bin file data to the SPI interface module to realize bin file data transmission between the UWB wireless module and the host computer. The SPI interface module is used to receive the bin file data and transmit the bin file data to the ZYNQ master module, and continuous sending of the bin file data is realized by using double pointers; the double pointers include a receiving pointer and a sending pointer. The ZYNQ master module is used to receive the bin file data, transmit the bin file data to the DDR3 cache module after packetizing the bin file data, extract a data group frame formed after caching, and send the data group frame to the FLASH storage module after packetizing; when dynamic updating is performed, the ZYNQ master module reads the data group frame from the FLASH storage module and puts the data group frame into a specified space of the DDR3 cache module. The DDR3 cache module is used for caching the packaged bin file data, framing the packaged bin file data, restoring the entire bin file data, and providing the ZYNQ master module for extraction; when performing dynamic updating, it is used for receiving the data frames transmitted by the ZYNQ master module and providing the PL end for downloading to complete configuration updating. The FLASH storage module is used for storing the data frames and providing the ZYNQ master module for reading. The power module is used for converting the input current power into the specified current power to supply power to the system.

[0009] Further, the power module is composed of a power conversion chip, which can convert the input 12-28V DC power into the required power of the system, including 5V, 3.3V, 1.8V, 1.5V and 1.0V current power.

[0010] Further, the ZYNQ master module uses split mirror encoding to mirror partition the bin file data, forms a split mirror file, and then transmits it to the cache module for caching.

[0011] Further, the split mirror partition includes FSBL, PL bit stream and ARM program, which can simultaneously divide multiple PL bit streams and ARM programs, including PL bit stream 1, ARM program 1, PL bit stream 2 and ARM program 2; the position sequence is FSBL, PL bit stream 1, ARM program 1, PL bit stream 2 and ARM program 2.

[0012] Further, when the ZYNQ master module receives bin file data, the positions of the FSBL, PL bit stream 1 and ARM program 1 remain unchanged, and the bin file data is placed in the PL bit stream 2 and ARM program 2.

[0013] Further, the ZYNQ master module performs the following operations when receiving the bin file data: determine whether the message, preamble and CRC in the UWB frame format are correct; When the message, preamble and CRC are all correct, the bin file data part is parsed to form a data frame, which is transmitted to the DDR3 cache module for caching; After the DDR3 cache module receives all the data frames, it frames, restores the entire bin file data, and provides the ZYNQ master module for extraction.

[0014] Further, CRC verification can be added to the framed data during the process of restoring the entire bin file data. Further, the ZYNQ master module uses split mirror encoding to mirror partition the bin file data, forms a split mirror file, and then transmits it to the cache module for caching.

[0015] Further, when performing dynamic updating, the following is included: After the DDR3 cache module receives the data group frame transmitted by the ZYNQ master module, an official library function Xil_DCacheFlushRange is called to flush the contents in the DDR3 cache module; Before the data group frame is downloaded from the PL end through the DDR3 cache module, the core of the PL end is reset and initialized to restore the initial value.

[0016] Further, the specified space is greater than or equal to the size of the data group frame.

[0017] Further, the UWB wireless module adopts an error checking combined with a timeout mechanism to determine whether the bin file data transmitted by the upper computer is incorrect; when it is determined to be incorrect, the UWB wireless module is reset and reenters the receiving state; the upper computer retransmits the current frame, and if there is no data frame, a handshake frame is transmitted.

[0018] The wireless dynamic updating system provided by the application sets a UWB wireless module, adopts DW1000 ultra-wideband wireless technology, is suitable for the updating conditions of ultra-wideband wireless, and guarantees the timeliness and integrity of data transmission; a ZYNQ master module is set, split mirror encoding is adopted to mirror partition the bin file data, BIT data stream or ARM program part can be updated at one time; through the unique flow transfer mode of bin file data in the ZYNQ master module, FLASH storage module and DDR3 cache module, the technical effect that updating can be continued even in the case of power failure is realized, the wireless updating and dynamic loading functions of the whole system work cooperatively, the problems of wired connection and power failure restart are solved, and the online updating and dynamic loading mode is enriched. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is the structure block diagram of the wireless dynamic updating system based on ultra-wideband wireless provided by the application; Figure 2 is the processing flowchart of a single UWB wireless module provided by the application; Figure 3 is the schematic diagram of a ring buffer provided by the application; Figure 4 is the processing flowchart of the error checking combined with the timeout mechanism provided by the application; Figure 5 is the arrangement diagram of the split mirror file in the FLASH storage module provided by the application. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is further described below, but the scope of protection is not limited to what is described.

[0021] This invention provides a wireless dynamic update system based on ultra-wideband wireless technology, implemented using ZYNQ, such as... Figure 1 As shown, it includes a ZYNQ main control module, a power supply module, a FLASH storage module, a DDR3 cache module, an SPI interface module, and a UWB wireless module; Among them, P100, the UWB wireless module is used to receive the bin file data that needs to be updated sent by the host computer and transmit it to the SPI interface module to realize the data transmission of bin file between the UWB wireless module and the host computer; the UWB wireless module is composed of an ultra-wideband wireless chip and configuration circuit, such as the DW1000 chip and its configuration circuit.

[0022] The UWB wireless module employs an error checking and timeout mechanism to determine whether the bin file data sent by the host computer is erroneous. If an error is detected, the UWB wireless module resets and re-enters the receiving state to wait. The host computer retransmits the current frame; if no data frame is available, a handshake frame is sent. Figure 4 As shown.

[0023] The DW1000 employs ultra-wideband (UWB) wireless technology, transmitting data by sending and receiving extremely narrow pulses with durations in the nanosecond range or below. Its extremely high bandwidth and extremely low power spectral density enable it to resist interference from other narrowband and wideband wireless communication systems. The DW1000 uses nanosecond-level narrow pulses because the duration of these pulses is much shorter than the delay of multipath propagation, allowing the UWB wireless module to effectively separate multipath signals, thus giving UWB technology strong anti-multipath capabilities. The UWB wireless module uses intermittent pulses to transmit data; the pulse duration is very short, possibly 1 ns, resulting in a very low duty cycle and low system power consumption. Based on its advantages of low power consumption and strong anti-interference capabilities, the UWB wireless module uses the DW1000 chip.

[0024] The processing flow for a single UWB wireless module is as follows: Figure 2The UWB wireless module (receiver) receives the upgrade data transmitted from the host computer (sender) and stores it in a pre-defined storage area. This storage area consists of a two-dimensional array (transparent transmission mode). Data sent via serial port or received via DW1000 is packetized in 115-byte segments (configurable up to 1024 bytes including frame header and checksum). Received and transmitted via serial port (CAN) in conjunction with DMA, this process eliminates system overhead and increases system speed. The system has 80 packet groups set for serial port reception (tentative) and 40 packet groups set for serial port transmission (tentative). The storage area is used to buffer the transmitted and received data and forms a circular buffer. Figure 3 .

[0025] P200, the SPI interface module is used to receive the bin file data and transmit it to the ZYNQ main control module. It uses dual pointers to achieve continuous transmission of bin file data. The dual pointers include a receive pointer and a send pointer, which are used to achieve continuous data transmission and solve problems such as temporary network congestion.

[0026] The SPI interface module is connected to the PS peripheral interface of the ZYNQ main control module, eliminating the need for an external SPI control chip.

[0027] P300, the ZYNQ main control module is used to receive the bin file data, divide the bin file data into packets and transmit them to the DDR3 cache module for caching, extract the data frames formed after caching, package them and send them to the FLASH storage module; when performing dynamic updates, the ZYNQ main control module reads the data frames from the FLASH storage module and puts them into the designated space of the DDR3 cache module; the ZYNQ main control module is composed of an XC7Z020 chip and its configuration circuit.

[0028] The ZYNQ main control module uses split image encoding to mirror the bin file data, forming a split image file, which is then transmitted to the cache module for caching.

[0029] The split image partition includes FSBL, PL bitstream and ARM program, and can be divided into multiple PL bitstream and ARM program at the same time, including: PL bitstream 1, ARM program 1, PL bitstream 2 and ARM program 2; the position order is FSBL, PL bitstream 1, ARM program 1, PL bitstream 2 and ARM program 2.

[0030] When the ZYNQ main control module receives bin file data, the positions of FSBL, PL bit stream 1 and ARM program 1 remain unchanged, and the bin file data is placed in PL bit stream 2 and ARM program 2. The core image file of the ZYNQ main control module is BOOT.BIN, generated by the Xilinx toolchain (such as Vitis or SDK) using the bootgen tool. It is a binary container containing multiple logical partitions, each corresponding to a different functional module (such as FSBL, PL bitstream, and ARM program). Existing technology combines the FSBL, PL bitstream, and ARM program into a single BOOT.BIN file. This invention splits the FSBL, PL bitstream, and ARM program into a single image, allowing the FLASH storage module to simultaneously store multiple PL bitstreams and ARM programs. When the UWB wireless module B transmits data, it can be directly saved in the FLASH storage module. This is equivalent to dynamically loading another PL bitstream or ARM program during program execution, enabling uninterrupted program switching. The arrangement of the split image file in the FLASH storage module is as follows: Figure 5 As shown.

[0031] When the ZYNQ main control module receives the bin file data, it performs the following operations: Determine whether the message, preamble, and CRC in the UWB frame format are correct; Once the message, preamble, and CRC are all correct, the data portion of the bin file is parsed through data analysis to form a data frame, which is then passed to the DDR3 cache module for caching. After the DDR3 cache module receives all the data frames, it performs frame assembly, restores the entire bin file data, and provides it to the ZYNQ main control module for extraction.

[0032] The specified space is greater than or equal to the size of the data frame.

[0033] Specifically, the bin file sent by the host computer needs to be generated by the Xilinx toolchain (such as Vitis or SDK) using the bootgen tool. Configuring the offset address and file memory size within the tool ensures the file's validity. The host computer sends a maximum of 1024 bytes of frame data at a time, therefore data packetization is necessary, dividing the bin file data and placing it within each frame. Upon receiving the bin file, the UWB wireless module at the receiving end first checks the message, preamble, and CRC in the UWB frame format. If all three are correct, it parses the bin file data portion through data analysis, forming data frames that are then passed to the DDR3 cache module. The DDR3 cache module receives all data frames and assembles them to reconstruct the entire bin file data. During this process, a CRC check can be added after framing to ensure error-free framing. After framing is complete, the complete bin file data can be transferred to the FLASH storage module.

[0034] P400, the DDR3 cache module is used to cache the packaged bin file data, frame the packaged bin file data to form data frames, restore the entire bin file data, and provide it to the ZYNQ main control module for extraction; during dynamic updates, it is used to receive the data frames passed from the ZYNQ main control module, provide them to the PL end for download, and complete the configuration update; the DDR3 cache module is composed of a DDR3 chip and its configuration circuit; During the process of restoring the entire bin file data, you can add a CRC check after framing yourself.

[0035] When performing a dynamic update, the following should be included: After the DDR3 cache module receives the data frame from the ZYNQ main control module, it calls the official library function Xil_DCacheFlushRange to refresh the contents of the DDR3 cache module, ensuring that the PL end downloads successfully. Before the data frame is downloaded by the DDR3 cache module at the PL end, the core of the PL end is reset and initialized to restore the initial value; the core of the PL end includes SPI and GPIO; Specifically, after reloading, all states of the PL core will be restored to their initial values. When using the AXI_QUAD_SPI core, a reset operation must be performed before initialization after reloading; otherwise, the initialization of the SPI core will fail. Before the DDR3 cache module receives the data frame, a complete reset operation must be performed on the PL end; otherwise, the PL end will be abnormal. Judging from the program running status and the overall machine current display, the reloading process is successful, but the PL end does not actually start normally, and the ILA function cannot be used. At this time, simply calling PL_Reset in XDcfgInit can solve the problem of the PL end being abnormal.

[0036] The reason for the PL terminal anomaly: Reloading the bit stream (whether via PCAP or ICAP interface) does not reset or reinitialize the FPGA's internal clock management unit (MMCM / PLL) and ILA core. Resetting the entire PL terminal, however, simulates a "power-on" or "global reset," ensuring all hardware units start from a known clean state, which is completely consistent with the power-on state after directly programming the bin file data. All bits must be fully reloaded; attempting partial reloading will cause program errors and may trigger runaway during DMA transfers. The reloading method can be controlled through the PartialCfg parameter in the official library function: setting it to 0 indicates a full reload, and setting it to 1 indicates a partial reload.

[0037] P500, the FLASH storage module is used to store the data frames and provide them to the ZYNQ main control module for reading; the FLASH storage module is composed of FLASH chips and their configuration circuits.

[0038] P600, the power supply module is used to convert the input current power supply into a specified current power supply to power the system.

[0039] The power module consists of power conversion chips that can convert the input 12-28V DC power supply into the power required by the system, including 5V, 3.3V, 1.8V, 1.5V, and 1.0V current power supplies. The power module is composed of multiple power conversion chips, such as DC-DC converters and LDOs.

[0040] The wireless dynamic update system based on ultra-wideband wireless technology provided by this invention transmits bin file data from the ZYNQ main control module to the DDR3 cache module to complete data framing, and then to the FLASH storage module. During an update, the ZYNQ main control module reads the data frame to be updated from the FLASH storage module and transmits it to the PL terminal through the DDR3 cache module for update. Even when power is off, the system can still obtain the data frame to be updated from the FLASH storage module and transmit it to the DDR3 cache module to complete the current update operation. At the same time, it avoids the need for a power-off restart, saving the power-on initialization time of other modules on the hardware platform.

[0041] The main communication program, data processing program, and FLASH data of the wireless dynamic update system provided by this invention are stored on the PS terminal of the ZYNQ main control module; the PL terminal only provides the Block Design platform file.

[0042] The communication program is designed in C language and mainly includes DW1000 configuration, data packet framing, and data packet parsing. The data processing program is designed in C language. The data processing program mainly includes program configurations such as parsing data packets to restore the binary file packet structure, data caching, online loading of new mode register operations, storage address allocation, and software restart.

[0043] The FLASH data storage program is designed in C language. The FLASH data storage program mainly includes FLASH macro definition planning, FLASH read, write and erase underlying drivers.

[0044] The above-disclosed embodiments are merely specific examples of the present invention. However, the present invention is not limited thereto, and any variations that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A wireless dynamic updating system based on ultra-wideband wireless, characterized in that, The ZYNQ implementation includes a ZYNQ master module, a power module, a FLASH storage module, a DDR3 cache module, an SPI interface module and a UWB wireless module; The UWB wireless module is configured to receive bin file data to be updated sent by the upper computer, and transmit the bin file data to the SPI interface module to realize bin file data transmission between the UWB wireless module and the upper computer. The SPI interface module is configured to receive the bin file data and transmit the bin file data to the ZYNQ master module, and realize continuous sending of the bin file data by using double pointers. The ZYNQ master module is configured to receive the bin file data, transmit the bin file data to the DDR3 cache module after packetizing the bin file data, extract a data group frame formed after caching, and send the data group frame to the FLASH storage module after packetizing; when dynamic updating is performed, the ZYNQ master module reads the data group frame from the FLASH storage module and places the data group frame in a specified space of the DDR3 cache module. The DDR3 cache module is configured to cache the packetized bin file data, group frame the packetized bin file data, form a data group frame, restore the entire bin file data, and provide the ZYNQ master module with the bin file data for extraction; when dynamic updating is performed, the DDR3 cache module is configured to receive the data group frame transmitted by the ZYNQ master module, provide the data group frame to the PL end for downloading, and complete configuration updating. The FLASH storage module is configured to store the data group frame and provide the ZYNQ master module with the data group frame for reading. The power module is configured to convert an input current power into a specified current power to supply power to the system.

2. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, The power module is composed of a power conversion chip, and can convert an input 12-28V direct current power into required power of the system, including 5V, 3.3V, 1.8V, 1.5V and 1.0V current powers.

3. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, The ZYNQ master module adopts split mirror image coding to mirror partition the bin file data, forms a split mirror image file, and then transmits the split mirror image file to the cache module for caching.

4. The ultra-wideband wireless based wireless dynamic updating system of claim 3, wherein, The split mirror partition includes an FSBL, a PL bit stream and an ARM program, and can simultaneously divide multiple PL bit streams and ARM programs, including a PL bit stream 1, an ARM program 1, a PL bit stream 2 and an ARM program 2; the position sequence is FSBL, PL bit stream 1, ARM program 1, PL bit stream 2 and ARM program 2.

5. The ultra-wideband wireless based wireless dynamic updating system of claim 4, wherein, When the ZYNQ master module receives bin file data, the positions of the FSBL, the PL bit stream 1 and the ARM program 1 remain unchanged, and the bin file data is placed in the PL bit stream 2 and the ARM program 2.

6. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, When the ZYNQ master module receives the bin file data, the following operations are performed: determine whether a message, a preamble and a CRC in a UWB frame format are correct; When the message, preamble and CRC are all correct, the bin file data part is parsed by data analysis to form data frames, which are transmitted into the DDR3 cache module for caching; When the DDR3 cache module receives all the data frames, it frames and restores the entire bin file data, which is provided to the ZYNQ master module for extraction.

7. The ultra-wideband wireless based wireless dynamic updating system of claim 6, wherein, During the process of restoring the entire bin file data, CRC check can be added after framing.

8. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, When performing dynamic update, the following contents are included: After the ZYNQ master module transmits the data frames to the DDR3 cache module, the official library function Xil_DCacheFlushRange is called to refresh the contents in the DDR3 cache module. Before the data frames are downloaded to the PL end through the DDR3 cache module, the core of the PL end is reset and initialized to restore the initial value.

9. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, The specified space is greater than or equal to the size of the data frames.

10. The ultra-wideband wireless based wireless dynamic updating system of claim 1, wherein, The UWB wireless module uses error checking combined with timeout mechanism to determine whether the bin file data sent by the host computer is incorrect; when it is determined to be incorrect, the UWB wireless module is reset and reenters the receiving state; the host computer re-sends the current frame, and if there is no data frame, a handshake frame is sent.

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