Construction, simulation method and related device of mosfet current simulation model

Abstract

This application provides a method and apparatus for constructing and simulating a MOSFET current simulation model, which is used to simulate multi-gate finger MOSFETs. The method for constructing the MOSFET simulation model includes: acquiring drain current measurements of multiple test MOSFETs with different gate finger values ​​under a test voltage; calculating the intrinsic current of each test MOSFET under the test voltage based on the test voltage and drain current measurements; adjusting the target simulation parameters in the MOSFET simulation model based on the intrinsic current; and obtaining the intrinsic simulation model of the target MOSFET when the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within a specified error range under the test voltage. This application improves the accuracy of the MOSFET simulation model in simulating the current of multi-gate finger MOSFETs.

Description

Technical Field

[0001] The embodiments in this application relate to the field of semiconductor integrated circuit simulation modeling technology, specifically to a method for constructing a MOSFET simulation model, a method for simulating MOSFET current, and related apparatus. Background Technology

[0002] In the process of integrated circuit chip design, in order to improve chip performance without increasing chip area, MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) are usually designed as multi-finger structures. Each gate finger structure and its corresponding active region can be equivalent to a MOSFET unit, thus dividing a single MOSFET with a large width and length into several parallel MOSFET units with smaller width and length, saving chip area occupied by a single MOSFET and optimizing chip layout.

[0003] To predict the electrical characteristics of integrated circuits under various operating conditions and verify the feasibility of chip design, R&D personnel typically simulate the overall operating state of the integrated circuit and the individual devices within it under various operating conditions using integrated circuit simulation programs (Simulation Program with Integrated Circuit Emphasis, SPICE) and integrated circuit device simulation models before chip tape-out. They then combine the simulation results to adjust the chip design or manufacture the chip.

[0004] However, researchers found that the simulation accuracy of existing integrated circuit device simulation models for multi-gate finger MOSFETs is low when using them to simulate the total drain current of multi-gate finger MOSFETs. Summary of the Invention

[0005] In view of this, several embodiments of this application provide a method for constructing a MOSFET simulation model, a method for simulating MOSFET current, and related apparatus, so as to improve the simulation accuracy of the MOSFET simulation model for the total drain current of a multi-gate finger MOSFET.

[0006] In one aspect, an embodiment of this application provides a method for constructing a MOSFET simulation model, the MOSFET simulation model being used to simulate a multi-gate finger MOSFET; the method for constructing the MOSFET simulation model includes: acquiring drain current measurements of multiple test MOSFETs under a test voltage; in the multiple test MOSFETs, any two test MOSFETs have different gate finger values; calculating the intrinsic current of the multiple test MOSFETs under the test voltage based on the test voltage and the drain current measurements; wherein the intrinsic current is the total drain current through the test MOSFETs under the test voltage when the parasitic resistance is zero; adjusting the target simulation parameters in the MOSFET simulation model based on the intrinsic current, and obtaining a target MOSFET intrinsic simulation model when the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within a specified error range under the test voltage.

[0007] Optionally, the step of calculating the intrinsic current of the plurality of test MOSFETs under the test voltage based on the test voltage and the drain current measurement value includes: calculating the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and the drain current measurement value; and calculating the intrinsic current of the plurality of test MOSFETs under the test voltage based on the test voltage and the intrinsic resistance of the MOSFET.

[0008] Optionally, the step of calculating the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and the drain current measurement includes: calculating the circuit resistance corresponding to multiple test MOSFETs based on the test voltage and the drain current measurement; fitting the circuit resistance corresponding to the test MOSFET with the reciprocal of the number of gate fingers in the test MOSFET using a linear function model as the fitting model to obtain a first fitting result; using the slope of the first fitting result as the intrinsic resistance of the MOSFET and the ordinate of the first fitting result as the parasitic resistance.

[0009] Optionally, the step of adjusting the target simulation parameters in the MOSFET simulation model based on the intrinsic current, and obtaining the target MOSFET intrinsic simulation model when the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within a specified error range under the test voltage, includes: using a linear function model as the fitting model to fit the relationship between the intrinsic current of the test MOSFET under the test voltage and the gate index of the test MOSFET, obtaining a second fitting result; obtaining an intrinsic current target dataset based on the second fitting result, and inputting the intrinsic current target dataset into the MOSFET simulation model; adjusting the target simulation parameters in the MOSFET simulation model until the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within a specified error range under the test voltage, thus obtaining the target MOSFET intrinsic simulation model.

[0010] Optionally, the MOSFET simulation model is equipped with a model selection flag; the method for constructing the MOSFET simulation model further includes: adjusting the target simulation parameters in the MOSFET simulation model based on the drain current measurement value; and obtaining a target MOSFET measurement simulation model when the error between the simulated drain current measurement value output by the MOSFET simulation model and the drain current measurement value falls within a specified error range under the test voltage; wherein the values ​​of the target simulation parameters in the target MOSFET measurement simulation model are different from the values ​​of the target simulation parameters in the target MOSFET intrinsic simulation model, and the values ​​of the model selection flags corresponding to the target MOSFET intrinsic simulation model and the target MOSFET measurement simulation model are different.

[0011] Optionally, when the MOSFET simulation model is BSIM4, the target simulation parameters include at least one of threshold voltage, low field mobility, and saturation velocity.

[0012] In another aspect, one embodiment of this application provides a method for simulating MOSFET current, the method being used to simulate the intrinsic current of a multi-gate finger MOSFET; the method includes: obtaining the operating voltage and gate finger parameters of a target MOSFET; calling the intrinsic simulation model of the target MOSFET in the MOSFET simulation model to output the simulated intrinsic current of the target MOSFET under the operating voltage; wherein the simulated intrinsic current is the simulated value of the total drain current through the target MOSFET under the operating voltage when the parasitic resistance is zero.

[0013] Optionally, the MOSFET simulation model further includes a target MOSFET measurement simulation model; the MOSFET simulation model is equipped with a model selection flag; the MOSFET current simulation method further includes: when the model selection flag is set to a first value, calling the target MOSFET intrinsic simulation model to simulate the total drain current through the target MOSFET under the operating voltage; when the model selection flag is set to a second value, calling the target MOSFET measurement simulation model to simulate the total drain current through the target MOSFET under the operating voltage.

[0014] In another aspect, one embodiment of this application provides an electronic device, including: a memory and a processor, the memory storing a computer program executable on the processor, the processor executing the computer program to implement a method for constructing a MOSFET simulation model or a method for simulating MOSFET current as described in the above embodiments.

[0015] In another aspect, one embodiment of this application provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements a method for constructing a MOSFET simulation model or a method for simulating MOSFET current as described in the above embodiments.

[0016] In several embodiments provided in this application, the drain current of multiple test MOSFETs with different gate finger numbers under test voltage is obtained as drain current measurement values. The intrinsic current of multiple test MOSFETs under test voltage is calculated based on the test voltage and drain current measurement values. The intrinsic current is the total drain current through the test MOSFETs under test voltage when the parasitic resistance is zero. The target simulation parameters in the MOSFET simulation model are then adjusted based on the intrinsic current. When the error between the simulated intrinsic current output by the MOSFET simulation model under test voltage and the intrinsic current falls within a specified error range, the intrinsic simulation model of the target MOSFET is obtained. The unexpected effects achieved include: calculating the intrinsic current that excludes the influence of parasitic resistance using the drain current measurement values ​​obtained from multiple test MOSFETs with different gate finger numbers, and then adjusting the target simulation parameters of the MOSFET simulation model using the intrinsic current to obtain the intrinsic simulation model of the target MOSFET. This makes the output of the intrinsic simulation model of the target MOSFET more accurately reflect the intrinsic electrical characteristics of the gate finger MOSFET, thereby improving the simulation accuracy of the intrinsic current of the gate finger MOSFET when using the model for integrated circuit simulation. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in describing the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A top-view structural diagram of a multi-gate finger MOSFET provided for related technologies.

[0019] Figure 2 This is a schematic diagram illustrating the process of simulating the total drain current of a multi-gate finger MOSFET using an existing integrated circuit device simulation model, for related technologies.

[0020] Figure 3 A schematic diagram of the circuit structure of a multi-gate MOSFET in operation, provided for related technologies.

[0021] Figure 4 A comparative diagram showing the measured total drain current, theoretical total drain current, and simulated total drain current obtained by simulating a multi-gate finger MOSFET using existing integrated circuit device simulation models, for related technologies.

[0022] Figure 5 This is a flowchart illustrating the method for constructing a MOSFET simulation model provided in an embodiment of this application.

[0023] Figure 6 This is a schematic diagram of the first fitting result obtained by fitting the relationship between the circuit resistance of multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFETs, using a linear function as the fitting model, as provided in the embodiments of this application.

[0024] Figure 7 This is a schematic diagram of the fitting line obtained by fitting the relationship between the device resistance of multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFET, using a linear function as the fitting model, as provided in the embodiments of this application.

[0025] Figure 8 This is a flowchart illustrating the MOSFET current simulation method provided in an embodiment of this application.

[0026] Figure 9 This diagram illustrates the comparison between the simulated current and the actual current obtained by simulating the total drain current of a multi-gate finger MOSFET using the MOSFET simulation model provided in this application embodiment.

[0027] Structural designation explanation

[0028] 100. Multi-gate finger MOSFET; 110. Finger gate; 120. Common active region; 130. Common doped well region. Detailed Implementation

[0029] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0030] The accompanying drawings provided in this application are only schematic illustrations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component may be changed, and the layout of the components may also be more complex.

[0031] In the description of the embodiments of this application, it should be understood that the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," "center," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of the stated features.

[0032] In related technologies, to ensure that the current drive capability meets device design requirements, a single MOSFET requires a relatively long channel length, resulting in a large footprint for the MOSFET along the channel extension direction. Furthermore, a significant amount of space needs to be reserved at the edges of the active region and / or well region occupied by a single MOSFET to achieve electrical isolation from other devices. With the trend towards miniaturization and high integration in integrated circuits, the number of individual MOSFETs that can be placed in a smaller chip area is limited, restricting the improvement of overall chip performance.

[0033] To improve the overall performance of a chip with limited chip area, researchers have attempted to improve a single MOSFET into a multi-gate finger MOSFET.

[0034] Please see Figure 1When the gate index of the multi-gate MOSFET 100 is greater than or equal to 3, multiple finger gates 110 are arranged at intervals and share the same common active region 120 and the same common doped well region 130, forming an alternating "gate-active region-gate" structure. In this way, a single MOSFET is transformed into multiple parallel MOSFET units. On the one hand, adjacent finger gates 110 can share the active region between them. Within this active region, the drain of the MOSFET unit corresponding to one finger gate 110 can be formed, and the source of the MOSFET unit corresponding to the other finger gate 110 can also be formed. This transforms a single MOSFET with a long channel into multiple parallel MOSFET units with shorter channels, thereby improving the MOSFET current drive capability without significantly increasing the chip area. On the other hand, all finger gates 110 belong to the same device. The spacing between adjacent finger gates 110 only needs to meet the minimum spacing requirement under the manufacturing process node, without having to meet the isolation spacing requirement between different independent devices. Furthermore, multiple finger gates 110 sharing a common doped well region 130 can save the area of ​​the inter-well isolation region between independent doped well regions, thereby increasing the number of MOSFET devices that can be arranged in the same chip area and improving the chip processing speed.

[0035] Please see Figure 2 After modifying a single MOSFET into a multi-gate finger MOSFET, researchers used an integrated circuit device simulation model to simulate various performance parameters of multiple multi-gate finger MOSFETs with different gate finger numbers. The specific simulation process may include steps S110, S120, and S130.

[0036] S110: Measure the total drain current of multiple multi-gate MOSFETs with different gate index values ​​under the power supply voltage.

[0037] Please see Figure 3 For each multi-gate MOSFET 100, a drain-source voltage equal to the supply voltage (VDD) is applied across the drain and source terminals of the multi-gate MOSFET 100. And apply a gate-source voltage (Voltage between Gate and Source) to the gate and source terminals of the multi-gate MOSFET 100 to turn on the MOSFET. After that, the total current in the working circuit connected to the multi-gate MOSFET100 is... I Measurements were performed to obtain the measured total drain current of the multi-gate MOSFET 100.

[0038] S120: Adjust the model parameters of the existing integrated circuit device simulation model based on the measured total drain current to obtain the target integrated circuit device simulation model.

[0039] Researchers used BSIM4 (Berkeley Short-channel IGFET Model 4) and / or HiSIM (Hiroshima-university STARC IGFET Model), which are widely used in the industry, as the basic models. They input the measured total drain current into BSIM4 and / or HiSIM, adjusted the model parameters, and made the model output gradually approach the measured total drain current. When the error between the model output and the measured total drain current falls within a specified error range, for example, when the error between the model output and the measured total drain current falls within ±5%, the model with adjusted parameters is used as the simulation model of the target integrated circuit device.

[0040] S130: Using the target integrated circuit device simulation model, output the simulated total drain current through a multi-gate finger MOSFET at a given voltage as a function of the gate finger magnitude.

[0041] Please see Figure 4 After obtaining the simulation model of the target integrated circuit device, the researchers used the simulation model to simulate the relationship between the simulated total drain current and the gate index of multi-gate MOSFETs with different gate index numbers under a given voltage. Subsequently, a two-dimensional coordinate system was established with the gate index number as the abscissa and the total drain current as the ordinate. The simulated total drain current curve output by the simulation model of the target integrated circuit device, the measured total drain current data points, and the theoretical total drain current data points of multi-gate MOSFETs with different gate index numbers under a given voltage were plotted in this two-dimensional coordinate system.

[0042] Depend on Figure 4It can be seen that when the gate index of a multi-gate MOSFET is less than or equal to 3, the theoretical total drain current data points and the measured total drain current data points basically coincide, and the simulated total drain current curve is also close to both. However, as the number of gate fingers increases, the difference between the measured total drain current data points and the theoretical total drain current data points becomes increasingly larger, and the changing trends of the simulated total drain current curve and the measured total drain current data points are quite similar. Therefore, the error between the simulated total drain current curve and the theoretical total drain current data points continues to increase. That is, as the number of gate fingers increases, the simulation accuracy of the target integrated circuit device simulation model for the theoretical total drain current of the multi-gate MOSFET continuously decreases. When the gate index is greater than or equal to 6, the simulation accuracy of the target integrated circuit device simulation model can no longer meet the simulation accuracy requirements of the chip design stage.

[0043] The reason why the simulation accuracy of the above target integrated circuit device simulation model decreases continuously with the increase of the number of gate fingers is that the parasitic resistance effect is not accurately isolated and characterized in the process of simulating multi-gate finger MOSFETs using the target integrated circuit device simulation model.

[0044] Please continue reading. Figure 3 Ignoring parasitic resistance effects and assuming that the length, width, material, and other parameters of each gate finger structure in the multi-gate MOSFET 100 are identical, the theoretical total drain current through the multi-gate MOSFET 100 is a linear superposition of the drain currents of each MOSFET unit connected in parallel. Therefore, the drain current through each MOSFET unit is the product of the reciprocal of the number of gate fingers and the theoretical total drain current. In this case, adding one more gate finger structure is equivalent to adding one more MOSFET unit in parallel, and the increment of the theoretical total drain current is always equal to the drain current through each MOSFET unit.

[0045] However, structures such as metal interconnects, contact holes, and leads can introduce device resistance into the operating circuit connected to the multi-gate MOSFET 100. Parasitic resistance in series Parasitic resistance It will divide the voltage; therefore, the actual drain-source voltage of the multi-gate MOSFET 100 is... Less than the supply voltage. As the number of gate fingers increases, the number of parallel MOSFET cells increases, increasing the total drain current through the multi-gate MOSFET 100 as a whole. However, the drain current through each individual MOSFET cell decreases, thereby reducing the overall voltage division of the multi-gate MOSFET 100 device and decreasing parasitic resistance. The voltage drop across the gate increases. The measured total drain current is essentially the steady-state total drain current through the multi-gate MOSFET 100 after it is connected to the operating circuit. Therefore, with each additional gate finger, the increase in the measured total drain current is less than the increase in the theoretical total drain current. Since the model parameters of the target integrated circuit device simulation model are adjusted based on the measured total drain current, as the number of gate fingers increases, the error between the simulated total drain current output by the target integrated circuit device simulation model and the theoretical total drain current will gradually increase.

[0046] Therefore, it is necessary to provide a method for constructing a MOSFET simulation model, a method for simulating MOSFET current, and related devices to reduce the impact of parasitic resistance effects on the simulation accuracy of the MOSFET simulation model.

[0047] Please see Figure 5 One embodiment of this application provides a method for constructing a MOSFET simulation model. This MOSFET simulation model can be used to simulate multi-gate finger MOSFETs. Specifically, a multi-gate finger MOSFET can be an integrated circuit device that integrates several identical MOSFET cells in parallel within the same active region and doped well region. Each gate finger structure in a multi-gate finger MOSFET serves as the gate of a MOSFET cell. The gate finger structure can be made of polysilicon or materials such as tungsten (W), copper (Cu), or aluminum (Al). When the gate finger index of a multi-gate finger MOSFET is greater than or equal to 3, similar to related technologies, multiple gate finger structures can be arranged at intervals and can share the same active region and the same doped well region, forming an alternating "gate-active region-gate" structure.

[0048] To improve the simulation accuracy of the target MOSFET simulation model while reducing the workload of constructing it, the target MOSFET simulation model can be obtained by making local adjustments to an existing MOSFET simulation model. Therefore, in this embodiment, the MOSFET simulation model can be a BSIM4 or HiSIM series model.

[0049] In this embodiment, the method for constructing the MOSFET simulation model may include steps S210, S220 and S230.

[0050] S210: Obtain the drain current measurement values ​​of multiple test MOSFETs under the test voltage.

[0051] To improve the accuracy of the intrinsic simulation model of the target MOSFET for simulating the drain current of multi-gate finger MOSFETs, the drain current of multiple test multi-gate finger MOSFETs with different gate indexes can be measured at the same test voltage. That is, the drain current measurement value can be used as the basis for subsequent mathematical analysis to remove the influence of parasitic resistance voltage division effect in the drain current measurement value.

[0052] In this embodiment, the test MOSFET can be a multi-gate finger MOSFET used for measuring electrical characteristic parameters. Specifically, among the multiple test MOSFETs, any two test MOSFETs have different gate indexes. Taking three test MOSFETs as an example, the gate indexes of the test MOSFETs can be 1, 2, and 4, respectively. Apart from the different gate indexes, the other structural parameters of the different test MOSFETs, such as the geometric parameters and materials of each gate finger structure, the channel length, channel width, and active region doping concentration of each parallel MOSFET unit, are all the same, in order to reduce the interference of factors other than the gate index on the drain current measurement data.

[0053] To obtain the drain current measurement data of the test MOSFET, in this embodiment, the test voltage can be the voltage applied between the drain and source of the test MOSFET. For example, to make the drain current measurement data closer to the total drain current under actual operating conditions of the MOSFET device, the test voltage can be equal to the power supply voltage, i.e., the system supply voltage.

[0054] In this embodiment, the drain current measurement value can be the total drain current in the working circuit connected to the test MOSFET under the test voltage. Specifically, under the same test voltage, a semiconductor parameter analyzer can be used to measure the drain terminals of multiple test MOSFETs, and the total current passing through the drain terminals of the test MOSFETs is taken as the drain current measurement value.

[0055] S220: Calculate the intrinsic current of multiple test MOSFETs under the test voltage based on the test voltage and drain current measurement values.

[0056] To improve the simulation accuracy of the target MOSFET simulation model, the researchers used a mathematical analytical method to construct a system of simultaneous equations based on the obtained drain current measurements, and solved for the intrinsic current of each test MOSFET under the test voltage.

[0057] In this embodiment, the intrinsic current can be used to reflect the current drive capability of the MOSFET device itself. Specifically, the intrinsic current can be the total drain current of the MOSFET under the test voltage, assuming zero parasitic resistance.

[0058] To achieve quantitative decoupling of intrinsic resistance and parasitic resistance, reduce the impact of gate index on the simulation accuracy of MOSFET simulation model, and provide adjustment target data that reflects the intrinsic performance of MOSFET device for subsequent parameter adjustment of MOSFET simulation model, so that the performance parameter values ​​simulated by the target MOSFET intrinsic simulation model are closer to the intrinsic performance parameter values ​​of MOSFET device, in this embodiment, the step of calculating the intrinsic current of multiple test MOSFETs under the test voltage based on the test voltage and drain current measurement values ​​may include sub-steps S221 and S222.

[0059] S221: Calculate the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and drain current measurements.

[0060] Please continue reading. Figure 3 Without considering parasitic resistance Under the influence of voltage divider, the intrinsic current is essentially the result of applying the entire test voltage across the resistance of the MOSFET device. The current at both ends is calculated under ideal conditions based on Ohm's law. Therefore, to calculate the intrinsic current, it is necessary to first calculate the intrinsic resistance and parasitic resistance of the MOSFET.

[0061] In this embodiment, the intrinsic resistance of a MOSFET can be the equivalent resistance of each MOSFET cell connected in parallel within a MOS-FET, without considering the influence of parasitic resistance. Specifically, the intrinsic resistance of a MOSFET can be used to characterize the intrinsic channel conductivity of each MOSFET cell in the test MOSFET. The value of the intrinsic resistance of a MOSFET is affected by factors such as the geometry of the MOSFET cell, the manufacturing process of the test MOSFET, and the operating conditions of the test MOSFET. For example, geometric parameters such as the channel length and channel width of the MOSFET cell, manufacturing process parameters such as the channel doping concentration distribution, and operating condition parameters such as the gate-source voltage and temperature can all affect the value of the intrinsic resistance of the MOSFET. Since the several MOSFET cells connected in parallel in the test MOSFET are identical, the intrinsic resistance of each MOSFET cell is also the same.

[0062] In this embodiment, the parasitic resistance can be the equivalent resistance introduced into the working circuit connected to the test MOSFET by structures other than the intrinsic channel of each MOSFET cell in the test MOSFET. Specifically, the parasitic resistance can be introduced into the working circuit through structures such as metal interconnects, contact holes, and leads, and connected in series with the intrinsic resistance of the MOSFET. The value of the parasitic resistance can be affected by factors such as the topology of the working circuit, the integrated circuit manufacturing process, and the operating conditions of the working circuit. For example, circuit topology parameters such as the material of the metal interconnect layer, the contact hole structure, and the lead length; integrated circuit manufacturing process parameters such as the doping concentration and junction depth of the source / drain diffusion region of the MOSFET cell, and the layout design rules; and operating condition parameters such as temperature can all affect the value of the parasitic resistance.

[0063] To determine the intrinsic resistance and parasitic resistance of a MOSFET using mathematical analytical methods, the parasitic resistance in the working circuit connected to different test MOSFETs is kept constant under the same test conditions.

[0064] To simultaneously determine the intrinsic resistance and parasitic resistance of the MOSFET, suppress the interference of measurement errors on the determination of their resistance values, and improve the stability and reliability of the resistance determination results, in this embodiment, the step of calculating the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and drain current measurement values ​​may include sub-steps S2211 and S2212.

[0065] S2211: Calculate the circuit resistance corresponding to multiple test MOSFETs based on the test voltage and drain current measurement values.

[0066] Since the test voltage and drain current measurements are parameters of the overall working circuit connected to the corresponding test MOSFET, a system of simultaneous equations can be established based on the test voltage and drain current measurements of multiple test MOSFETs. Then, the total resistance of the working circuit corresponding to multiple test MOSFETs, i.e., the circuit resistance, can be calculated based on Ohm's law.

[0067] Please refer to Formula 1. In this embodiment, a first correlation can be established between the test voltage, the drain current measurement, the intrinsic resistance of the MOSFET, the parasitic resistance, and the gate index of the test MOSFET based on Ohm's law and the parallel resistance calculation rules.

[0068] Formula 1

[0069] in, This indicates the test voltage, and the unit can be volts (V). This indicates the gate index of the MOSFET being tested. Indicates the gate index quantity is The test MOSFET corresponds to the measured drain current value, which can be expressed in amperes (A). Indicates parasitic resistance. This indicates the intrinsic resistance of the MOSFET, and both can be measured in ohms (Ω).

[0070] Please refer to Formula 2. After the first correlation is established, taking the gate index of multiple test MOSFETs as 1, 2, and 4 as an example, the first set of simultaneous equations can be established based on the first correlation and the measured values ​​of the test voltage and drain current corresponding to the multiple test MOSFETs.

[0071] Formula 2

[0072] Please refer to Formula 3. Subsequently, the first correlation shown in Formula 1 can be mathematically transformed by dividing both sides of the equation by the measured drain current value, thus converting the first correlation into the second correlation.

[0073] Formula 3

[0074] in, Indicates the gate index quantity is The circuit resistance corresponding to the MOSFET being tested can be expressed in ohms (Ω). The meanings and units of the remaining parameters are the same as those of the corresponding parameters in the first correlation, and will not be repeated here.

[0075] Please refer to Formula 4. After the second correlation is established, taking the gate index of multiple test MOSFETs as an example of 1, 2, and 4 respectively, the first simultaneous equations can be mathematically transformed based on the second correlation, as shown in Formula 3, to obtain the second simultaneous equations.

[0076] Formula 4

[0077] Substitute the test voltage and the measured drain current values ​​corresponding to the multiple test MOSFETs into the second set of simultaneous equations shown in Formula 4 to calculate the circuit resistance corresponding to the multiple test MOSFETs.

[0078] S2212: Using a linear function model as the fitting model, fit the relationship between the circuit resistance of the tested MOSFET and the reciprocal of the number of gate fingers in the tested MOSFET to obtain the first fitting result.

[0079] After obtaining the circuit resistances corresponding to multiple test MOSFETs, in order to quantitatively separate the two coupling parameters, intrinsic resistance and parasitic resistance of the MOSFET, a linear function model can be used as the fitting model. The linear relationship between the circuit resistance corresponding to the test MOSFET and the reciprocal of the number of gate fingers in the test MOSFET can be determined by the data fitting method, and then the intrinsic resistance and parasitic resistance of the MOSFET can be obtained.

[0080] Please see Figure 6 In this embodiment, a first two-dimensional coordinate system can be established first, with the reciprocal of the number of gate fingers in the test MOSFET as the abscissa and the circuit resistance as the ordinate. The circuit resistance data points corresponding to multiple test MOSFETs are then plotted in this first two-dimensional coordinate system. Subsequently, using a linear function model as the fitting model, fitting methods such as the minimum absolute deviation method and the least squares method are employed to fit the relationship between the circuit resistance corresponding to multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFET, obtaining a first fitting result, which is then plotted in the first two-dimensional coordinate system.

[0081] Since the parasitic resistance is essentially the inherent resistance within the working circuit without considering the connection of the test MOSFET, and the change in circuit resistance with the reciprocal of the number of gate fingers in the test MOSFET is entirely caused by the change in the number of intrinsic resistances of the parallel MOSFETs, the ordinate of the first fitting result can be taken as the parasitic resistance, and the slope of the first fitting result can be taken as the intrinsic resistance of the MOSFET.

[0082] S222: Calculate the intrinsic current of multiple test MOSFETs under the test voltage based on the test voltage and the intrinsic resistance of the MOSFETs.

[0083] After calculating the intrinsic resistance and parasitic resistance of the MOSFET, the intrinsic current can be calculated directly based on Ohm's law and the calculation rules for parallel resistance, according to the test voltage and the calculated intrinsic resistance of the MOSFET.

[0084] Please refer to Formulas 5 and 6. In this embodiment, the overall device resistance of each test MOSFET can first be calculated based on the calculation rules of parallel resistance, according to the intrinsic resistance of the MOSFET and the gate index of each test MOSFET. Then, assuming the parasitic resistance is zero, a third correlation relationship is established between the test voltage, the device resistance of the test MOSFET, and the intrinsic current based on Ohm's law. Based on the third correlation relationship, the intrinsic current of each test MOSFET is calculated according to the test voltage and the resistance value of the test MOSFET.

[0085] Formula 5

[0086] Formula 6

[0087] in, Indicates the gate index quantity is The intrinsic current of the MOSFET is measured, and the unit can be amperes (A). Indicates the gate index quantity is The device resistance of the MOSFET is tested, and the unit can be ohms (Ω). The meanings and units of the remaining parameters are the same as those of the same parameters in the first and second correlation relationships, and will not be repeated here.

[0088] Please see Figure 7 First, multiple device resistance data points of the test MOSFETs can be plotted in the first two-dimensional coordinate system. Then, using a linear function model as the fitting model, and employing fitting methods such as the minimum absolute deviation method and the least squares method, the relationship between the device resistance of the multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFETs can be fitted. This yields a fitted straight line representing the relationship between the device resistance of the multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFETs, which is then directly plotted in the first two-dimensional coordinate system. Figure 7 It can be seen that the fitting line of the relationship between the device resistance of multiple test MOSFETs and the reciprocal of the number of gate fingers in the test MOSFET is essentially a straight line formed by translating the first fitting result along the vertical axis to the origin.

[0089] S230: Adjust the target simulation parameters in the MOSFET simulation model based on the intrinsic current. Under the test voltage, if the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within the specified error range, the target MOSFET intrinsic simulation model is obtained.

[0090] To improve the accuracy of the MOSFET simulation model in simulating the intrinsic current of MOSFETs, after obtaining the intrinsic current of each test MOSFET, the intrinsic current of each test MOSFET can be used as target data to adjust the target simulation parameters in the MOSFET simulation model. This allows the output of the MOSFET simulation model under the conditions of test voltage and a given number of gate fingers to gradually approach the intrinsic current of the test MOSFET with the same number of gate fingers. As a result, the final target MOSFET intrinsic simulation model can more accurately reproduce the current-voltage relationship under ideal conditions without parasitic resistance effects when simulating multi-gate finger MOSFETs.

[0091] In this embodiment, the step of adjusting the target simulation parameters in the MOSFET simulation model based on the intrinsic current, and obtaining the target MOSFET intrinsic simulation model when the error between the simulated intrinsic current and the intrinsic current of the MOSFET simulation model output falls within the specified error range under the test voltage, may include sub-steps S231, S232 and S233.

[0092] S231: Using a linear function model as the fitting model, fit the relationship between the intrinsic current of the MOSFET under the test voltage and the gate index of the MOSFET to obtain the second fitting result.

[0093] To save on process costs and time, the number of test MOSFETs and the drain current measurements obtained based on them is limited, resulting in a corresponding limitation of intrinsic current data for the test MOSFETs. Therefore, to improve the simulation accuracy of the intrinsic simulation model of the target MOSFET, a second fitting result can be obtained by fitting the relationship between the intrinsic current of the test MOSFET at the test voltage and the gate index magnitude in the test MOSFET. This second fitting result then provides a larger number of target intrinsic current data.

[0094] In this embodiment, the fitting method and process for obtaining the second fitting result are similar to those for obtaining the first fitting result in the above embodiment, and will not be repeated here.

[0095] S232: Obtain the intrinsic current target dataset based on the second fitting result, and input the intrinsic current target dataset into the MOS-FET simulation model.

[0096] In this embodiment, the intrinsic current target dataset can be used as a dataset for adjusting the model parameters of the MOSFET simulation model. Specifically, the intrinsic current target dataset can include the intrinsic currents of a large number of multi-gate MOSFETs with different gate finger numbers under the test voltage. Besides the intrinsic current data of the test MOSFET under the test voltage calculated in the above embodiment, the remaining data in the intrinsic current target dataset can be fitting data.

[0097] S233: Adjust the target simulation parameters in the MOSFET simulation model until, under the test voltage, the error between the simulated intrinsic current and the intrinsic current output by the MOSFET simulation model falls within the specified error range, thus obtaining the target MOSFET intrinsic simulation model.

[0098] In this embodiment, the values ​​of the target simulation parameters in the MOSFET simulation model can be continuously adjusted. After each adjustment, the error between the simulated intrinsic current output by the MOSFET simulation model and the corresponding data in the intrinsic current target dataset is calculated under the test voltage and the same gate index. If the error does not fall within the specified error range, the above process is repeated until the error falls within the specified error range. Then, the values ​​of the target simulation parameters in the MOSFET simulation model are determined, and the target MOSFET intrinsic simulation model is obtained.

[0099] Since an excessively small error range may cause the intrinsic simulation model of the target MOSFET to overfit the fitted data and lose its generalization ability, while an excessively large error range may not meet the simulation accuracy requirements in actual production, in order to reduce the risk of overfitting or underfitting of the intrinsic simulation model of the target MOSFET, in this embodiment, the specified error range can be 5%.

[0100] To simplify the process of obtaining the intrinsic simulation model of the target MOSFET from the MOSFET simulation model, only a small number of parameters in the MOSFET simulation model that have a critical impact on the simulation accuracy of the MOSFET drain current can be adjusted. Therefore, in this embodiment, when the MOSFET simulation model is BSIM4, the target simulation parameters may include the threshold voltage ( Low field mobility ( ) and saturation velocity ( At least one of the following: The threshold voltage can be the long-channel threshold voltage when the body-source voltage of the MOSFET device is zero, i.e., when the body-source is short-circuited.

[0101] To meet the simulation requirements under different simulation conditions before chip tape-out, and to achieve the construction of a dual MOSFET simulation model within the same model framework—one for simulating the intrinsic characteristic parameters of the MOSFET and the other for simulating the measurement characteristic parameters of the MOSFET—in some embodiments, the MOSFET simulation model may be equipped with a model selection flag. Correspondingly, the method for constructing the MOSFET simulation model may further include: adjusting the target simulation parameters in the MOSFET simulation model based on the drain current measurement value; and obtaining the target MOSFET measurement simulation model when the error between the simulated drain current measurement value output by the MOSFET simulation model and the actual drain current measurement value falls within a specified error range under test voltage.

[0102] In this embodiment, the target MOSFET measurement simulation model and the target MOSFET intrinsic simulation model are built based on the same fundamental model. Specifically, except for the different target dataset, the process of constructing the target MOSFET measurement simulation model is basically the same as the process of obtaining the target MOSFET intrinsic simulation model in the above embodiments, and will not be repeated here.

[0103] In this embodiment, the values ​​of the target simulation parameters in the target MOSFET measurement simulation model are different from those in the target MOSFET intrinsic simulation model, and the values ​​of the model selection flags corresponding to the target MOSFET measurement simulation model and the target MOSFET intrinsic simulation model are also different.

[0104] Please refer to Equations 7 and 8. Taking the MOSFET simulation model as BSIM4, and the target simulation parameters including saturation velocity and low-field mobility as an example, the values ​​of saturation velocity and low-field mobility can be determined based on the gate index and the model selection flag. For example, the model selection flag corresponding to the intrinsic simulation model of the target MOSFET can be 1, and the model selection flag corresponding to the measurement simulation model of the target MOSFET can be 0.

[0105] Formula 7

[0106] Formula 8

[0107] in, For saturation velocity, For low field mobility, , , , These are all parameters related to the gate index. Select a flag for simulation.

[0108] Please see Figure 8 Another embodiment of this application provides a method for simulating MOSFET current. This method can be used to simulate the intrinsic current of a multi-gate finger MOSFET. The method may include steps S310 and S320.

[0109] S310: Obtain the operating voltage and gate index of the target MOSFET.

[0110] In this embodiment, the operating voltage can be the drain-source voltage of the target MOSFET when it is in operation. Specifically, a semiconductor parameter analyzer can be used to measure the target MOSFET to obtain its operating voltage.

[0111] In this embodiment, the target MOSFET can be a multi-gate finger MOSFET. The gate finger number can be the number of gate finger structures in the target MOSFET.

[0112] S320: Calls the intrinsic simulation model of the target MOSFET in the MOSFET simulation model and outputs the simulated intrinsic current of the target MOSFET under the operating voltage.

[0113] In this embodiment, the simulated intrinsic current can be the simulated value of the total drain current through the target MOSFET under the operating voltage when the parasitic resistance is zero.

[0114] To meet the simulation requirements under different simulation conditions before chip tape-out, in some embodiments, the MOSFET simulation model may further include a target MOSFET measurement simulation model. Correspondingly, the MOSFET simulation model may be equipped with a model selection flag. In this case, the MOSFET current simulation method may further include: when the model selection flag is set to a first value, calling the target MOSFET intrinsic simulation model to simulate the total drain current through the target MOSFET under the operating voltage; when the model selection flag is set to a second value, calling the target MOSFET measurement simulation model to simulate the total drain current through the target MOSFET under the operating voltage. Specifically, the first value can be 1, and the second value can be 0.

[0115] In this embodiment, the values ​​of the target simulation parameters in the intrinsic simulation model of the target MOSFET are different from the values ​​of the target simulation parameters in the measurement simulation model of the target MOSFET. Specifically, when the MOSFET simulation model is BSIM4, the target simulation parameters may include the threshold voltage ( Low field mobility ( ) and saturation velocity ( At least one of the following: The threshold voltage can be the long-channel threshold voltage when the body-source voltage of the MOSFET device is zero, i.e., when the body-source is short-circuited.

[0116] Please see Figure 9 Researchers established a second two-dimensional coordinate system with gate index as the x-axis and total drain current as the y-axis. The drain current measurement data points, intrinsic current data points, and the output fitting curves of the intrinsic simulation model and the measurement simulation model of the target MOSFET obtained in the above embodiments were plotted together in the second two-dimensional coordinate system.

[0117] Depend on Figure 9It can be seen that the output fitting curve of the intrinsic simulation model of the target MOSFET is approximately a straight line and is quite close to the intrinsic current data point. The slope of the output fitting curve of the measurement simulation model of the target MOSFET gradually decreases with the increase of the number of gate fingers, and is quite close to the drain current measurement data point. When the number of gate fingers is less than or equal to 4, the output fitting curves of the two simulation models are quite close. As the number of gate fingers increases, the difference between the output fitting curves of the two simulation models gradually increases.

[0118] Another embodiment of this application provides an electronic device that may include a memory and a processor. The memory stores a computer program that can run on the processor. When the processor executes the computer program, it can implement the method for constructing a MOSFET simulation model or the method for simulating MOSFET current as described in the above embodiments.

[0119] Another embodiment of this application provides a computer-readable storage medium on which a computer program can be stored. When executed by a processor, the computer program can implement the method for constructing a MOSFET simulation model or the method for simulating MOSFET current as described in the above embodiments.

[0120] For other technical effects of the MOSFET current simulation method, electronic device, and computer-readable storage medium described in the above embodiments, please refer to other embodiments of this application for comparison and explanation, and they will not be repeated here.

[0121] In the MOSFET simulation model construction method, MOSFET current simulation method, and related apparatus provided in this application embodiment, the drain current of multiple test MOSFETs with different gate indexes under the test voltage is obtained as drain current measurement values. The intrinsic current of the multiple test MOSFETs under the test voltage is calculated based on the test voltage and the drain current measurement values. This intrinsic current is the total drain current through the test MOSFETs under the test voltage when the parasitic resistance is zero. The target simulation parameters in the MOSFET simulation model are then adjusted based on the intrinsic current. When the error between the simulated intrinsic current output by the MOSFET simulation model under the test voltage and the intrinsic current falls within a specified error range, the target MOSFET intrinsic simulation model is obtained. Furthermore, a model selection flag is set in the MOSFET simulation model, and the target simulation parameters in the MOSFET simulation model are directly adjusted based on the drain current measurement values ​​to obtain the target MOSFET measurement simulation model. The model used for simulation is determined according to the value of the model selection flag. Unexpected effects achieved include: calculating the intrinsic current, excluding the parasitic resistance effect, using drain current measurements obtained from test MOSFETs with multiple gate finger counts; then adjusting the target simulation parameters of the MOSFET simulation model using the intrinsic current to obtain the target MOSFET intrinsic simulation model. This allows the output of the target MOSFET intrinsic simulation model to more accurately reflect the intrinsic electrical characteristics of multi-gate finger MOSFETs. Furthermore, switching between the target MOSFET intrinsic simulation model and the target MOSFET measurement simulation model is achieved based on the model selection flag value. This improves the simulation accuracy of the intrinsic current of multi-gate finger MOSFETs using the target MOSFET intrinsic simulation model and meets the simulation requirements for different simulation conditions.

[0122] It is understood that the specific examples in this application are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of this application.

[0123] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0124] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0125] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0126] As should be understood from the several embodiments provided in this application, the disclosed electronic devices and computer-readable storage media can be implemented in other ways. For example, the embodiments of the electronic devices and computer-readable storage media described above are merely illustrative.

[0127] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method of constructing a MOSFET analog model, characterized by, The MOSFET simulation model is used to simulate multi-gate finger MOSFETs; the method for constructing the MOSFET simulation model includes: The drain current measurements of multiple test MOSFETs under test voltage are obtained respectively; among the multiple test MOSFETs, the gate index values ​​of any two test MOSFETs are different; Based on the test voltage and the measured drain current, the intrinsic current of each of the test MOSFETs under the test voltage is calculated; wherein, the intrinsic current is the total drain current through the test MOSFETs under the test voltage when the parasitic resistance is zero. Based on the intrinsic current, the target simulation parameters in the MOSFET simulation model are adjusted. Under the test voltage, when the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within a specified error range, a target MOSFET intrinsic simulation model is obtained, including: Using a linear function model as the fitting model, the relationship between the intrinsic current of the test MOSFET under the test voltage and the gate index of the test MOSFET is fitted to obtain a second fitting result; Based on the second fitting result, the intrinsic current target dataset is obtained, and the intrinsic current target dataset is input into the MOSFET simulation model. Adjust the target simulation parameters in the MOSFET simulation model until, under the test voltage, the error between the simulated intrinsic current output by the MOSFET simulation model and the intrinsic current falls within the specified error range, thus obtaining the target MOSFET intrinsic simulation model.

2. The method of constructing a MOSFET analog model according to claim 1, wherein, The step of calculating the intrinsic current of each of the test MOSFETs under the test voltage based on the test voltage and the measured drain current includes: Calculate the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and the measured drain current. The intrinsic current of each of the test MOSFETs at the test voltage is calculated based on the test voltage and the intrinsic resistance of the MOSFET.

3. The method of constructing a MOSFET analog model according to claim 2, wherein, The steps for calculating the intrinsic resistance and parasitic resistance of the MOSFET based on the test voltage and the measured drain current include: Based on the test voltage and the measured drain current, calculate the circuit resistance corresponding to each of the test MOSFETs; Using a linear function model as the fitting model, the circuit resistance corresponding to the test MOSFET is fitted to the relationship between the number of gate fingers in the test MOSFET and the change of the circuit resistance, resulting in a first fitting result. The slope of the first fitting result is taken as the intrinsic resistance of the MOSFET, and the ordinate of the first fitting result is taken as the parasitic resistance.

4. The method of constructing a MOSFET analog model according to claim 1, wherein The MOSFET simulation model is equipped with a model selection flag; The method for constructing the MOSFET simulation model also includes: Based on the drain current measurement value, the target simulation parameters in the MOSFET simulation model are adjusted. Under the test voltage, if the error between the simulated drain current measurement value output by the MOSFET simulation model and the drain current measurement value falls within a specified error range, a target MOSFET measurement simulation model is obtained. The values ​​of the target simulation parameters in the target MOSFET measurement simulation model are different from the values ​​of the target simulation parameters in the target MOSFET intrinsic simulation model, and the values ​​of the model selection flags corresponding to the target MOSFET intrinsic simulation model and the target MOSFET measurement simulation model are different.

5. The method for constructing a MOSFET simulation model according to any one of claims 1 to 4, characterized in that, When the MOSFET simulation model is BSIM4, the target simulation parameters include at least one of threshold voltage, low field mobility, and saturation velocity.

6. A method for simulating MOSFET current, characterized in that, The MOSFET current simulation method is used to simulate the intrinsic current of a multi-gate finger MOSFET; the MOSFET current simulation method includes: Obtain the operating voltage and gate index of the target MOSFET; The intrinsic current of the target MOSFET under the operating voltage is output by calling the intrinsic simulation model of the target MOSFET in the MOSFET simulation model; wherein, the intrinsic simulation current is the simulated value of the total drain current of the target MOSFET under the operating voltage when the parasitic resistance is zero, and the intrinsic simulation model of the target MOSFET is determined based on the construction method of the MOSFET simulation model according to any one of claims 1 to 5.

7. The method for simulating MOSFET current according to claim 6, characterized in that, The MOSFET simulation model also includes a target MOSFET measurement simulation model; the MOSFET simulation model is equipped with a model selection flag; the MOSFET current simulation method further includes: When the model selection flag is set to the first value, the intrinsic simulation model of the target MOSFET is invoked to simulate the total drain current through the target MOSFET under the operating voltage; When the model selection flag is set to the second value, the target MOSFET measurement simulation model is invoked to simulate the total drain current through the target MOSFET under the operating voltage.

8. An electronic device, comprising: A memory and a processor, the memory storing a computer program executable on the processor, characterized in that, when the processor executes the computer program, it implements a method for constructing a MOSFET simulation model as described in any one of claims 1 to 5 or a method for simulating MOSFET current as described in claim 6 or 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the method for constructing a MOSFET simulation model as described in any one of claims 1 to 5, or the method for simulating MOSFET current as described in claim 6 or 7.

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