Simulation test method and simulation test equipment for semiconductor device

Abstract

The invention discloses a simulation test method and simulation test equipment for a semiconductor device, and the method comprises the steps: carrying out the three-dimensional modeling based on the layout of the semiconductor device, and obtaining a three-dimensional model; based on the three-dimensional model, carrying out two-dimensional modeling along a first section direction of the three-dimensional source region to obtain a first two-dimensional model; based on the three-dimensional model, carrying out two-dimensional modeling along a second section direction of the three-dimensional body region to obtain a second two-dimensional model; based on the two-dimensional source region in the first two-dimensional model and the two-dimensional body region in the second two-dimensional model, determining a body electrode position, the body electrode position being located in the two-dimensional source region and / or the bottom boundary of the two-dimensional source region; according to the position of the body electrode, defining the body electrode in the first two-dimensional model to form a third two-dimensional model; and performing a two-dimensional simulation test on the third two-dimensional model. According to the invention, simulation resource saving and simulation accuracy can be considered.

Description

Technical Field

[0001] This invention relates to the field of semiconductor design, and more particularly to a simulation testing method and simulation testing equipment for semiconductor devices. Background Technology

[0002] In semiconductor manufacturing, it is common to see layout designs where the body electrode and the source electrode are arranged in a cross pattern, resulting in them not being on the same cross-section.

[0003] like Figure 1 As shown, both the N-type source region 11 and the P-type body region 21 are located within the P-well 20, and the N-type source region 11 and the P-type body region 21 are arranged alternately along the Y direction. To perform device electrical simulation to guide design improvements, the device needs to be modeled. In practice, a cross-section is obtained along the A1-A2 direction as shown... Figure 2 As shown, the cross-section is obtained along the B1-B2 direction. Figure 3 As shown, the N-type source region 11 and the P-type body region 21 are not on the same cross section. Correspondingly, the source electrode and the body electrode are not on the same cross section, making it impossible to successfully use the two-dimensional modeling of their coplanarity for electrical simulation.

[0004] To perform electrical simulations, the following two methods are commonly used: Method 1: Create a 3D model based on the layout and directly perform simulation testing on the model formed by the 3D model; Method 2: Place the P-type body region 21 and the body electrode on the side (e.g., Figure 4 (as shown) or bottom (as shown) Figure 5 (As shown).

[0005] However, if method one is used, it will consume a huge amount of simulation resources and time for larger devices. If method two is used, it cannot reflect the normal effect of bias voltage on shallower parts of the device, and for non-counteracting devices, the body electrode often cannot be placed on the side. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a simulation testing method and simulation testing equipment for semiconductor devices, so as to balance the conservation of simulation resources and the accuracy of simulation.

[0007] To solve the above-mentioned technical problems, the present invention provides a simulation testing method for semiconductor devices, comprising: performing three-dimensional modeling based on the layout of the semiconductor device to obtain a three-dimensional model, wherein the three-dimensional model includes a three-dimensional substrate, a three-dimensional well region and a three-dimensional drift region located within the three-dimensional substrate and adjacent along a first direction, a three-dimensional drain region located within the three-dimensional drift region, a plurality of three-dimensional source regions and a plurality of three-dimensional volume regions located within the three-dimensional well region, and source electrodes defined on the surface of the three-dimensional source regions, wherein the conductivity types of the three-dimensional source regions and the three-dimensional volume regions are opposite, and the plurality of three-dimensional source regions and the plurality of three-dimensional volume regions are alternately arranged along a second direction, the second direction being perpendicular to the first direction; based on the... A three-dimensional model is constructed by performing two-dimensional modeling along a first cross-sectional direction of the three-dimensional source region to obtain a first two-dimensional model, wherein the first cross-sectional direction is parallel to the first direction; based on the three-dimensional model, a two-dimensional model is constructed along a second cross-sectional direction of the three-dimensional volume region to obtain a second two-dimensional model, wherein the second cross-sectional direction is parallel to the first direction; based on the two-dimensional source region in the first two-dimensional model and the two-dimensional volume region in the second two-dimensional model, the position of the volume electrode is determined, wherein the position of the volume electrode is located within the two-dimensional source region and / or at the bottom boundary of the two-dimensional source region; according to the position of the volume electrode, a volume electrode is defined in the first two-dimensional model to form a third two-dimensional model; and two-dimensional simulation testing is performed on the third two-dimensional model.

[0008] Optionally, the method for determining the position of the volume electrode based on the two-dimensional source region in the first two-dimensional model and the two-dimensional volume region in the second two-dimensional model includes: obtaining the corresponding two-dimensional source region injection depth in the first two-dimensional model according to a preset concentration limit value; obtaining the corresponding two-dimensional volume region injection depth in the second two-dimensional model according to the preset concentration limit value; and determining the position of the volume electrode according to the two-dimensional source region injection depth, the two-dimensional volume region injection depth, and the preset depth.

[0009] Optionally, the preset concentration limit value is 1e19 atoms / cm³. 3 .

[0010] Optionally, the method for determining the position of the body electrode based on the two-dimensional source region injection depth, the two-dimensional body region injection depth, and a preset depth includes: comparing the two-dimensional source region injection depth, the two-dimensional body region injection depth, and the preset depth; when both the two-dimensional source region injection depth and the two-dimensional body region injection depth are less than the preset depth, determining the two-dimensional source region injection depth as the body electrode position; when either the two-dimensional source region injection depth or the two-dimensional body region injection depth is greater than the preset depth, and the other is less than the preset depth, taking the depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth as the body electrode position; when both the two-dimensional source region injection depth and the two-dimensional body region injection depth are greater than the preset depth, taking the depth region between the larger of the two-dimensional source region injection depth and the two-dimensional body region injection depth and the preset depth as the body electrode region.

[0011] Optionally, the method of defining a volume electrode in the first two-dimensional model to form a third two-dimensional model according to the volume electrode position includes: if the volume electrode position is the two-dimensional source region injection depth, then in the first two-dimensional model, the two-dimensional source region injection depth is defined as the volume electrode, where the two-dimensional source region is the part in the first two-dimensional model corresponding to the three-dimensional source region; if the volume electrode position is the depth region between the two-dimensional source region injection depth and the two-dimensional volume region injection depth, the greater of the two-dimensional source region injection depth and the two-dimensional volume region injection depth and the preset depth, then in the first two-dimensional model, the corresponding depth region in the two-dimensional source region is replaced and defined as an equipotential volume electrode region.

[0012] Optionally, the preset depth is 0.2 micrometers.

[0013] Optionally, the conductivity type of the three-dimensional well region and the three-dimensional volume region is P-type, and the conductivity type of the three-dimensional drift region, the three-dimensional drain region and the three-dimensional source region is N-type.

[0014] Optionally, the three-dimensional model further includes: a three-dimensional grating structure located on the surface of the three-dimensional substrate, and the three-dimensional grating structure spanning the boundary between the three-dimensional well region and the three-dimensional drift region along the first direction, and the three-dimensional grating structure also located on a portion of the surface of the three-dimensional source region and a portion of the surface of the three-dimensional volume region.

[0015] Accordingly, the technical solution of the present invention also provides a simulation testing device for performing any of the simulation testing methods described above.

[0016] Accordingly, the present invention also provides an electronic device, comprising: a memory for storing code; and a processor for executing the code in the memory to implement any of the simulation testing methods described above.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects: The semiconductor device simulation testing method and simulation testing equipment provided by the technical solution of the present invention obtain a first two-dimensional model by performing two-dimensional modeling along the first cross-sectional direction of the three-dimensional source region based on a three-dimensional model, and a second two-dimensional model by performing two-dimensional modeling along the second cross-sectional direction of the three-dimensional volume region based on the three-dimensional model. The position of the volume electrode is determined based on the two-dimensional source region in the first two-dimensional model and the two-dimensional volume region in the second two-dimensional model. The position of the volume electrode is located within the two-dimensional source region and / or at the bottom boundary of the two-dimensional source region. According to the position of the volume electrode, the volume electrode is defined in the first two-dimensional model to form a third two-dimensional model. Two-dimensional simulation testing is performed on the third two-dimensional model, thereby integrating two two-dimensional models into the same two-dimensional model and performing simulation testing on the integrated two-dimensional model. Thus, both the conservation of simulation resources and the accuracy of simulation are taken into account. Attached Figure Description

[0018] Figure 1 It is a type of map design; Figure 2 It corresponds Figure 1 A schematic cross-sectional view along the central axis from A1 to A2; Figure 3 It corresponds Figure 1 A cross-sectional view from B1 to B2 in the middle direction; Figure 4 This is a cross-sectional schematic diagram showing the P-type body region and body electrode positioned on the side. Figure 5 This is a cross-sectional schematic diagram showing the P-type body region and body electrode located at the bottom; Figure 6 This is a flowchart illustrating the simulation and testing method for semiconductor devices according to an embodiment of the present invention. Figure 7 This is a schematic diagram of the layout of a semiconductor device according to an embodiment of the present invention; Figure 8 This is a schematic diagram of a three-dimensional model in the simulation and testing method for semiconductor devices according to an embodiment of the present invention; Figure 9 It is along Figure 8 A schematic diagram of the first two-dimensional model along the first cross-sectional direction; Figure 10 It is along Figure 8 A schematic diagram of the second two-dimensional model along the second cross-sectional direction; Figure 11This is a flowchart illustrating the method for determining the position of the body electrode in an embodiment of the present invention; Figure 12 This is a schematic diagram of the two-dimensional source region injection depth in an embodiment of the present invention; Figure 13 This is a schematic diagram of the injection depth in a two-dimensional volume region according to an embodiment of the present invention; Figure 14 This is a schematic diagram of the body electrode defined in the third two-dimensional model of this invention; Figure 15 This is a schematic diagram of the equipotential electrode region defined in the third two-dimensional model of this invention.

[0019] Explanation of reference numerals in the attached figures: 11. N-type source region; 21. P-type body region; 20. P-trap; 210. Map drift area; 211. Map missing area; 221. Map source area; 222. Map body area; 230. Layout gate region; 300, Three-dimensional substrate; 310. Three-dimensional drift region; 311. Three-dimensional leak region; 320. Three-dimensional well region; 321. Three-dimensional source region; 330. Three-dimensional grid structure; 421. Two-dimensional source region; 422. Two-dimensional volume region; d1, injection depth of the two-dimensional source region; d2, injection depth of the two-dimensional volume region. Detailed Implementation

[0020] As described in the background section, existing electrical simulations struggle to balance resource conservation with simulation accuracy.

[0021] To address the aforementioned technical problems, the present invention provides a simulation testing method and equipment for semiconductor devices. This method involves creating a first two-dimensional model by performing two-dimensional modeling along a first cross-sectional direction of a three-dimensional source region based on a three-dimensional model. Then, a second two-dimensional model is created by performing two-dimensional modeling along a second cross-sectional direction of a three-dimensional volume region based on the three-dimensional model. The position of the volume electrode is determined based on the two-dimensional source region in the first two-dimensional model and the two-dimensional volume region in the second two-dimensional model. The volume electrode is located within the two-dimensional source region and / or at its bottom boundary. Based on the position of the volume electrode, a volume electrode is defined in the first two-dimensional model to form a third two-dimensional model. Finally, two-dimensional simulation testing is performed on the third two-dimensional model. This method integrates two two-dimensional models into a single two-dimensional model and performs simulation testing on the integrated model, achieving both resource conservation and high accuracy in simulation.

[0022] To make the above-mentioned objectives, features, and beneficial effects of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus. Additionally, directional terms such as above, below, up, down, upward, downward, left, right, etc., are used relative to exemplary embodiments as they are shown in the figures, with upward or upper directions pointing towards the top of the corresponding figure and downward or lower directions pointing towards the bottom of the corresponding figure.

[0024] Figure 6 This is a schematic flowchart of the simulation testing method for semiconductor devices according to an embodiment of the present invention.

[0025] Please refer to Figure 6 The simulation and testing method for semiconductor devices may include: step S100, performing three-dimensional modeling based on the layout of the semiconductor device to obtain a three-dimensional model.

[0026] In this embodiment, an LDMOS device is used as the semiconductor device to illustrate the simulation and testing method for the semiconductor device.

[0027] In other embodiments, the semiconductor device may also be CMOS.

[0028] Please refer to Figure 7 The layout of a semiconductor device may include: a layout substrate region (not shown), a layout drift region 210, a layout well region (not shown), a layout drain region 211, a plurality of layout source regions 221, a plurality of layout body regions 222 and a layout gate region 230.

[0029] The map drift region 210 is adjacent to the map trap region along direction X1.

[0030] The map leakage area 211 is located within the map drift area 210.

[0031] Both the source region 221 and the body region 222 are located within the trap region, and several source regions 221 and several body regions 222 are arranged alternately along the direction Y1.

[0032] The direction Y1 is perpendicular to the direction X1.

[0033] The layout gate region 230 spans the boundary between the layout drift region 210 and the layout well region.

[0034] Please refer to Figure 8 Correspondingly, based on Figure 7 The layout of the semiconductor device is modeled in three dimensions. The resulting three-dimensional model may include: a three-dimensional substrate 300, a three-dimensional drift region 310, a three-dimensional well region 320, a three-dimensional drain region 311, several three-dimensional source regions 321, several three-dimensional volume regions (not shown), and source electrodes (not shown).

[0035] Both the three-dimensional well region 320 and the three-dimensional drift region 310 are located within the three-dimensional substrate 300, and the three-dimensional well region 320 and the three-dimensional drift region 310 are adjacent to each other along the first direction X.

[0036] First direction X and Figure 7 The direction X1 in the middle corresponds to this.

[0037] The three-dimensional leak region 311 is located within the three-dimensional drift region 310.

[0038] Several three-dimensional source regions 321 and several three-dimensional volume regions are located within the three-dimensional trap region 320, and the several three-dimensional source regions 321 and several three-dimensional volume regions are arranged alternately along the second direction Y.

[0039] The second direction Y is perpendicular to the first direction X. The second direction Y is... Figure 7 The direction Y1 corresponds to the direction in the middle.

[0040] The conductivity type of the three-dimensional source region 321 is opposite to that of the three-dimensional volume region.

[0041] In this embodiment, the conductivity type of the three-dimensional well region 320 and the three-dimensional volume region is P-type, while the conductivity type of the three-dimensional drift region 310, the three-dimensional drain region 311 and the three-dimensional source region 321 is N-type.

[0042] The source electrode is defined on the surface of the three-dimensional source region 321.

[0043] Please continue to refer to this. Figure 8 In this embodiment, the three-dimensional model may further include a three-dimensional grating structure 330.

[0044] The three-dimensional gate structure 330 is located on the surface of the three-dimensional substrate 300, and the three-dimensional gate structure 330 spans the boundary between the three-dimensional well region 320 and the three-dimensional drift region 310 along the first direction X. In addition, the three-dimensional gate structure 330 is also located on part of the surface of the three-dimensional source region 321 and part of the surface of the three-dimensional volume region.

[0045] Please continue to refer to this. Figure 6 and Figure 9 The simulation test method for semiconductor devices may also include: step S200, based on the three-dimensional model, performing two-dimensional modeling along the first cross-sectional direction of the three-dimensional source region to obtain the first two-dimensional model.

[0046] The first cross-sectional direction is parallel to the first direction X.

[0047] It should be noted that, for ease of understanding, Figure 7 The diagram illustrates the cross-sectional directions C1-C2 corresponding to the first cross-sectional direction. Figure 9 This illustrates the first two-dimensional model obtained after two-dimensional modeling along the first cross-sectional direction of the three-dimensional source region. The first cross-sectional direction corresponds to the cutting plane of the three-dimensional source region, and the second cross-sectional direction corresponds to the cutting plane of the three-dimensional volume region.

[0048] Please continue to refer to this. Figure 6 and Figure 10 The simulation test method for semiconductor devices also includes: step S300, based on the three-dimensional model, performing two-dimensional modeling along the second cross-sectional direction of the three-dimensional volume region to obtain the second two-dimensional model.

[0049] The second cross-sectional direction is parallel to the first direction X.

[0050] It should be noted that, for ease of understanding, Figure 7 The diagram illustrates the cross-sectional directions D1-D2 corresponding to the second cross-sectional direction. Figure 10 This illustrates the second two-dimensional model obtained after two-dimensional modeling along the second cross-sectional direction of the three-dimensional source region.

[0051] Please continue to refer to this. Figure 6 The simulation test method for semiconductor devices may also include: step S400, determining the position of the body electrode based on the two-dimensional source region in the first two-dimensional model and the two-dimensional body region in the second two-dimensional model.

[0052] The bulk electrode is located within the two-dimensional source region and / or at the bottom boundary of the two-dimensional source region.

[0053] Please refer to Figure 11 Regarding step S400, the method for determining the position of the volume electrode based on the two-dimensional source region in the first two-dimensional model and the two-dimensional volume region in the second two-dimensional model may include: Step S410: Based on the preset concentration limit value, obtain the corresponding two-dimensional source region injection depth d1 in the first two-dimensional model.

[0054] Step S420: Based on the preset concentration limit value, obtain the corresponding two-dimensional volume injection depth d2 in the second two-dimensional model.

[0055] Step S430: Determine the position of the body electrode based on the two-dimensional source region injection depth d1, the two-dimensional body region injection depth d2, and the preset depth.

[0056] Please refer to Figure 12 Step S410 specifically refers to: in the first two-dimensional model, by determining the position corresponding to the preset concentration limit value in the two-dimensional source region 421 corresponding to the three-dimensional source region 321, the distance between the position and the surface of the two-dimensional source region 421 is the two-dimensional source region injection depth d1.

[0057] Preferably, the preset concentration limit value is 1e19 atoms / cm³. 3 1e19atoms / cm 3 It is a typical source region concentration limit in TCAD.

[0058] Please refer to Figure 13 Step S420 specifically refers to: in the second two-dimensional model, by determining the position corresponding to the preset concentration limit value in the two-dimensional volume region 422 corresponding to the three-dimensional volume region, the distance between the position and the surface of the two-dimensional volume region 422 is the two-dimensional volume region injection depth d2.

[0059] Preferably, d2 = d1.

[0060] Typically, the channel between the source and drain regions of a semiconductor device is on the surface of the semiconductor device, while the channel between the body and drain regions is below the depth of the source region. To avoid these two channels from interfering with each other, it is preferable to design d2=d1.

[0061] Regarding step S430, the method for determining the position of the body electrode based on the two-dimensional source region injection depth, the two-dimensional body region injection depth, and the preset depth may include: comparing the two-dimensional source region injection depth, the two-dimensional body region injection depth, and the preset depth D.

[0062] Specifically, when both the two-dimensional source region injection depth and the two-dimensional body region injection depth are less than a preset depth, the two-dimensional source region injection depth is determined as the body electrode location; when either the two-dimensional source region injection depth or the two-dimensional body region injection depth is greater than the preset depth and the other is less than the preset depth, the depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth is taken as the body electrode location; when both the two-dimensional source region injection depth and the two-dimensional body region injection depth are greater than the preset depth, the depth region between the larger of the two-dimensional source region injection depth and the preset depth is taken as the body electrode region.

[0063] For ease of understanding, the following is combined with Figures 11 to 13 Please provide a detailed explanation.

[0064] Please refer to Figures 11 to 13 Regarding step S430, the method for determining the position of the bulk electrode based on the two-dimensional source region injection depth d1, the two-dimensional volume region injection depth d2, and the preset depth includes: Step S431: Compare the two-dimensional source region injection depth d1, the two-dimensional volume region injection depth d2, and the preset depth D.

[0065] If d1 < D and d2 < D, execute step S432, taking d1 as the position of the body electrode.

[0066] If d1 < D and d2 > D, execute step S433, taking the depth region formed by d1 to d2 as the location of the body electrode.

[0067] If d1 > D and d2 < D, execute step S434, and take the depth region formed by d1 to d2 as the position of the body electrode.

[0068] If d1 > D, and d2 > D, and d1 > d2, execute step S435, and take the depth region formed by D to d1 as the body electrode region.

[0069] If d1 > D, and d2 > D, and d1 < d2, execute step S436, and take the depth region formed by D to d2 as the body electrode region.

[0070] Preferably, the preset depth D is 0.2 micrometers.

[0071] 0.2 micrometers is a typical source region depth in TCAD. If either the two-dimensional source region implantation depth d1 or the two-dimensional body region implantation depth d2 exceeds 0.2 micrometers, it indicates poor characterization of the semiconductor device, and the source region of the semiconductor device has an adverse effect on the remaining non-source regions below it. Therefore, if d1 < D and d2 < D, it indicates that the current semiconductor device design has good characterization, and the d1 position can be directly used as the body electrode position; if d1 < D and d2 > D, or if d1 > D and d2 < D, then the entire depth region formed by d1 to d2 is used as the equipotential body electrode position. This allows for the replacement of the region in the source region that exceeds the preset depth D and causes adverse effects with this equipotential body electrode position, resulting in a more accurate simulation; if d1 > D, d2 > D, and d1 > d2, then the depth region formed by D to d1 is used as the body electrode region, thereby... The entire depth region from D to d1 is used as the equipotential volume electrode position. When setting the volume electrode, the region in the source area that exceeds the preset depth D and causes adverse effects is replaced by the equipotential volume electrode position, so as to perform a more accurate simulation. If d1 > D, d2 > D, and d1 < d2, then the depth region from D to d2 is used as the volume electrode region. By using the entire depth region from D to d2 as the equipotential volume electrode position, the region in the source area that exceeds the preset depth D and causes adverse effects is replaced by the equipotential volume electrode position, so as to perform a more accurate simulation.

[0072] Please continue to refer to this. Figure 6 The simulation testing method for semiconductor devices further includes: step S500, defining a body electrode in the first two-dimensional model according to the body electrode position to form a third two-dimensional model.

[0073] Specifically, regarding step S500, the method for forming a third two-dimensional model based on the first two-dimensional model and the position of the bulk electrode may include: Step S510: If the two-dimensional source region injection depth is taken as the body electrode position, then in the first two-dimensional model, the two-dimensional source region injection depth is defined as the body electrode.

[0074] Step S520: If the depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth, the depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth and the preset depth is taken as the body electrode position, then in the first two-dimensional model, the corresponding depth region in the two-dimensional source region is replaced and defined as the equipotential body electrode region.

[0075] Please refer to Figure 14 In step S510, a third two-dimensional model is formed by defining the d1 position of the two-dimensional source region 421 as the bulk electrode in the first two-dimensional model.

[0076] Please refer to Figure 15 In step S520, a third two-dimensional model is formed by replacing the depth regions formed by d1 to d2, D to d1, or D to d2 in the two-dimensional source region 421 with the equipotential bulk electrode regions in the first two-dimensional model.

[0077] It should be noted that, for ease of understanding, Figure 14 and Figure 15 The main purpose is to illustrate the relationship between the two-dimensional source region 421 and the position of the bulk electrode.

[0078] Please continue to refer to this. Figure 6 The simulation test method for semiconductor devices also includes: step S600, performing two-dimensional simulation test on the third two-dimensional model.

[0079] In the semiconductor device simulation testing method of this invention, a first two-dimensional model is obtained by performing two-dimensional modeling along the first cross-sectional direction of the three-dimensional source region 321 based on the three-dimensional model. A second two-dimensional model is obtained by performing two-dimensional modeling along the second cross-sectional direction of the three-dimensional volume region based on the three-dimensional model. The position of the volume electrode is determined based on the two-dimensional source region 421 in the first two-dimensional model and the two-dimensional volume region 422 in the second two-dimensional model. The position of the volume electrode is located within the two-dimensional source region 421 and / or at the bottom boundary of the two-dimensional source region 421. According to the position of the volume electrode, the volume electrode is defined in the first two-dimensional model to form a third two-dimensional model. Two-dimensional simulation testing is performed on the third two-dimensional model. This integrates two two-dimensional models into the same two-dimensional model and performs simulation testing on the integrated two-dimensional model, thereby balancing the conservation of simulation resources and the accuracy of simulation.

[0080] Specifically, on the one hand, the channel between the source and drain regions of a semiconductor device is on the surface of the semiconductor device, while the channel between the body and drain regions and the electronic path between the body and the substrate are below the typical source region depth. On the other hand, the body region of a semiconductor device has low resistance and good conductivity, and can be regarded as an equipotential region. Therefore, the current situation in the simulation test based on the source electrode and the current situation in the simulation test based on the body electrode actually have very little interference with each other, or even no interference at all. In this embodiment, using this feature, the body electrode position located within the two-dimensional source region 421 and / or at the bottom boundary of the two-dimensional source region 421 is determined using the source region (two-dimensional source region 421) information in the first two-dimensional model and the body region (two-dimensional body region 422) information in the second two-dimensional model. This position does not interfere with the simulation of the current situation based on the source electrode, but can equivalently simulate the current situation based on the body electrode. Based on this body electrode position, the body electrode is defined in the first two-dimensional model, thereby realizing the formation of a third two-dimensional model that integrates the first two-dimensional model and the second two-dimensional model. Therefore, by conducting simulation tests on the integrated third-dimensional model, both simulation resource conservation and simulation accuracy can be achieved.

[0081] In practical applications, the simulation test results obtained by the simulation test method of this invention have an error rate of less than 5% compared with the structure obtained by the three-dimensional model simulation test, which can meet the accuracy requirements of simulation testing.

[0082] Accordingly, embodiments of the present invention also provide a simulation testing device for performing the simulation testing method as described in the above embodiments.

[0083] Accordingly, embodiments of the present invention also provide an electronic device, including: a memory for storing code; and a processor for executing the code in the memory to implement the simulation testing method as described in the above embodiments.

[0084] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of emulation testing of a semiconductor device, characterized by, The method comprises the following steps: three-dimensional modeling based on the layout of the semiconductor device to obtain a three-dimensional model, the three-dimensional model comprising a three-dimensional base, a three-dimensional well region and a three-dimensional drift region located in the three-dimensional base and adjacent along a first direction, a three-dimensional drain region located in the three-dimensional drift region, a plurality of three-dimensional source regions and a plurality of three-dimensional body regions located in the three-dimensional well region, and a source electrode defined on the surface of the three-dimensional source region, the three-dimensional source region having a conductivity type opposite to that of the three-dimensional body region, and the plurality of three-dimensional source regions and the plurality of three-dimensional body regions being arranged alternately along a second direction perpendicular to the first direction; two-dimensional modeling along a first cross-sectional direction of the three-dimensional source region based on the three-dimensional model to obtain a first two-dimensional model, the first cross-sectional direction being parallel to the first direction; two-dimensional modeling along a second cross-sectional direction of the three-dimensional body region based on the three-dimensional model to obtain a second two-dimensional model, the second cross-sectional direction being parallel to the first direction; determining a body electrode position based on a two-dimensional source region in the first two-dimensional model and a two-dimensional body region in the second two-dimensional model, the body electrode position being located in the two-dimensional source region and / or a bottom boundary of the two-dimensional source region; defining a body electrode in the first two-dimensional model according to the body electrode position to form a third two-dimensional model; performing two-dimensional simulation test on the third two-dimensional model.

2. The emulation test method of claim 1, wherein, The method for determining the body electrode position based on the two-dimensional source region in the first two-dimensional model and the two-dimensional body region in the second two-dimensional model comprises: obtaining a corresponding two-dimensional source region implantation depth in the first two-dimensional model according to a preset concentration limit value; obtaining a corresponding two-dimensional body region implantation depth in the second two-dimensional model according to the preset concentration limit value; determining the body electrode position according to the two-dimensional source region implantation depth, the two-dimensional body region implantation depth and a preset depth.

3. The emulation test method of claim 2, wherein, The preset concentration limit value is 1e19 atoms / cm 3 .

4. The emulation test method of claim 2, wherein, The method for determining the body electrode position according to the two-dimensional source region implantation depth, the two-dimensional body region implantation depth and a preset depth comprises: comparing the two-dimensional source region implantation depth, the two-dimensional body region implantation depth and the preset depth; when the two-dimensional source region implantation depth and the two-dimensional body region implantation depth are both smaller than the preset depth, determining the two-dimensional source region implantation depth as the body electrode position; when either of the two-dimensional source region implantation depth and the two-dimensional body region implantation depth is greater than the preset depth and the other is smaller than the preset depth, taking a depth region between the two-dimensional source region implantation depth and the two-dimensional body region implantation depth as the body electrode position; when the two-dimensional source region implantation depth and the two-dimensional body region implantation depth are both greater than the preset depth, taking a depth region between the greater one of the two-dimensional source region implantation depth and the two-dimensional body region implantation depth and the preset depth as the body electrode region.

5. The emulation test method of claim 4, wherein, The method for defining a body electrode in the first two-dimensional model according to the body electrode position to form a third two-dimensional model comprises: if the two-dimensional source region injection depth is the body electrode position in the first two-dimensional model, a two-dimensional source region injection depth of the two-dimensional source region is defined as a body electrode in the first two-dimensional model, and the two-dimensional source region is a part of the three-dimensional source region in the first two-dimensional model; if a depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth, or a depth region between the two-dimensional source region injection depth and the two-dimensional body region injection depth and the larger one of the two-dimensional source region injection depth and the two-dimensional body region injection depth and the preset depth is the body electrode position, the corresponding depth region in the two-dimensional source region is replaced and defined as an equipotential body electrode region in the first two-dimensional model.

6. The emulation test method of claim 4, wherein, The preset depth is 0.2 microns.

7. The method of claim 1, wherein The three-dimensional well region and the three-dimensional body region are P-type, and the three-dimensional drift region, the three-dimensional drain region and the three-dimensional source region are N-type.

8. The method of claim 7, wherein The three-dimensional model further comprises a three-dimensional gate structure, the three-dimensional gate structure is located on the surface of the three-dimensional base, and the three-dimensional gate structure crosses the boundary between the three-dimensional well region and the three-dimensional drift region along the first direction, and the three-dimensional gate structure is also located on part of the surface of the three-dimensional source region and part of the surface of the three-dimensional body region.

9. An emulation test device, characterized by, A device for performing the simulation test method as claimed in any one of claims 1 to 8.

10. An electronic device, comprising: Comprise: a memory for storing code; a processor for executing the code in the memory to implement the simulation test method of any one of claims 1 to 8.

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