SiC substrate surface defect detection system and method based on FPGA

Abstract

The invention discloses an FPGA-based SiC substrate surface defect detection system and method. The SiC substrate surface defect detection system comprises an image acquisition module, an FPGA processing module, an ARM processing module and an output module which are connected in sequence, and the ARM processing module is in bidirectional communication with the FPGA processing module, and is used for receiving the processed binary image, counting and classifying SiC surface defects through an improved Seed-Filling algorithm, and generating a defect detection result. The system and the method for detecting the surface defects of the SiC substrate based on the FPGA have the advantages of high parallelism of the FPGA and flexible control of the ARM, and the efficiency and the accuracy of monitoring the yield of the SiC substrate are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of image processing technology, and more specifically to an FPGA-based SiC substrate surface defect detection system and method. Background Technology

[0002] Silicon carbide (SiC), as a typical material for third-generation semiconductors, possesses characteristics such as wide bandgap, high breakdown voltage, high temperature stability, high frequency, and high power, making it a promising candidate for applications in power devices and other fields. However, defects and damage are inevitably introduced during the processing and fabrication of SiC materials. Furthermore, SiC applications require high yield rates and minimal defects. Therefore, rapidly screening for defects in SiC substrates and effectively counting and classifying them is crucial for monitoring the yield of SiC materials and achieving large-scale, high-quality SiC production.

[0003] As a third-generation semiconductor material, silicon carbide exhibits significant uniqueness in the formation mechanism, type, and impact of its substrate surface defects. These unique defects primarily stem from its distinctive crystal structure (e.g., polymorphic 4H-SiC), high-temperature PVT growth process, and high hardness (Mohs hardness 9.5). This results in a complex and diverse array of defects that are tightly coupled with internal stress, impurities, and the processing conditions, far exceeding the single defect modes of semiconductors like silicon (Si), gallium arsenide (GaAs), and gallium nitride (GaN) affected by oxidation or epitaxy. Consequently, SiC has a large number of relatively dense defects on its substrate surface, posing a significant challenge to defect identification. Furthermore, SiC's high refractive index (n≈2.65), anisotropic hexagonal crystal system, and wide bandgap (3.26 eV) result in weak optical response to defects (contrast less than 10-20%), appearing only as weak brightness / color gradients under a metallographic microscope. The high surface reflectivity (>30%) further blurs the edges due to glare artifacts, greatly increasing the difficulty of defect detection.

[0004] Currently, defect detection on SiC material surfaces includes both non-optical and optical methods. Non-optical methods include etching, transmission electron microscopy (TEM), and scanning electron microscopy (SEM), but etching often introduces irreversible damage. TEM and SEM methods suffer from bulky equipment, high costs, and are not suitable for automated production lines. Optical methods include optical microscopy, optical coherence tomography (OTC), and photoluminescence (PL), but these often require manual intervention. Manual intervention relies on human experience and suffers from inconsistent inspection standards, high error rates, and high labor costs. For automated inspection, methods include Fourier transform, edge detection algorithms, difference image processing, machine vision, and neural networks. The first three methods suffer from poor detection accuracy, while machine vision and neural networks consume too many resources and are unsuitable for edge deployment. Summary of the Invention

[0005] The purpose of this invention is to propose an FPGA-based SiC substrate surface defect detection system and method with high detection accuracy and high detection precision, but low power consumption.

[0006] This invention provides an FPGA-based SiC substrate surface defect detection system, comprising an image acquisition module, an FPGA processing module, an ARM processing module, and an output module connected in sequence. The image acquisition module is used to acquire metallographic microscope images of the SiC surface; The FPGA processing module is used to receive the metallurgical microscope image data and perform image preprocessing to obtain a processed binary image. The image preprocessing includes sequential image grayscale conversion, binarization, contrast-limited adaptive histogram equalization, and morphological processing. The ARM processing module communicates bidirectionally with the FPGA processing module to receive the processed binary image and to count and classify SiC surface defects using an improved Seed-Filling algorithm, thereby generating defect detection results. The output module is used to output the defect detection results through the serial port and the display port; The improved Seed-Filling algorithm includes an adaptive threshold seed filling module.

[0007] The improved Seed-Filling algorithm includes an adaptive threshold seed filling module, a weighted area calculation and defect severity scoring module, and a hierarchical seed filling and multi-scale defect merging module. The improved Seed-Filling algorithm specifically includes the following steps: a. Scanning steps: Scan each pixel in the processed binary image in a preset order; b. Starting from a single pixel, search for pixels with the same pixel value in the surrounding neighborhood and mark them as the same connected component.

[0008] When an unlabeled foreground pixel is encountered, it is used as a seed point to initialize a new connected component; c. Region filling and marking steps: Fill the connected region where the seed point is located, and record the boundary information of the connected region at the same time; The adaptive threshold seed filling module dynamically adjusts the local threshold T during the seed filling process. local The specific process includes: i) Determine the initial threshold for the seed point and set this initial threshold as the global threshold T. global ; ii) Starting from the seed point, fill the defect area. During the seed filling process, acquire the statistical characteristic parameters of the currently filled defect area in real time. The statistical characteristic parameters include the gray standard deviation σ, which reflects the non-uniformity of the filled defect area. region and the average gray level H of the filled defect area region ; iii) Based on the global threshold T global and the gray standard deviation σ of the filled defect area region Through formula The local threshold T is calculated. local , where α is an adjustment factor with a value of 0.36; iv) For the candidate pixel p to be judged, obtain its grayscale value g. p If satisfied If the condition is met, then the candidate pixel p is added to the current filled defect region; v) Repeat steps ii) to iv) until the defective areas on the SiC substrate surface are completely filled.

[0009] The improved Seed-Filling algorithm also includes simultaneously calculating and outputting the number of defects and the weighted area A during the seed-filling process. weighted The weighted centroid coordinates and severity score S are used to calculate the severity score. The specific process includes: First, for each pixel i within the filled defect area, obtain its grayscale value g. i And the minimum gray value g of the current defect area. min and the maximum grayscale value g max ; through formula The normalized weight ω of pixel i is calculated. i Normalized weights ω iUsed to characterize the contribution of pixel i in the defect region; Then, the normalized weights ω for all pixels within the defect region i Accumulate using the formula The weighted area A of the defect region was calculated. weighted ; Obtain the associated parameters of the defect region, including the region perimeter P and the area of ​​the minimum enclosing rectangle BBox of the defect region. area ; through formula The defect density D was calculated. density Introducing weighting coefficients β, γ, and δ, using the formula... The severity score S is calculated; the severity score S is used to prioritize defects and assist users in prioritizing high-risk defects, where β=0.5, γ=0.3, and δ=0.2. Based on the normalized weight ω of pixel i i and the coordinates of pixel i (x i y i ), through formula Calculate the weighted centroid coordinates of the defect region.

[0010] Furthermore, the improved Seed-Filling algorithm of this invention also includes: layered seed filling, multi-scale defect merging, and hierarchical output information during the seed filling process, specifically including the following: I) Determine two types of filling thresholds for surface defect detection on SiC substrates: a small-scale strict threshold for identifying small defects and a large-scale relaxed threshold for merging adjacent defects; II) The small-scale strict threshold is used to perform seed filling operation on the SiC substrate surface image, traversing the image and filling all small defect regions that meet the small-scale strict threshold condition, to obtain multiple initial independent defect regions. III) For the initial multiple independent defect regions, obtain the association parameters between every two adjacent independent defect regions, and combine them using the similarity formula. Calculate the merged similarity Sim between two adjacent independent defect regions; The correlation parameter includes: the centroid distance d between the two regions. centroid The average gray levels μ1 and μ2 of the two regions, and the scale parameter σ d , and σ d It is 1 / 10 of the width of the currently detected image; IV) If the merging similarity Sim>0.7, then the large-scale relaxed threshold is used to merge two adjacent independent defect regions into a single defect region, and the weighted area A of the merged defect region is updated. weighted Weighted centroid coordinates; If the merged similarity Sim ≤ 0.7, otherwise the independent states of the two regions are preserved; Repeat steps III) and IV) until all initial independent defect regions have been traversed and the merging judgment has been completed. Finally, the hierarchical information of the defects is output, which includes the total number of defects and the details of the sub-defects contained in each merged defect region.

[0011] This invention improves the sensitivity to gradient defects (such as shallow pits) by introducing adaptive seed filling, thereby reducing false positives caused by noise in SiC identification.

[0012] The image preprocessing includes sequential image grayscale conversion, binarization, contrast-limited adaptive histogram equalization, and morphological processing; it can reduce glare and enhance edge and local contrast, providing a strong feature image for the subsequent improved Seed-Filling algorithm.

[0013] SiC surface defects can cause uneven grayscale due to variations in lighting or material. To address the issue of missed defects with fixed thresholds, this invention proposes adaptive threshold seed filling, dynamically adjusting the threshold to avoid missed detections. Traditional area calculations only count pixels, ignoring the "severity" of defects. This invention proposes a weighted area calculation and defect severity scoring mechanism, introducing severity scores to prioritize defects and help users prioritize high-risk defects. Traditional single-layer filling algorithms may treat adjacent small defects as independent, while SiC surface defects often have a clustered distribution. This invention proposes a layered seed filling and multi-scale defect merging method to accurately determine the distribution type of defects.

[0014] Furthermore, in the SiC substrate surface defect detection system of the present invention, the adaptive histogram equalization process for contrast limitation during image preprocessing includes the following steps: 1) Divide the image to be enhanced into N×N non-overlapping sub-blocks of the same size, where N is a positive integer; 2) Calculate the grayscale histogram for each sub-block to obtain the pixel frequency corresponding to different grayscale levels in each sub-block; 3) Calculate the clipping threshold for each sub-block: Where T is the cropping threshold, L is the total number of pixels in the sub-block, H is the number of gray levels contained in the sub-block, and nclip is a custom cropping constraint factor; , where μ is the standard deviation of the image to be enhanced, σ is the mean of the image to be enhanced, and d is the adjustment constant, 3≤d≤5; 4) Redistribute pixel values ​​in the grayscale histogram of each sub-block: If the pixel frequency of a certain grayscale level is greater than the clipping threshold, adjust the pixel frequency of that grayscale level to the clipping threshold, and evenly distribute the redundant pixel frequency exceeding the clipping threshold to other grayscale levels of that sub-block. 5) Calculate the cumulative distribution function of the grayscale histogram of each sub-block after pixel value redistribution, and perform histogram equalization processing on the sub-block based on the cumulative distribution function; 6) Use bilinear interpolation to reconstruct the image of all equalized sub-blocks to obtain the enhanced image.

[0015] Furthermore, in the SiC substrate surface defect detection system of the present invention, the binarization in the image preprocessing process is a fixed threshold segmentation, and D(i) is the pixel value of the binarized result image; , where S(i) is the grayscale pixel value and Th is the set threshold size.

[0016] Binarization plays a crucial role in target processing and segmentation. The goal is to separate the target region of interest from irrelevant, information-free regions, thereby reducing image data volume and facilitating subsequent processing. The system described in this invention detects and classifies target defects. For images captured by a metallurgical microscope, the contrast between defects and the background is relatively strong. Defect extraction and segmentation can be achieved by directly applying a threshold to the grayscale image.

[0017] Furthermore, in the SiC substrate surface defect detection system of the present invention, the morphological processing in the image preprocessing process includes using a 3×3 matrix structure as the structuring element B, and filtering out small noise points through an operation of first etching and then dilation. Image morphological processing is a processing method based on the morphology of binary images. Morphological processing can often eliminate unnecessary components in the image structure, such as uneven edges or incomplete edge binary points in the original binary image. At the same time, morphological processing cannot change the general components of the original image, but only optimizes some details, which is beneficial to subsequent connected component processing.

[0018] Furthermore, in the SiC substrate surface defect detection system of the present invention, the image grayscale conversion during the image preprocessing process adopts a weighted processing method; , where S(i) is the grayscale pixel value, R, G, and B correspond to the red, green, and blue color components respectively, and a, b, and c correspond to the corresponding weights respectively.

[0019] The image acquisition module of this invention uses a metallurgical microscope, and the acquired images are represented in RGB format. It includes three image channels: R, G, and B, with corresponding data values ​​from 0 to 255. These three values ​​together determine the color of a pixel; therefore, a pixel in a typical image requires 24 bits. Converting a color image to a grayscale image essentially merges the data channels.

[0020] Furthermore, in the SiC substrate surface defect detection system of the present invention, the ARM processing module employs a four-connected-domain algorithm, starting from a seed point and continuously expanding to the four-neighborhood until the entire connected domain is scanned. The four-connected-domain algorithm determines the connectivity of the target pixel's top, bottom, left, and right pixels.

[0021] Furthermore, in the SiC substrate surface defect detection system of the present invention, the programmable I / O interface of the FPGA acquires the color image output by the metallographic microscope, performs image preprocessing operation on the PL end of the FPGA, stores the processed binary image data in the BRAM module, the PS end of the ARM reads the data in the BRAM and realizes the detection of SiC surface defects through the improved Seed-Filling algorithm, and finally outputs the defect quantification index through the serial port and displays the original image and the preprocessed image synchronously through the DP interface.

[0022] The SiC substrate surface defect detection system described in this invention acquires image data from a metallographic microscope, requiring preprocessing operations to be performed on an FPGA. In traditional CPUs, image processing is done frame-by-frame. This means that a frame must be completely transmitted to the processing unit before any computation can be performed. The advantages of FPGA processing are its real-time performance and high parallelism. In this invention's system, the FPGA employs a row-level, pixel-level preprocessing method.

[0023] Storage architecture design: FPGAs need to implement row-level and pixel-level image processing to leverage their parallelism for pipelined processing, trading area for speed to improve processing efficiency. Meanwhile, pixel-level image processing methods facilitate rapid, fine-grained image processing, and the design of the storage structure is a crucial step in achieving pixel-level processing.

[0024] When designing circuits for serially input image data, it is necessary to introduce storage structures to achieve parallel processing.

[0025] In the preprocessing design for grayscale image conversion and binarized image segmentation, grayscale image data can be obtained by performing mathematical calculations on a single pixel, without the need for additional memory for auxiliary calculations.

[0026] Erosion, dilation, and adaptive histogram equalization operations involve processing pixels around a given pixel. A 3×3 pixel window is required for these operations. The system employs a row buffer scheme; for input image data, it is fed into the double-ended RAM of the row buffer, allowing for direct output of the processed image data with only a delay of two rows of input data.

[0027] The data source for the ARM side is the image data after image preprocessing is completed on the PL side. After the image operation is completed on the PL side, the data is stored in the BRAM, and the control signal is pulled high to notify the ARM side to perform data acquisition.

[0028] Furthermore, in this invention, the communication between the PL end and the PS end, as well as the operation and output methods of the entire system, are all implemented on the Vitis development platform.

[0029] The Xilinx Vitis development environment provides various development kits, simulation platforms, and a complete library of hardware acceleration resources. It enables development at a higher level of abstraction, including C, C++, and OpenCL, and offers graphical and command-line development tools such as the Vitis compiler, analyzer, and debugger. Vitis can adapt resources and optimize hardware implementation based on given algorithms and software code, facilitating software algorithm implementation and significantly improving the efficiency of hardware engineers.

[0030] After designing the PL-side hardware circuit in Vivado, the corresponding hardware components, i.e., the XSA hardware components, are exported. The Vitis platform includes various software components and a software runtime environment. Based on the provided hardware information and the debugged software algorithm, the corresponding compiled files are exported and downloaded to the FPGA development board using a JTAG debugger.

[0031] This invention also provides a method for detecting surface defects on a SiC substrate based on an FPGA. The method is based on any of the SiC substrate surface defect detection systems described above, and specifically includes the following steps: S1. Image acquisition: The SiC surface is photographed using a metallographic microscope to obtain raw metallographic microscope images containing defects; S2, FPGA processing: The original metallurgical microscope image is input into the FPGA processing module, and grayscale conversion, binarization, contrast-limited adaptive histogram equalization and morphological processing are performed in sequence to obtain a processed and standardized binary image. S3, ARM Defect Identification: The processed and standardized binary image is transmitted to the ARM processing module, and the defect area is detected and analyzed by the improved Seed-Filling algorithm; S4. Result Output: The defect detection results are output synchronously through the serial port and display port.

[0032] The beneficial effects of the FPGA-based SiC substrate surface defect detection system and method described in this invention are as follows: First, this invention employs a combination of FPGA and ARM architectures for defect detection. The parallel architecture of the FPGA excels in high-speed image filtering, distortion correction, and noise removal. Image preprocessing algorithms are performed on the FPGA, while connected component algorithms are performed on the ARM, coordinating the overall process. By fully leveraging the high parallelism of the FPGA and the flexible control advantages of the ARM, a row-level and pixel-level pipelined preprocessing workflow is constructed. The FPGA, through row buffer design and a three-stage pipeline, implements preprocessing operations such as grayscale conversion, binarization, CLAHE enhancement, and morphological opening operations in hardware acceleration. Compared to the traditional frame-level serial processing of CPUs, data processing latency is significantly reduced, meeting the processing requirements of real-time image input for metallurgical microscopes. Furthermore, compared to GPU systems, this architecture eliminates the need for complex data transmission protocols. Efficient data interaction between the PL and PS ends significantly reduces data transmission latency. Based on the low power consumption of the FPGA and the low cost of the ARM, this invention addresses the pain points of traditional inspection equipment—bulky, energy-intensive, and difficult to deploy in pipelines—providing a feasible and reliable solution for online inspection in the large-scale production of SiC substrates.

[0033] Furthermore, this invention employs a modified Seed-Filling algorithm for defect detection. Starting from a single pixel, it searches for pixels with the same value in the surrounding neighborhood and marks them as the same connected component. Then, it continues searching for the next connected component, starting from other seed pixels. Its advantages include significantly reducing computational redundancy and repetitive stack operations by filling consecutive pixels or voxels at once, and it excels at handling connected defects, accurately filling irregularly shaped areas such as cracks or stains. Moreover, the adaptive threshold seed filling solves the problem of missed detection of shallow pit defects caused by fixed thresholds by dynamically adjusting local thresholds; the weighted area calculation and severity scoring mechanism breaks through the limitation of traditional methods that only count the number of pixels, and achieves quantitative ranking of defect risks by integrating grayscale weights, defect density and perimeter information, helping users to prioritize the handling of high-risk defects, and significantly improving the engineering guidance value of the detection results; the layered seed filling and multi-scale merging strategy effectively solve the problem of misjudgment of clustered defects, greatly improving the defect counting accuracy. Compared with the traditional Two-Pass algorithm and the basic Seed-Filling algorithm, it greatly enhances the ability to identify complex connected regions, and is suitable for detection scenarios with diverse and dense defects in SiC substrates.

[0034] Furthermore, the image preprocessing workflow of this invention specifically addresses the technical challenges of high reflectivity, low contrast, and glare artifacts in SiC substrates: the CLAHE algorithm, by improving the cropping constraint factor and combining the image standard deviation and mean, achieves adaptive contrast enhancement, increasing the grayscale difference between defects and the background by 3-5 times, significantly improving edge clarity; morphological opening operations, through a 3×3 matrix window with erosion followed by dilation, effectively filter out noise caused by surface glare, greatly improving the smoothness of defect area edges; combined with fast segmentation using fixed threshold binarization, the defect feature recognition of the preprocessed image is significantly improved, providing strong feature input for subsequent algorithms. This workflow completely replaces the traditional manual intervention detection method, not only eliminating the problem of inconsistent detection standards caused by reliance on human experience, thus reducing the detection error rate, but also greatly shortening the detection time of SiC substrates, reducing labor costs, and significantly improving the efficiency and accuracy of SiC substrate yield monitoring.

[0035] This invention also reproduces the Two-Pass connected component algorithm in a Python script and compares it with the system monitoring results. The results show that the connected component algorithm processing results are consistent with those of the Python script. Compared with the current mainstream CPUs and GPUs, FPGAs have the characteristics of low power consumption and low cost. Therefore, this invention solves the pain point of semiconductor substrate defect detection and promotes the industry towards high efficiency and intelligence. Attached Figure Description

[0036] Figure 1 This is a block diagram of the SiC substrate surface defect detection system described in Embodiment 1 of the present invention; Figure 2 This is based on the row cache storage structure principle described in Embodiment 1 of the invention; Figure 3 This is an internal connection diagram of the FPGA processing module described in Embodiment 1 of the present invention; Figure 4 This is a diagram of the system communication interconnection module in Embodiment 1 of the present invention; Figure 5 This is the original metallographic image displayed by the DP interface in Embodiment 1 of the present invention; Figure 6 This refers to the preprocessed image synchronously displayed via the DP interface in Embodiment 1 of the present invention; Figure 7 This is a simulation result diagram from Embodiment 1 of the present invention; Figure 8 This is a comparison chart of the results in Example 1 of the present invention. Detailed Implementation

[0037] To provide a clearer understanding of the technical features, objectives, and effects of the present invention, specific embodiments are now described in detail with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the detailed embodiments, conventional conditions or conditions provided by the manufacturer shall apply.

[0038] In the following description, when referring to the accompanying drawings, the same numbers in different drawings denote the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure. Specific Implementation Method 1

[0039] An FPGA-based SiC substrate surface defect detection system includes an image acquisition module, an FPGA processing module, an ARM processing module, and an output module connected in sequence. The image acquisition module is used to acquire metallographic microscope images of the SiC surface; The FPGA processing module is used to receive the metallurgical microscope image data and perform image preprocessing to obtain a processed binary image. The image preprocessing includes sequential image grayscale conversion, binarization, contrast-limited adaptive histogram equalization, and morphological processing. The ARM processing module communicates bidirectionally with the FPGA processing module to receive the processed binary image and to count and classify SiC surface defects using an improved Seed-Filling algorithm, thereby generating defect detection results. The output module is used to output the defect detection results through the serial port and the display port; The improved Seed-Filling algorithm includes an adaptive threshold seed filling module; The adaptive threshold seed filling module dynamically adjusts the local threshold T during the seed filling process. local The specific process includes: i) Determine the initial threshold for the seed point and set this initial threshold as the global threshold T. global ; ii) Starting from the seed point, fill the defect area. During the seed filling process, acquire the statistical characteristic parameters of the currently filled defect area in real time. The statistical characteristic parameters include the gray standard deviation σ, which reflects the non-uniformity of the filled defect area. regionand the average gray level H of the filled defect area region ; iii) Based on the global threshold T global and the gray standard deviation σ of the filled defect area region Through formula The local threshold T is calculated. local , where α is an adjustment factor with a value of 0.36; iv) For the candidate pixel p to be judged, obtain its grayscale value g. p If satisfied If the condition is met, then the candidate pixel p is added to the current filled defect region; v) Repeat steps ii) to iv) until the defective areas on the SiC substrate surface are completely filled. Specific Implementation Method Two

[0040] A method for detecting surface defects on a SiC substrate based on FPGA, specifically including the following steps: S1. Image acquisition: The SiC surface is photographed using a metallographic microscope to obtain raw metallographic microscope images containing defects; S2, FPGA processing: The original metallurgical microscope image is input into the FPGA processing module, and grayscale conversion, binarization, contrast-limited adaptive histogram equalization and morphological processing are performed in sequence to obtain a processed and standardized binary image. S3, ARM Defect Identification: The processed and standardized binary image is transmitted to the ARM processing module, and the defect area is detected and analyzed by the improved Seed-Filling algorithm; S4. Result Output: The defect detection results are output synchronously through the serial port and display port.

[0041] In other embodiments, the SiC surface defect categories supported by the improved Seed-Filling algorithm of this invention include: surface scratches, appearing as thin, elongated straight lines or arc-shaped grooves; dust particles / foreign objects, appearing as randomly distributed bright or dark spots; screw dislocations (TSD), edge dislocations (TED), and base plane dislocations (BPD), wherein TED and TSD are through-type dislocations, and TED and TSD are hexagonal pits with a base, while BPD is shell-shaped.

[0042] Example 1: An FPGA-based SiC substrate surface defect detection system, such as Figure 1 As shown, it includes an image acquisition module, an FPGA processing module, an ARM processing module, and an output module connected in sequence. The image acquisition module is used to acquire metallographic microscope images of the SiC surface; The FPGA processing module is used to receive the metallurgical microscope image data and perform image preprocessing to obtain a processed binary image. The image preprocessing includes sequential image grayscale conversion, binarization, contrast-limited adaptive histogram equalization, and morphological processing. The ARM processing module communicates bidirectionally with the FPGA processing module to receive the processed binary image and to count and classify SiC surface defects using an improved Seed-Filling algorithm, thereby generating defect detection results. The output module is used to output the defect detection results through the serial port and the display port.

[0043] In this embodiment 1, the improved seed-filling algorithm includes an adaptive threshold seed filling module; The adaptive threshold seed filling module dynamically adjusts the local threshold T during the seed filling process. local The specific process includes: i) Determine the initial threshold for the seed point and set this initial threshold as the global threshold T. global ; ii) Starting from the seed point, fill the defect area. During the seed filling process, acquire the statistical characteristic parameters of the currently filled defect area in real time; the statistical characteristic parameters include the gray standard deviation σ of the filled defect area. region and the average gray level H of the filled defect area region The gray standard deviation σ of the filled defect area region Used to reflect the non-uniformity of defective areas; iii) Based on the global threshold T global and the gray standard deviation σ of the filled defect area region Through formula The local threshold T is calculated. local , where α is an adjustment factor with a value of 0.36; iv) For the candidate pixel p to be judged, obtain its grayscale value g. p If satisfied If the condition is met, then the candidate pixel p is added to the current filled defect region; v) Repeat steps ii) to iv) until the defective areas on the SiC substrate surface are completely filled.

[0044] The improved Seed-Filling algorithm also includes simultaneously calculating and outputting the number of defects and the weighted area A during the seed-filling process. weighted The weighted centroid coordinates and severity score S are used to calculate the severity score. The specific process includes: First, for each pixel i within the filled defect area, obtain its grayscale value g. i And the minimum gray value g of the current defect area. min and the maximum grayscale value g max ; through formula The normalized weight ω of pixel i is calculated. i Normalized weights ω i Used to characterize the contribution of pixel i in the defect region; Then, the normalized weights ω for all pixels within the defect region i Accumulate using the formula The weighted area A of the defect region was calculated. weighted ; Obtain the associated parameters of the defect region, including the region perimeter P and the area of ​​the minimum enclosing rectangle BBox of the defect region. area ; through formula The defect density D was calculated. density Introducing weighting coefficients β, γ, and δ, using the formula... The severity score S is calculated; the severity score S is used to prioritize defects and assist users in prioritizing high-risk defects, where β=0.5, γ=0.3, and δ=0.2. Based on the normalized weight ω of pixel i i and the coordinates of pixel i (x i y i ), through formula Calculate the weighted centroid coordinates of the defect region.

[0045] The improved Seed-Filling algorithm further includes layered seed filling and multi-scale defect merging during the seed filling process, outputting hierarchical information. This hierarchical information includes the total number of defects and details of the sub-defects contained in each merged defect region, specifically including the following: I) Determine two types of filling thresholds for surface defect detection on SiC substrates: a small-scale strict threshold for identifying small defects and a large-scale relaxed threshold for merging adjacent defects; II) The small-scale strict threshold is used to perform seed filling operation on the SiC substrate surface image, traversing the image and filling all small defect regions that meet the small-scale strict threshold condition, to obtain multiple initial independent defect regions. III) For the initial multiple independent defect regions, obtain the correlation parameters between every two adjacent independent defect regions, wherein the correlation parameters include: the centroid distance d between the two regions. centroid The average gray levels μ1 and μ2 of the two regions, and the scale parameter σ d , and σ dIt is 1 / 10 of the width of the currently detected image; through the merging similarity formula Calculate the merged similarity Sim between two adjacent independent defect regions; IV) If the merging similarity Sim>0.7, then the large-scale relaxed threshold is used to merge two adjacent independent defect regions into a single defect region, and the weighted area A of the merged defect region is updated. weighted Weighted centroid coordinates; if the merged similarity Sim≤0.7, otherwise retain the independent state of the two regions; Repeat steps III) and IV) until all initial independent defect regions have been traversed and the merging judgment has been completed, and finally the hierarchical information of the defects is output.

[0046] In this embodiment 1, the adaptive histogram equalization for contrast limitation in the image preprocessing process includes the following steps: 1) Divide the image to be enhanced into N×N non-overlapping sub-blocks of the same size, where N is a positive integer; 2) Calculate the grayscale histogram for each sub-block to obtain the pixel frequency corresponding to different grayscale levels in each sub-block; 3) Calculate the clipping threshold for each sub-block: Where T is the cropping threshold, L is the total number of pixels in the sub-block, H is the number of gray levels contained in the sub-block, and nclip is a custom cropping constraint factor; , where μ is the standard deviation of the image to be enhanced, σ is the mean of the image to be enhanced, and d is the adjustment constant, 3≤d≤5; 4) Redistribute pixel values ​​in the grayscale histogram of each sub-block: If the pixel frequency of a certain grayscale level is greater than the clipping threshold, adjust the pixel frequency of that grayscale level to the clipping threshold, and evenly distribute the redundant pixel frequency exceeding the clipping threshold to other grayscale levels of that sub-block. 5) Calculate the cumulative distribution function of the grayscale histogram of each sub-block after pixel value redistribution, and perform histogram equalization processing on the sub-block based on the cumulative distribution function; 6) Use bilinear interpolation to reconstruct the image of all equalized sub-blocks to obtain the enhanced image.

[0047] The binarization in the image preprocessing process is a fixed threshold segmentation, and D(i) is the pixel value of the binarized result image; In the formula, S(i) is the grayscale pixel value, and Th is the set threshold value. In this embodiment 1, because SiC has a high refractive index (n≈2.65), anisotropic hexagonal crystal system, and wide bandgap (3.26 eV), the defect optical response is weak (contrast less than 10-20%), and it only shows a weak brightness / color gradient under a metallographic microscope. Therefore, setting the threshold to 66 is determined to be the best.

[0048] The morphological processing in the image preprocessing process includes using a 3×3 matrix structure as the structuring element B, and filtering out small noise points through an operation of erosion followed by dilation.

[0049] The image grayscale conversion during the image preprocessing process employs a weighted processing method. In the formula, S(i) is the grayscale pixel value, R, G, and B correspond to the red, green, and blue color components, respectively, and a, b, and c correspond to the corresponding weights.

[0050] The ARM processing module uses a four-connected domain algorithm, starting from a seed point and continuously expanding to the four-neighborhood until the entire connected domain is scanned.

[0051] The FPGA's programmable I / O interface acquires color images output from a metallographic microscope. Image preprocessing is performed at the PL end of the FPGA, and the processed binary image data is stored in the BRAM module. The PS end of the ARM reads the data in the BRAM and detects SiC surface defects through an improved Seed-Filling algorithm. Finally, the defect quantification index is output through the serial port, and the original image and the preprocessed image are displayed synchronously through the DP interface.

[0052] In this embodiment 1, a double-ended RAM with a width of twice the pixel was designed as a buffer structure in the specific Verilog HDL design. This buffers two rows of image data; rows 1 and 2 are output and buffered in RAM, becoming rows 2 and 3. When the next row of image data is input, the latest row, along with rows 2 and 3, constitutes three rows of real-time image data. Figure 2 As shown, the input image data is an M×N image. By setting the RAM depth of the row buffer to the depth of one row of data, row buffering can be achieved. Setting the RAM width to n times the data bandwidth creates an n+1 row data buffer, facilitating further data processing.

[0053] In this embodiment 1, an FPGA is used as the hardware platform. Its programmable I / O is used to acquire data from the input color image of the metallurgical microscope, separate the R, G, and B channels, perform grayscale conversion using the grayscale image calculation formula, and finally perform binarization, adaptive histogram equalization, and erosion and dilation operations.

[0054] The product coefficients corresponding to R, G, and B are all floating-point numbers. In FPGAs, floating-point operations require significant resources; therefore, a floating-point to fixed-point conversion method was adopted in the system design. First, the floating-point number is multiplied by 256, and the corresponding integer value is the amplification factor. Leveraging the high parallelism of the FPGA, a three-stage pipeline was designed to perform multiplication, addition, and further addition operations. The calculation result is then right-shifted to achieve a reduction by the corresponding factor, thus obtaining the grayscale image.

[0055] The grayscale image is binarized, and the grayscale image segmentation is obtained by using combinational logic to perform threshold judgment. The designed threshold is the center value of grayscale, 127.

[0056] The system employs a 3×3 sliding matrix window for opening operations. A row-buffered storage architecture is used to obtain three rows of image data, and the matrix window is generated after a two-clock-cycle delay. The opening operation involves first performing an erosion operation followed by a dilation operation. The erosion operation performs a bitwise AND operation on the nine image data points in the matrix; that is, if all pixel values ​​in the window are 255, the output pixel value is 255; otherwise, the output pixel value is 0. The dilation operation performs a bitwise OR operation on the nine image data points in the matrix; that is, if all pixel values ​​in the window are 0, the output pixel value is 0; otherwise, the output pixel value is 255.

[0057] The preprocessing module includes a grayscale conversion module, a threshold judgment module, an adaptive histogram equalization module, an erosion module, and a dilation module. The internal module connections are designed as follows: Figure 3 As shown.

[0058] The data transmission process is similar. The image information is input through the rgb2ycbcr module, and a data comparator is used to perform threshold segmentation on the output o_y_8b signal. The coor module erodes the binary image, and the expan module implements image dilation.

[0059] The above modules are packaged and encapsulated, and their ports are brought out. After data processing is completed, the data is transmitted to BRAM to facilitate data interaction with the ARM terminal.

[0060] In this embodiment 1, the FPGA development board used by the system is equipped with four 1GB high-speed DDR4 SDRAM chips and 20.6Mb of Block RAM resources. Conventional FPGA development boards usually have off-chip memory and on-chip memory. Off-chip memory has the advantage of large capacity, but higher latency and requires specially written bus interface. The binary image after binarization thresholding occupies little memory and the system has high real-time requirements, so the system uses BRAM for small batch data interaction.

[0061] In the Vivado development software, hardware design utilizes the AXIBRAMController module in the IP library, which allows control of the BlockRAM via the AXI bus. The introduction of the AXI bus enables the PS (Power Switch) to directly control the read and write operations of the BlockRAM, facilitating timely data transfer.

[0062] In the system design, the PL-side BRAM control module is responsible for the actual control of the BRAM module. The control logic is as follows: after detecting that the BRAM image data is completely written, the start signal is pulled high, and the preprocessing module begins working. After the PL-side completes image preprocessing, the done signal is pulled high, and the PS-side reads the BRAM data. The interconnection between the PS-side and PL-side is achieved through the built-in AXI bus BRAM controller. The data interaction module between the PS-side and PL-side is connected as follows: Figure 4 As shown.

[0063] The system operates as follows: The system needs to run completely on Vitis. The program's workflow is as follows: Import the image data into the Vitis platform; The PS terminal writes data to the BRAM via the AXI bus; The PL terminal reads data from the control terminal. Perform image preprocessing operations; PL preprocessing complete, write back to BRAM; Notify the PS to read the BRAM; Perform connected component algorithm on the PS side; Output and print the results; Meanwhile, the system introduces an interrupt service routine. The purpose of the interrupt is to better coordinate the linkage operation between the PS end and the PL end. When the PL end finishes preprocessing the image, a GPIO interrupt is triggered. That is, after receiving the PL end's work completion signal, the relevant operation on the PS end is executed.

[0064] In the specific detection process based on the SiC substrate surface defect detection system described in Embodiment 1, the SiC surface is first photographed using a metallographic microscope to obtain an original metallographic microscope image containing the defects, such as... Figure 5 As shown.

[0065] The original metallurgical microscope image is then input into the FPGA processing module, where grayscale conversion, binarization, adaptive histogram equalization with contrast limiting, and morphological processing are performed sequentially to obtain a processed, standardized binary image; as shown. Figure 6 As shown.

[0066] The processed and standardized binary image is transmitted to the ARM processing module, and the defective region is detected and analyzed by the improved Seed-Filling algorithm; Finally, the defect detection results are output synchronously via serial port and display port. The results are also displayed synchronously via DP interface. Figure 5 The original image shown, Figure 5 There are a total of 11 defects, which correspond to 7 screw dislocation defects, 2 base plane dislocation defects, and 2 dust particle defects. Figure 6 The preprocessed image shown, after preprocessing, yields a binarized image that accurately displays the shape and grayscale features of the defect; and the defect quantification indicators are output via serial port, such as... Figure 8 As shown, this displays the precise coordinates and area shape data of the printing defect.

[0067] Figure 7 This is a simulation waveform diagram for image preprocessing on the FPGA side. The first row contains the image input data, and subsequent rows represent the image "windowing" process: the waveforms in array_00 and array01 are displayed with a 1-clk delay, corresponding to the 1-clk input of the input data; the waveforms in array_10 and array20 are displayed with a 1-clk delay, corresponding to the 1-line input of the row buffer. The waveform display is as expected, the sliding matrix window data acquisition is normal, and it provides the basic processing module for all preprocessing operations.

[0068] The entire FPGA simulation also includes file processing. The Vivado simulation platform software is used to import the RGB data (txt file) of the defect image, convert it into a waveform input, and after passing through the FPGA's preprocessing circuit module, the preprocessed image data is exported and displayed using a Python script. The system then verifies whether the image display meets expectations.

[0069] The improved Seed-Filling algorithm described in this invention was used on the ARM side for subsequent processing, and debugging was performed on the Vitis platform using printing. To verify the correctness of the improved Seed-Filling algorithm, another connected component algorithm was reproduced in a Python script. Specifically, the Two-Pass algorithm was used. This algorithm is a classic connected component labeling method widely used in computer vision, characterized by its simplicity and accuracy. It has been included in mainstream image processing libraries such as OpenCV and is a recognized standard reference algorithm in academia and industry. This method completes connected component labeling by scanning the image twice: the first scan establishes adjacency relationships between pixels and assigns temporary labels, and the second scan unifies the labels according to the equivalence table, accurately identifying all connected regions in the image. However, compared with the method described in this invention, the Two-Pass algorithm requires additional label storage space and equivalence table maintenance overhead, resulting in higher memory consumption when processing large-scale images; its two full-image scans also lead to longer processing times, making it difficult to meet real-time requirements; furthermore, this algorithm requires complex data structures for hardware implementation, making it unsuitable for deployment on resource-constrained embedded FPGA platforms.

[0070] The processing results of the two are compared to verify the improved Seed-Filling algorithm performed on the PS end of the present invention. The final verification result also verifies the functionality of the entire system.

[0071] The results show that, Figure 8 As shown, the improved Seed-Filling algorithm designed on the PS side in this invention functions normally and is consistent with the results of the connected component algorithm in the Python script. Figure 8 The left side shows the results of the connected component algorithm using a Python script, while the right side shows the results of the FPGA-based SiC substrate surface defect detection system described in this invention.

Claims

1. An FPGA-based SiC substrate surface defect detection system, characterized in that, The image acquisition module, the FPGA processing module, the ARM processing module and the output module are sequentially connected; The image acquisition module is used for acquiring a metallographic microscope image of a SiC surface; The FPGA processing module is used for receiving the metallographic microscope image data and performing image preprocessing to obtain a processed binary image; the image preprocessing includes image grayscale conversion, binarization, contrast-limited adaptive histogram equalization and morphological processing in sequence; The ARM processing module is in bidirectional communication with the FPGA processing module, is used for receiving the processed binary image, and realizes counting and classification of SiC surface defects through an improved Seed-Filling algorithm to generate a defect detection result; The output module is used for outputting the defect detection result through a serial port and a display port. The improved Seed-Filling algorithm includes an adaptive threshold seed filling module. The adaptive threshold seed filling module dynamically adjusts the local threshold T in the seed filling process local The specific process includes: i) determining an initial threshold value for the seed point, setting the initial threshold value as the global threshold value T global ; ii) performing defect area filling with the seed point as a starting point, and acquiring statistical characteristic parameters of the current filled defect area in real time during the seed filling process; the statistical characteristic parameters include a gray standard deviation σ region and an average gray H region of the filled defect area, which reflect the non-uniformity of the filled defect area. iii) calculating the local threshold T by the formula local wherein a is an adjustment factor, and takes a value of 0.36;​ iv) for the candidate pixel p to be judged, obtaining its gray value g p , if the condition of is satisfied, the candidate pixel p is added to the current filled defect region; v) repeating steps ii) to iv) until complete filling of the defect area on the SiC substrate surface is completed.

2. The SiC substrate surface defect detection system of claim 1, wherein: The improved Seed-Filling algorithm further comprises: in the seed filling process, synchronously calculating and outputting the number of defects, the weighted area A weighted , the weighted centroid coordinates, and the severity score S; the specific process comprises: First, for each pixel i in the filled defect region, its gray value g i , the minimum gray value g min and the maximum gray value g max of the current defect region are obtained. The normalized weight ω i of pixel i is calculated by the formula i , which represents the contribution of pixel i in the defect region. Then, the normalized weight ω of all pixels in the defect area is calculated i The accumulation is carried out, and the weighted area A of the defect area is calculated by the formula weighted ;​ Secondly, the associated parameters of the defect area are acquired, and the associated parameters include an area perimeter P and a minimum enclosing rectangle area BBox of the defect area area ; a defect density D is calculated through a formula density ; weight coefficients β, γ and δ are introduced, a severity score S is calculated through a formula ; the severity score S is used for priority sorting of the defects and assisting a user in preferentially processing high-risk defects, wherein β=0.5, γ=0.3 and δ=0.2.​ Based on the normalized weight ω of the pixel i i and the coordinates (x i , y i ) of the pixel i, the weighted centroid coordinates of the defect area are calculated by the formula ​ 3. The SiC substrate surface defect detection system of claim 2, wherein: The improved Seed-Filling algorithm further includes: in the seed filling process, hierarchical seed filling, multi-scale defect merging and output of hierarchical information; specifically including the following: I) determining two types of filling thresholds for SiC substrate surface defect detection: a small-scale strict threshold for identifying small defects and a large-scale loose threshold for merging adjacent defects; II) performing a seed filling operation on the SiC substrate surface image using the small-scale strict threshold, traversing the image and filling all small defect areas meeting the small-scale strict threshold condition to obtain an initial plurality of independent defect areas; III) for the initial plurality of independent defect regions, obtaining a correlation parameter of each two adjacent independent defect regions, calculating a merging similarity Sim of the two adjacent independent defect regions by a merging similarity formula , The correlation parameters include: the distance d of the two region centers centroid , the average gray levels μ1 and μ2 of the two regions, and the scale parameter σ d , and σ d is 1 / 10 of the current detection image width IV) if the merging similarity Sim > 0.7, then merging the two adjacent independent defect regions into one integral defect region by using the large-scale loose threshold, and updating the weighted area A of the merged defect region weighted , the weighted centroid coordinates; If the merging similarity Sim is less than or equal to 0.7, the independent state of the two areas is maintained; repeating steps III) and IV) until all initial independent defect areas are traversed and the merging judgment is completed, and finally outputting hierarchical information of the defects; the hierarchical information includes the total number of defects and the details of the sub-defects contained in each merged defect area.

4. The SiC substrate surface defect detection system of claim 1, wherein: The contrast-limited adaptive histogram equalization process in the image preprocessing process includes the following steps: 1) dividing the image to be enhanced into N×N non-overlapping sub-blocks of the same size, wherein N is a positive integer; 2) calculating the gray level histogram of each sub-block to obtain the pixel frequency corresponding to each gray level in each sub-block; 3) calculating the clipping threshold of each sub-block: where T is the clipping threshold, L is the total number of pixels of the sub-block, H is the number of gray levels contained in the sub-block, and nclip is a user-defined clipping limit factor. wherein μ is the standard deviation of the image to be enhanced, σ is the mean value of the image to be enhanced, and d is a tuning constant, 3 < d < 5. 4) re-distributing the pixel values of the gray level histogram of each sub-block: if the pixel frequency of a certain gray level is greater than the clipping threshold, the pixel frequency of the gray level is adjusted to the clipping threshold, and the redundant pixel frequency exceeding the clipping threshold is uniformly distributed to other gray levels of the sub-block; 5) calculating the cumulative distribution function of the gray level histogram of each sub-block after pixel value re-distribution, and performing histogram equalization processing on the sub-block based on the cumulative distribution function; 6) reconstructing the image of all sub-blocks after equalization processing using a bilinear interpolation method to obtain an enhanced image.

5. The SiC substrate surface defect detection system of claim 1, wherein The binarization in the image preprocessing process is fixed threshold segmentation, and D(i) is a pixel value of a result image after binarization. wherein S(i) is a gray pixel value, and Th is a set threshold size.

6. The SiC substrate surface defect detection system of claim 1, wherein, The morphological processing in the image preprocessing process includes using a 3×3 matrix structure as a structure element B to filter out small impurities through erosion followed by dilation.

7. The SiC substrate surface defect detection system of claim 1, wherein: The image gray scale conversion in the image preprocessing process adopts a weighted processing method; where S(i) is the gray pixel value, R, G, B respectively correspond to red, green, blue three color components, and a, b, c respectively correspond to the corresponding weight values.

8. The SiC substrate surface defect detection system of claim 1, wherein: The ARM processing module adopts a four-connected domain algorithm, and expands from a seed point to a 4-neighborhood until scanning the entire connected domain.

9. The SiC substrate surface defect detection system of claim 1, wherein: The programmable IO interface of the FPGA collects color images output by a metallographic microscope, performs image preprocessing operations on the PL end of the FPGA, stores the processed binary image data to the BRAM module, the PS end of the ARM reads the data in the BRAM and realizes the detection of SiC surface defects through an improved Seed-Filling algorithm, and finally outputs the defect quantitative index through a serial port and synchronously displays the original image and the preprocessed image through a DP interface.

10. A method for detecting surface defects of a SiC substrate based on FPGA, characterized in that, The SiC substrate surface defect detection method is based on the SiC substrate surface defect detection system of any one of claims 1-9, and specifically includes the following steps: S1, image acquisition: taking an SiC surface through a metallographic microscope to obtain an original metallographic microscope image containing defects; S2, FPGA processing: inputting the original metallographic microscope image into the FPGA processing module to sequentially perform gray scale conversion, binarization, adaptive histogram equalization with contrast restriction, and morphological processing to obtain a processed standardized binary image; S3, ARM defect recognition: transmitting the processed standardized binary image to the ARM processing module to detect and analyze the defect area through an improved Seed-Filling algorithm; S4, result output: synchronously outputting the defect detection result through a serial port and a display port.

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