Devices, systems, and methods for storing memory metadata

Abstract

The disclosure relates to devices, systems, and methods for storing memory metadata. A memory bank of a memory device may be divided into column planes. Each column plane may be associated with a column selection. In some examples, one or more physical column planes may be selectively configured to store metadata. When the memory device is configured to not store metadata, the column selection may be arranged as a virtual column plane to allow data to be stored in a physical column plane for metadata. The physical column plane may be arranged as a virtual plane to store the data. Different mappings of the virtual plane to the physical plane may be used.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices. Background Technology

[0002] Specifically, this disclosure relates to memory, such as dynamic random access memory (DRAM). Information can be stored in memory cells that can be organized into arrays of rows (word lines) and columns (bit lines). Various types of information can be stored in the array, such as data, error correction code (ECC) data, and metadata. Data can be information provided by external devices (e.g., controllers, processors, host systems). ECC data can provide information that can be used to detect and / or correct errors in the data. Metadata can provide information about the data, ECC data, the memory device, and / or devices communicating with the memory device (e.g., controllers).

[0003] DRAM users are increasingly utilizing metadata to supplement the data stored in memory arrays. For example, metadata can be used to store "poisoned bits" indicating that the data associated with the metadata is erroneous and should be discarded and / or replaced by external devices (such as controllers, host, and / or system chips). In another instance, metadata can store pointers to memory locations, allowing external devices to determine where in the array the next associated data will be accessed. In some applications, this can be analogous to the head and / or end of a linked list. These are just examples, and other uses for metadata are possible.

[0004] Metadata can be stored in one or more column planes of a memory array. In some configurations, metadata can be retrieved along with data and ECC data in a single pass (e.g., a single access operation) (e.g., by a controller), as described in U.S. Patent Applications Nos. 18 / 504,215, 18 / 504,302, 18 / 504,324, and 18 / 504,353, which are incorporated herein by reference for any purpose. However, in some configurations, addressable memory space may be lost. Some users are sensitive to the loss of space for storing data in order to store metadata. These users want to forgo as little array density as possible while still utilizing the metadata. In some configurations, metadata can be retrieved along with data and ECC data in multiple passes, as described in U.S. Patent Applications Nos. 18 / 430,381, 18 / 431,306, and 18 / 441,830, which are incorporated herein by reference for any purpose. Retrieving all desired information from the memory device in two passes allows for more efficient storage of metadata. However, multiple passes increase access time, which can degrade performance in some applications. Therefore, it is desirable for memory devices to efficiently store metadata and allow single-pass access to the memory array. Summary of the Invention

[0005] On one hand, this disclosure provides an apparatus comprising: a memory array including a storage bank, wherein the storage bank includes a first physical column plane, a plurality of physical column planes and an error correction code (ECC) plane; and a mode register configured to store a value, wherein: when the value is a first state, the first physical column plane is configured to store metadata, the plurality of physical column planes are configured to store data, and the ECC plane is configured to store ECC data; wherein when the value is a second state, the plurality of physical column planes are configured to store the data, a first portion of the first physical column plane is configured to store data, a first portion of the first physical column plane is configured to store the ECC data, a second portion of the ECC plane is configured to store ECC data, and a fourth portion of the ECC plane is configured to store data.

[0006] On the other hand, this disclosure further provides a system comprising: a controller; and a memory module including a plurality of memory devices, wherein at least one of the plurality of memory devices includes: a memory array including a storage bank, wherein the storage bank includes a first physical column plane, a plurality of physical column planes and an error correction code (ECC) plane; and a mode register configured to store a value, wherein: when the value is a first state, the first physical column plane is configured to store metadata, the ECC plane is configured to store ECC data, and the plurality of physical column planes are configured to store data; and when the value is a second state, a portion of the first physical column plane, a first portion of the ECC plane and the plurality of physical column planes are configured to store the data, and another portion of the first physical column plane and another portion of the ECC plane are configured to store the ECC data.

[0007] In another aspect, this disclosure further provides a method comprising: receiving a mode register write command and a value to be written to the mode register; writing the value to the mode register in response to the mode register write command; configuring a first physical column plane to store metadata and configuring a plurality of physical column planes to store data when the value is in a first state; and configuring the plurality of physical column planes to store the data, configuring the first physical column plane to store the data and error correction code (ECC) data, and configuring the ECC plane to store the data and ECC data when the value is in a second state. Attached Figure Description

[0008] Figure 1 This is a block diagram of at least a portion of a computing system according to some embodiments of the present disclosure.

[0009] Figure 2 This is a block diagram of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 3 This is a block diagram of a portion of a memory device according to some embodiments of the present disclosure.

[0011] Figure 4 This is a block diagram of a portion of a memory device arranged according to some embodiments of the present disclosure.

[0012] Figure 5 This is a block diagram of a portion of a memory device arranged according to some embodiments of the present disclosure.

[0013] Figure 6 A table showing indications of physical column plane suppression according to some embodiments of the present disclosure is provided.

[0014] Figure 7 A block diagram and a table of decoding schemes comprising a portion of a memory device according to some embodiments of the present disclosure.

[0015] Figure 8 A table showing indications of physical column plane suppression according to some embodiments of the present disclosure is provided.

[0016] Figure 9 A table containing decoding schemes according to some embodiments of this disclosure.

[0017] Figure 10 A table showing indications of physical column plane suppression according to some embodiments of the present disclosure is provided.

[0018] Figure 11 A table illustrating physical column plane suppression of indicated bounded fault implementations according to some embodiments of the present disclosure.

[0019] Figure 12 This is a flowchart of a method according to some embodiments of the present disclosure.

[0020] Figure 13 This is a flowchart of a method according to some embodiments of the present disclosure.

[0021] Figure 14 This is a flowchart of a method according to some embodiments of the present disclosure.

[0022] Figure 15 This is a flowchart of a method according to some embodiments of the present disclosure.

[0023] Figure 16 This is a flowchart of a method according to some embodiments of the present disclosure.

[0024] Figure 17 This is a flowchart of a method according to some embodiments of the present disclosure. Detailed Implementation

[0025] The following description of certain embodiments is merely illustrative and is not intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form part of and are illustrated by description, showing specific embodiments in which the described systems and methods can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed systems and methods, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features that are obvious to those skilled in the art will not be discussed so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be considered as intended to be limiting, and the scope of this disclosure is defined only by the appended claims.

[0026] Semiconductor memory devices can store information in multiple memory cells. Information can be stored as binary code, and each memory cell can store a single information bit as either logic high (e.g., "1") or logic low (e.g., "0"). Memory cells can be organized at the intersections of word lines (rows) and bit lines (columns) of an array. The memory can be further organized into one or more banks. Banks can be organized into banks, where each bank group contains one or more banks. Each bank can contain multiple rows and columns. During operation, the memory device can receive commands and specify addresses for one or more rows and one or more columns, and then execute the commands on the memory cells at the intersections of the specified rows and columns (and / or along the entire row / column). The addresses can further specify the bank group and / or bank used to execute the commands. In some applications, rows can be specified by 17-bit row addresses and columns by 12-bit column addresses. However, the number of bits used for the address can vary depending on the size and / or organization of the memory.

[0027] Columns are typically organized into column planes, each containing an array of individual columns activated entirely by a column select signal (CS) (e.g., column select). Each memory bank may contain a number of X column planes. A column plane may receive a number of N column select (CS) signals, each of which activates a number of M individual bit lines. As used herein, a column select group or CS group may generally refer to a set of bit lines activated by a given value of a CS signal within a column plane. Column select signals may be represented by column addresses (CA) (all or part of them). In response to a column select signal, data may be provided from the corresponding location on the column plane. Data from the column plane associated with a column select signal may be referred to as a cache line.

[0028] As discussed in the "Background Art" section, it is desirable for memory arrays to support single-pass access while minimizing the loss of addressable memory space within the array. Furthermore, it is desirable for memory arrays to be selectively configured to store metadata. For example, some users may not want to utilize metadata and may use memory array space for data rather than metadata.

[0029] According to embodiments of this disclosure, a memory device may include a memory array that can be selectively configured (e.g., enabled) to store metadata. In some embodiments, the memory array may include 16 column planes for data, 1 column plane for metadata, and 1 column plane for ECC data (total = 18 CP). In some embodiments, the memory array may include 16 column planes for data, 2 column planes for metadata, and 1 column plane for ECC data (total = 19 CP). Optionally, some embodiments may additionally include a Global Column Redundancy (GCR) plane. When storing metadata (e.g., by a mode register) is enabled, in some embodiments, each data column plane is associated with 60 column select signals, and the metadata and ECC planes are each associated with 64 column select signals. In some embodiments, each data column plane is associated with 56 column select signals, and the metadata and ECC planes are each associated with 64 column select signals. When storing metadata is disabled, the column select signals may be activated in such a way that the memory array operates as if 16 data planes and 1 ECC data plane (total = 17 CP) are present.

[0030] Providing one or more additional column planes for metadata allows for efficient storage of metadata within the memory array and enables retrieval of data, metadata, and ECC data in a single pass. Furthermore, the embodiments disclosed herein allow for flexible use of the memory array to store metadata or to utilize metadata space to store data when metadata is not desired.

[0031] Figure 1 This is a block diagram of at least a portion of a computing system according to some embodiments of the present disclosure. The computing system 100 includes a memory module 102 and a controller 106 communicating with the memory module 102. In some embodiments, the controller 106 may be included in or communicate with a processor (not shown). The memory module 102 may include one or more memory devices 104. Figure 1 In the example shown, there are eight memory devices 104 (0 to 7). However, in other embodiments, there may be more or fewer memory devices (e.g., four devices, 16 devices). In some embodiments, additional memory devices 104 may be included to provide redundancy. In some embodiments, the memory module 102 may be a dual in-line memory module (DIMM). In some embodiments, Figure 1The content shown may represent only half of the DIMM (e.g., one of two channels). In other words, memory module 102 may contain 16 memory devices 104.

[0032] The controller 106 can provide commands, addresses, and / or data (e.g., data, metadata, or both) to and receive data from one or more of the memory devices 104. In some embodiments, the memory device 104 may be an x4 or x8 memory device. That is, four or eight DQ terminals (e.g., pins) may be active. In some embodiments, the memory device 104 may support both x4 and x8 operation. In some embodiments, whether the memory device 104 operates in x4 or x8 mode may be at least partially based on a mode register stored in the memory device 104. Figure 1 The value is not shown in the figure. In some embodiments, memory device 104 may be a x16 memory device.

[0033] In some applications, each of the memory devices 104 can provide 8 bits of metadata for a total of 4 bytes of data. In some applications, each of the memory devices 104 can provide 16 bits of metadata for a total of 8 bytes of data. The controller 106 can receive cache lines from the memory devices 104 containing 128 bits of data and 8 or 16 bits of metadata. In some embodiments, the amount of metadata provided may be based on values ​​stored in the mode register of the memory devices 104.

[0034] In some embodiments, whether or not metadata is stored can be based on the value stored in the mode register of memory device 104. For example, when a value is stored in the mode register, metadata can be stored and provided as described herein. When another value is stored in the mode register, metadata may not be stored. When this value is stored, all column selections can be used to provide data back and forth to the array. Thus, the same memory can be used for applications that want metadata and applications that do not want metadata.

[0035] As will be described in more detail herein, when metadata is stored, the physical column planes (e.g., physical planes) of the memory device 104 associated with the data and metadata are accessed by activating the corresponding column select signals of the physical column planes. When metadata is not stored, the memory device 104 may configure the column select signals to be activated in a manner to form several virtual column planes (e.g., virtual planes) for accessing the data. In some embodiments, the number of virtual planes may be less than the number of physical planes for the data and metadata (e.g., 16 data + 1 metadata = a total of 17 physical planes to a total of 16 virtual planes). In some embodiments, the number of bit lines activated on the virtual planes may be equal to the number of bit lines activated in the physical planes during memory access operations. “Virtual plane” means that the column select signals may be activated or suppressed in a manner that does not correspond to physical planes of the memory array of the memory device 104. However, from the perspective of the controller 106, the memory device 104 may receive and output data as if the virtual plane were a physical column plane.

[0036] Figure 2 This is a block diagram of a semiconductor device according to some embodiments of the present disclosure. The device may be semiconductor device 200 and will be referred to as such. In some embodiments, semiconductor device 200 may include, but is not limited to, a dynamic random access memory (DRAM) device integrated into a single semiconductor chip. In some instances, the DRAM may be double data rate (DDR) memory. In some embodiments, Figure 1 One or all of the memory devices 104 (0 to 7) may include semiconductor devices 200.

[0037] Semiconductor device 200 includes a memory die. The die may be mounted on an external substrate, such as a memory module substrate, motherboard, or the like (e.g., a multilayer package (PoP)). Semiconductor device 200 may further include a memory array 250. Memory array 250 includes multiple memory banks BANK0 to 15, each memory bank including multiple word lines WL, multiple bit lines BL, and multiple memory cells MC disposed at the intersections of the multiple word lines WL and the multiple bit lines BL. Although Figure 2The diagram shows 16 memory banks, but memory array 250 can contain any number of memory banks. Word line selection (WL) is performed by row decoder 240, and bit line selection (BL) is performed by column decoder 245. A sense amplifier (SAMP) is positioned for its corresponding bit line (BL) and connected to at least one corresponding local I / O line pair (LIOT / B), which can be coupled via a transmission gate (TG) (which acts as a switch) to at least one corresponding main I / O line pair (MIOT / B). The TG can be coupled to one or more read / write amplifiers (RWAMP) 255, which can be coupled to error correction code (ECC) circuitry 235. ECC circuitry 235 can be coupled to I / O circuitry 260, which can be coupled to one or more external terminals of semiconductor device 200. Read data from bit line BL is amplified by the sense amplifier SAMP and transmitted via the complementary local data line (LIOT / B), the transmission gate (TG), and the complementary main data line (MIOT / B) to the read / write amplifier 255 and then to the ECC circuit 235. Conversely, write data output from the ECC circuit 235 is transmitted via the complementary main data line MIOT / B, the transmission gate TG, and the complementary local data line LIOT / B to the sense amplifier SAMP and written into the memory cell MC coupled to bit line BL.

[0038] The semiconductor device 200 may employ multiple external terminals, including command and address terminals coupled to the command / address (C / A) bus to receive command and address signals, clock terminals for receiving clocks CK_t and CK_c, data terminals DQ and RDQS, and power supply terminals VDD, VSS, VDDQ, and VSSQ.

[0039] The C / A terminal can be supplied with address and memory address signals from an external source (e.g., from controller 202). The address and memory address signals supplied to the address terminal are transmitted to the address decoder 212 via command / address input circuitry 205. Address decoder 212 receives the address signals and supplies the decoded row address signal XADD to row decoder 240 and the decoded column address signal YADD to column decoder 245. Address decoder 212 also receives the memory address signal BADD and supplies it to both row decoder 240 and column decoder 245.

[0040] The C / A terminals may be further supplied with command signals from, for example, controller 202. In some embodiments, controller 202 may be implemented or included in controller 106. The command signal may be provided as an internal command signal ICMD to command decoder 215 via command / address input circuitry 205. Command decoder 215 includes circuitry to decode the internal command signal ICMD to generate various internal signals and commands for performing operations, such as a row activation signal (ACT) for selecting a word line. Another example may be providing internal signals to enable circuitry to perform operations, such as a control signal for enabling a signal input buffer that receives a clock signal.

[0041] Each storage bank BANK0 to 15 can be organized into multiple physical column planes (CPs). Each column plane can be associated with multiple column selections (e.g., CS0 to 63, CS0 to 59, CS0 to 55). In some embodiments, different column planes can be used to store different types of information. For example, some column planes can store data while another plane stores ECC data. Optionally, another plane can store GCR data. According to embodiments of this disclosure, array 250 can be selectively configured to utilize one or more column planes to store metadata.

[0042] The C / A terminal can receive access commands as read commands. When a read command is received and the memory bank address, row address, and column address are provided in time with the read command, a codeword containing read data, metadata, and read ECC data (e.g., parity bits) is read from the memory cells in memory array 250 corresponding to the row and column addresses. The read command is received by command decoder 215, which provides an internal command causing the read data from memory array 250 to be provided to ECC circuit 235. ECC circuit 235 can use the parity bits in the codeword to determine whether the codeword contains any errors, and if any errors are detected, the errors can be corrected to generate a correction codeword (e.g., by changing the state of the erroneous identification bit). The correction codeword (without parity bits) is output from the data terminal DQ via input / output circuit 260.

[0043] The C / A terminal can receive access commands as write commands. When a write command is received and the memory bank address, row address, and column address are supplied in a timely manner as part of the write operation, write data is supplied to the ECC circuit 235 via the DQ terminal. The write data supplied to the data terminal DQ (which may contain write data and metadata) is written to the memory cells in the memory array 250 corresponding to the row and column addresses. The write command is received by the command decoder 215, which provides an internal command causing the write data to be received by the data receiver in the input / output circuit 260. The write data is supplied to the ECC circuit 235 via the input / output circuit 260. The ECC circuit 235 can generate ECC data (e.g., several parity bits) based on the write data, and the write data and parity bits can be provided as codewords to the memory array 250 to be written into the memory cell MC.

[0044] ECC circuit 235 can be used to ensure the fidelity of data read from a specific group of memory cells relative to data written to memory cells in that group. Semiconductor device 200 may include several different ECC circuits 235, each responsible for a different portion of the memory cells MC of memory array 250. For example, one or more ECC circuits 235 may be present for each bank of memory array 250. Typically, each bank BANK0 to 15 includes column planes for storing ECC data (e.g., parity bits) and additional column planes (e.g., 16 column planes) for storing data. In these applications, ECC circuit 235 generates eight bits of ECC data (e.g., 8 bits of ECC data) for each 128-bit cache line. This allows ECC circuit 235 to provide single-bit error correction.

[0045] Command decoder 215 can access mode register 275, which is programmed with information for setting various modes and characteristics of operation of semiconductor device 200. For example, mode register 275 can provide parameters that allow semiconductor device 200 to operate at different frequencies, provide different burst lengths, allow memory banks BANK0 to 15 to be organized into different groups, operate in x4, x8, or x16 modes, and / or other different operating conditions. In some embodiments, mode register 275 may contain multiple registers.

[0046] Information in mode register 275 can be programmed by providing a mode register write command to semiconductor device 200, causing semiconductor device 200 to perform a mode register write operation. In some embodiments, data to be written to mode register 275 is provided via C / A terminals and / or DQ terminals. Command decoder 215 accesses mode register 275 and provides internal signals based on programming information and internal command signals to control the circuitry of semiconductor device 200 accordingly. Information programmed into mode register 275 can be provided externally by semiconductor device 200 using a mode register read command that causes semiconductor device 200 to access mode register 275 and provide programming information (e.g., to memory controller 202). In some embodiments, information can be provided via C / A terminals and / or DQ terminals.

[0047] According to embodiments of this disclosure, mode register 275 is programmable to have a value that determines whether semiconductor device 200 stores metadata. When a value is stored in the register, metadata may not be stored (e.g., in an operating mode where metadata is disabled). When another value is stored in the register, metadata may also be stored (e.g., in an operating mode where metadata is enabled). In some embodiments, mode register 275 is programmable to have an additional value that determines the number of metadata bits stored.

[0048] Based on the value stored in the mode register 275, the mode register may provide one or more signals to the column decoder 245. In some embodiments, the signals from the mode register 275 may enable or disable one or more decoder circuits (or one or more components thereof). The decoder circuits may determine which column select signals are activated and / or which physical column planes are accessed during an access operation (e.g., a read or write operation).

[0049] According to embodiments of this disclosure, selectively activating or suppressing column selection signals associated with one or more physical column planes can allow the formation of virtual column planes. This allows the semiconductor device 200 to appear as if it were a controller 202 with a different number of column planes than the number of physical column planes in the array 250.

[0050] The external terminals included in semiconductor device 200, including clock and data clock terminals, are supplied with external clock signals and complementary external clock signals. External clock signals CK_t and CK_c can be supplied to clock input circuit 220. An input buffer included in clock input circuit 220 transmits the external clock signal when enabled. For example, the input buffer transmits the CK_t and CK_c signals when enabled by the CKE signal from command decoder 215. Clock input circuit 220 can use the external clock signal transmitted via the enabled input buffer to generate an internal clock signal ICK. The internal clock signal ICK is supplied to internal clock circuit 230 to provide one or more clock signals to various components of semiconductor device 200.

[0051] The internal clock circuit 230 includes circuitry for providing internal clock signals with various phase and frequency controls based on received internal clock signals. For example, the internal clock circuit 230 may include a clock path ( Figure 2 (Not shown in the diagram), it receives the ICK clock signal and provides the internal clock signals ICK and ICKD to the command decoder 215. Optionally, the input / output circuit 260 may include clock circuitry and driver circuitry for generating and providing the RDQS signal to the controller.

[0052] Power supply terminals are supplied with power supply potentials VDD and VSS. These power supply potentials VDD and VSS are supplied to internal voltage generator circuit 270. Internal voltage generator circuit 270 generates various internal potentials VPP, VOD, VARY, VPERI, and the like, as well as a reference potential ZQVREF, based on the power supply potentials VDD and VSS. Internal potential VPP is mainly used in line decoder 240, internal potentials VOD and VARY are mainly used in sense amplifiers included in memory array 250, and internal potential VPERI is used in many other circuit blocks.

[0053] The power supply terminal is also supplied with a power supply potential VDDQ. The power supply potential VDDQ is supplied to the input / output circuit 260 together with the power supply potential VSS. In an embodiment of this disclosure, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of this disclosure, the power supply potential VDDQ may be a different potential than the power supply potential VDD. However, a dedicated power supply potential VDDQ is used for the input / output circuit 260 so that power supply noise generated by the input / output circuit 260 does not propagate to other circuit blocks.

[0054] Figure 3 This is a block diagram of a portion of a memory device according to some embodiments of the present disclosure. In some embodiments, memory device 300 may represent Figure 2A portion of the semiconductor device 200 or Figure 1 Part of one or more of the memory devices 104. Figure 3 The display can be a storage medium (e.g.) Figure 2 The memory arrays 310 to 316 and 320 to 326 (parts of BANK0 to 15) and selected circuitry (e.g., ECC circuitry 332) in the data path. Figure 2 235) and IO circuit 334 (e.g. Figure 2 Part of 260). For clarity, some circuits and signals have been removed. Figure 3 The view is omitted.

[0055] Memory device 300 is organized into several column planes 310 to 316. Each of the column planes represents a portion of the memory bank. Each column plane 310 to 316 contains several memory cells at the intersection of word lines WL and bit lines. Bit lines can be grouped together into groups activated by the value of a column select (CS) signal. For clarity, only a single vertical line is used to represent the bit line of each column select group; however, multiple columns may exist that are accessed by this CS value. For example, each line may represent 8 bit lines that are all accessed by the CS value. As used herein, the CS 'value' may refer to (e.g., from a column decoder, for example...) Figure 2 (245) provides the decoding signal for the bit line group. The first value can represent the first value of the multi-bit CS signal, or be valid after decoding the signal line associated with this value. The word line can extend across multiple column planes 310 to 316.

[0056] The memory device 300 includes a set of column planes 310 for storing data and at least one column plane 316 for storing metadata. The memory device 300 may include an ECC column plane 312 for storing ECC information (e.g., error correction parity bits).

[0057] In some embodiments, the memory device 300 may further include an optional Global Column Redundancy (GCR) column plane 314. In some embodiments, the GCR column plane 314 may have fewer memory cells than the data column plane 310 (e.g., fewer column selection groups). The GCR CP 314 includes several redundant columns that can be used as portions of a repair operation. If the value of the CS signal is identified as containing a defective memory cell in one of the data column planes 310, the memory may be remapped so that data that would otherwise be stored in that column plane is instead stored in the GCR CP 314 due to the CS value.

[0058] In an exemplary embodiment, memory device 300 may include 16 data column planes 310(0) to 310(15) and one metadata column plane 316. When the metadata column plane 316 is included, each of the data column planes 310 contains 60 sets of column selects activated by the value of a column select signal, and the metadata column plane contains 64 sets of column selects activated by the value of a column select signal (e.g., a total of 1024 column selects). Each set of column selects contains 8 bit lines. Thus, when the word line is opened in response to a row address and a column select signal is provided to each of the 17 column planes, 8 bits are accessed from each of the 17 column planes, for a total of 136 bits (128 data bits and 8 metadata bits). A column select signal is also provided to ECC column plane 312, but for the additional 8 bits, this column select signal may be a different value than the value provided to column plane 310. If the repair has been performed, GCR CP 314 can still be accessed and the value on the GCR LIO can be used, while ignoring the LIO of the column plane it replaces. Therefore, the maximum number of bits that can be retrieved as part of an access pass is 136 bits from data column plane 310 (8 bits replaced by GCR CP 314 if the repair has been performed) and 8 additional bits from ECC CP 312.

[0059] In another example, memory device 300 may include 16 data column planes 310(0) to 310(15) and 2 metadata column planes 316. When the 2 metadata column planes 316 are included, each of the data column planes 310 contains 56 sets of column selects activated by the value of the column select signal and the metadata column plane contains 64 sets of column selects activated by the value of the column select signal (e.g., a total of 1024 column selects). Each set of column selects contains 8 bit lines. Thus, when the word line is opened in response to the row address and the column select signal is provided to each of the 18 column planes, 8 bits are accessed from each of the 18 column planes, for a total of 144 bits (128 data bits and 16 metadata bits). The column select signal is also provided to ECC column plane 312, but for the additional 8 bits, this column select signal may be a different value than the value provided to column plane 310. If the repair has been performed, GCR CP 314 can still be accessed and the value on the GCR LIO can be used, while ignoring the LIO of the column plane it replaces. Therefore, the maximum number of bits that can be retrieved as part of an access pass is 128 bits from the data column plane 310 (8 bits replaced by GCR CP 314 if the repair has been performed), 16 bits from the metadata column plane 316, and 8 additional bits from ECC CP 312.

[0060] During a read operation, data can be provided from column plane 310 to sense amplifier 320 and to ECC circuit 332. Metadata can be provided from column plane 316 to sense amplifier 326, and ECC data can be provided from column plane 312 to sense amplifier 322 and to ECC circuit 332. (If repair has been performed, data can also be provided from column plane 314 to sense amplifier 324 and to ECC circuit 332.) ECC circuit 332 can use the ECC data provided from column plane 312 to correct and / or detect errors in the data and / or metadata. ECC circuit 332 can output the data and metadata (corrected, if necessary) to I / O circuit 334. I / O circuit 334 can provide the data and metadata to DQ. DQ can then deliver the data and metadata to an external device (e.g., a controller, such as...). Figure 1 106 and / or Figure 2 (202 in the example). Optionally, the ECC circuit 332 may further provide error information for output on the DQ.

[0061] During a write operation, data and metadata may be received from the DQ by I / O circuitry 334 and provided to ECC circuitry 332. Optionally, error information may also be received and provided to ECC circuitry 332. ECC circuitry 332 may generate parity bits and / or other error correction information for the data and metadata. ECC circuitry 332 may provide data to sense amplifier 320 for storage in column plane 310. Metadata may be provided to sense amplifier 326 for storage in column plane 316, and error correction information may be provided to sense amplifier 322 for storage in column plane 312. (If repair has been performed, data may also be provided from ECC circuitry 332 to sense amplifier 324 for storage in column plane 314.)

[0062] When memory device 300 is not configured to store metadata, the controller can anticipate 128 bits of data for cache lines, even when metadata column plane 316 is used to store data instead of metadata, providing 136 or 144 bits of data. However, not using metadata column plane 316 to store data would reduce the data storage capacity of the memory array containing column planes 310 to 316. Therefore, when memory device 300 is configured not to store metadata, the activation of column selection can be modified to form a virtual plane by column planes 310 and 316. In some embodiments, the number of virtual planes may be equal to the number of data column planes 310.

[0063] Figure 4 This is a block diagram of a portion of a memory device arranged according to some embodiments of the present disclosure. In some embodiments, memory device 400 may represent Figure 3 The memory device 300 shown in the image Figure 2Semiconductor device 200 and / or Figure 1 Part of one or more of the memory devices 104 shown in the figure. Figure 4 The display can be a storage medium (e.g.) Figure 2 The memory arrays 410 to 416 (BANK0 to 15) and a portion of selected circuitry (e.g., subword line drivers SWD430 and DQ 428) in the data path.

[0064] The memory device 400 has several physical column planes within the memory bank. Figure 4 In the example shown, there are 16 data column planes 410 (0 to 15) (CP0 to 15), 1 metadata column plane 416 (MD), 1 ECC column plane 412, and 1 GCR plane 414. In some embodiments, these column planes may correspond to column planes 310 to 316.

[0065] Metadata column plane 416 can be associated with 64 column select signals, and data column plane 410 can each be associated with 60 column select signals. When no metadata is stored in the memory array, it may be desirable for each data column plane 410 to be associated with 64 rather than 60 column select signals.

[0066] exist Figure 4 In the embodiment shown, different numbers of column select signals are "borrowed" from other physical column select planes. For example, CP0 borrows 4 CS from CP1 to form a virtual CP0 associated with 64 CS, CP1 borrows 8 CS from CP2 to form a virtual CP1 associated with 64 CS, and so on. CP7 borrows 32 CS from metadata column plane 416 to form a virtual CP7, and CP8 borrows the remaining 32 CS from metadata column plane 416 to form a virtual CP8. CP8 "borrows" 28 CS from CP9 and CP9 borrows 24 CS from CP10, and so on, to form their respective virtual planes associated with 64 CS. As shown, metadata column plane 416 borrows all of its column select signals from the virtual data column planes, so there are no longer any column select signals associated with metadata column plane 416. Therefore, all virtual data column planes are associated with 64 column select signals.

[0067] Figure 5 This is a block diagram of a portion of a memory device arranged according to some embodiments of the present disclosure. In some embodiments, memory device 500 may represent Figure 3 The memory device 300 shown in the image Figure 2 Semiconductor device 200 and / or Figure 1 Part of one or more of the memory devices 104 shown in the figure. Figure 5 The display can be a storage medium (e.g.) Figure 2The memory arrays 510 to 516 (BANK0 to 15) and a portion of selected circuitry (e.g., subword line drivers 530 and DQ 528) in the data path.

[0068] The memory device 500 has several physical column planes within the memory bank. Figure 5 In the example shown, there are 16 data column planes 510 (0 to 15) (CP0 to 15), 2 metadata column planes 516 (0 to 1) (MD), 1 ECC column plane 512, and 1 GCR plane 514. In some embodiments, these column planes may correspond to column planes 310 to 316.

[0069] Metadata column planes 516 can each be associated with 64 column select signals, and data column planes 510 can each be associated with 56 column select signals. When no metadata is stored in the memory array, it is expected that each data column plane 510 will be associated with 64 rather than 56 column select signals.

[0070] exist Figure 5 In the embodiment shown, different numbers of column select signals are “borrowed” from other physical column select planes. For example, CP0 borrows 8 CS from CP1 to form a virtual CP0 associated with 64 CS, CP1 borrows 16 CS from CP2 to form a virtual CP1 associated with 64 CS, and so on. CP7 borrows 64 CS from metadata column plane 516(0) to form a virtual CP7. CP8 borrows 64 CS from metadata column plane 516(1) to form a virtual CP8. CP8 “borrows” 56 CS from CP9 and CP9 borrows 48 CS from CP10, and so on, to form their respective virtual planes associated with 64 CS. As shown, metadata column plane 516(0 to 1) borrows all of its column select signals from the virtual data column planes, so there are no longer any column select signals associated with metadata column plane 516(0 to 1). Therefore, all virtual data column planes are associated with 64 column select signals.

[0071] Even if the memory device is capable of providing more than 128 bits of data per cache line due to the additional physical column plane, external devices such as controllers (e.g., controllers 106 and / or 202) may not be configured to receive more than 128 bits of data when the memory device does not store metadata. Therefore, when the memory device is configured to use a virtual plane, for example... Figure 4 and 5 As shown, column selection signals for one or more physical column planes can be suppressed to output the desired amount of data (e.g., 128 bits) from the virtual plane. Figure 4 In the example shown, column selection associated with a physical plane can be suppressed to prevent memory from providing 136 bits of data. Figure 5 In the example shown, column selection associated with the two physical column planes can be suppressed to prevent the memory from providing 144 bits of data.

[0072] Figure 6 A table indicating physical column plane suppression is shown according to some embodiments of the present disclosure. In some embodiments, when memory (e.g., one or more of memory device 104 and / or semiconductor device 200) is referenced as... Figure 4 When describing the general configuration, the suppression schemes depicted in Table 600 can be used.

[0073] The top row of Table 600 indicates the physical column plane. The next row indicates the number of columns selected in each of the physical planes, and the physical planes used by the memory device when it is in metadata-stored operation mode (MD ON). The third row indicates the physical plane used when the memory device is in... Figure 4 The arrangement of column selections shown in the image is for the MDOFF (Metadata Not Stored) operation mode.

[0074] Below the first three rows are several columns providing more details about the physical column plane suppression scheme. The first column indicates the column selection (CS), and the second column indicates the operating mode (MODE) of the memory device. The mode for the entire column is MD OFF (no metadata is stored). In some embodiments, the physical column plane may not be suppressed when metadata is stored. The vertical lines separating the columns indicate the position of the subword line drivers (SWD0 to 10) relative to the physical column plane. In some embodiments, the SWD may be contained within SWD430.

[0075] The remaining columns of Table 600 indicate the column selection signals (CS) of the physical planes associated with a given virtual plane. For example, in MD OFF mode, looking at the column indicated by arrow 602, CS0 to 55 of physical CP1 are associated with virtual CP1, but CS60 to 63 of physical CP1 are associated with virtual CP0. CS56 to 59 of physical CP1 are not associated with any virtual plane. Looking at the next column indicated by arrow 604, the remaining CS of virtual CP1 are contained within CS56 to 63 of physical CP2.

[0076] The filled squares in Table 600 indicate column selections of physical planes that are not associated with any virtual plane. These column selections of physical planes should be suppressed during memory access operations. For example, suppose CS0, CS1, CS2, and / or CS3 are activated (e.g., by a column decoder, such as...). Figure 2(See column 245 in Table 600). Referring to the last two columns of Table 600, virtual CP15 is formed by CS0 to 3 of physical CP14 (as shown in the column indicated by arrow 606) and CS4 to 63 of physical CP15 (as shown in the column indicated by arrow 608). Therefore, CS0 to 3 of physical CP15 are not associated with any virtual plane. Therefore, activation of CS0 to 3 in physical CP15 should be suppressed. Similarly, virtual CP14 is associated with CS0 to 7 of physical CP13 and CS8 to 63 of physical CP14. As seen in the column indicated by arrow 606, CS4 to 7 of physical CP14 are not associated with any virtual plane. Therefore, activation of CS4 to 7 of physical CP14 should be suppressed.

[0077] The column indicated by arrow 610 refers to the physical metadata plane. It should be noted that, unlike the physical data column plane which is associated with 60 column select signals, the metadata plane is associated with 64 column select signals. Furthermore, in MD OFF mode, all column select signals of the metadata plane are "borrowed" to the virtual data plane (CP7 and CP8 in the example shown). Therefore, all column selects in the physical metadata plane are associated with the virtual plane, and all column selects in the metadata plane are not suppressed. Similarly, in Figure 6 The example shown does not provide suppression of column selection in the physical ECC plane.

[0078] Figure 7 A block diagram and a table of decoding schemes comprising a portion of a memory device according to some embodiments of the present disclosure. The memory device 701 can be used as... Figure 1 The memory device 104 and / or Figure 2 A portion of one or more of the semiconductor devices 200 is included. Memory device 701 includes a column decoder 745, which includes column select (CS) suppression circuitry. In some embodiments, column decoder 745 may be used to implement column decoder 245 or may be included in column decoder 245. Memory device 701 includes a mode register 775. In some embodiments, mode register 775 may be used to implement mode register 275 or may be included in mode register 275.

[0079] Mode register 775 is programmable with one or more values ​​to set operating modes and / or parameters for the operation of memory device 701. For example, mode register 775 is programmable with a value in a first state indicating that metadata is stored in the memory array (e.g., memory array 250). When metadata is stored in the memory array, mode register 775 may provide an invalid enable signal En to CS suppression circuit 747, causing the column decoder not to suppress the activation of any column selection in the physical column plane. Mode register 775 is programmable with a value in a second state indicating that metadata is not stored in the memory array. When metadata is not stored in the memory array, mode register 775 may provide an valid En signal to CS suppression circuit 747 to suppress column selection in certain physical column planes.

[0080] In some embodiments, the CS suppression circuit 747 may include one or more logic circuits to implement a decoding scheme to provide desired suppression of column selection when enabled. For example, the CS suppression circuit 747 may include decoding logic to implement reference Figure 6 The suppression scheme is described. In some embodiments, the CS suppression circuit 747 may include one or more logic circuits implementing the binary decoding scheme shown in Table 700.

[0081] The first column of Table 700 indicates the column selection signal (CS). The next six columns indicate the binary inputs to be decoded. The last column indicates the physical column plane (CP) to which the indicated CS is suppressed. The first four inputs can be used to indicate the CP to be suppressed (columns labeled 5 to 2). The CS suppression circuit 747 can invert the first four inputs to determine the physical column plane to suppress CS activation of a specific CS. For example, in row CS3:0, the input is "0000". After inversion, this is "1111", which corresponds to 15. Therefore, as indicated by the last column, CS activation in physical CP15 is suppressed when CS0, CS1, CS2, or CS3 is selected to be active. This is consistent with... Figure 6 Matching, where CS0 to 3 of CP15 are masked.

[0082] In the CS suppression circuit 747, any suitable logic circuitry can be used to implement Table 700. In some embodiments, the remaining two inputs (columns labeled 1 to 0) may be omitted. In other embodiments, the remaining inputs may be used to provide additional information to other components of the CS suppression circuit 747 and / or the column decoder 745.

[0083] Figure 8 A table indicating physical column plane suppression is shown according to some embodiments of the present disclosure. In some embodiments, when memory (e.g., one or more of memory device 104 and / or semiconductor device 200) is referenced as... Figure 5 When describing the general configuration, the suppression schemes depicted in Table 800 can be used.

[0084] The top row of Table 800 indicates the physical column plane. The next row indicates the number of columns selected in each of the physical planes, and the physical plane used by the memory device when it is in metadata-stored operation mode (MD ON). The third row indicates the physical plane used when the memory device is in... Figure 5 The arrangement of column selections is shown in the operating mode (MD OFF) when metadata is not stored.

[0085] Below the first three rows are several columns providing more details about the physical column plane suppression scheme. The first column indicates the column selection (CS), and the second column indicates the operating mode (MODE) of the memory device. The mode for the entire column is MD OFF (no metadata is stored). In some embodiments, the physical column plane may not be suppressed when metadata is stored. The vertical lines separating the columns indicate the position of the subword line drivers (SWD0 to 10) relative to the physical column plane. In some embodiments, the SWD may be contained within SWD430.

[0086] The remaining columns of Table 800 indicate the column selection signals (CS) of the physical planes associated with a given virtual plane. For example, looking at the column indicated by arrow 802, CS0 to 47 of physical CP1 are associated with virtual CP1, but CS56 to 63 of physical CP1 are associated with virtual CP0. CS48 to 55 of physical CP1 are not associated with any virtual plane. Looking at the next column indicated by arrow 804, the remaining CS of virtual CP1 are contained within CS48 to 63 of physical CP2.

[0087] The filled squares in Table 800 indicate the column selections of physical planes that are not associated with any virtual plane. These column selections of physical planes should be suppressed during memory access operations. Figure 6 The scheme shown in the diagram, on the contrary, suppresses column selection on both physical planes. This is at least partly due to the arrangement of the memory array containing two metadata planes (in the columns indicated by arrows 810 and 812) rather than... Figure 5 This is a metadata plane shown in the image. For example, suppose any or all of CS0 through 7 are activated (e.g., by a column decoder, such as...). Figure 2 (See 245 in the original text). Looking at the columns indicated by arrows 806 and 808, CS0 through 7 of physical columns CP7 and CP15 are not associated with any virtual plane. Therefore, activation of CS0 through 7 in physical columns CP7 and CP15 should be suppressed.

[0088] As previously discussed, unlike the physical data column plane which is associated with 56 column select signals, the metadata plane is associated with 64 column select signals. Furthermore, in MD OFF mode, all column select signals from the metadata plane are "borrowed" to the virtual data plane (CP7 and CP8 in the illustrated example). Therefore, all column selects in the physical metadata plane are associated with the virtual plane, and all column selects in the metadata plane are not suppressed. Similarly, in Figure 8 The example shown does not provide suppression of column selection in the physical ECC plane.

[0089] Figure 9 A table containing decoding schemes according to some embodiments of this disclosure. In some embodiments, Figure 9 The decoding scheme shown in the image can be derived from... Figure 7 The memory device 701 shown in the figure is implemented.

[0090] Mode register 775 is programmable with one or more values ​​to set operating modes and / or parameters for the operation of memory device 701. For example, mode register 775 is programmable with a value in a first state indicating that metadata is stored in the memory array (e.g., memory array 250). When metadata is stored in the memory array, mode register 775 may provide an invalid enable signal En to CS suppression circuit 747, causing the column decoder not to suppress the activation of any column selection in the physical column plane. Mode register 775 is programmable with a value in a second state indicating that metadata is not stored in the memory array. When metadata is not stored in the memory array, mode register 775 may provide an valid En signal to CS suppression circuit 747 to suppress column selection in certain physical column planes.

[0091] In some embodiments, the CS suppression circuit 747 may include one or more logic circuits to implement a decoding scheme to provide desired suppression of column selection when enabled. For example, the CS suppression circuit 747 may include decoding logic to implement reference Figure 8 The suppression scheme is described. In some embodiments, the CS suppression circuit 747 may include one or more logic circuits implementing the binary decoding scheme shown in Table 900.

[0092] The first column of Table 900 indicates the column selection signal (CS). The next six columns indicate the binary inputs to be decoded. The last column indicates the physical column plane (CP) to which the indicated CS is suppressed. The first three inputs can be used to indicate the CP to be suppressed (columns labeled 5 to 3). The CS suppression circuit 747 can invert the first three inputs to determine the first physical column plane to suppress CS activation of a specific CS. For example, in row CS7:0, the input is "000". After inversion, this is "111", which corresponds to 7. Therefore, as indicated by the last column, CS activation in physical CP07 is suppressed when any or all of CS0 to 7 are selected and activated. The CS suppression circuit 747 can add 8 to the inverted input to determine the second physical column plane to suppress CS activation. Continuing the above example, "111" plus 8 is "1111", which corresponds to 15. Therefore, as indicated by the last column, CS activation in physical CP15 is suppressed. This is consistent with... Figure 8 Matching, where CS0 to 7 of CP07 and CP15 are blocked.

[0093] In the CS suppression circuit 747, any suitable logic circuitry can be used to implement Table 900. In some embodiments, the remaining two inputs (columns labeled 2 to 0) may be omitted. In other embodiments, the remaining inputs may be used to provide additional information to other components of the CS suppression circuit 747 and / or the column decoder 745.

[0094] In some embodiments, the CS suppression circuit 747 may include logic circuitry to implement tables 700 and 900. In some embodiments, the mode register 775 is programmable with a value indicating which decoding scheme should be enabled. In a first state, the mode register 775 may provide a signal to enable the logic circuitry implementing table 700 and disable the logic circuitry implementing table 900. In a second state, the mode register 775 may provide a signal to enable the logic circuitry implementing table 900 and disable the logic circuitry implementing table 700. In some embodiments, when metadata is stored in a memory array, the mode register 775 may disable both sets of logic circuitry.

[0095] Memory devices (e.g., memory device 104, semiconductor device 200) according to embodiments disclosed herein can generate and store ECC data that can be used by ECC circuitry (e.g., ECC circuitry 235, ECC circuitry 332) to correct errors in data and / or metadata. Typically, ECC circuitry can only correct and / or detect a specific number of errors in a set of bits. For example, some ECC circuitry can correct one error in a set of data and detect up to two errors. The number of errors that can be corrected and / or detected can be based on the number of bits to be corrected and the number of parity bits generated.

[0096] The capabilities of a system's ECC circuit may have additional limitations. For example, a system ECC circuit may be limited to correcting errors in certain portions of the data. For instance, an ECC circuit might be able to correct errors in the upper half-byte (e.g., 4 bits) or lower half-byte of a single byte, but not errors extending across half-bytes. Therefore, a "fault line" may exist between the upper and lower half-bytes. Errors crossing the fault line may not be correctable by the ECC circuit. Therefore, it is desirable to use techniques to prevent errors from "smearing" across fault lines to reduce the risk and / or frequency of uncorrectable errors. When the error is confined to either side of the fault line, it can be referred to as a "bounded fault" implementation.

[0097] The location of the fault line (e.g., between the upper and lower nibble lines) can be based on various factors, such as how error correction data is generated, the physical layout of the memory device, and / or other factors. According to embodiments of this disclosure, data in a virtual plane spanning physical column planes can be mapped in a way that reduces the risk of errors crossing the fault line. For example, the data in the virtual plane can be stored in one or more physical column planes, and when multiple physical column planes are used, all column planes are positioned on the same side of the fault line.

[0098] In some embodiments, data may be mapped such that the data of the virtual plane is stored in the upper or lower byte of the memory device. Depending on the layout of the memory array, in some embodiments, this may include mapping the data of the virtual plane such that data for each virtual plane is provided on a word line driven by a sub-word line driver associated with the same half-byte. In some embodiments, mapping the data of the virtual plane across physical column planes may provide a bounded fault-compliant implementation.

[0099] Figure 10 A table showing indications of physical column plane suppression according to some embodiments of the present disclosure is provided. The suppression schemes depicted in Table 1000 can be used when a memory (e.g., one or more of memory device 104 and / or semiconductor device 200) utilizes a metadata column plane.

[0100] Table 1000 can be roughly similar to Figure 6 Table 600 is shown in the table. Specifically, the column plane suppression scheme is the same between the two tables. However, contrary to Table 600, each physical column plane CP is associated only with the data of the corresponding virtual plane. For example, as shown in the column indicated by arrow 1002, physical column plane CP2 is associated only with the data of virtual column plane CP2, while... Figure 6 In the current layout, the physical column plane CP2 is associated with the data of the virtual column planes CP2 and CP1. The remaining data for each virtual plane CP0 to 15 is stored in the column indicated by arrow 1004 in the metadata plane. This change requires no modification. Figure 6 The column suppression scheme is shown in the image.

[0101] However, the mappings shown in Table 1000 increase the risk of uncorrectable errors. For example, such as... Figure 10 As shown, data from the physical metadata plane is driven by the subword line driver SWD4, located between the physical planes CP7 and MD. If SWD4 is defective, it can lead to incorrect data transmission or reception and / or erroneous data storage. Therefore, data stored in the virtual plane within the physical metadata plane may be received with errors. While the metadata plane can store data associated only with the four column select signals of each virtual plane, errors will occur in the half-byte that differs from the remaining portion of the data in the half-virtual plane. Therefore, the half-virtual plane will be at greater risk of uncorrectable errors because errors can be smeared across both the upper and lower half-bytes.

[0102] Return to Figure 6 The data mapping from the virtual plane to the physical column plane reduces the location of errors smeared across nibble boundaries. Therefore, in some applications, the mapping shown in Table 600 may be better than that shown in Table 1000. However, despite the improvement, the mapping shown in Table 600 may not necessarily conform to bounded faults when a lower nibble / upper nibble error fault line exists. Figure 6 In the mapping shown, SWD4 receives data associated with virtual planes CP6, CP7, and CP8. If SWD4 transmits faulty data, errors may occur on both sides of the nibble fault lines of the data associated with CS0 through 31 because the data in virtual plane CP8 spans the upper and lower nibble boundaries. Therefore, the ECC circuit may be unable to correct errors in virtual plane CP8.

[0103] Figure 11 A table illustrating physical column plane suppression of bounded fault implementation schemes according to some embodiments of the present disclosure is provided. The suppression schemes depicted in Table 1100 can be used when a memory (e.g., one or more of memory device 104 and / or semiconductor device 200) utilizes a metadata column plane.

[0104] Table 1100 can be roughly similar to Figure 6 Table 600 is shown in the diagram. Specifically, the column plane suppression scheme is the same between the two tables. However, contrary to Table 600, the ECC data associated with CS0 through 31 is mapped to the physical metadata plane, as shown in the column indicated by arrow 1102, and the CP8 data associated with CS0 through 31 is mapped to the physical ECC plane, as shown in the column indicated by arrow 1104. This remapping now allows a portion of the CP8 data to be provided to SWD5. This limits faults and prevents errors from crossing nibble fault boundaries. Because both the ECC plane and the MD plane contain 64 column selections, no suppression is required, and the remapping does not require modification of the suppression scheme.

[0105] It should be understood that Figure 11 This is merely a bounded fault data mapping from the virtual plane to the physical column plane. Other mappings can also provide bounded fault implementation schemes. Furthermore, depending on the number of virtual and physical column planes, memory layout (e.g., the number and location of subword drivers) and / or other factors (e.g., the ECC algorithm used), other mappings can provide bounded fault implementation schemes for the virtual plane.

[0106] Figures 12 to 17 The flowchart illustrates an example of a method that can be performed according to embodiments of the present disclosure, allowing single-pass access to data, metadata, and ECC data when metadata storage is enabled, and access to data when metadata storage is disabled. The method may be wholly or partially implemented by a computing system (e.g., Figure 1 The computing system 100 shown in the image), and the device (e.g.) Figure 1 Memory device 104 in Figure 2 Semiconductor devices 200, as shown in the exhibition Figure 3 The memory device 300 shown in the image Figure 4 The memory device 400 shown in the image Figure 5 The memory device 500 and / or shown in the image Figure 7 (One or more of the memory devices 701 shown in the figure) execute.

[0107] Figure 12 This is a flowchart of a method according to some embodiments of the present disclosure. According to some embodiments, the method illustrated in flowchart 1200 allows single-pass access to data, metadata, and ECC data when metadata storage is enabled, and access to data when metadata storage is disabled.

[0108] At block 1202, it is possible to "provide column selection signals to a plurality of column planes configured to store data and a first column plane configured to store metadata". In some embodiments, the provision may be performed by a column decoder, such as column decoder 245.

[0109] At block 1204, it is possible to "receive data from multiple column planes and metadata from a first column plane associated with a column selection signal". In some embodiments, the sense amplifier may receive data and metadata, such as... Figure 2 The sensor amplifier SAMP shown in the image Figure 3 The sensor amplifiers 320, 322, 324 and 326 are shown in the image.

[0110] Optionally, the method shown in flowchart 1200 may further include block 1206, in which "providing a column select signal to a second column plane configured to store error correction code (ECC) data" can be performed. The provision can be performed by a column decoder. The method may further include "receiving ECC data from the second column plane associated with the column select signal" performed at block 1208.

[0111] Optionally, the method shown in flowchart 1200 may further include “providing data, metadata, and ECC data to ECC circuitry” as indicated by block 1210, and “correcting errors in the data, metadata, or a combination thereof” as indicated by block 1212. In some embodiments, the data may be corrected by the ECC circuitry based on the ECC data. The method may further include block 1214, in which “providing the error-corrected data and metadata from the ECC circuitry to the input / output circuitry” is performed. In some embodiments, the data and / or metadata may be provided to a controller, such as controller 106 and / or controller 202.

[0112] When the column plane has been repaired, the method shown in flowchart 1200 may include providing the column selection signal from the column decoder to the global column redundancy (GCR) plane and receiving data or metadata from the GCR plane associated with the column selection signal at multiple sense amplifiers.

[0113] Optionally, the method may further include receiving a mode register write command and writing a value to the mode register in response to the mode register write command, wherein the state configuration metadata of the value is stored in a second plane. In some embodiments, the mode register may be mode register 275 and / or 775.

[0114] Figure 13 This is a flowchart of a method according to some embodiments of the present disclosure. The method shown in flowchart 1300 allows a physical column plane to be arranged to store data and metadata, or arranged to store data. For example, as referenced... Figure 3 , 4 The descriptions in figures 5, 6, and 8 are not limited to these figures.

[0115] At block 1302, a "receive mode register write command and value to be written to the mode register" can be executed. In some embodiments, the command may be received from the controller at a memory device. In response to the mode register write command, at block 1304, a "write value to the mode register" can be executed. In some embodiments, when the value is in a first state, the method may include configuring a first physical column plane to store metadata and configuring a plurality of physical column planes to store data, and when the value is in a second state, the method may further include configuring the first physical column plane and the plurality of physical column planes to store data.

[0116] In some embodiments, configuring a first physical column plane and a plurality of physical column planes to store data includes configuring the first physical column plane and the plurality of physical column planes as a plurality of virtual planes. In some embodiments, configuring the plurality of virtual planes includes providing a first set of column select signals from the first column plane to the first virtual plane among the plurality of virtual planes and providing a second set of column select signals from the first column plane to the second virtual plane. In some embodiments, all of the plurality of virtual planes are associated with column select signals from at least two different physical column planes.

[0117] Optionally, the method shown in flowchart 1300 may further include block 1306, wherein, when the value is a first state, the action of “providing a valid column select signal from the column decoder to a first physical column plane and multiple physical column planes” is performed. The method may further include “receiving metadata from the first physical column plane and data from the multiple physical column planes associated with the valid column select signal”, as indicated by block 1308.

[0118] Optionally, the method shown in flowchart 1300 may further include block 1310, wherein when the value is a second state, the action of "providing a valid column select signal from the column decoder to at least one of a first physical column plane and a plurality of physical column planes" is performed. The method may further include "receiving data from at least one of the first physical column plane and a plurality of physical column planes associated with the valid column select signal," as indicated by block 1312.

[0119] Figure 14 This is a flowchart of a method according to some embodiments of the present disclosure. The method shown in flowchart 1400 can provide a column selection suppression scheme according to some embodiments of the present disclosure. For example, as referenced... Figure 6 and 7 Descriptions, but not limited to these figures.

[0120] At box 1402, a "Receive mode register write command and value to be written to the mode register" can be executed. In response to the mode register write command, at box 1404, a "Write value to mode register" can be executed. When the value is in the first state, the method may include configuring the first physical column plane to store metadata and configuring multiple physical column planes to store data.

[0121] When the value is in the second state, the method shown in flowchart 1400 may further include "configuring the first physical column plane and the plurality of physical column planes to store data" performed at block 1406 and "selectively suppressing the column select signal of one of the plurality of physical column planes with the column decoder" performed at block 1408. In some embodiments, the method in flowchart 1400 may include enabling the column decoder to perform selective suppression when the value is in the second state. In some embodiments, enabling the column decoder includes providing an enable signal from the mode register to the column select suppression circuitry of the column decoder. In some embodiments, when suppression is enabled, the column decoder provides a valid column select signal to the first physical column plane and all but one of the plurality of physical column planes. In some embodiments, the method includes disabling the column decoder from selectively suppressing the column select signal when the value is in the first state.

[0122] Optionally, the method shown in flowchart 1400 may further include block 1410, in which "decoding the input to determine the physical column planes among a plurality of column planes to suppress the column selection signal" is performed. In some embodiments, decoding includes inverting a plurality of binary inputs.

[0123] Optionally, the method shown in flowchart 1400 may further include receiving data from a first physical column plane associated with the valid column select signal and all but one of a plurality of physical column planes. In some embodiments, the method shown in flowchart 1400 may further include providing the valid column select signal to a second physical column plane configured to store error correction code (ECC) data and receiving ECC data from the second physical column plane associated with the valid column select signal. In some embodiments, the method may further include providing the data and ECC data to error correction code (ECC) circuitry and correcting errors in the data based on the ECC data.

[0124] Figure 15 This is a flowchart of a method according to some embodiments of the present disclosure. The method shown in flowchart 1500 can be implemented in an architecture where two physical planes are used to store metadata when metadata storage is enabled. When metadata storage is disabled, the two metadata planes can be used to store data. For example, as referenced... Figure 5 , 8 And 9 are described, but not limited to these figures.

[0125] At block 1502, the action of "providing a column select signal to multiple column planes" can be performed. In some embodiments, the provisioning can be performed by a column decoder. The column planes can be configured to store data, and the first and second column planes can be configured to store metadata. At block 1504, the action of "receiving data from multiple column planes and metadata from the first and second column planes associated with the column select signal" can be performed. In some embodiments, the data and metadata can be received at multiple sense amplifiers.

[0126] Optionally, the method shown in flowchart 1500 may further include receiving a mode register write command and a value to be written to the mode register, and writing the value to the mode register in response to the mode register write command. When the value is in a first state, the method may include configuring a first column plane and a second column plane to store metadata and configuring multiple column planes to store data, and when the value is in a second state, the method may include configuring the first column plane, the second column plane, and multiple column planes to store data.

[0127] In some embodiments, configuring the first column plane, the second column plane, and the plurality of column planes to store data includes configuring the first column plane, the second column plane, and the plurality of column planes as a plurality of virtual planes. In some embodiments, configuring the plurality of virtual planes includes providing a first set of column select signals from the first column plane to the first virtual plane among the plurality of virtual planes and providing a second set of column select signals from the second column plane to the second virtual plane. In some embodiments, the first column plane and the second column plane are each associated with 64 column select signals, each of the plurality of column planes is associated with 60 column select signals, and each of the plurality of virtual planes is associated with 64 column select signals.

[0128] In some embodiments, when metadata storage is disabled (e.g., the value is in a second state), the method may include selectively suppressing column selection signals of two of a plurality of column planes using a column decoder. In some embodiments, the method may further decode the inputs to determine two of the plurality of column planes to suppress column selection signals, wherein decoding includes inverting a plurality of binary inputs to determine a first suppressed column plane and adding 8 to the inverted plurality of binary inputs to determine a second suppressed column plane. In some embodiments, the number of the plurality of binary inputs is 3. In some embodiments, different pairs of the plurality of column planes have column selection signals suppressed due to a different set of column selection signals from the plurality of column selection signals. In some embodiments, the number of the plurality of column selection signals is 64, and each set of column selection signals comprises 8 of the plurality of column selection signals.

[0129] Figure 16This is a flowchart of a method according to some embodiments of the present disclosure. The method shown in flowchart 1600 can map data associated with a virtual plane to a physical column plane to reduce or eliminate uncorrectable errors by providing a bounded fault implementation.

[0130] At block 1602, a "receive mode register write command and value to be written to the mode register" can be executed. At block 1604, in response to the mode register write command, a "write value to the mode register" can be executed. When the value is in a first state, the method may include configuring a first physical column plane among a plurality of column planes to store metadata and configuring the remainders among the plurality of physical column planes to store data. When the value is in a second state, the method may include "configuring a plurality of physical column planes to store data, wherein the data is associated with a plurality of virtual planes, wherein the data of an individual among the plurality of virtual planes is configured to be stored in one or more of the plurality of physical column planes on the same side of the fault line," as indicated by block 1606. In some embodiments, the fault line is located between the lower half-byte and the upper half-byte.

[0131] Optionally, in some embodiments, the method in flowchart 1600 may further include storing individual data from a plurality of virtual planes in one or more of a plurality of physical column planes associated with the same subword line driver. In some embodiments, the method in flowchart 1600 may further include storing individual data from a plurality of virtual planes in one or more of a plurality of physical column planes associated with one or more subword line drivers on the same side of the fault line.

[0132] Optionally, when the value is in the second state, the method in flowchart 1600 may further include storing data of multiple virtual planes in multiple physical column planes and storing error correction code (ECC) data associated with the data in an ECC plane. The method may further include providing data associated with the virtual planes among the multiple virtual planes and ECC data corresponding to the virtual planes to an ECC circuit and correcting errors in the data using the ECC circuit based on the ECC data. In some embodiments, providing data associated with the virtual planes includes providing data from two physical column planes among the multiple column planes. In some embodiments, the error is on a first or second side of the fault line.

[0133] Figure 17 This is a flowchart of a method according to some embodiments of the present disclosure. The method shown in flowchart 1700 can utilize the ECC plane to provide a bounded fault-compliant implementation. For example, as referenced... Figure 11 describe.

[0134] At block 1702, a "receive mode register write command and value to be written to the mode register" can be executed. In response to the mode register write command, at block 1704, a "write value to the mode register" can be executed. When the value is in a first state, the method may include configuring the first physical column plane to store metadata and configuring multiple physical column planes to store data. When the value is in a second state, the method may include "configuring multiple physical column planes to store data, configuring the first physical column plane to store data and error correction code (ECC) data, and configuring the ECC plane to store data and ECC data," as indicated by block 1706. In some embodiments, configuring the first physical column plane, the ECC plane, and the multiple physical column planes to store data includes configuring the first physical column plane, the ECC plane, and the multiple physical column planes as multiple virtual planes.

[0135] Optionally, the method shown in flowchart 1700 may further include: block 1708, in which "receiving data associated with a first virtual plane and a second virtual plane among a plurality of virtual planes in association with a first sub-word line driver"; and block 1710, in which "receiving ECC data stored in a first physical plane in association with a first sub-word line driver".

[0136] Optionally, the method shown in flowchart 1700 may further include: block 1712, in which "receiving data associated with a third and fourth virtual plane among a plurality of virtual planes in association with a second sub-word line driver"; and block 1714, in which "receiving ECC data stored in an ECC plane in association with a second sub-word line driver".

[0137] In some embodiments, when the value is a first state, the method may include receiving metadata associated with a first physical column plane among a plurality of physical column planes and data associated with a second physical column plane in association with a first sub-word line driver, and receiving ECC data associated with an ECC plane and data associated with a third physical column plane among a plurality of physical column planes in association with a second sub-word line driver.

[0138] Optionally, the method shown in flowchart 1700 may include: activating column select signals from column select signals 0 to 31; receiving data associated with a first virtual plane among a plurality of virtual planes from the ECC plane in response to the column select signals; and receiving ECC data from a first physical column plane in response to the column select signals. The method may further include: activating column select signals from column select signals 32 to 63; receiving data associated with a second virtual plane among a plurality of virtual planes from the first physical column plane in response to the column select signals; and receiving ECC data from the ECC plane in response to the column select signals. In some embodiments, data is received in association with a first subword line driver, and ECC data is received in association with a second subword line driver.

[0139] As disclosed herein, providing one or more additional column planes for metadata allows for efficient storage of metadata in the memory array and enables retrieval of data, metadata, and ECC data in a single pass. Furthermore, utilizing virtual column planes allows for the flexible use of more physical column planes to store data when no metadata is being used.

[0140] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes, or may be separated and / or performed between individual means or parts of a system, apparatus, or method according to the present invention.

[0141] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, while the system of the invention has been described in particular detail with reference to exemplary embodiments, it should be understood that those skilled in the art will conceive of numerous modifications and alternative embodiments without departing from the broader and contemplated spirit and scope of the system of the invention as set forth in the appended claims. Thus, the specification and drawings should be regarded as illustrative and not intended to limit the scope of the appended claims.

Claims

1. An apparatus comprising: a memory array including a bank, wherein the bank includes a first physical column plane, a plurality of physical column planes, and an error correction code (ECC) plane; and a mode register configured to store a value, wherein: when the value is a first state, the first physical column plane is configured to store metadata, the plurality of physical column planes are configured to store data, and the ECC plane is configured to store ECC data; wherein when the value is a second state, the plurality of physical column planes are configured to store the data, a first portion of the first physical column plane is configured to store data, a first portion of the first physical column plane is configured to store the ECC data, and a second portion of the ECC plane is configured to store ECC data, and a fourth portion of the ECC plane is configured to store data.

2. The apparatus of claim 1, wherein the first physical column plane, the plurality of physical column planes, and the ECC plane are each associated with a plurality of column select signals, wherein when the value is in the second state, the plurality of column select signals are associated with a plurality of virtual column planes configured to store the data.

3. The apparatus of claim 2, wherein a first set of the plurality of column select signals of the first physical column plane are associated with the ECC data, and a second set of the plurality of column select signals of the first physical column plane are associated with the data of a first virtual plane of the plurality of virtual column planes.

4. The apparatus of claim 3, wherein the first set of the plurality of column select signals of a second physical column plane of the plurality of physical column planes are associated with the data of the first virtual plane, and the second set of the plurality of column select signals of the second physical column plane are associated with the data of a second virtual plane.

5. The apparatus of claim 4, further comprising a sub word line driver, wherein the first physical column plane is configured to provide the ECC data and the data of the first virtual plane associated with the sub word line driver, and the second physical column plane is configured to provide the first virtual plane and the data of the second virtual plane associated with the sub word line driver.

6. The apparatus of claim 3, wherein the first set of the plurality of column select signals of the ECC plane are associated with the data of a third virtual plane of the plurality of virtual planes, and the second set of the plurality of column select signals of the ECC plane are associated with the ECC data.

7. The apparatus of claim 6, further comprising a second sub word line driver, wherein the ECC column plane is configured to provide the ECC data associated with the second sub word line driver and the data associated with the third virtual plane.

8. The apparatus of claim 7, wherein the second sub word line driver is different from a sub word line driver associated with the ECC data from the first physical column plane and the data of the first virtual plane.

9. The apparatus of claim 3, wherein the first set of the plurality of column select signals comprises 32 column select signals and the second set of the plurality of column select signals comprises 32 column select signals.

10. The apparatus of claim 3, wherein each of the plurality of virtual planes is associated with 64 column select signals of the plurality of column select signals.

11. A system comprising: a controller; and a memory module comprising a plurality of memory devices, wherein at least one memory device of the plurality of memory devices comprises: a memory array including a bank, wherein the bank includes a first physical column plane, a plurality of physical column planes, and an error correction code (ECC) plane; and a mode register configured to store a value, wherein: when the value is a first state, the first physical column plane is configured to store metadata, the ECC plane is configured to store ECC data, and the plurality of physical column planes are configured to store data, and when the value is a second state, a portion of the first physical column plane, a first portion of the ECC plane, and the plurality of physical column planes are configured to store the data, and another portion of the first physical column plane and another portion of the ECC plane are configured to store the ECC data.

12. The system of claim 11, wherein the controller is configured to provide the value to the mode register.

13. The system of claim 11, wherein the first physical column plane is associated with a first sub word line driver and the ECC plane is associated with a second sub word line driver.

14. The system of claim 11, wherein each of the plurality of physical column planes is associated with 60 column select signals, the first physical column plane is associated with 64 column select signals, and the ECC plane is associated with 64 column select signals.

15. The system of claim 11, wherein at least a portion of a plurality of column select signals associated with the plurality of physical column selection planes, the first physical column plane, and the ECC plane are associated with a plurality of virtual planes configured to store data.

16. The system of claim 15, wherein all but two of the plurality of column select signals are associated with two different ones of the plurality of virtual planes.

17. The system of claim 15, wherein half of the plurality of column select of the ECC plane are associated with the ECC data and the other half of the plurality of column select signals of the ECC plane are associated with a first virtual plane of the plurality of virtual planes, and half of the plurality of column select signals of the first physical column plane are associated with the ECC data and the other half are associated with a second virtual plane of the plurality of virtual planes.

18. A method comprising: receiving a mode register write command and a value to be written to a mode register; writing the value to the mode register in response to the mode register write command; configuring a first physical column plane to store metadata and configuring a plurality of physical column planes to store data when the value is a first state; and configuring the plurality of physical column planes to store the data, configuring the first physical column plane to store the data and error correction code (ECC) data, and configuring an ECC plane to store data and ECC data when the value is a second state.

19. The method of claim 18, wherein configuring the first physical column plane, the ECC plane, and the plurality of physical column planes to store the data comprises configuring the first physical column plane, the ECC plane, and the plurality of physical column planes as a plurality of virtual planes.

20. The method of claim 19, further comprising: receiving the data associated with a first virtual plane and a second virtual plane of the plurality of virtual planes in association with a first sub word line driver; and receiving the ECC data stored in the first physical column plane at the first sub word line driver.

21. The method of claim 20, further comprising: receiving the data associated with a third virtual plane and a fourth virtual plane of the plurality of virtual planes in association with a second sub word line driver; and receiving the ECC data stored in the ECC plane in association with the second sub word line driver.

22. The method of claim 18, wherein when the value is the first state, the method further comprises: receiving the metadata associated with the first physical column plane and the data associated with a second physical column plane of the plurality of physical column planes in association with a first sub word line driver; and receiving the ECC data associated with the ECC plane and the data associated with a third physical column plane of the plurality of physical column planes in association with a second sub word line driver.

23. The method of claim 19, further comprising: activating a column select signal from column select signals 0-31; receiving data associated with a first virtual plane of the plurality of virtual planes from the ECC plane in response to the column select signal; and receiving ECC data from the first physical column plane in response to the column select signal.

24. The method of claim 23, further comprising: activating a column select signal from column select signals 32-63; receiving data associated with a second virtual plane of the plurality of virtual planes from the first physical column plane in response to the column select signal; and receiving ECC data from the ECC plane in response to the column select signal.

25. The method of claim 23, wherein the data is received in association with a first sub word line driver and the ECC data is received in association with a second sub word line driver.

Images