Charging circuit and power adapter

Abstract

The invention relates to the technical field of electronic circuits, in particular to a charging circuit and a power adapter, the charging circuit comprises a first transistor unit, a second transistor unit, a current control unit, a voltage stabilization control unit and a main control unit; the first transistor unit and the second transistor unit output charging current to a load or a first charging interface, and the main control unit receives a current feedback adjusting signal to control the first transistor unit and the second transistor unit to output corresponding charging current; the current control unit controls the charging current output by the first transistor unit and the second transistor unit to be balanced; the voltage stabilization control unit controls the output charging voltage to be stabilized at a reference voltage value. According to the charging circuit provided by the invention, relatively large charging current can be provided for the electronic equipment in a balanced manner, so that the charging speed of the electronic equipment is ensured, rapid charging of the electronic equipment is realized, and the endurance problem of the electronic equipment is solved.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more particularly to a charging circuit and a power adapter. Background Technology

[0002] With the widespread use of smartphones and the increasing demand from users for longer battery life, fast charging technology for smartphones has emerged as lithium battery technology has yet to achieve a breakthrough in improving energy density. It can replenish the battery in a short time, thus highlighting the increasing importance of fast charging technology.

[0003] Without revolutionary breakthroughs in battery materials and chemistry, improving charging technology for smart devices has become the main development direction. Among related technologies, increasing battery capacity and improving charging current are the main approaches to solving charging problems. However, for low-end electronic products, in order to reduce costs, new charging circuits are designed to increase charging current, thereby improving the charging speed of electronic devices and ensuring rapid recharging. Summary of the Invention

[0004] This application provides a charging circuit and a power adapter to solve the technical problem of insufficient battery life of mobile terminals in related technologies. By increasing the charging current of electronic devices, the purpose of quickly replenishing the power of electronic devices is achieved.

[0005] In a first aspect, this application provides a charging circuit, the charging circuit comprising: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, and a main control unit; The input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage. The output terminals of the first transistor unit and the second transistor unit are both connected to the charging output terminal. The charging output terminal is used to connect to a load or a first charging interface to output charging current to the load or the first charging interface. The main control unit is used to receive current feedback adjustment signals and output corresponding control voltage signals according to the current feedback adjustment signals. The control voltage signals are used to control the first transistor unit and the second transistor unit to output corresponding charging currents. The current control unit is used to sample the input current at the input terminal of each transistor unit and output a corresponding current balancing control signal according to the input current, so as to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing. The voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal, and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and the preset reference voltage value, so as to control the output charging voltage to be stable at the reference voltage value.

[0006] In one possible design, the charging circuit further includes a constant current charging unit connected to the charging output terminal. The main control unit is also used to receive a pre-charge trigger signal fed back from the load end, and output a first enable signal to the constant current charging unit according to the pre-charge trigger signal; the constant current charging unit outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0007] In one possible design, the control signal output pin of the main control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively, so as to output the control voltage signal to the first transistor unit and the second transistor unit, respectively. The input terminal of the current control unit is connected to the input terminal of the first transistor unit and the input terminal of the second transistor unit, respectively, and the output terminal of the current control unit is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively, so as to output the current equalization control signal to the first transistor unit and the second transistor unit.

[0008] In one possible design, the main control unit includes a charging detection pin connected to a power input terminal to detect whether an external power source is connected to the power input terminal, and outputs a corresponding indication signal based on the detection result; and when the indication signal indicates that an external power source is connected, it controls the first transistor unit, the second transistor unit, and the voltage regulation control unit to start working. The input terminals of the first transistor unit and the second transistor unit are both connected to the power input terminal, which is used to receive the input current from an external power source.

[0009] In one possible design, the charging circuit further includes a first charging interface for connecting a load. The charging output terminal is connected to the power supply pin on the first charging interface; the clock signal pin and data communication pin of the main control unit are respectively connected to the corresponding clock signal pin and data communication pin on the first charging interface.

[0010] In one possible design, the first transistor unit includes a first transistor and a first NMOS transistor. The emitter of the first transistor is the input terminal of the first transistor unit, and the collector of the first transistor is the output terminal of the first transistor unit. The emitter of the first transistor is connected to the power input terminal, the base of the first transistor is connected to the drain of the first NMOS transistor, the source of the first NMOS transistor is the control terminal of the first transistor unit, the source of the first NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the first NMOS transistor is connected to the power input terminal. The second transistor unit includes a second transistor and a second NMOS transistor. The emitter of the second transistor is the input terminal of the second transistor unit, and the collector of the second transistor is the output terminal of the second transistor unit. The emitter of the second transistor is connected to the power input terminal, the base of the second transistor is connected to the drain of the second NMOS transistor, the source of the second NMOS transistor is the control terminal of the second transistor unit, the source of the second NMOS transistor is connected to the output terminal of the current control unit and the control signal output pin of the main control unit, and the gate of the second NMOS transistor is connected to the power input terminal.

[0011] In one possible design, the charging circuit further includes a first resistor and a second resistor; a first end of the first resistor is connected to the power input terminal, and a second end of the first resistor is connected to the emitter of the first transistor; a first end of the second resistor is connected to the power input terminal, and a second end of the second resistor is connected to the emitter of the second transistor. The current control unit includes a first operational amplifier, a second operational amplifier, and a third operational amplifier; the non-inverting input terminal of the first operational amplifier is connected to the first terminal of the first resistor, the inverting input terminal of the first operational amplifier is connected to the second terminal of the first resistor, and the output terminal of the first operational amplifier is connected to the inverting input terminal of the third operational amplifier. The non-inverting input terminal of the second operational amplifier is connected to the first terminal of the second resistor, the inverting input terminal of the second operational amplifier is connected to the second terminal of the second resistor, and the output terminal of the second operational amplifier is connected to the non-inverting input terminal of the third operational amplifier. The output terminal of the third operational amplifier is connected to the control terminal of the first transistor unit and the control terminal of the second transistor unit, respectively.

[0012] In one possible design, the constant current charging unit includes a first reference voltage generation chip, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth operational amplifier, and a first NMOS transistor; The enable terminal of the first reference voltage generation chip is connected to the first enable pin on the main control unit. The voltage output pin of the first reference voltage generation chip is connected to the first end of the sixth resistor. The second end of the sixth resistor is connected to the non-inverting input terminal of the fourth operational amplifier and the first end of the seventh resistor. The second end of the seventh resistor is grounded. The output terminal of the fourth operational amplifier is connected to the first end of the ninth resistor. The second end of the ninth resistor is connected to the gate of the third NMOS transistor. The drain of the third NMOS transistor is connected to the charging output terminal. The source of the third NMOS transistor is connected to the first end of the eighth resistor and the first end of the tenth resistor. The second end of the eighth resistor is connected to the inverting input terminal of the fourth operational amplifier. The second end of the tenth resistor is grounded. The first reference voltage generation chip is used to receive the first enable signal output by the main control unit, and output the first reference voltage signal when triggered by the first enable signal.

[0013] In one possible design, the voltage regulation control unit includes a second reference voltage generation chip, a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor, and a third PMOS transistor; The enable terminal of the second reference voltage generation chip is connected to the second enable pin on the main control unit. The voltage output pin of the second reference voltage generation chip is connected to the non-inverting input terminal of the fifth operational amplifier. The output terminal of the fifth operational amplifier is connected to the first terminal of the thirteenth resistor. The second terminal of the thirteenth resistor is connected to the drain of the third PMOS transistor. The source of the third PMOS transistor is connected to the power supply pin on the first charging interface and the first terminal of the fourteenth resistor. The second terminal of the fourteenth resistor is connected to the inverting input terminal of the fifth operational amplifier. The main control unit is further configured to output a second enable signal to the second reference voltage generation chip when an external power supply is detected to be connected to the power input terminal; the second reference voltage generation chip is configured to output a second reference voltage signal when triggered by the second enable signal.

[0014] Secondly, this application provides a power adapter, which includes a charging circuit as described in any of the preceding claims.

[0015] The charging circuit provided by the first aspect above includes: a first transistor unit, a second transistor unit, a current control unit, a voltage regulation control unit, and a main control unit; the input terminals of the first transistor unit and the second transistor unit are both used to receive input voltage, and the output terminals of the first transistor unit and the second transistor unit are both connected to a charging output terminal, which is used to connect to a load or a first charging interface to output charging current to the load or the first charging interface; the main control unit is used to receive a current feedback adjustment signal and output a corresponding control voltage signal according to the current feedback adjustment signal, which is used to control the first transistor unit and the second transistor unit to output the corresponding charging current; the current control unit is used to sample the input current at the input terminals of each transistor unit and output a corresponding current balancing control signal according to the input current to control the charging current output by the first transistor unit and the second transistor unit to achieve balancing; the voltage regulation control unit is used to sample the battery voltage value output at the charging output terminal and output a corresponding voltage regulation control signal according to the relationship between the battery voltage value and a preset reference voltage value to control the output charging voltage to stabilize at the reference voltage value. As can be seen, according to the charging circuit provided in this application, the first transistor unit and the second transistor unit work simultaneously, which can provide a large charging current to the electronic device in a balanced manner to ensure the charging speed of the electronic device, thereby realizing rapid power replenishment of the electronic device and solving the battery life problem of the electronic device.

[0016] The beneficial effects provided by the other aspects and the various possible designs of the other aspects can be found in the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0017] Figure 1 A schematic diagram of the overall structure of the charging system provided for related technologies; Figure 2 This is a schematic diagram of the overall structure of the charging system provided in the embodiments of this application; Figure 3 This is a schematic diagram of the overall structure of the charging circuit provided in the embodiments of this application; Figure 4 This is a schematic diagram of the specific structure of the charging circuit provided in the embodiment of this application. Detailed Implementation

[0018] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0020] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0021] While current fast charging technologies offer high charging speeds and power, they are costly and the chargers are bulky. Existing fast charging solutions typically integrate the charging chip module into a single device. However, both switching charging and linear charging solutions have certain drawbacks, primarily the release of power loss as heat during charging. In a room temperature of 25 degrees Celsius, especially while gaming, the phone's temperature rises between 25 and 35 degrees Celsius, eventually reaching around 50 to 55 degrees Celsius. This heat issue is particularly noticeable when playing demanding games outdoors in summer. Combined with the high current consumption of the power management chip and backlight, the heat problem is further exacerbated, not only affecting the user experience but also potentially shortening the chip's lifespan.

[0022] Figure 1 Please refer to the overall structural diagram of the charging system provided for related technologies. Figure 1 As shown, the charging system for electronic devices provided by related technologies mainly includes: a first charging adapter 100, a first USB interface 101, a second USB interface 102, and a first charging management unit 103. The first USB interface 101 and the second USB interface 102 are connected via a Universal Serial Bus (USB). The AC-DC conversion module within the first charging adapter 100 converts 220V AC power into a constant 5V DC voltage output. This 5V voltage is then transmitted to the first charging management unit 103 via the USB cable. Upon receiving the 5V voltage, the first charging management unit 103, under the control of a charging chip and a power management chip (PMIC), charges the battery. Currently, most electronic products on the market use existing charging solutions.

[0023] However, when charging electronic devices using the charging circuits provided by related technologies, the charging circuit at the power adapter end can only achieve voltage conversion and cannot output a constant charging voltage and current in an adjustable manner based on feedback from the electronic device. This necessitates constant voltage and constant current processing of the DC power output from the power adapter within the electronic device, thereby increasing internal heat generation and potentially causing electromagnetic interference in some electronic devices.

[0024] To overcome the shortcomings of the aforementioned related technologies, this application provides a charging circuit suitable for power adapters. It uses a parallel mode to construct two basic transistor unit circuits. Under the joint action of the current control unit, voltage regulation control unit, and main control unit, the total charging current is kept constant. When an electronic device is charged using a power adapter with the charging circuit provided in this application, the heat generated by the device during charging is reduced, improving user experience, extending device life, and increasing safety. Ultimately, it provides a low-cost cooling solution for electronic devices such as smartwatches, Bluetooth headsets, and other small consumer electronics.

[0025] Figure 2 For a schematic diagram of the overall structure of the charging system provided in the embodiments of this application, please refer to [link / reference]. Figure 2 As shown, the charging system provided in this application mainly comprises a second charging adapter 200, a third USB interface 201, a fourth USB interface 202, and a second charging management unit 203.

[0026] The charging adapter 200 circuit consists of a 220V AC input unit, an AC-DC conversion module, a charging module, and a logic control unit 200_1. The third USB interface 201 and the fourth USB interface 202 are connected via existing USB signal cables. The AC-DC conversion module converts the 220V AC power into 5V DC power, which is then used as the input voltage for the charging module and logic control unit 200_1. After processing by the charging circuit within the charging module and logic control unit 200_1, a VBAT_Charge power signal is output to charge the battery.

[0027] It should be noted that the charging circuit provided in this application is mainly used in the charging module and logic control unit 200_1 in the power adapter to output a stable charging voltage and charging current to the second charging management unit 203 in the electronic device. In this way, the second charging management unit 203 does not need to be equipped with additional voltage and current processing circuits and related control chips, which reduces the heat generation of the internal circuit of the electronic device, saves the internal space of the electronic device, and avoids the problem of electromagnetic interference in the electronic device.

[0028] Figure 3 For a schematic diagram of the overall structure of the charging circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 3 As shown, the charging circuit provided in this embodiment includes: a first transistor unit 31, a second transistor unit 32, a current control unit 33, a voltage regulation control unit 35, and a main control unit 34.

[0029] The input terminals of the first transistor unit 31 and the second transistor unit 32 are both used to receive input voltage. The output terminals of the first transistor unit 31 and the second transistor unit 32 are both connected to the charging output terminal S2, which is used to connect to a load or a first charging interface to output charging current to the load or the first charging interface. The main control unit 34 is used to receive current feedback adjustment signals and output corresponding control voltage signals V_drive according to the current feedback adjustment signals. The control voltage signal V_drive is used to control the first transistor unit 31 and the second transistor unit 32 to output corresponding charging currents. The current control unit 33 is used to sample the input current at the input terminals of each transistor unit and output corresponding current balancing control signals according to the input current to control the charging current output by the first transistor unit 31 and the second transistor unit 32 to achieve balancing. The voltage regulation control unit 35 is used to sample the battery voltage value output at the charging output terminal S2 and output corresponding voltage regulation control signals according to the relationship between the battery voltage value and the preset reference voltage value to control the output charging voltage to stabilize at the reference voltage value.

[0030] According to the charging circuit provided in this embodiment, when an external DC power is input, the first transistor unit 31 and the second transistor unit 32 work simultaneously. The main control unit 34 adjusts the output current of the first transistor unit 31 and the second transistor unit 32 according to the current feedback adjustment signal. At the same time, the current control unit 33 can control the output current values ​​of the first transistor unit 31 and the second transistor unit 32 to achieve balance. The voltage regulation control unit 35 can ensure that the output charging voltage is stable at the target value. In this way, a large charging current and a stable charging voltage can be provided to the electronic device in a balanced manner to ensure the charging speed of the electronic device, thereby realizing rapid power replenishment of the electronic device and solving the battery life problem of the electronic device.

[0031] In one embodiment of this application, the charging circuit further includes a constant current charging unit 36, which is connected to the charging output terminal S2; the main control unit 34 is also used to receive a pre-charge trigger signal fed back from the load terminal, and output a first enable signal to the constant current charging unit 36 ​​according to the pre-charge trigger signal; the constant current charging unit 36 ​​outputs a pre-charge current value under the trigger of the first enable signal to pre-charge the load.

[0032] Understandably, to protect battery lifespan, battery charging typically includes four stages: pre-charge, constant current charging, constant voltage charging, and trickle / pulses. The charging current is relatively small during the pre-charge and trickle / pulses stages. In this embodiment, to meet the requirements of low-current charging, the aforementioned constant current charging unit 36 ​​is provided. When the battery charging voltage is detected to be low, the main control unit 34 controls the constant current charging unit 36 ​​to operate, diverting a portion of the charging current to a smaller value. This ensures safe charging of the battery during the pre-charge and trickle / pulses stages, thereby guaranteeing battery lifespan.

[0033] In one embodiment of this application, the control signal output pin of the main control unit 34 is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively, so as to output the control voltage signal V_drive to the first transistor unit 31 and the second transistor unit 32, respectively. The control voltage signal V_drive is used to control the magnitude of the current output by the control terminal of the first transistor unit 31 and the second transistor unit 32, that is, the control voltage signal V_drive is used to control the magnitude of the first charging current I1 output by the first transistor unit 31 and the second charging current I2 output by the second transistor unit 32.

[0034] Among them, the main control unit 34 is the main control unit of the charging circuit in this embodiment. It can be a microcontroller unit (MCU) or other types of management chips with control functions.

[0035] In one embodiment of this application, the input terminal of the current control unit 33 is connected to the input terminal of the first transistor unit 31 and the input terminal of the second transistor unit 32, respectively, and the output terminal of the current control unit is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively, so as to output the current balancing control signal to the first transistor unit 31 and the second transistor unit 32, respectively. The current balancing control signal is mainly used to adjust the magnitude of the current flowing through the first transistor unit 31 and the second transistor unit 32, so that the magnitude of the two currents output by the first transistor unit 31 and the second transistor unit 32 is the same, so as to achieve the purpose of current balancing.

[0036] In one embodiment of this application, the input terminals of the first transistor unit 31 and the second transistor unit 32 are both connected to the power input terminal S1, which is used to receive the input current from an external power source. The main control unit 34 includes a charging detection pin, Power-EINT, which is connected to the power input terminal S1 via a third resistor R3 to detect whether an external power source is connected to the power input terminal S1. Based on the detection result, a corresponding indication signal is output. When the indication signal indicates that an external power source is connected, the first transistor unit 31, the second transistor unit 32, and the voltage regulation control unit 35 are controlled to start working, providing a relatively large charging current and a stable charging voltage to the electronic device in a balanced manner, thus ensuring the charging speed of the electronic device. Specifically, the charging detection pin Power-EINT of the main control unit 34 is a charging detection port. When there is a charging power output, the charging detection pin Power-EINT receives a 5V signal from the AC-DC conversion module, thus initiating the charging process of the entire circuit system.

[0037] Figure 4 For a detailed structural diagram of the charging circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 4 As shown, in one embodiment of this application, the charging circuit further includes a first charging interface 37, which is used to connect to a load or to a charging port on an electronic device; the charging output terminal S2 is connected to the power supply pin on the first charging interface 37; the clock signal pin SCL and the data communication pin SDA of the main control unit 34 are respectively connected to the corresponding clock signal pin and data communication pin on the first charging interface 37.

[0038] Please continue reading Figure 4As shown, in one embodiment of this application, the first transistor unit 31 includes a first transistor Q1 and a first NMOS (N-Metal-Oxide-Semiconductor) transistor Q3. The emitter of the first transistor Q1 is the input terminal of the first transistor unit 31, and the collector of the first transistor Q1 is the output terminal of the first transistor unit 31. The emitter of the first transistor Q1 is connected to the power input terminal S1, the base of the first transistor Q1 is connected to the drain of the first NMOS transistor Q3, the source of the first NMOS transistor Q3 is the control terminal of the first transistor unit 31, and the source of the first NMOS transistor Q3 is connected to the output terminal of the current control unit 33 and the control signal of the main control unit 34, respectively. The output pins are connected as follows: the gate of the first NMOS transistor Q3 is connected to the power input terminal S1; the second transistor unit 32 includes a second transistor Q2 and a second NMOS transistor Q4. The emitter of the second transistor Q2 is the input terminal of the second transistor unit 32, and the collector of the second transistor Q2 is the output terminal of the second transistor unit 32. The emitter of the second transistor Q2 is connected to the power input terminal S1, the base of the second transistor Q2 is connected to the drain of the second NMOS transistor Q4, the source of the second NMOS transistor Q4 is the control terminal of the second transistor unit 32, and the source of the second NMOS transistor Q4 is connected to the output terminal of the current control unit 33 and the control signal output pin of the main control unit 34, respectively. The gate of the second NMOS transistor Q4 is connected to the power input terminal S1. In this embodiment, both the first transistor Q1 and the second transistor Q2 are PNP type transistors.

[0039] In one embodiment of this application, the charging circuit further includes a first resistor R1 and a second resistor R2; the first end of the first resistor R1 is connected to the power input terminal S1, and the second end of the first resistor R1 is connected to the emitter of the first transistor Q1; the first end of the second resistor R2 is connected to the power input terminal S1, and the second end of the second resistor R2 is connected to the emitter of the second transistor Q2; the current control unit 33 includes a first operational amplifier A1, a second operational amplifier A2, and a third operational amplifier A3; the non-inverting input terminal of the first operational amplifier A1 is connected to the first end of the first resistor R1, the inverting input terminal of the first operational amplifier A1 is connected to the second end of the first resistor R1, and the output terminal of the first operational amplifier A1 is connected to the inverting input terminal of the third operational amplifier A3; the non-inverting input terminal of the second operational amplifier A2 is connected to the first end of the second resistor R2, the inverting input terminal of the second operational amplifier A2 is connected to the second end of the second resistor R2, and the output terminal of the second operational amplifier A2 is connected to the non-inverting input terminal of the third operational amplifier A3; the output terminal of the third operational amplifier A3 is connected to the control terminal of the first transistor unit 31 and the control terminal of the second transistor unit 32, respectively.

[0040] In one embodiment, the charging circuit further includes a first diode D1, a fourth resistor R4, and a fifth resistor R5. The output terminal of the third operational amplifier A3 is connected to the anode of the first diode D1. The cathode of the first diode D1 is connected to the first terminals of both the fourth and fifth resistors R4 and R5. The second terminal of the fourth resistor R4 is connected to the source of the second NMOS transistor Q4, and the second terminal of the fifth resistor R5 is connected to the source of the first NMOS transistor Q3. The fourth resistor R4 and the fifth resistor R5 are used to adjust the current dynamics between the first transistor unit 31 and the second transistor unit 32 to be equal. The first diode D1 is used to isolate the output of the current control unit 33 and the control voltage signal V_drive output by the main control unit 34 to prevent mutual interference.

[0041] In one scenario, during the charging process, when a difference arises between the first charging current I1 of the first transistor unit 31 and the second charging current I2 of the second transistor unit 32, the gate-source voltage V of the first NMOS transistor Q3 and the second NMOS transistor Q4... GS The situation will be different. In order to keep the first charging current I1 and the second charging current I2 the same, the circuit will automatically adjust the voltage V between the drain and source of the two NMOS transistors through the fifth resistor R5 and the fourth resistor R4. GS This makes the base Ib current of the first NMOS transistor Q3 and the second NMOS transistor Q4 the same, and ultimately keeps the first charging current I1 and the second charging current I2 the same and maintains a dynamic balance.

[0042] Furthermore, the current control unit 33 is used to regulate and manage the charging current balance between the first transistor unit 31 and the second transistor unit 32, and can keep the charging current of the two transistor units basically consistent within a very short response time. Without the current control unit 33, the voltage drop would be different due to the inconsistent impedance of each charging branch during the charging process, which would eventually lead to reverse current flow between the transistor units and affect operation.

[0043] The first charging current I1 flows through the first resistor R1, and the voltage drop across the first resistor R1 is V. R1 The non-inverting and inverting input terminals of the first operational amplifier A1 are connected to the two ends of the first resistor R1, and the voltage drop V across the first resistor R1 is... R1 By reducing the voltage V R1 After amplification, the output value of the first operational amplifier A1 is input to the inverting input of the third operational amplifier A3. Similarly, the charging current I2 flows through the second resistor R2, and the voltage drop across the second resistor R2 is V. R2The non-inverting and inverting input terminals of the second operational amplifier A2 are connected across the second resistor R2, and the voltage drop across the second resistor R2 is V. R2 By reducing the voltage V R2 After amplification, the output value of the second operational amplifier A2 is input to the non-inverting input terminal of the third operational amplifier A3. The third operational amplifier A3 adjusts the magnitudes of the first charging current I1 and the second charging current I2 through negative feedback by comparing the voltage values ​​across the amplified first resistor R1 and the second resistor R2, ultimately achieving a dynamic balance between the current values ​​of the first charging current I1 and the second charging current I2.

[0044] For transistors, the formula for the current flowing through each of the first transistor Q1 and the second transistor Q2 is: I EC =β×Ib formula (1) Where β is the amplification factor of each transistor. In this embodiment, the amplification factors of the first transistor Q1 and the second transistor Q2 are the same. Ib is the current flowing through the first NMOS transistor Q3 and the second NMOS transistor Q4. Ib controls the current I flowing through the first transistor Q1 and the second transistor Q2. EC The magnitude of the current, Ib, depends on the conduction level of the first NMOS transistor Q3 and the second NMOS transistor Q4 in this embodiment.

[0045] In one embodiment of this application, please continue to refer to Figure 4 As shown, the constant current charging unit 36 ​​includes a first reference voltage generation chip U2, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a fourth operational amplifier A4, and a third NMOS transistor Q5. The enable terminal of the first reference voltage generation chip U2 is connected to the first enable pin on the main control unit 34. The voltage output pin of the first reference voltage generation chip U2 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is connected to the non-inverting input terminal of the fourth operational amplifier A4 and the first end of the seventh resistor R7, respectively. The second end of the seventh resistor R7 is grounded. The fourth operational amplifier A4... The output terminal is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected to the gate of the third NMOS transistor Q5, the drain of the third NMOS transistor Q5 is connected to the charging output terminal S2, the source of the third NMOS transistor Q5 is connected to the first end of the eighth resistor R8 and the first end of the tenth resistor R10 respectively, the second end of the eighth resistor R8 is connected to the inverting input terminal of the fourth operational amplifier A4, and the second end of the tenth resistor R10 is grounded; the first reference voltage generation chip U2 is used to receive the first enable signal GPIO1 output by the main control unit 34, and output the first reference voltage signal under the trigger of the first enable signal GPIO1.

[0046] In one embodiment, when the first enable signal GPIO1 output by the main control unit 34 is high, the first reference voltage generation chip U2 is turned on and operates. The first reference voltage signal output by the first reference voltage generation chip U2 is VREF_OUT. VREF_OUT is divided by the series-connected sixth resistor R6 and seventh resistor R7, and the voltage after voltage division is used as the input voltage V at the non-inverting input terminal of the fourth operational amplifier A4. a4 In this embodiment, VREF_OUT is set to 2.5V. The input voltage V is obtained after voltage division by the sixth resistor R6 and the seventh resistor R7. a4 The voltage is 1V. At this time, if the voltage V at the positive input terminal of the fourth operational amplifier A4 is... a4 Greater than the negative input voltage V b4 Then the output of the fourth operational amplifier A4 continuously increases, the conduction level of the third NMOS transistor Q5 continuously increases, and the current I... SINK The increase causes the voltage drop V across the tenth resistor R10 to increase. R10 Increase, voltage drop V R10 The voltage is input to the inverting input of the fourth operational amplifier A4 through the eighth resistor R8 until the voltage at the negative input terminal V... b4 and the positive input voltage V a4 If the currents are the same, the circuit remains balanced. At this time, the current I... SINK The value is I SINK = 1V / R10.

[0047] In one embodiment of this application, the voltage regulation control unit 35 includes a second reference voltage generation chip U3, a fifth operational amplifier A5, a thirteenth resistor R13, a fourteenth resistor R14, and a third PMOS transistor Q6. The enable terminal of the second reference voltage generation chip U3 is connected to the second enable pin on the main control unit 34, the voltage output pin of the second reference voltage generation chip U3 is connected to the non-inverting input terminal of the fifth operational amplifier A5, the output terminal of the fifth operational amplifier A5 is connected to the first terminal of the thirteenth resistor R13, the second terminal of the thirteenth resistor R13 is connected to the drain of the third PMOS transistor Q6, the source of the third PMOS transistor is connected to the power supply pin on the first charging interface 37 and the first terminal of the fourteenth resistor R14, and the second terminal of the fourteenth resistor R14 is connected to the inverting input terminal of the fifth operational amplifier A5. The main control unit 37 is also used to output a second enable signal GPIO2 to the second reference voltage generation chip U3 when an external power supply is detected to be connected to the power input terminal S1. The second reference voltage generation chip U3 is used to output a second reference voltage signal under the trigger of the second enable signal GPIO2.

[0048] Specifically, when the second enable signal GPIO2 output by the main control unit 37 is high, the second reference voltage generation chip U3 outputs a stable second reference voltage signal VREF_OUT_4V. The voltage value of VREF_OUT_4V is 4V, and it serves as the non-inverting input voltage of the fifth operational amplifier A5. The conduction level of the third PMOS transistor Q6 is adjusted and controlled through the operational amplifier's negative feedback to obtain a stable charging voltage VBAT_Charge, for example, VBAT_Charge = 4V. This charging voltage VBAT_Charge is connected to the positive terminal of the battery via a USB cable to charge the battery.

[0049] In this embodiment, the battery voltage range can be 2.5V-4.4V. The charging current IBAT_Charge is ultimately poured into the battery and supplies power to the entire system through the battery.

[0050] In one embodiment, when the charging adapter is connected to 220V AC mains, the 5V voltage output by the AC-DC conversion module is connected to the power input port. The charging detection pin Power-EINT of the main control unit 34 is 5V (this Power-EINT signal is the system's charging detection interrupt signal, used to determine whether the charger is connected to AC mains; if the charger is connected to AC mains, Power-EINT is 5V, and the system displays a charging icon; if the charger is not connected to AC mains, Power-EINT is 0V, and the system does not display a charging icon). After the system detects a valid interrupt, it starts charging. The charging drive pin of the main control unit 34 outputs a control voltage signal V_drive, which turns on the first NMOS transistor Q3 and the second NMOS transistor Q4 simultaneously, making them operate in the variable resistance region of the NMOS transistors. The first transistor Q1 and the second transistor Q2 operate in the linear amplification region according to the voltage state. The emitter currents flowing through the first transistor Q1 and the second transistor Q2 are the first charging current I1 and the second charging current I2, respectively. According to the above formula (1), the functions of the first NMOS transistor Q3 and the second NMOS transistor Q4 are to adjust the emitter currents through the first transistor Q1 and the second transistor Q2 respectively, and ultimately control the actual charging current I. SUM size.

[0051] In this embodiment, the current relationship is I SUM =I1+I2; Additionally, I SUM = I SINK +I BAT_ Charge ; where I SUM It is the sum of the currents output by the first transistor unit 31 and the second transistor unit 32, I SINK I is the current flowing into the constant current charging unit 36 ​​when the constant current charging unit 36 ​​is turned on. BAT_ ChargeIt is the net current flowing into the battery, which is the actual charging current value.

[0052] After the system detects that the Power-EINT interrupt signal is valid, synchronously... Figure 2 The power management chip (PMIC) in the system detects the battery voltage. If the battery voltage is between 2.2V and 3.2V, the system initiates a pre-charging process. At this time, the PMIC transmits a command to the main control unit 34 through the I2C interface signals SDA and SCL. This command sets the first enable signal GPIO1 to a high level. When the first enable signal GPIO1 controlled by the main control unit 34 is high, the first reference voltage generation chip U2 is turned on and starts working. The first reference voltage signal output by the first reference voltage generation chip U2 is VREF_OUT. The first reference voltage signal VREF_OUT is divided by the sixth resistor R6 and the seventh resistor R7 connected in series. The voltage after voltage division is used as the input voltage V of the non-inverting input terminal of the fourth operational amplifier A4. a4 In this embodiment, the first reference voltage signal VREF_OUT is set to 2.5V. After being divided by the sixth resistor R6 and the seventh resistor R7, the input voltage V... a4 It is 1V.

[0053] At this time, if the voltage V at the non-inverting input terminal of the fourth operational amplifier A4 a4 Greater than the negative input voltage V b4 As the output of the fourth operational amplifier A4 increases, the conduction level of the third NMOS transistor Q5 also increases, resulting in a current I... SINK The increase causes the voltage drop V across the tenth resistor R10 to increase. R10 Get bigger, V R10 The voltage is input to the inverting input of the fourth operational amplifier A4 through the eighth resistor R8 until the voltage at the negative input terminal V... b4 and the positive input voltage V a4 If the currents are the same, the circuit remains balanced. At this time, the current I... SINK The value is I SINK = 1V / R10. In this embodiment, the current is I. SINK The pre-charge current value can be obtained by setting different values ​​for the tenth resistor R10, thus obtaining different I values. SINK The current value is used to obtain different pre-charge current values.

[0054] like Figure 2 The power management chip PMIC detects that the battery voltage is greater than 3.2V and feeds this information back to the main control unit 34. The main control unit 34 then sets the first enable signal GPIO1 to a low level to control the first reference voltage generation chip U2 to turn off, and the system directly enters the constant current charging stage.

[0055] In one scenario, after the main control unit 34 detects that the interrupt signal Power-EINT is valid, it synchronously sets the output second enable signal GPIO2 to a high level, and the second reference voltage generation chip U3 outputs a stable voltage V. REF_OUT_4V V REF_OUT_4V The voltage is 4V, which serves as the non-inverting input voltage of the fourth operational amplifier A4. Through negative feedback adjustment by the voltage regulation control unit 35, the conduction level of the third PMOS transistor Q6 is controlled to obtain a stable VBAT_Charge voltage value of 4V. This voltage VBAT_Charge is connected to the positive terminal of the battery via a USB cable to charge the battery.

[0056] If the software's preset charging current value is I SW_SET During actual charging, fluctuations in the output power of the charging adapter due to surges or other reasons, or sudden changes in the charging path impedance due to temperature variations, can affect the actual charging current I. BAT_ Charge When fluctuations occur, the ADC module of the power management chip (PMIC) samples a change in the battery voltage at the battery terminal. It then sends this change in battery voltage to the main control unit 34 via a communication signal line. The main control unit 34 adjusts the control voltage signal V_drive output from the signal pin through internal negative feedback, thereby dynamically adjusting the actual charging current I. SUM Based on the above, we can further divide the situation into the following two categories: Scenario 1: If the actual charging current value I BAT_ Charge The charging current value I is greater than the software preset value. SW_SET Then, through negative feedback, the system will increase the voltage value of the control voltage signal V_drive. At this time, the gate-source voltage difference Vgs = Vg - Vs of the first NMOS transistor Q3 and the second NMOS transistor Q4 will decrease. Since the gate-source voltage difference Vgs decreases, the conduction degree of the first NMOS transistor Q3 and the second NMOS transistor Q4 will decrease, and the corresponding on-resistance Rds will increase, thereby reducing the base current Ib. According to formula (1), the current I between the emitter and collector of the first transistor Q1 and the second transistor Q2 will decrease. EC It will decrease. Ultimately, the actual charging current of the circuit in this embodiment will decrease and eventually adjust to I. BAT_ Charge =I SW_SET Until then, the control voltage signal V_drive voltage value no longer changes and reaches dynamic equilibrium.

[0057] Scenario 2: If the actual charging current value I BAT_ Charge Less than the software-preset charging current value I SW_SETThen, through negative feedback, the system will lower the voltage value of the control voltage signal V_drive. At this time, the gate-source voltage difference Vgs = Vg - Vs of the first NMOS transistor Q3 and the second NMOS transistor Q4 will increase. Since the gate-source voltage difference Vgs increases, the conduction degree of the first NMOS transistor Q3 and the second NMOS transistor Q4 will be enhanced, and the corresponding on-resistance Rds will decrease, thereby increasing the base current Ib. According to formula (1), the current I between the emitter and collector of the first transistor Q1 and the second transistor Q2 will increase. EC It will increase; ultimately, the actual charging current of the circuit in this embodiment will increase, and will eventually adjust to I. BAT_ Charge =I SW_SET The control voltage signal V_drive voltage value no longer changes and reaches dynamic equilibrium.

[0058] In one scenario, during the charging process, when a difference arises between the first charging current I1 of the first transistor unit 31 and the second charging current I2 of the second transistor unit 32, the gate-source voltage VGS of the first NMOS transistor Q3 and the second NMOS transistor Q4 will be different. In order to keep the first charging current I1 and the second charging current I2 the same, the circuit will automatically adjust the gate-source voltage difference Vgs of the first NMOS transistor Q3 and the second NMOS transistor Q4 through the fifth resistor R5 and the fourth resistor R4, so that the base current Ib of the first NMOS transistor Q3 and the second NMOS transistor Q4 are the same, and finally keep the first charging current I1 and the second charging current I2 the same and maintain a dynamic balance state.

[0059] Furthermore, the first charging current I1 flows through the first resistor R1, and the voltage drop across the first resistor R1 is V. R1 The non-inverting and inverting input terminals of the first operational amplifier A1 are connected across the first resistor R1 to sample the voltage drop V across the first resistor R1. R1 By reducing the voltage V R1 After amplification, the output value of the first operational amplifier A1 is input to the inverting input of the third operational amplifier A3. Similarly, the second charging current I2 flows through the second resistor R2, and the voltage drop across the second resistor R2 is V. R2 The non-inverting and inverting input terminals of the second operational amplifier A2 are connected across the second resistor R2 to sample the voltage drop V across the second resistor R2. R2 By reducing the voltage V R2 After amplification, the output value of the second operational amplifier A2 is input to the non-inverting input terminal of the third operational amplifier A3. The third operational amplifier A3 adjusts the currents of the first charging current I1 and the second charging current I2 through negative feedback by comparing the voltage values ​​across the amplified first resistor R1 and the second resistor R2, and finally makes the current values ​​of the first charging current I1 and the second charging current I2 dynamically balanced.

[0060] This application provides a power adapter, which includes a charging circuit as provided in any of the above embodiments; thus, the power adapter provided in this embodiment is as follows: Figure 2 As shown, the power adapter provided in this embodiment can provide a stable and balanced charging current for electronic devices, while reducing the heat generated by the device during charging, improving user experience, and extending the service life of electronic devices.

[0061] It should be noted that the charging circuit provided in this application can be applied to electronic devices to provide a stable and balanced charging current for the battery, and the dual-output can increase the charging current value to improve the charging speed; at the same time, the charging circuit provided in this embodiment can also be applied to power adapters, so that the power adapter can provide a stable and balanced charging current for electronic devices, while reducing the heat generated by the device during charging.

[0062] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A charging circuit, characterized by, The charging circuit comprises a first transistor unit, a second transistor unit, a current control unit, a voltage stabilization control unit and a master control unit; The input end of the first transistor unit and the input end of the second transistor unit are both used for receiving an input voltage, the output end of the first transistor unit and the output end of the second transistor unit are both connected with a charging output end, and the charging output end is used for connecting a load or a first charging interface to output a charging current to the load or the first charging interface; The master control unit is used for receiving a current feedback adjustment signal and outputting a corresponding control voltage signal according to the current feedback adjustment signal, and the control voltage signal is used for controlling the first transistor unit and the second transistor unit to output a corresponding charging current; The current control unit is used for sampling an input current on each transistor unit input end and outputting a corresponding current balance control signal to control the charging currents output by the first transistor unit and the second transistor unit to reach balance; The voltage stabilization control unit is used for sampling a battery voltage value output on the charging output end and outputting a corresponding voltage stabilization control signal according to the size relationship between the battery voltage value and a preset reference voltage value to control the output charging voltage to stabilize at the reference voltage value.

2. The charging circuit of claim 1, wherein, The charging circuit further comprises a constant current charging unit connected with the charging output end; The master control unit is further used for receiving a pre-charging trigger signal fed back by a load end and outputting a first enable signal to the constant current charging unit according to the pre-charging trigger signal, and the constant current charging unit outputs a pre-charging current value to pre-charge the load under the triggering of the first enable signal.

3. The charging circuit of claim 2, wherein, The control signal output pin of the master control unit is connected with the control end of the first transistor unit and the control end of the second transistor unit respectively to output the control voltage signal to the first transistor unit and the second transistor unit respectively; The input end of the current control unit is connected with the input end of the first transistor unit and the input end of the second transistor unit respectively, and the output end of the current control unit is connected with the control end of the first transistor unit and the control end of the second transistor unit respectively to output the current balance control signal to the first transistor unit and the second transistor unit respectively.

4. The charging circuit of claim 3, wherein, The master control unit comprises a charging detection pin connected with a power input end to detect whether an external power source is connected to the power input end and output a corresponding indication signal according to the detection result, and when the indication signal represents that the external power source is connected, the first transistor unit, the second transistor unit and the voltage stabilization control unit are controlled to start working; The input end of the first transistor unit and the input end of the second transistor unit are both connected with the power input end, and the power input end is used for receiving an input current input by an external power source.

5. The charging circuit of claim 4, wherein, The charging circuit further comprises a first charging interface used for connecting a load. The charging output is connected with the power supply pin on the first charging interface; the clock signal pin and the data communication pin of the master control unit are respectively connected with the corresponding clock signal pin and data communication pin on the first charging interface.

6. The charging circuit of claim 4, wherein, The first transistor unit comprises a first triode and a first NMOS tube, the emitter of the first triode is the input end of the first transistor unit, and the collector of the first triode is the output end of the first transistor unit; the emitter of the first triode is connected with the power input end, the base of the first triode is connected with the drain of the first NMOS tube, the source of the first NMOS tube is the control end of the first transistor unit, and the source of the first NMOS tube is respectively connected with the output end of the current control unit and the control signal output pin of the master control unit, and the gate of the first NMOS tube is connected with the power input end; The second transistor unit comprises a second triode and a second NMOS tube, the emitter of the second triode is the input end of the second transistor unit, and the collector of the second triode is the output end of the second transistor unit; the emitter of the second triode is connected with the power input end, the base of the second triode is connected with the drain of the second NMOS tube, the source of the second NMOS tube is the control end of the second transistor unit, and the source of the second NMOS tube is respectively connected with the output end of the current control unit and the control signal output pin of the master control unit, and the gate of the second NMOS tube is connected with the power input end.

7. The charging circuit of claim 4, wherein, The charging circuit further comprises a first resistor and a second resistor; the first end of the first resistor is connected with the power input end, and the second end of the first resistor is connected with the emitter of the first triode; the first end of the second resistor is connected with the power input end, and the second end of the second resistor is connected with the emitter of the second triode; The current control unit comprises a first operational amplifier, a second operational amplifier and a third operational amplifier; the same direction input end of the first operational amplifier is connected with the first end of the first resistor, the opposite direction input end of the first operational amplifier is connected with the second end of the first resistor, and the output end of the first operational amplifier is connected with the opposite direction input end of the third operational amplifier; The same direction input end of the second operational amplifier is connected with the first end of the second resistor, the opposite direction input end of the second operational amplifier is connected with the second end of the second resistor, and the output end of the second operational amplifier is connected with the same direction input end of the third operational amplifier; The output end of the third operational amplifier is respectively connected with the control end of the first transistor unit and the control end of the second transistor unit.

8. The charging circuit of claim 7, wherein, The constant current charging unit comprises a first reference voltage generation chip, a sixth resistor, a seventh resistor, an eighth resistor, a ninth resistor, a tenth resistor, a fourth operational amplifier and a third NMOS tube; The enable end of the first reference voltage generation chip is connected with a first enable pin on the master control unit, the voltage output pin of the first reference voltage generation chip is connected with a first end of the sixth resistor, the second end of the sixth resistor is connected with a same direction input end of the fourth operational amplifier and a first end of the seventh resistor respectively, the second end of the seventh resistor is grounded, the output end of the fourth operational amplifier is connected with a first end of the ninth resistor, the second end of the ninth resistor is connected with a gate of the third NMOS tube, the drain of the third NMOS tube is connected with the charging output end, the source of the third NMOS tube is connected with a first end of the eighth resistor and a first end of the tenth resistor respectively, the second end of the eighth resistor is connected with a reverse input end of the fourth operational amplifier, and the second end of the tenth resistor is grounded. The first reference voltage generation chip is configured to receive a first enable signal output by the master control unit and output a first reference voltage signal under triggering of the first enable signal.

9. The charging circuit of claim 8, wherein, The voltage stabilizing control unit comprises a second reference voltage generation chip, a fifth operational amplifier, a thirteenth resistor, a fourteenth resistor and a third PMOS tube. The enable end of the second reference voltage generation chip is connected with a second enable pin on the master control unit, the voltage output pin of the second reference voltage generation chip is connected with a same direction input end of the fifth operational amplifier, the output end of the fifth operational amplifier is connected with a first end of the thirteenth resistor, the second end of the thirteenth resistor is connected with a drain of the third PMOS tube, the source of the third PMOS tube is connected with a power supply pin on the first charging interface and a first end of the fourteenth resistor respectively, and the second end of the fourteenth resistor is connected with a reverse input end of the fifth operational amplifier. The master control unit is further configured to output a second enable signal to the second reference voltage generation chip when detecting that an external power supply is connected to the power supply input end, and the second reference voltage generation chip is configured to output a second reference voltage signal under triggering of the second enable signal.

10. A power adapter, characterized by The power adapter comprises the charging circuit according to any one of claims 1-9.

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