Low noise amplifier

Abstract

The application relates to the field of wireless communication technology and provides a low-noise amplifier, which comprises an input matching circuit, a main amplification circuit, an output matching circuit, a gain adjusting circuit, an attenuation circuit and a bias control circuit; the output end of the main amplification circuit is connected with the input end of the output matching circuit; the input end of the gain adjusting circuit is used for connecting a power supply; the output end of the gain adjusting circuit is connected with the output end of the main amplification circuit; the output end of the output matching circuit is connected with the input end of the attenuation circuit; the output end of the attenuation circuit is used for connecting a signal output port; the bias control circuit is used for controlling the opening and closing of the main amplification circuit; the output matching circuit is used for output impedance matching and signal attenuation output through the attenuation circuit; and the gain adjusting circuit is used for switching the gain position of the main amplification circuit. The low-noise amplifier can flexibly realize the switching of different gain positions, optimize the linearity and reduce the area and chip cost.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more particularly to a low-noise amplifier. Background Technology

[0002] Low-noise amplifiers (LNAs) are a crucial component of wireless communication systems, primarily used in the radio frequency (RF) front-end of wireless receivers. As the first active device in the receiver's RF front-end, the LNA plays a vital role in the system's performance. To ensure receiver sensitivity, the LNA typically needs a certain gain to amplify the weak signal received by the antenna, while effectively suppressing noise from subsequent modules, and the LNA itself also needs to have very low noise. When the system receives high-power signals from the antenna, to prevent distortion and damage to subsequent active components, the LNA must have variable gain and an extended dynamic range. Therefore, in addition to meeting system requirements for gain and noise, high linearity is also essential for low-noise amplifiers.

[0003] In existing technologies, such as Figure 1 As shown, the low-noise amplifier mainly consists of an input matching circuit, a common-source-common-gate main amplification branch, an output matching circuit, a bias branch, and an output attenuation network. The radio frequency signal is input from the signal input terminal RFIN, connected to the first terminal of the matching inductor Lg, and then output from the second terminal of the matching inductor Lg, connected to the first terminal of the input DC blocking capacitor Cin. The signal is then output from the second terminal of the input DC blocking capacitor Cin and connected to the gate of the CS transistors (NM1-NM3). After amplification by the common-source-common-gate main amplification branch, the signal reaches the first terminal of the output DC blocking capacitor Cout, and then output from the second terminal of the output DC blocking capacitor Cout, connected to the input terminal of the output attenuation network (ATT). Finally, the signal is output through the output attenuation network and fed to the subsequent circuit modules.

[0004] The diode-connected transistor NM4 in the bias branch acts as a mirror transistor to provide bias current to the CS transistor. The first terminal of the gate bias resistor RB1 is connected to the gate of NM4, and the second terminal is connected to the gate of the CS transistor. This is used to isolate the RF and analog circuit modules; its value should be appropriate to avoid introducing excessive noise. VCG, after low-pass filtering by a filter circuit composed of resistor R1 and capacitor C1, provides bias voltage to the gate terminal of the common-gate transistor NM0. Inductors Ls1~Ls3 and inductor Ld serve as source degradation inductors and load inductors, respectively, to provide input and output matching. The resistor Rbank, connected in parallel with inductor Ld, allows for gain adjustment at different levels. The output attenuation network ATT, connected in series with the second terminal of the output DC blocking capacitor Cout, is mainly used for gain reduction under large signals.

[0005] Therefore, traditional linearity optimization schemes for low-noise amplifiers mainly involve dividing the CS transistor into three different branches (H, M, and L). The sources of these three CS transistor branches are shorted together and connected to three inductors Ls below, controlled by switches (SW-1, SW-2, and SW-3). By rationally selecting the branches where the CS transistors and inductors Ls are turned on, different gain levels and linearity optimization can be achieved. However, this scheme has a drawback: to achieve switching between different CS transistor branches and inductor Ls branches, each CS transistor branch and inductor Ls branch typically requires a separate switch. To reduce the large insertion loss and noise figure (NF) introduced by the switching branches, the switches used for switching are usually relatively large, especially at high gain levels. This leads to an increase in chip area, which is detrimental to reducing chip cost.

[0006] In summary, traditional low-noise amplifiers primarily utilize output attenuation and switching between the CS transistor and the source degraded inductor to achieve different gain levels and optimize linearity. However, this method has certain disadvantages in terms of circuit structure. To achieve gain switching while minimizing the insertion loss of the switching switch itself, especially in high-gain mode, the size of the switch used to switch the CS transistor and Ls transistor cannot be too small. Sometimes, to obtain a lower noise figure, a larger switching switch may be required, which undoubtedly leads to a waste of more chip area. Summary of the Invention

[0007] To address the shortcomings of the existing technologies, this invention proposes a low-noise amplifier to solve the problems of poor gain and linearity optimization and large overall area of ​​existing low-noise amplifiers.

[0008] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0009] This invention provides a low-noise amplifier, which includes: an input matching circuit, a main amplification circuit, an output matching circuit, a gain adjustment circuit, an attenuation circuit, and a bias control circuit.

[0010] The input terminal of the input matching circuit is connected to the signal input port. The output terminal of the input matching circuit is connected to the input terminal of the main amplifier circuit. The output terminal of the main amplifier circuit is connected to the input terminal of the output matching circuit. The input terminal of the gain adjustment circuit is connected to the power supply. The output terminal of the gain adjustment circuit is connected to the output terminal of the main amplifier circuit. The output terminal of the output matching circuit is connected to the input terminal of the attenuation circuit. The output terminal of the attenuation circuit is connected to the signal output port. The bias control circuit is used to control the on and off of the main amplifier circuit. The input matching circuit is used to achieve input impedance matching for the RF signal input to the main amplifier circuit. The main amplifier circuit amplifies the RF signal. The output matching circuit is used to achieve output impedance matching for the RF signal output by the main amplifier circuit and attenuates the signal output through the attenuation circuit. The gain adjustment circuit is used to switch the gain level of the main amplifier circuit.

[0011] The main amplifier circuit includes a first MOSFET, a second MOSFET, and a third MOSFET. The gate of the first MOSFET is connected to the gate of the second MOSFET and together serve as the input terminal of the main amplifier circuit. The source of the first MOSFET is grounded, and the source of the second MOSFET is grounded. The drain of the first MOSFET is connected to the drain of the second MOSFET and the source of the third MOSFET. The gate of the third MOSFET is used to connect to an external logic control circuit, and the drain of the third MOSFET serves as the output terminal of the main amplifier circuit.

[0012] The bias control circuit includes a current source, a fourth MOSFET, a first resistor, a first switch, and a second switch. The input terminal of the current source is connected to a power supply, and the output terminal of the current source is connected to the drain and gate of the fourth MOSFET. The source of the fourth MOSFET is connected to the control terminal of the first switch, and the output terminal of the first switch is grounded. The gate of the fourth MOSFET is also connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the control terminal of the second switch, the first output terminal of the second switch is connected to the gate of the first MOSFET, and the second output terminal of the second switch is connected to the gate of the second MOSFET. The current source provides bias current to the fourth MOSFET, and the bias current controls the switching on and off of the first and second MOSFETs via the second switch.

[0013] Preferably, the input matching circuit includes a first inductor, with a first end of the first inductor serving as the input terminal of the input matching circuit and a second end of the first inductor serving as the output terminal of the input matching circuit.

[0014] Preferably, the low-noise amplifier further includes a second inductor and a third inductor. The first end of the second inductor is connected to the source of the first MOSFET, and the second end of the second inductor is grounded. The second inductor is used to provide input impedance matching for the first MOSFET. The first end of the third inductor is connected to the source of the second MOSFET, and the second end of the third inductor is grounded. The third inductor is used to provide input impedance matching for the second MOSFET.

[0015] Preferably, the low-noise amplifier further includes a substrate, on which a ground terminal, a first pin, and a second pin are provided. The second inductor and the third inductor are respectively integrated on the substrate. The first end of the second inductor is connected to the first pin, and the second end of the second inductor is connected to the ground terminal. The first end of the third inductor is connected to the second pin, and the second end of the third inductor is connected to the ground terminal. The first pin is connected to the source of the first MOSFET, and the second pin is connected to the source of the second MOSFET.

[0016] Preferably, the low-noise amplifier further includes a first capacitor and a second capacitor; the first terminal of the first capacitor is connected to the first terminal of the second capacitor and is jointly connected to the output terminal of the input matching circuit; the second terminal of the first capacitor is connected to the gate of the first MOSFET; the first capacitor is used to block the DC signal output by the input matching circuit and then output it to the gate of the first MOSFET; the second terminal of the second capacitor is connected to the gate of the second MOSFET; the second capacitor is used to block the DC signal output by the input matching circuit and then output it to the gate of the second MOSFET.

[0017] Preferably, the output matching circuit includes a third capacitor, the first end of which serves as the input terminal of the output matching circuit, and the second end of which serves as the output terminal of the output matching circuit.

[0018] Preferably, the gain adjustment circuit includes an adjustable resistor and a fourth inductor. The first end of the adjustable resistor and the first end of the fourth inductor are connected together to the power supply, and the second end of the adjustable resistor is connected to the second end of the fourth inductor. The adjustable resistor is used to achieve different gain levels.

[0019] Preferably, the low-noise amplifier further includes a filter circuit, the input terminal of which is connected to the external logic control circuit, and the output terminal of which is connected to the gate of the third MOS transistor. The filter circuit is used to provide a bias voltage to the gate of the third MOS transistor after low-pass filtering.

[0020] Preferably, the filter circuit includes a fourth capacitor and a second resistor; the first end of the second resistor serves as the input terminal of the filter circuit, the second end of the second resistor is connected to the first end of the fourth capacitor and serves as the output terminal of the filter circuit, and the second end of the fourth capacitor is grounded.

[0021] Preferably, the attenuation circuit is an ATT attenuator.

[0022] Compared with related technologies, in the embodiments of the present invention, the input terminal of the input matching circuit is used to connect to the signal input port, the output terminal of the input matching circuit is connected to the input terminal of the main amplifier circuit, the output terminal of the main amplifier circuit is connected to the input terminal of the output matching circuit, the input terminal of the gain adjustment circuit is used to connect to the power supply, the output terminal of the gain adjustment circuit is connected to the output terminal of the main amplifier circuit, the output terminal of the output matching circuit is connected to the input terminal of the attenuation circuit, the output terminal of the attenuation circuit is used to connect to the signal output port, and the bias control circuit is used to control the on and off of the main amplifier circuit; the input matching circuit is used to achieve impedance matching for the radio frequency signal, the main amplifier circuit amplifies the radio frequency signal, and the output matching circuit is used to achieve output impedance matching for the radio frequency signal output by the main amplifier circuit, and the attenuation circuit attenuates the signal. The output gain adjustment circuit is used to switch the gain level of the main amplifier circuit; the gate of the fourth MOSFET in the bias control circuit is connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the control terminal of the second switch, the first output terminal of the second switch is connected to the gate of the first MOSFET, and the second output terminal of the second switch is connected to the gate of the second MOSFET; the current source is used to provide bias current for the fourth MOSFET, and the bias current controls the turn-on and turn-off of the first and second MOSFETs via the second switch; by simplifying the existing CS transistor amplification branch, eliminating the large switching transistor used to switch the CS transistor and the source inductor Ls branch, and transferring this switching control to a smaller bias control switch, not only can gain and linearity be optimized, but the RF section area can also be effectively reduced, thus lowering chip cost. Attached Figure Description

[0023] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0024] Figure 1 Circuit diagram of a low-noise amplifier provided for the prior art;

[0025] Figure 2 The circuit diagram of the low-noise amplifier provided in Embodiment 1 of the present invention;

[0026] Figure 3 The circuit diagram of the low-noise amplifier provided in Embodiment 2 of the present invention;

[0027] Figure 4 This is a schematic diagram of the substrate of the low-noise amplifier provided in Embodiment 2 of the present invention.

[0028] Among them, 100 is the low-noise amplifier of Example 1, 1 is the input matching circuit, 2 is the main amplification circuit, 3 is the output matching circuit, 4 is the gain adjustment circuit, 5 is the attenuation circuit, 6 is the bias control circuit, 61 is the first switch, 62 is the second switch, and 7 is the filter circuit.

[0029] 200. Low-noise amplifier of embodiment 2; 201. Substrate; 202. First pin; 203. Second pin. Detailed Implementation

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0031] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0032] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0033] Example 1

[0034] Please see Figure 2 As shown, this embodiment of the invention provides a low-noise amplifier 100, which includes: an input matching circuit 1, a main amplification circuit 2, an output matching circuit 3, a gain adjustment circuit 4, an attenuation circuit 5, and a bias control circuit 6.

[0035] The input terminal of the input matching circuit 1 is connected to the signal input port RFIN. The output terminal of the input matching circuit 1 is connected to the input terminal of the main amplifier circuit 2. The output terminal of the main amplifier circuit 2 is connected to the input terminal of the output matching circuit 3. The input terminal of the gain adjustment circuit 4 is connected to the power supply VDD. The output terminal of the gain adjustment circuit 4 is connected to the output terminal of the main amplifier circuit 2. The output terminal of the output matching circuit 3 is connected to the input terminal of the attenuation circuit 5. The output terminal of the attenuation circuit 5 is connected to the signal output port RFOUT. The bias control circuit 6 is used to control the on and off of the main amplifier circuit 2. The input matching circuit 1 is used to achieve impedance matching for the RF signal input to the main amplifier circuit 2. The main amplifier circuit 2 amplifies the RF signal. The output matching circuit 3 is used to achieve output impedance matching for the RF signal output by the main amplifier circuit 2 and attenuates the signal output through the attenuation circuit 5. The gain adjustment circuit 4 is used to switch the gain level of the main amplifier circuit 2.

[0036] The main amplifier circuit 2 includes a first MOSFET M1, a second MOSFET M2, and a third MOSFET M3. The gate of the first MOSFET M1 is connected to the gate of the second MOSFET M2 and together serve as the input terminal of the main amplifier circuit 2. The source of the first MOSFET M1 is grounded, and the source of the second MOSFET M2 is grounded. The drain of the first MOSFET M1 is connected to the drain of the second MOSFET M2 and the source of the third MOSFET M3. The gate of the third MOSFET M3 is used to connect to an external logic control circuit, and the drain of the third MOSFET M3 serves as the output terminal of the main amplifier circuit 2.

[0037] The bias control circuit 6 includes a current source Ibias, a fourth MOSFET M4, a first resistor R1, a first switch 61 (single-pole single-throw switch, SW0), and a second switch 62 (single-pole double-throw switch, SW1, SW2). The input terminal of the current source Ibias is connected to the power supply VDD, and the output terminal of the current source Ibias is connected to the drain and gate of the fourth MOSFET M4, respectively. The source of the fourth MOSFET M4 is connected to the control terminal of the first switch 61, and the output terminal of the first switch 61 is grounded. The gate of the fourth MOSFET M4 is also connected to the first terminal of the first resistor R1, and the second terminal of the first resistor R1 is connected to the control terminal of the second switch 62. The first output terminal of the second switch 62 is connected to the gate of the first MOSFET M1, and the second output terminal of the second switch 62 is connected to the gate of the second MOSFET M2. The current source Ibias is used to provide bias current to the fourth MOSFET M4, and the bias current controls the turning on and off of the first MOSFET M1 and the second MOSFET M2 via the second switch 62. The fourth MOSFET M4 is supplied with operating current through the current source Ibias. The first resistor R1 is used to isolate the RF and analog circuit modules. The value of R1 should be moderate to avoid introducing excessive noise and to improve the overall linearity. When the first switch 61 is open, the fourth MOSFET M4 can be connected in a diode configuration as a mirror transistor to provide bias current to the first MOSFET M1 and the second MOSFET M2.

[0038] Specifically, by simplifying the existing CS transistor amplification branch, the large switching transistor used to switch between the CS transistor and the source inductor Ls branch is eliminated, and this switching control is implemented by a smaller bias control switch. Since this bias control circuit 6 is not in the main amplification circuit 2, the size of the selected switching transistor can be relatively small without affecting RF performance such as gain and noise. Through reasonable logic design, this bias control circuit 6 can flexibly select the left and right first MOS transistors M1 and second MOS transistors M2 to achieve the desired path, which not only optimizes gain and linearity but also effectively reduces the RF section area and lowers chip cost.

[0039] In this embodiment, the input matching circuit 1 includes a first inductor L1. The first end of the first inductor L1 serves as the input terminal of the input matching circuit 1, and the second end of the first inductor L1 serves as the output terminal of the input matching circuit 1. After input matching through the first inductor L1, the radio frequency signal is output to the gates of the first MOSFET M1 and the second MOSFET M2, respectively.

[0040] In this embodiment, the low-noise amplifier 100 further includes a second inductor L2 and a third inductor L3. The first end of the second inductor L2 is connected to the source of the first MOSFET M1, and the second end of the second inductor L2 is grounded. The second inductor L2 is used to provide input impedance matching for the first MOSFET M1. The first end of the third inductor L3 is connected to the source of the second MOSFET M2, and the second end of the third inductor L3 is grounded. The third inductor L3 is used to provide input impedance matching for the second MOSFET M2. By using the second inductor L2 and the third inductor L3 as source degradation inductors for the first MOSFET M1 and the second MOSFET M2, respectively, input impedance matching, noise figure optimization, and gain stability improvement for the first MOSFET M1 and the second MOSFET M2 can be achieved.

[0041] In this embodiment, the low-noise amplifier 100 further includes a first capacitor C1 and a second capacitor C2. The first end of the first capacitor C1 and the first end of the second capacitor C2 are connected and jointly connected to the output terminal of the input matching circuit 1. The second end of the first capacitor C1 is connected to the gate of the first MOSFET M1. The first capacitor C1 is used to block the DC signal output by the input matching circuit 1 before outputting it to the gate of the first MOSFET M1. The second end of the second capacitor C2 is connected to the gate of the second MOSFET M2. The second capacitor C2 is used to block the DC signal output by the input matching circuit 1 before outputting it to the gate of the second MOSFET M2. The DC blocking effect is achieved by using the first capacitor C1 and the second capacitor C2 as the gates of the first MOSFET M1 and the second MOSFET M2, respectively.

[0042] In this embodiment, the output matching circuit 3 includes a third capacitor C3. The first terminal of the third capacitor C3 serves as the input terminal of the output matching circuit 3, and the second terminal of the third capacitor C3 serves as the output terminal of the output matching circuit 3. The third capacitor C3 can be used for output matching and DC blocking of the amplified radio frequency signal.

[0043] In this embodiment, the gain adjustment circuit 4 includes an adjustable resistor R3 and a fourth inductor L4. The first terminal of the adjustable resistor R3 and the first terminal of the fourth inductor L4 are connected together to the power supply VDD, and the second terminal of the adjustable resistor R3 is connected to the second terminal of the fourth inductor L4. The adjustable resistor R3 is used to achieve gain adjustment at different levels. By connecting the adjustable resistor R3 and the fourth inductor L4 in parallel to the power supply VDD, gain adjustment at different levels can be achieved.

[0044] In this embodiment, the low-noise amplifier 100 further includes a filter circuit 7. The input terminal of the filter circuit 7 is connected to the external logic control circuit, and the output terminal of the filter circuit 7 is connected to the gate of the third MOS transistor M3. The filter circuit 7 is used to provide a bias voltage to the gate of the third MOS transistor M3 after low-pass filtering. The gate control voltage VCG output by the external logic control circuit is low-pass filtered by the filter circuit 7 to provide a bias voltage to the gate of the third MOS transistor M3.

[0045] In this embodiment, the filter circuit 7 includes a fourth capacitor C4 and a second resistor R2. The first end of the second resistor R2 serves as the input terminal of the filter circuit 7, and the second end of the second resistor R2 is connected to the first end of the fourth capacitor C4 and serves as the output terminal of the filter circuit 7. The second end of the fourth capacitor C4 is grounded. The second resistor R2 and the fourth capacitor C4 form a passive first-order low-pass filter, which allows low-frequency signals to pass through while attenuating or blocking high-frequency interference signals. This can be used to suppress the noise of the low-noise amplifier 100 and ensure the stability of the amplifier's DC operating point.

[0046] In this embodiment, the attenuation circuit 5 is an ATT (Attenuator) attenuator. An ATT attenuator is a circuit module used to reduce signal amplitude / power without significantly changing the signal waveform or frequency characteristics. Through signal attenuation, the circuit gain level can be flexibly adjusted.

[0047] The specific working principle of this invention is as follows:

[0048] The radio frequency (RF) signal is input through the signal input port RFIN. It passes through the first terminal of the first inductor L1 for input matching, and then through the second terminal of the first inductor L1 for DC blocking via the first capacitor C1 and the second capacitor C2. The signal is then output to the gates of the first MOSFET M1 and the second MOSFET M2, respectively. The RF signal is amplified by the first and second MOSFETs M1 and M2, and then further amplified by the third MOSFET M3 to improve the power amplification effect. An adjustable resistor R3 and a fourth inductor L4 are connected in parallel to the power supply VDD, allowing for gain adjustment at different levels. The gate control voltage VCG output by the external logic control circuit is low-pass filtered by the filter circuit 7 and then used to provide a bias voltage to the gate of the third MOSFET M3. The second inductor L2 and the third inductor L3 act as source degradation inductors, providing input matching for the first and second MOSFETs M1 and M2, respectively. The fourth inductor L4 acts as a load inductor, providing output matching. After DC blocking via the third capacitor C3, the signal is used for gain reduction under large signal conditions via the attenuation circuit 5. By rationally selecting the branch where the first MOSFET M1 and the second inductor L2 are turned on, or the branch where the second MOSFET M2 and the third inductor L3 are turned on, the switching of different gain levels and the optimization of linearity can be achieved.

[0049] Example 2

[0050] Please see the appendix Figures 3-4 As shown, this embodiment of the invention provides a low-noise amplifier 200, which further includes a substrate 201. The substrate 201 is provided with a ground terminal GND, a first pin 202, and a second pin 203. A second inductor L2 and a third inductor L3 are respectively integrated on the substrate 201. The first end of the second inductor L2 is connected to the first pin 202, and the second end of the second inductor L2 is connected to the ground terminal GND. The first end of the third inductor L3 is connected to the second pin 203, and the second end of the third inductor L3 is connected to the ground terminal GND. The first pin 202 is connected to the source of the first MOSFET M1, and the second pin 203 is connected to the source of the second MOSFET M2.

[0051] In order to further reduce the chip area, in this second embodiment, the second inductor L2 and the third inductor L3 used for gain control and linearity optimization in the first embodiment are removed from the chip, and only the corresponding first pin 202 (L2-PIN) and second pin 203 (L3-PIN) are retained. The source degradation inductors of the removed second inductor L2 and third inductor L3 are designed and implemented on the substrate 201. By utilizing the high Q value (quality factor) design and low cost design of the substrate 201, not only can the RF noise performance be further optimized, but the chip area and cost can also be further reduced. Finally, through reasonable logic design, the branch of the first MOSFET M1 and the second inductor L2 or the second MOSFET M2 and the third inductor L3 can be flexibly selected, which can not only realize the switching of different gain levels and the optimization of linearity, but also reduce the chip area and cost.

[0052] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A low-noise amplifier, characterized in that, The low-noise amplifier includes: an input matching circuit, a main amplification circuit, an output matching circuit, a gain adjustment circuit, an attenuation circuit, and a bias control circuit. The input terminal of the input matching circuit is connected to the signal input port. The output terminal of the input matching circuit is connected to the input terminal of the main amplifier circuit. The output terminal of the main amplifier circuit is connected to the input terminal of the output matching circuit. The input terminal of the gain adjustment circuit is connected to the power supply. The output terminal of the gain adjustment circuit is connected to the output terminal of the main amplifier circuit. The output terminal of the output matching circuit is connected to the input terminal of the attenuation circuit. The output terminal of the attenuation circuit is connected to the signal output port. The bias control circuit is used to control the on and off of the main amplifier circuit. The input matching circuit is used to achieve input impedance matching for the RF signal input to the main amplifier circuit. The main amplifier circuit amplifies the RF signal. The output matching circuit is used to achieve output impedance matching for the RF signal output by the main amplifier circuit and attenuates the signal output through the attenuation circuit. The gain adjustment circuit is used to switch the gain level of the main amplifier circuit. The main amplifier circuit includes a first MOSFET, a second MOSFET, and a third MOSFET. The gate of the first MOSFET is connected to the gate of the second MOSFET and together serve as the input terminal of the main amplifier circuit. The source of the first MOSFET is grounded, and the source of the second MOSFET is grounded. The drain of the first MOSFET is connected to the drain of the second MOSFET and the source of the third MOSFET. The gate of the third MOSFET is used to connect to an external logic control circuit, and the drain of the third MOSFET serves as the output terminal of the main amplifier circuit. The bias control circuit includes a current source, a fourth MOSFET, a first resistor, a first switch, and a second switch. The input terminal of the current source is connected to a power supply, and the output terminal of the current source is connected to the drain and gate of the fourth MOSFET. The source of the fourth MOSFET is connected to the control terminal of the first switch, and the output terminal of the first switch is grounded. The gate of the fourth MOSFET is also connected to the first terminal of the first resistor, the second terminal of the first resistor is connected to the control terminal of the second switch, the first output terminal of the second switch is connected to the gate of the first MOSFET, and the second output terminal of the second switch is connected to the gate of the second MOSFET. The current source provides bias current to the fourth MOSFET, and the bias current controls the switching on and off of the first and second MOSFETs via the second switch.

2. The low-noise amplifier according to claim 1, characterized in that, The input matching circuit includes a first inductor, with a first end of the first inductor serving as the input terminal of the input matching circuit and a second end of the first inductor serving as the output terminal of the input matching circuit.

3. The low-noise amplifier according to claim 2, characterized in that, The low-noise amplifier further includes a second inductor and a third inductor. The first end of the second inductor is connected to the source of the first MOSFET, and the second end of the second inductor is grounded. The second inductor is used to provide input impedance matching for the first MOSFET. The first end of the third inductor is connected to the source of the second MOSFET, and the second end of the third inductor is grounded. The third inductor is used to provide input impedance matching for the second MOSFET.

4. The low-noise amplifier according to claim 3, characterized in that, The low-noise amplifier further includes a substrate, on which a ground terminal, a first pin, and a second pin are provided. The second inductor and the third inductor are respectively integrated on the substrate. The first end of the second inductor is connected to the first pin, and the second end of the second inductor is connected to the ground terminal. The first end of the third inductor is connected to the second pin, and the second end of the third inductor is connected to the ground terminal. The first pin is connected to the source of the first MOSFET, and the second pin is connected to the source of the second MOSFET.

5. The low-noise amplifier according to claim 1, characterized in that, The low-noise amplifier further includes a first capacitor and a second capacitor; the first terminal of the first capacitor is connected to the first terminal of the second capacitor and is jointly connected to the output terminal of the input matching circuit, the second terminal of the first capacitor is connected to the gate of the first MOS transistor, and the first capacitor is used to block the DC signal output by the input matching circuit and output it to the gate of the first MOS transistor; the second terminal of the second capacitor is connected to the gate of the second MOS transistor, and the second capacitor is used to block the DC signal output by the input matching circuit and output it to the gate of the second MOS transistor.

6. The low-noise amplifier according to claim 1, characterized in that, The output matching circuit includes a third capacitor, the first end of which serves as the input terminal of the output matching circuit, and the second end of which serves as the output terminal of the output matching circuit.

7. The low-noise amplifier according to claim 6, characterized in that, The gain adjustment circuit includes an adjustable resistor and a fourth inductor. The first end of the adjustable resistor and the first end of the fourth inductor are connected together to the power supply, and the second end of the adjustable resistor is connected to the second end of the fourth inductor. The adjustable resistor is used to achieve different gain levels.

8. The low-noise amplifier according to claim 1, characterized in that, The low-noise amplifier further includes a filter circuit. The input terminal of the filter circuit is used to connect to the external logic control circuit, and the output terminal of the filter circuit is connected to the gate of the third MOS transistor. The filter circuit is used to provide a bias voltage to the gate of the third MOS transistor after low-pass filtering.

9. The low-noise amplifier according to claim 8, characterized in that, The filter circuit includes a fourth capacitor and a second resistor; the first end of the second resistor serves as the input terminal of the filter circuit, the second end of the second resistor is connected to the first end of the fourth capacitor and serves as the output terminal of the filter circuit, and the second end of the fourth capacitor is grounded.

10. The low-noise amplifier according to claim 1, characterized in that, The attenuation circuit is an ATT attenuator.

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