High-power single-pole double-throw radio frequency switch based on CMOS technology

Abstract

The invention discloses a high-power single-pole double-throw radio frequency switch based on a CMOS (Complementary Metal Oxide Semiconductor) process. The switch adopts a cross-controlled series-parallel stack architecture, wherein series and parallel stack switch groups of the transmitting branch and the receiving branch are cross-controlled by complementary control ends. The switch adopts a novel independent bias technology, equivalent negative voltage turn-off is realized by applying a high level to the source and drain electrodes of the stacked switch group in a turn-off state and applying a low level to the grid electrode, and an internal negative voltage circuit is not needed. In order to realize bias and direct current isolation, two ends of each stacked switch group are connected in series with blocking capacitors. According to the scheme, transistor stacking is combined, the power processing capacity and linearity of the switch are remarkably improved, the design is simplified, low insertion loss and high isolation are achieved within the ultra-wideband range, and the ultra-wideband switch is suitable for the fields of 5G mobile communication, radar detection and the like.

Description

Technical Field

[0001] This invention relates to the field of radio frequency integrated circuit design technology, and specifically to a single-pole double-throw radio frequency switch circuit using Si-based CMOS technology with a novel independent biasing technology and a series-parallel stacked structure. Background Technology

[0002] The global wireless communication technology is undergoing rapid iteration, and its application scenarios have expanded from the military, industrial, and broadcasting sectors of the 1990s to a wide range of civilian consumer and commercial services, becoming a key infrastructure of modern society. As the core foundation of wireless communication technology, radio frequency (RF) chips undertake core tasks such as RF signal transmission and reception, frequency synthesis, and power amplification, directly determining the performance of communication systems and occupying a strategic position in the defense and civilian markets of various countries. The core functions of a radio frequency (RF) communication system are information transmission and reception, frequency modulation, and power amplification. Achieving these functions requires the integration of key modules such as power amplifiers (PAs), low-noise amplifiers (LNAs), antennas, RF switches, and filters. Among these, the RF switch, as the active control component in the chip that enables signal path switching, is not only the core of transmit / receive mode switching but also the hub for dynamic matching of the antenna and transmit / receive link in a multi-mode, multi-frequency architecture. Its performance is determined by key parameters such as insertion loss, isolation, return loss, and power handling capability (commonly measured by the P1dB compression point). In silicon-based CMOS technology, RF switches face inherent challenges: insertion loss attenuates transmit and receive signals, reduces receiver sensitivity, worsens noise figure, and increases transmit power consumption while weakening transmission range; excellent isolation prevents high-power signal leakage at the transmitter from damaging sensitive devices such as LNAs; with the development of 5G and IoT technologies, RF switches need to significantly improve power handling capabilities to avoid signal distortion and electromagnetic interference. Traditional methods to improve power handling capabilities, such as transistor stacking with negative bias, are effective, but they introduce negative bias generation circuitry, leading to increased chip area, power consumption, and design complexity, and may introduce additional digital noise.

[0003] Therefore, there is an urgent need for an RF switch solution that can achieve high power processing capability, low insertion loss, and high isolation under standard CMOS technology, while avoiding the drawbacks of complex negative voltage circuits. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects of existing silicon-based CMOS RF switches, such as easy saturation and breakdown and poor linearity when subjected to high power, as well as the circuit complexity, high power consumption and high noise caused by traditional negative voltage bias schemes, and to provide a high linearity, high power single-pole double-throw RF switch with simple structure and excellent performance.

[0005] The object of this invention is achieved in the following manner: A high-power single-pole double-throw radio frequency switch based on CMOS technology includes: a transmit port TX, a receive port RX, an antenna port ANT, a first control terminal Vg_TX, and a second control terminal Vg_RX; The radio frequency switch includes a transmitting branch and a receiving branch; The transmit branch includes a first stacked switch group connected in series between the TX and the ANT, and a second stacked switch group connected in parallel between the TX and ground; The receiving branch includes a third stacked switch group connected in series between the ANT and RX, and a fourth stacked switch group connected in parallel between the RX and ground; The first control terminal Vg_TX simultaneously controls the first stacked switch group and the fourth stacked switch group; The second control terminal Vg_RX simultaneously controls the third stacked switch group and the second stacked switch group; The switch employs independent biasing technology, which achieves equivalent reverse bias by applying a high DC potential to the source and drain of the stacked switch group in the off state while applying a low level to the gate. In the transmit and receive branches, each stacked switch group has a DC blocking capacitor connected in series at both ends to isolate the DC bias potential from the RF port.

[0006] The first stacked switch group is a first series-connected stacked MOSFET group Ms1-Msn, the second stacked switch group is a first parallel-connected stacked MOSFET group Xs1-Xsn, the third stacked switch group is a second series-connected stacked MOSFET group Xp1-Xpn, and the fourth stacked switch group is a second parallel-connected stacked MOSFET group Mp1-Mpn.

[0007] The first control terminal Vg_TX is connected to the common gate of the first series-stacked MOSFET group Ms1-Msn and the second parallel-stacked MOSFET group Mp1-Mpn; the second control terminal Vg_RX is connected to the common gate of the second series-stacked MOSFET group Xp1-Xpn and the first parallel-stacked MOSFET group Xs1-Xsn.

[0008] Each stacked switch group consists of at least two CMOS process NMOS transistors stacked in series.

[0009] It also includes a gate resistor Rg, which is connected between the gate of each transistor and the corresponding control terminal.

[0010] It also includes the drain-source resistor Rds, which is connected between the source and drain of each transistor.

[0011] It also includes a body resistor Rb, which is connected between the body of each transistor and the negative bias node.

[0012] The capacitance value of the DC blocking capacitor is selected to ensure that its impedance is much smaller than the equivalent resistance Ron of the stacked switch group in the on state within the operating frequency band of the RF switch.

[0013] The beneficial effects of this invention are as follows: 1. High power handling capability and linearity: This invention adopts a MOSFET series-parallel stacked structure combined with a novel independent biasing technology, achieving an equivalent negative voltage turn-off effect without using internal negative voltage. This ensures uniform RF voltage distribution, significantly improving the P1dB compression point and linearity of the switch, and enabling it to withstand higher RF power. 2. Simplified design and reduced cost: Compared to traditional negative voltage solutions for RF switches, this invention has significant advantages in power handling capability and chip area. It eliminates the need for complex negative voltage generation circuits, reducing power consumption, chip area, and design complexity, and also reducing digital noise interference. 3. Excellent RF performance: By optimizing the stacking number, bias resistor, and DC blocking capacitor, low insertion loss, high isolation, and good port matching are achieved in the ultra-wideband range (e.g., 0.5-6GHz). Attached Figure Description

[0014] Figure 1 This is a structural block diagram of the radio frequency switch of the present invention; Figure 2 This is a structural block diagram of a radio frequency switch provided in an embodiment of the present invention; Figure 3 A block diagram of a single MOS switch structure provided in an embodiment of the present invention; Figure 4 A block diagram of the radio frequency switch signal for the transmission mode provided in an embodiment of the present invention; Figure 5 A block diagram of the radio frequency switch signal for the receiving mode provided in an embodiment of the present invention; Figure 6 The return loss of each port under the RF switch simulation at a frequency of 0.5-6GHz provided in the embodiments of the present invention; Figure 7 The insertion loss and isolation performance of the RF switch at a frequency of 0.5-6GHz provided in the embodiments of the present invention are shown.

[0015] Figure 8 The input P1dB value under RF switch simulation in the 0.5-6GHz frequency band is provided in the embodiment of the present invention. Detailed Implementation

[0016] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0017] It should be noted that the following detailed descriptions are exemplary and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same technical meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0018] like Figure 1 As shown, the present invention provides a high-power single-pole double-throw radio frequency switch based on CMOS technology, including: a transmit port TX, a receive port RX, an antenna port ANT, a first control terminal Vg_TX, and a second control terminal Vg_RX; The radio frequency switch includes a transmitting branch and a receiving branch; The transmit branch includes a first stacked switch group connected in series between the TX and the ANT, and a second stacked switch group connected in parallel between the TX and ground; The receiving branch includes a third stacked switch group connected in series between the ANT and RX, and a fourth stacked switch group connected in parallel between the RX and ground; The first control terminal Vg_TX simultaneously controls the first stacked switch group and the fourth stacked switch group; The second control terminal Vg_RX simultaneously controls the third stacked switch group and the second stacked switch group; The switch employs independent biasing technology, which achieves equivalent reverse bias by applying a high DC potential to the source and drain of the stacked switch group in the off state while applying a low level to the gate. In the transmit and receive branches, each stacked switch group has a DC blocking capacitor connected in series at both ends to isolate the DC bias potential from the RF port.

[0019] The first stacked switch group is a first series-connected stacked MOSFET group Ms1-Msn, the second stacked switch group is a first parallel-connected stacked MOSFET group Xs1-Xsn, the third stacked switch group is a second series-connected stacked MOSFET group Xp1-Xpn, and the fourth stacked switch group is a second parallel-connected stacked MOSFET group Mp1-Mpn.

[0020] The first control terminal Vg_TX is connected to the common gate of the first series-stacked MOSFET group Ms1-Msn and the second parallel-stacked MOSFET group Mp1-Mpn; the second control terminal Vg_RX is connected to the common gate of the second series-stacked MOSFET group Xp1-Xpn and the first parallel-stacked MOSFET group Xs1-Xsn.

[0021] Each stacked switch group consists of at least two CMOS process NMOS transistors stacked in series.

[0022] It also includes a gate resistor Rg, which is connected between the gate of each transistor and the corresponding control terminal.

[0023] It also includes the drain-source resistor Rds, which is connected between the source and drain of each transistor.

[0024] It also includes a body resistor Rb, which is connected between the body of each transistor and the negative bias node.

[0025] The capacitance value of the DC blocking capacitor is selected to ensure that its impedance is much smaller than the equivalent resistance Ron of the stacked switch group in the on state within the operating frequency band of the RF switch.

[0026] Example: like Figure 2 The diagram illustrates a circuit schematic of a specific embodiment. The RF switch includes a transmit port TX, a receive port RX, and an antenna port ANT. The transmit branch includes: a first series-connected stacked NMOS group Ms1-Ms5 (i.e., a first stacked switch group) connected in series between TX and ANT, and a first parallel-connected stacked NMOS group Xs1-Xs5 (i.e., a second stacked switch group) connected in parallel between TX and ground. The receive branch includes: a second series-connected stacked NMOS group Xp1-Xp5 (i.e., a third stacked switch group) connected in series between ANT and RX, and a second parallel-connected stacked NMOS group Mp1-Mp5 (i.e., a fourth stacked switch group) connected in parallel between RX and ground.

[0027] To achieve cross-control and independent bias: The gates of Ms1-Ms5 and Mp1-Mp5 are connected to the first control terminal Vg_TX.

[0028] The gates of Xp1-Xp5 and Xs1-Xs5 are connected together to the second control terminal Vg_RX.

[0029] At both ends of each stacked switch group, a DC blocking capacitor (CBLK) is connected in series. Specifically, DC blocking capacitors CBLK_TX1 and CBLK_TX2 are located at both ends of the Ms1-Ms5 branch (TX side and ANT side), respectively; DC blocking capacitor CBLK_Xs is located on the TX side of the Xs1-Xs5 branch; DC blocking capacitor CBLK_Xp is located on the ANT side of the Xp1-Xp5 branch; DC blocking capacitors CBLK_RX1 and CBLK_RX2 are located at both ends of the Mp1-Mp5 branch (RX side and ground side), respectively; and DC blocking capacitor CBLK_Mp is located on the RX side of the Mp1-Mp5 branch.

[0030] Matching inductors L1, L2, and L3 are used for port impedance matching.

[0031] like Figure 3The diagram illustrates in detail the external bias component connections of a single stacked MOSFET (Ms1 as an example). The gate resistor Rg is AC-floated to minimize gate oxide breakdown caused by RF signal coupling and reduce RF signal leakage. The drain and source biases are connected by a large resistor. The drain-source resistor Rds provides DC potential to the source and drain terminals of each MOSFET. In a series-parallel RF switch, the drain-source resistor Rds stabilizes the DC potential of the MOSFET's source and drain at 0V. Rgnd is the bias resistor at the MOSFET body, used to reduce RF signal leakage. Resistors of the same value are connected across the source and drain terminals of the stacked MOSFETs, which helps to evenly distribute the source and drain voltages of each MOSFET in the turn-off branch, improving the linearity of the switch.

[0032] like Figure 4 As shown, in transmit mode, the RF switch has Vg_TX at a high level and Vg_RX at a low level. At this time, Ms1-Ms5 (first group) are on, equivalent to a low-impedance on-resistance Ron; Xs1-Xs5 (second group) are off, equivalent to a high-impedance parasitic capacitance Coff, used to reduce RF signal leakage to ground. The RF signal can then be effectively transmitted between TX and ANT. Simultaneously, Xp1-Xp5 (third group) are off, equivalent to a high-impedance parasitic capacitance Coff, providing isolation between the transmit port and the RX port. Mp1-Mp5 (fourth group) are on, equivalent to a low-impedance equivalent resistance Ron, guiding signals leaking to the RX port to ground, further enhancing isolation. The on-resistance Ms1-Ms5 provide a low-loss path from TX to ANT. Using independent biasing technology, the source and drain terminals of the off-state Xs1-Xs5 and Xp1-Xp5 are set to a high potential (VDD), effectively turning them off; the on-state Mp1-Mp5 bypasses any signals that might leak into the RX path to ground. All DC blocking capacitors effectively prevent DC bias voltage from entering the RF port.

[0033] like Figure 5As shown, in receive mode, the RF switch has Vg_RX at a high level and Vg_TX at a low level. At this time, Xp1-Xp5 (third group) are on, equivalent to a low-impedance on-resistance Ron; Mp1-Mp5 (fourth group) are off, equivalent to a high-impedance parasitic capacitance Coff, used to reduce RF signal leakage to ground. The RF signal can then be effectively transmitted between ANT and RX. Simultaneously, Ms1-Ms5 (first group) are off, equivalent to a high-impedance parasitic capacitance Coff, providing isolation between the receive port and the TX port; Xs1-Xs5 (second group) are on, equivalent to a low-impedance equivalent resistance Ron, guiding the signal leaking to the TX port to ground, further enhancing isolation. The on-resistance Xp1-Xp5 provide a low-loss path from ANT to RX. When Ms1-Ms5 and Mp1-Mp5 are turned off, their source and drain are set to a high potential (VDD); when Xs1-Xs5 are turned on, any signals that may leak into the TX path are bypassed to ground.

[0034] Figure 6 The return loss of each port under the RF switch simulation at a frequency of 0.5-6GHz provided in this embodiment of the invention is shown by the simulation curve. It can be seen from the simulation curve that the S11 of each port is less than -10dB within the covered frequency range, which meets the requirements of the RF port.

[0035] Figure 7 The insertion loss and isolation performance of the RF switch at a frequency of 0.5-6GHz provided in this embodiment of the invention are shown by the simulation curves. It can be seen from the simulation curves that within the covered frequency band, the insertion loss S21 is less than -1.4dB and the isolation S31 is greater than -30dB. It can be seen that this embodiment meets the requirements of low insertion loss and high isolation.

[0036] Figure 8 The input P1dB compression point under RF switch simulation at a frequency of 0.5-6GHz provided in this embodiment of the invention is shown by the simulation curve. It can be seen that P1dB is greater than 38dBm, indicating that this embodiment meets the power processing capability requirements.

[0037] Figures 6 to 8 The simulation results (as described above) verify that this embodiment has excellent return loss (<-10dB), insertion loss (<-1.4dB), isolation (>30dB), and high input P1dB (>38dBm) performance in the 0.5-6GHz frequency band.

[0038] In summary, this invention, through a three-in-one design of a cross-controlled series-parallel stacked architecture, a novel independent biasing technology, and a necessary DC blocking capacitor structure, efficiently solves the power and linearity bottlenecks of silicon-based CMOS RF switches, achieving a high-performance, low-cost single-pole double-throw switch.

[0039] This invention improves power handling capability by combining a series-parallel stacked structure with an independent biasing method in the RF switch. When a single transistor processes a high-power RF signal, the swing of the high-power signal may cause the parasitic PN junction inside the transistor in the off state to re-conduct or break down, resulting in RF signal power leakage and thus reducing the power handling capability of the switch. To achieve high power handling capability, this invention uses transistor stacking to improve the linearity of the switch. Traditional negative voltage drive circuits use negative voltage to control the gate DC level of the MOSFET in the off state, effectively improving the power handling capability of the stacked structure, but also suffer from defects such as spurious emission power level, digital switch noise, and power consumption. To improve the linearity of the stacked structure while avoiding the adverse effects of negative voltage drivers, this invention proposes a novel independent biasing technology based on the research of the working mechanism of negative voltage drive circuits. It can achieve similar performance to a negative voltage controlled switch, but unlike conventional negative voltage biasing methods, this novel independent biasing method does not require internal negative voltage generation, has no additional power consumption or digital noise, and can equivalently replace the negative voltage biasing method, while achieving a 5-watt power handling capability.

[0040] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several changes and improvements without departing from the overall concept of the present invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A high power single-pole double-throw radio frequency switch based on CMOS process, characterized in that: The application relates to a radio frequency switch. The radio frequency switch comprises a transmitting port (TX), a receiving port (RX), an antenna port (ANT), a first control terminal (Vg_TX) and a second control terminal (Vg_RX). The radio frequency switch comprises a transmitting branch and a receiving branch. The transmitting branch comprises a first stacked switch group connected in series between the TX and the ANT, and a second stacked switch group connected in parallel between the TX and the ground. The receiving branch comprises a third stacked switch group connected in series between the ANT and the RX, and a fourth stacked switch group connected in parallel between the RX and the ground. The first control terminal (Vg_TX) simultaneously controls the first stacked switch group and the fourth stacked switch group. The second control terminal (Vg_RX) simultaneously controls the third stacked switch group and the second stacked switch group. The switch adopts an independent biasing technology, and high DC voltage is applied to the source-drain electrodes of the stacked switch group in the off state, and low voltage is applied to the gate, so that equivalent reverse biasing is realized. In the transmitting branch and the receiving branch, a DC blocking capacitor is connected in series at both ends of each stacked switch group, and is used for isolating the DC biasing voltage and the radio frequency port.

2. The high power single pole double throw radio frequency switch based on CMOS process according to claim 1, characterized in that: The first stacked switch group is a first series stacked MOSFET group (Ms1-Msn), the second stacked switch group is a first parallel stacked MOSFET group (Xs1-Xsn), the third stacked switch group is a second series stacked MOSFET group (Xp1-Xpn), and the fourth stacked switch group is a second parallel stacked MOSFET group (Mp1-Mpn).

3. The high power single pole double throw radio frequency switch based on CMOS process according to claim 2, characterized in that: The first control terminal (Vg_TX) is connected to the common gate of the first series stacked MOSFET group (Ms1-Msn) and the second parallel stacked MOSFET group (Mp1-Mpn); and the second control terminal (Vg_RX) is connected to the common gate of the second series stacked MOSFET group (Xp1-Xpn) and the first parallel stacked MOSFET group (Xs1-Xsn).

4. The high power single pole double throw radio frequency switch based on CMOS process of claim 1, wherein: Each stacked switch group is composed of at least two CMOS process NMOS transistors connected in series.

5. The high power single pole double throw radio frequency switch based on CMOS process of claim 1, wherein: A gate resistor (Rg) is further arranged and connected between the gate of each transistor and the corresponding control terminal.

6. The high power single pole double throw radio frequency switch based on CMOS process of claim 1, wherein: A drain-source resistor (Rds) is further arranged and connected across the source and the drain of each transistor.

7. The high power single pole double throw radio frequency switch based on CMOS process according to claim 1, wherein: A body terminal resistor (Rb) is further arranged and connected between the body terminal of each transistor and a negative voltage biasing node.

8. The high power single pole double throw radio frequency switch based on CMOS process according to claim 1, wherein: The capacitance of the DC blocking capacitor is selected to satisfy that the impedance of the DC blocking capacitor is far smaller than the equivalent resistance Ron of the stacked switch group in the on state in the working frequency band of the radio frequency switch.

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