Data processing method, device and equipment for QC-LDPC decoder

Abstract

The invention discloses a data processing method, device and equipment for a QC-LDPC decoder. The method comprises the following steps: storing posterior probability information into a first memory; in the reading stage of the QC-LDPC decoder, soft information corresponding to a layer where a check matrix is located is read from a first memory or a second memory, a check node value corresponding to the layer where the check matrix is located is read from a third memory, and a variable node update value is stored in the second memory; and in a write-in stage of the QC-LDPC decoder, reading the variable node update value from the second memory, storing the check node update value to a third memory, storing the soft information update value to the first memory and the second memory, and storing the soft information update value to the second memory. And the decoding result is read from the second memory after iteration is completed. By optimizing caching and calling of information such as check nodes, variable nodes and soft information, use of memory resources is reduced.

Description

Technical Field

[0001] This application belongs to the field of communication technology technology, and in particular relates to a data processing method, apparatus and equipment for a QC-LDPC decoder. Background Technology

[0002] As a channel coding scheme with performance approaching channel capacity, quasi-cyclic low-density parity-check codes (QC-LDPC) possess numerous advantages such as low coding complexity, self-interleaving, and low error flatness, making them a preferred channel coding scheme for recent wireless LAN standards (e.g., IEEE 802.11n / ac / ax). Furthermore, QC-LDPC codes achieve excellent error correction performance in wireless communication systems and are increasingly used in low-latency and regional decoding architectures of practical baseband chips.

[0003] To address the issues of low throughput and high storage resource consumption in QC-LDPC decoding, the QC-LDPC decoding algorithm primarily employs a layered decoding algorithm, continuously improved from the BP decoding algorithm. This algorithm improves convergence speed by timely exchanging node information between layers. Furthermore, different degrees of parallelism can be selected during hardware implementation to reduce latency and increase throughput. Currently, in the implementation of the layered decoding algorithm, updated check node and variable node information are calculated for each iteration for use in the next iteration. Multiple iterations yield the correct decoding result. To reduce the time spent on each iteration, the updated check node and variable node results from each iteration are stored for easy use between layers and in the next iteration. Therefore, minimizing memory resources and memory usage during hardware implementation is a major factor affecting decoder performance. Summary of the Invention

[0004] The embodiments of this application provide a data processing method, apparatus, and device for a QC-LDPC decoder, which can reduce the use of memory resources and improve decoder performance.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part by practice of this application.

[0006] According to a first aspect of the embodiments of this application, a data processing method for a QC-LDPC decoder is provided, the data processing method for the QC-LDPC decoder comprising: Store the posterior probability information in the first memory; During the reading phase of the QC-LDPC decoder, soft information corresponding to the layer where the parity matrix is ​​located is read from the first memory or the second memory, and parity node value corresponding to the layer where the parity matrix is ​​located is read from the third memory. The variable node update value is determined according to the soft information and the parity node value, and the variable node update value is stored in the second memory. The minimum value, the second smallest value, and the sequence number corresponding to the minimum value of the variable node update value are determined. During the write phase of the QC-LDPC decoder, the variable node update value is read from the second memory, the check node update value is determined according to the minimum value, the second smallest value and the sequence number corresponding to the minimum value, the soft information update value is determined according to the check node update value and the variable node update value, the check node update value is stored in the third memory, and the soft information update value is stored in the first memory and the second memory to complete the iteration of the layer where the check matrix is ​​located; After all layers of the verification matrix have been iterated, the decoding result is determined based on the soft information update value, and the decoding result is read from the second memory.

[0007] In some embodiments of this application, based on the foregoing scheme, reading the soft information corresponding to the layer where the parity-check matrix is ​​located from the first memory or the second memory includes: If the current iteration number is the first or second iteration of the layer where the check matrix is ​​located, the soft information corresponding to the layer where the check matrix is ​​located is read from the first memory; otherwise, the soft information corresponding to the layer where the check matrix is ​​located is read from the second memory.

[0008] In some embodiments of this application, based on the foregoing scheme, storing the soft information update value in the first memory and the second memory includes: If the current iteration number is the first iteration of the layer where the verification matrix is ​​located, the soft information update value is stored in the first memory; otherwise, the soft information update value is stored in both the first memory and the second memory.

[0009] In some embodiments of this application, based on the foregoing scheme, the first memory is a random access memory (RAM) with a depth of 32 and a bit width of 567; the second memory is a RAM with a depth of 32 and a bit width of 567; and the third memory is a RAM with a depth of 128 and a bit width of 405.

[0010] In some embodiments of this application, based on the foregoing scheme, the data processing method of the QC-LDPC decoder further includes: The order of reading and writing variable nodes, the order of reading and writing check nodes, the order of storing non-zero values ​​in the base matrix of the check matrix, the order of storing posterior probability information, and the order of outputting decoding results are stored according to the code rate, code length, and the layer where the check matrix is ​​located.

[0011] In some embodiments of this application, based on the foregoing scheme, the data processing method of the QC-LDPC decoder further includes: Based on the code rate, the code length, and the layer where the parity check matrix is ​​located, the target variable node read / write order, the target parity node read / write order, the target posterior probability information storage order, and the target decoding result output order are obtained. The posterior probability information is stored according to the storage order of the target posterior probability information; The target variable node update value, the soft information, and the soft information update value are read and written according to the target variable node read and write order. The check node value and the check node update value are read and written according to the target check node read and write order; The decoding results are output according to the target decoding result output order.

[0012] In some embodiments of this application, based on the foregoing scheme, the data processing method of the QC-LDPC decoder further includes: Set waiting times for the read / write order of the variable nodes and the read / write order of the verification nodes.

[0013] According to a second aspect of the embodiments of this application, a data processing apparatus for a QC-LDPC decoder is provided, the data processing apparatus for the QC-LDPC decoder comprising: A posterior probability information storage unit is used to store posterior probability information into the first memory; The decoder reading unit is used to read the soft information corresponding to the layer where the parity check matrix is ​​located from the first memory or the second memory during the reading stage of the QC-LDPC decoder, read the parity check node value corresponding to the layer where the parity check matrix is ​​located from the third memory, determine the variable node update value according to the soft information and the parity check node value, store the variable node update value in the second memory, and determine the minimum value, the second smallest value and the sequence number corresponding to the minimum value of the variable node update value. The decoder writing unit is used to read the variable node update value from the second memory during the writing stage of the QC-LDPC decoder, determine the check node update value according to the minimum value, the second smallest value and the sequence number corresponding to the minimum value, determine the soft information update value according to the check node update value and the variable node update value, store the check node update value to the third memory, and store the soft information update value to the first memory and the second memory to complete the iteration of the layer where the check matrix is ​​located; The decoding result reading unit is used to determine the decoding result based on the soft information update value after all layers of the parity check matrix have been iterated, and to read the decoding result from the second memory.

[0014] According to a third aspect of the present application, a data processing device for a QC-LDPC decoder is provided. The data processing device for the QC-LDPC decoder includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0015] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program, when executed by a processor, implements the steps of the method described above.

[0016] In this application, posterior probability information is stored in a first memory. During the read phase of the QC-LDPC decoder, soft information corresponding to the layer where the parity check matrix is ​​located is read from the first or second memory, and the parity check node value corresponding to the layer where the parity check matrix is ​​located is read from a third memory. The updated value of the variable node is then stored in the second memory. During the write phase of the QC-LDPC decoder, the updated value of the variable node is read from the second memory, the updated value of the parity check node is stored in the third memory, and the updated value of the soft information is stored in both the first and second memories. After the iteration is completed, the decoding result is read from the second memory. By optimizing the caching and retrieval of information such as parity check nodes, variable nodes, and soft information, the use of memory resources is reduced.

[0017] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings: Figure 1 This is a flowchart illustrating the data processing method of a QC-LDPC decoder in one embodiment; Figure 2 A schematic diagram showing the coordinates of non-zero values ​​in the parity check matrix with a code rate of 1 / 2 and a code length of 1944. Figure 3 A schematic diagram of data processing with a code rate of 1 / 2 and a code length of 1944, involving 8 iterations of layered decoding. Figure 4 This is a schematic diagram of the hardware architecture of a QC-LDPC decoder in one embodiment; Figure 5 This is a schematic diagram illustrating the variable node update value and soft information read / write address in one embodiment; Figure 6 This is a schematic diagram of the bypass structure in the first memory in one embodiment; Figure 7 This is a schematic diagram illustrating data processing during the decoding of two sets of data in one embodiment; Figure 8 This is a structural block diagram of the data processing device of a QC-LDPC decoder in one embodiment; Figure 9 This is an internal structural diagram of the data processing device of a QC-LDPC decoder in one embodiment. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0020] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0021] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0022] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such uses of these terms can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described.

[0024] For QC-LDPC decoder implementations in the IEEE 802.11 protocol, which have different requirements for decoding length, decoding rate, delay, and throughput, this application provides a QC-LDPC decoder data processing method that achieves both low storage resource consumption and high throughput. This method enables the QC-LDPC decoder to have low-latency, high-throughput decoding capabilities while consuming relatively few memory resources. To meet the high throughput and low latency requirements of the QC-LDPC decoder in the IEEE 802.11 protocol, a low-resource-consumption management strategy is adopted, utilizing input buffer management, parity nodes, variable nodes, parity matrix, and read-write sequential storage management.

[0025] Figure 1 This is a flowchart illustrating the data processing method of a QC-LDPC decoder in one embodiment, as shown below. Figure 1 As shown, a data processing method for a QC-LDPC decoder is provided, which may include the following steps: Step 101: Store the posterior probability information in the first memory.

[0026] In the specific implementation, the reading and writing order of variable nodes, the reading and writing order of check nodes, the non-zero values ​​in the base matrix of the check matrix, the storage order of posterior probability information, and the output order of decoding results can be stored according to the code rate, code length, and the layer where the check matrix is ​​located, so as to facilitate reading and writing during subsequent decoding.

[0027] The verification evidence base matrix needs to be 1 bit wider when stored, mainly for resetting during cyclic shifting to prevent data errors.

[0028] The read / write order of the verification node can be stored based on the code length, code rate, the position of the matrix in the corresponding layer, and the number of non-zero values ​​in the previous layer, such as... Figure 2 As shown, the address corresponding to the first column of the first row is 1, the address corresponding to the fifth column of the first row is 2, ... the address corresponding to the 14th column of the first row is 7, and the base value is 0 at this time; the address corresponding to the first column of the second row is 1, the address corresponding to the 15th column of the second row is 7, and so on, until all layers are completed. This can reduce the bit width during storage, thereby reducing storage resources.

[0029] It is important to note that in read-write sequential storage, in order to form a pipelined architecture and ensure that the result of the previous layer has been calculated before the next layer reads, a waiting time can be set for the read-write order of variable nodes and the read-write order of check nodes. For example, if the read order is 24, it means that the waiting time is in progress.

[0030] The storage order of posterior probability information and the output order of decoding results can be the same, and the reading and writing order of variable nodes and the reading and writing order of soft information can be the same.

[0031] After storing information such as the read / write order, the read / write order of the target variable nodes, the read / write order of the target parity nodes, the storage order of the target posterior probability information, and the output order of the target decoding results can be found based on the code rate, code length, and the layer where the parity check matrix is ​​located. The posterior probability information is stored according to the storage order of the target posterior probability information. The updated values ​​of the variable nodes, soft information, and updated values ​​of the soft information are read and written according to the read / write order of the target variable nodes. The parity node values ​​and updated values ​​of the parity nodes are read and written according to the read / write order of the target parity nodes. The decoding results are output according to the output order of the target decoding results.

[0032] Step 102: In the reading stage of the QC-LDPC decoder, read the soft information corresponding to the layer where the parity matrix is ​​located from the first memory or the second memory, read the parity node value corresponding to the layer where the parity matrix is ​​located from the third memory, determine the variable node update value based on the soft information and the parity node value, store the variable node update value in the second memory, and determine the minimum value, the second smallest value, and the sequence number corresponding to the minimum value of the variable node update value.

[0033] Specifically, if the current iteration number is the first or second iteration of the layer where the check matrix is ​​located, the soft information corresponding to the layer where the check matrix is ​​located is read from the first memory; otherwise, the soft information corresponding to the layer where the check matrix is ​​located is read from the second memory.

[0034] In the specific implementation, the first memory is a random access memory (RAM) with a depth of 32 and a bit width of 567; the second memory is a RAM with a depth of 32 and a bit width of 567; and the third memory is a RAM with a depth of 128 and a bit width of 405.

[0035] Step 103: In the writing stage of the QC-LDPC decoder, the variable node update value is read from the second memory, the check node update value is determined according to the minimum value, the second smallest value and the sequence number corresponding to the minimum value, the soft information update value is determined according to the check node update value and the variable node update value, the check node update value is stored in the third memory, and the soft information update value is stored in the first memory and the second memory to complete the iteration of the layer where the check matrix is ​​located.

[0036] Specifically, if the current iteration number is the first iteration of the layer containing the verification matrix, the soft information update value is stored in the first memory; otherwise, the soft information update value is stored in both the first and second memories.

[0037] Step 104: After all layers of the parity check matrix have been iterated, determine the decoding result based on the soft information update value and read the decoding result from the second memory.

[0038] It should be understood that during the read and write phases of the layered decoding algorithm, information needs to be stored and retrieved from the first memory q_mem, the second memory t_mem, and the third memory r_mem. The input posterior probability information needs to be stored in the first memory q_mem in the order it was stored; after a frame of data is stored, the decoding state begins, such as... Figure 3 The data processing diagram shown illustrates that during decoding, soft information is read from the first memory q_mem in the order of variable node reading based on the layer number, code length, and code rate of the parity check matrix. The updated values ​​of the variable nodes are calculated and stored in the second memory t_mem, and the minimum, second minimum, and their corresponding indices are calculated. At this point, the soft information for the next layer can be read using the same operation. Simultaneously, the updated values ​​of the variable nodes are read from the second memory t_mem in the order of variable node writing based on the layer number, code length, and code rate of the parity check matrix. The updated values ​​of the parity check nodes are calculated and stored in the third memory r_mem. The updated values ​​of the soft information are calculated and stored in the first memory q_mem and the second memory t_mem. At this point, the calculation for that layer is complete. After traversing all layers, one iteration is completed until the preset number of iterations is reached, yielding the final decoding result. Finally, the decoding result is read out of the second memory t_mem in sequence.

[0039] To reduce storage resources, the variable node update value and soft information can share a dual-port RAM, while the check node update value is stored in a separate RAM. During the first iteration of calculating the variable node update value, the check node's value is 0. Therefore, in the first iteration, the check node's output can be set to 0, and data is not read from the third memory (r_mem). This avoids resetting the third memory (r_mem) to zero after each decoding iteration, reducing decoding latency and improving throughput.

[0040] It should be noted that the layered decoding algorithm can employ two parallel operations to reduce latency. These two operations are called the Min Phase (reading phase) and the Sel Phase (writing phase). The reading phase calculates the updated value of each layer's variable node in each iteration, and obtains the minimum, second-minimum, and index corresponding to the minimum value. The writing phase calculates the updated values ​​of the check nodes and soft information for that layer. When calculating the check node update value, it compares the index of the current node with the minimum index calculated in the reading phase. If they match, the second-minimum value is multiplied by the normalization factor to obtain the check node update value; otherwise, the minimum value is selected. The soft information update value is determined based on the soft information sign bits of all inputs to that layer, the current node's sign bit, and the check node update value. This completes the update of the check nodes and soft information for that layer. After traversing all layers of the parity-check matrix, one decoding iteration is completed.

[0041] according to Figure 2 and Figure 3 As can be seen, if the hardware implementation follows the prescribed parity-check matrix arrangement, and the two stages mentioned in the layered decoding algorithm are pipelined, the waiting time required for message interdependence between adjacent layers is relatively long. That is, the update of the nth layer node needs to wait for the update result of the (n-1)th layer's soft information, and the waiting time increases with the number of iterations. To reduce the waiting time, the QC-LDPC decoder in this embodiment implements a new out-of-order arrangement method to complete the layered decoding. The out-of-order arrangement will not be specifically described in this paper; the analysis will focus on the memory usage during hardware implementation.

[0042] Figure 4 This is a schematic diagram of the hardware architecture of a QC-LDPC decoder in one embodiment, such as... Figure 4As shown, the QC-LDPC decoder mainly consists of computation, control, and storage-related modules. The main modules include a soft information cache management module, a parity check matrix and read / write order storage module, a circular shift module, a variable node storage module, a variable node computation module, a parity check node storage module, a main control module, a core computation module, and an output module. The system comprises the following modules: a soft information cache management module for storing input data and soft information update values ​​during the first and second iterations; a check matrix and read / write order storage module for storing variable node read / write order, check node read / write order, non-zero values ​​in the check matrix base matrix, posterior probability information storage order, and decoding result output order; a cyclic shift module for cyclically shifting soft information based on the check matrix value before calculating variable node update values ​​during the read phase; a variable node calculation module for storing variable node update values ​​calculated during the read phase and soft information update values ​​from the second to the eighth iteration; a central control module for allocating and calling memory for check nodes, variable nodes, and soft information during each iteration; a check node storage module for storing check node update values ​​at each layer; and a core calculation module for calculating the minimum, second minimum, and corresponding index of each layer during the read phase, as well as the check node update values ​​and soft information update values ​​at each layer during the write phase.

[0043] During the decoding process, since the parity check matrix is ​​not a regular LDPC code, meaning that the degree of each layer is not the same and the information dependency between the data in each layer is different after being shuffled, the waiting time required for adjacent layers is different. To solve this problem, waiting time needs to be inserted in the reading and writing stages according to different code rates and code lengths. That is, the reading and writing order can be stored as 24, indicating that the data is invalid at this time, which is the waiting time, so that the pipeline can proceed smoothly.

[0044] The specific process for hardware implementation is as follows: 1. Cache the input soft information in sequence. After caching is complete, perform the first iteration calculation, which is the reading phase. 2. After determining the reading order of soft information during all layer iterations of the parity-check matrix based on the code rate and code length (24 indicates that the padding time does not participate in the calculation) and the number of calculations involved in that layer, the soft information values ​​are read out in the reading order; 3. Based on the code rate and code length, obtain the parity check matrix value corresponding to the soft information read in the previous step for this layer. Perform a cyclic shift on the soft information value to obtain the variable node value. At the same time, read out the corresponding parity check node value (the parity check node value of all layers is 0 in the first iteration, and the parity check node update value calculated in the previous iteration in subsequent iterations) and perform a subtraction operation to obtain the variable node update value of this layer. Store them in the order of reading. 4. Compare the absolute values ​​of the updated variable node values ​​to obtain the minimum value, the second smallest value, and the read sequence number corresponding to the minimum value, as well as the result of XORing the sign bit of the soft information of this layer, and then proceed to the writing stage; 5. After determining the writing order of soft information and the number of information involved in the calculation during the iteration of this layer based on the code rate and code length, read out the updated values ​​of the variable nodes according to the writing order; 6. According to the writing order, compare the sequence number of the variable node update value corresponding to the layer with the sequence number of the minimum value of the layer. If they match, multiply the second smallest value calculated by the layer by the normalization factor to obtain the check node update value and store it. Then, perform a calculation with the variable node update value and the sign bit result calculated in step 4 to obtain the soft information update value. 7. Based on the code rate and code length, obtain the parity check matrix value corresponding to the soft information during this iteration. Perform a cyclic shift on the updated soft information value to obtain the final result of this iteration and store it for use in the next iteration. (The calculation for the next layer's read phase is performed simultaneously with the calculation during the write phase.) If the number of iterations equals the preset number of iterations, stop the iteration; otherwise, proceed to step 2. 8. Read out the final decoding results in random order.

[0045] During iterative computation, the updated values ​​of variable nodes calculated at each layer need to be stored for calculating soft information update values ​​and check node update values ​​to reduce latency. This increases memory resources. Therefore, soft information and variable node update values ​​share a single RAM to minimize the latency of decoding each set of data without increasing memory resources. Using a ping-pong structure for soft information input and updates can effectively reduce fill time, but it significantly increases memory usage. This embodiment uses a single RAM for storing soft information update values ​​and variable node update values, greatly reducing memory usage.

[0046] The main control module involves three RAMs for storing and retrieving variable nodes, check nodes, and soft information. These three RAMs are the first memory q_mem, the second memory t_mem, and the third memory r_mem. (Return reference) Figure 1 Initially, soft information is stored in the first memory, q_mem. After a set of data is stored, decoding is performed. In the first iteration, the soft information update value generated by each layer is stored in the first memory, q_mem, and the soft information value required for the next layer is read from q_mem. In the second iteration, the soft information value is still read from the first memory, q_mem, but the soft information update value calculated for each layer is stored not only in the first memory, q_mem, but also in the second memory, t_mem. Figure 5As shown, during each iteration, each layer calculates the variable node update value in the Min phase of the read phase and stores it in the second memory t_mem. In the Sel phase of the write phase, it directly reads the value to calculate the soft information and check node update values, storing the check node update values ​​in the third memory r_mem. The soft information update values ​​are stored in the first memory q_mem for reading and calculation in the Min phase of the next layer. As mentioned earlier, to prevent excessive waiting time, the check matrix is ​​arranged in random order to reduce the dependency between adjacent layers. Also, considering the latency of reading and writing data in the hardware design, to avoid the update value calculated in the Sel phase of the previous layer not being written to the corresponding address addr1, while the Min phase of the current layer requires the update value at the same address addr1 for calculation, a bypass structure is used for either the first memory q_mem or the second memory t_mem. Figure 6 As shown, if the current read address matches the write address of the current or previous cycle, the soft information update value calculated in the write phase (Sel phase) is directly passed to or delayed by one cycle to the output of the read soft information in the next layer (Min phase). This saves one clock cycle for storage or retrieval. This means that the storage of the variable node update value is only used for the operation of this layer and does not participate in the operation of the next layer. Moreover, it is read before the soft information update value is calculated in the write phase (Sel phase). At this time, other data can be written to the corresponding second memory (t_mem) without affecting the storage and retrieval of the variable node update value. The soft information update value can be stored in the second memory (t_mem). The above function can be achieved by changing the second memory (t_mem) to a true dual-port RAM for reading and writing. In the third to eighth iterations, the read soft information and the calculated soft information update value are obtained from the second memory (t_mem). After the decoding is completed, the decoding result is also read from the second memory (t_mem).

[0047] The main control module controls the reading and writing of each memory during the read, write, and decode output stages, which may include the following steps: In the reading phase, the main information provided is the reading address of the soft information value and the check node value, as well as the selected RAM. In the writing phase, the main information provided is the reading address of the current layer variable node update value, the writing address of the check node and the soft information update value, as well as the selected RAM. In the decoding output phase, the main information provided is the output order of the decoding results and the selected RAM.

[0048] Figure 7 This is a schematic diagram illustrating the data processing during decoding in one embodiment, as shown below. Figure 7As shown, the soft information value of the next set of inputs can be written into the first memory q_mem before the first set of decoding outputs. This is because the second memory t_mem is used to store the updated variable node values ​​during the second set of decoding. Therefore, when entering the decoding stage, the decoding result of the first set has already been read out, and this does not affect the second set of decoding. The dashed line in the figure indicates that the maximum throughput can be achieved as long as the end time of the second set of inputs is the same as the output time of the first set of decodings.

[0049] After extensive simulation testing and engineering verification, this embodiment can support decoding at four code rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6, and three code lengths: 628, 1296, and 1944. The throughput meets the requirements of the WiFi protocol; for example, at a code length of 1944, a code rate of 5 / 6, and a main frequency of 160MHz, the throughput reaches 680Mbps. During DC synthesis, the SMIC 55nm process is selected, and this design has approximately 94W gates. Based on the above description, this application fully meets the requirements of IEEE 802.11 communication for QC-LDPC decoders.

[0050] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0051] Based on the same inventive concept, embodiments of this application also provide a data processing device for a QC-LDPC decoder, such as... Figure 8As shown, the data processing device for the QC-LDPC decoder may include: a posterior probability information storage unit 801, a decoder reading unit 802, a decoder writing unit 803, and a decoding result reading unit 804, wherein: the posterior probability information storage unit 801 is used to store posterior probability information in a first memory; the decoder reading unit 802 is used, during the reading phase of the QC-LDPC decoder, to read the soft information corresponding to the layer where the parity check matrix is ​​located from the first memory or the second memory, to read the parity check node value corresponding to the layer where the parity check matrix is ​​located from the third memory, to determine the variable node update value based on the soft information and the parity check node value, to store the variable node update value in the second memory, and to determine the variable node update value. The decoder write unit 803 is used to read the variable node update value from the second memory during the write phase of the QC-LDPC decoder, determine the check node update value according to the minimum, second minimum, and corresponding index of the minimum, determine the soft information update value according to the check node update value and the variable node update value, store the check node update value in the third memory, and store the soft information update value in the first and second memories to complete the iteration of the layer where the check matrix is ​​located; the decoding result reading unit 804 is used to determine the decoding result according to the soft information update value and read the decoding result from the second memory after all layers of the check matrix have been iterated.

[0052] In some embodiments of this application, based on the foregoing scheme, the decoder reading unit 802 is further configured to read the soft information corresponding to the layer where the parity check matrix is ​​located from the first memory when the current iteration number is the first or second iteration of the layer where the parity check matrix is ​​located; otherwise, it reads the soft information corresponding to the layer where the parity check matrix is ​​located from the second memory.

[0053] In some embodiments of this application, based on the aforementioned scheme, the decoder writing unit 803 is further configured to store the soft information update value to the first memory when the current iteration number is the first iteration of the layer where the parity check matrix is ​​located; otherwise, store the soft information update value to the first memory and the second memory.

[0054] In some embodiments of this application, based on the aforementioned scheme, the first memory has a depth of 32 and a bit width of 567; the second memory has a depth of 32 and a bit width of 567; and the third memory has a depth of 128 and a bit width of 405.

[0055] In some embodiments of this application, based on the aforementioned scheme, the data processing device of the QC-LDPC decoder may further include: a read-write order storage unit (not shown), used to store the read-write order of variable nodes, the read-write order of check nodes, the non-zero values ​​in the base matrix of the check matrix, the storage order of posterior probability information, and the output order of decoding results according to the code rate, code length, and the layer where the check matrix is ​​located.

[0056] In some embodiments of this application, based on the foregoing scheme, the data processing device of the QC-LDPC decoder may further include: a read / write unit (not shown), used to find the target variable node read / write order, target parity node read / write order, target posterior probability information storage order, and target decoding result output order according to the code rate, code length, and the layer where the parity check matrix is ​​located; store the posterior probability information according to the target posterior probability information storage order; read and write the variable node update value, soft information, and soft information update value according to the target variable node read / write order; read and write the parity node value and parity node update value according to the target parity node read / write order; and output the decoding result according to the target decoding result output order.

[0057] In some embodiments of this application, based on the foregoing scheme, the data processing device of the QC-LDPC decoder may further include: a waiting time setting unit (not shown), used to set the waiting time for the read / write order of variable nodes and the read / write order of check nodes.

[0058] The modules in the data processing device of the aforementioned QC-LDPC decoder can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware within or independently of the processor in a computer device, or stored in software within the memory of the computer device, so that the processor can call and execute the corresponding operations of each module.

[0059] Based on the same inventive concept, this application also provides a data processing device for a QC-LDPC decoder. Figure 9 This is an internal structural diagram of the data processing device of a QC-LDPC decoder in one embodiment, as shown below. Figure 9 As shown, the data processing device of the QC-LDPC decoder includes one or more memories 904, one or more processors 902, and at least one computer program (program code) stored in the memory 904 and executable on the processor 902. When the processor 902 executes the computer program, it implements the data processing method of the QC-LDPC decoder as described above.

[0060] Among them, Figure 9In this document, a bus architecture (represented by bus 900) is used. Bus 900 may include any number of interconnected buses and bridges, linking various circuits including one or more processors represented by processor 902 and memory represented by memory 904. Bus 900 may also link various other circuits such as peripheral devices, voltage regulators, and power management circuits, which are well known in the art and therefore will not be described further herein. Bus interface 905 provides an interface between bus 900 and receiver 901 and transmitter 903. Receiver 901 and transmitter 903 may be the same element, i.e., a transceiver, providing a unit for communicating with various other devices over a transmission medium. Processor 902 is responsible for managing bus 900 and general processing, while memory 904 can be used to store data used by processor 902 during operation.

[0061] Those skilled in the art will understand that Figure 9 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the data processing device of the QC-LDPC decoder to which the present application is applied. The specific data processing device of the QC-LDPC decoder may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0062] Based on the same inventive concept, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, performs the following steps: Store the posterior probability information in the first memory; During the reading phase of the QC-LDPC decoder, the soft information corresponding to the layer where the parity matrix is ​​located is read from the first memory or the second memory, the parity node value corresponding to the layer where the parity matrix is ​​located is read from the third memory, the variable node update value is determined based on the soft information and the parity node value, the variable node update value is stored in the second memory, and the minimum value, the second smallest value, and the sequence number corresponding to the minimum value of the variable node update value are determined. During the write phase of the QC-LDPC decoder, the variable node update value is read from the second memory, the check node update value is determined according to the minimum value, the second smallest value and the sequence number corresponding to the minimum value, the soft information update value is determined according to the check node update value and the variable node update value, the check node update value is stored in the third memory, and the soft information update value is stored in the first memory and the second memory to complete the iteration of the layer where the check matrix is ​​located. After all layers of the parity check matrix have been iterated, the decoding result is determined based on the soft information update value, and the decoding result is read from the second memory.

[0063] In one embodiment, when the computer program is executed by a processor, it also performs the following steps: If the current iteration number is the first or second iteration of the layer containing the parity check matrix, the soft information corresponding to the layer containing the parity check matrix is ​​read from the first memory; otherwise, the soft information corresponding to the layer containing the parity check matrix is ​​read from the second memory.

[0064] In one embodiment, when the computer program is executed by a processor, it also performs the following steps: If the current iteration number is the first iteration of the layer containing the verification matrix, the soft information update value is stored in the first memory; otherwise, the soft information update value is stored in the first memory and the second memory.

[0065] In one embodiment, when the computer program is executed by a processor, it also performs the following steps: The order of reading and writing variable nodes, the order of reading and writing check nodes, the order of storing non-zero values ​​in the base matrix of the check matrix, the order of storing posterior probability information, and the order of outputting decoding results are stored according to the code rate, code length, and the layer where the check matrix is ​​located.

[0066] In one embodiment, when the computer program is executed by a processor, it also performs the following steps: Based on the code rate, code length, and the layer where the parity check matrix is ​​located, the reading and writing order of the target variable node, the reading and writing order of the target parity check node, the storage order of the target posterior probability information, and the output order of the target decoding result can be found. The posterior probability information is stored according to the storage order of the target posterior probability information; The update values ​​of variable nodes, soft information, and update values ​​of soft information are read and written according to the read and write order of the target variable nodes; The check node value and the check node update value are read and written according to the read and write order of the target check node; Output the decoding results according to the output order of the target decoding results.

[0067] In one embodiment, when the computer program is executed by a processor, it also performs the following steps: Set waiting times for the read / write order of variable nodes and check nodes.

[0068] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored as one or more instructions or codes on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope and spirit of this application and the appended claims. For example, due to the nature of software, the functions described above may be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Furthermore, the functional units may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. The device embodiments described above are merely illustrative; for example, the division of units can be a logical functional division, and in actual implementation, there may be other division methods. For instance, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling, direct coupling, or communication connection may be through some interfaces; the indirect coupling or communication connection between units or modules may be electrical or other forms.

[0070] The units described as separate components may or may not be physically separate. Similarly, the components of the control device may or may not be physical units; they may be located in one place or distributed across multiple units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0071] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard drive, magnetic disk, or optical disk.

[0072] The above description is merely an embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A data processing method of a QC-LDPC decoder, characterized by, The data processing method of the QC-LDPC decoder comprises the following steps: storing the posterior probability information to a first memory; reading the soft information corresponding to the layer where the check matrix is located from the first memory or a second memory, reading the check node value corresponding to the layer where the check matrix is located from a third memory, determining the variable node update value according to the soft information and the check node value, storing the variable node update value to the second memory, and determining the minimum value, the second minimum value and the serial number corresponding to the minimum value of the variable node update value in the reading stage of the QC-LDPC decoder; reading the variable node update value from the second memory, determining the check node update value according to the minimum value, the second minimum value and the serial number corresponding to the minimum value, determining the soft information update value according to the check node update value and the variable node update value, storing the check node update value to the third memory, storing the soft information update value to the first memory and the second memory to complete the iteration of the layer where the check matrix is located in the writing stage of the QC-LDPC decoder; determining the decoding result according to the soft information update value and reading the decoding result from the second memory in the case that the iteration of all layers of the check matrix is completed.

2. The data processing method of a QC-LDPC decoder according to claim 1, wherein, The reading of the soft information corresponding to the layer where the check matrix is located from the first memory or the second memory comprises the following steps: reading the soft information corresponding to the layer where the check matrix is located from the first memory in the case that the current iteration number is the first iteration or the second iteration of the layer where the check matrix is located, otherwise, reading the soft information corresponding to the layer where the check matrix is located from the second memory.

3. The data processing method of QC-LDPC decoder according to claim 1, wherein, The storing of the soft information update value to the first memory and the second memory comprises the following steps: storing the soft information update value to the first memory in the case that the current iteration number is the first iteration of the layer where the check matrix is located, otherwise, storing the soft information update value to the first memory and the second memory.

4. The data processing method of a QC-LDPC decoder according to any one of claims 1 to 3, characterized in that, The first memory is a random access memory (RAM) with a depth of 32 and a bit width of 567; the second memory is a RAM with a depth of 32 and a bit width of 567; and the third memory is a RAM with a depth of 128 and a bit width of 405.

5. The data processing method of a QC-LDPC decoder according to any one of claims 1 to 3, characterized in that, The data processing method of the QC-LDPC decoder further comprises the following steps: storing the variable node read-write sequence, the check node read-write sequence, the non-zero value in the check matrix base matrix, the posterior probability information storage sequence and the decoding result output sequence according to the code rate, the code length and the layer where the check matrix is located.

6. The data processing method of QC-LDPC decoder according to claim 5, wherein, The data processing method of the QC-LDPC decoder further comprises the following steps: finding the target variable node read-write sequence, the target check node read-write sequence, the target posterior probability information storage sequence and the target decoding result output sequence according to the code rate, the code length and the layer where the check matrix is located; storing the posterior probability information according to the target posterior probability information storage sequence; reading and writing the variable node update value, the soft information and the soft information update value according to the target variable node read-write sequence. read and write the check node value and the check node update value according to the target check node read-write order; output the decoding result according to the target decoding result output order.

7. The data processing method of QC-LDPC decoder according to claim 5, wherein, The data processing method of the QC-LDPC decoder further comprises: setting a waiting time for the variable node read-write order and the check node read-write order.

8. A data processing apparatus of a QC-LDPC decoder, characterized by, The data processing device of the QC-LDPC decoder comprises: a posteriori probability information storage unit configured to store a posteriori probability information to a first memory; a decoder reading unit configured to, in a reading stage of the QC-LDPC decoder, read soft information corresponding to a layer where a check matrix is located from the first memory or the second memory, read a check node value corresponding to the layer where the check matrix is located from a third memory, determine a variable node update value according to the soft information and the check node value, store the variable node update value to the second memory, and determine a minimum value, a second minimum value and a serial number corresponding to the minimum value of the variable node update value; a decoder writing unit configured to, in a writing stage of the QC-LDPC decoder, read the variable node update value from the second memory, determine a check node update value according to the minimum value, the second minimum value and the serial number corresponding to the minimum value, determine soft information update value according to the check node update value and the variable node update value, store the check node update value to the third memory, store the soft information update value to the first memory and the second memory, and complete iteration of the layer where the check matrix is located; a decoding result reading unit configured to, in a case where iteration of all layers of the check matrix is completed, determine a decoding result according to the soft information update value, and read the decoding result from the second memory.

9. A data processing apparatus of a QC-LDPC decoder, comprising a memory and a processor, the memory storing a computer program, characterized in that, The processor implements the steps of the method of any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program implements the steps of the method of any one of claims 1 to 7 when executed by the processor.

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