General transmit control system bus signal simulation method

Abstract

The application relates to the technical field of computers and discloses a general transmission control system bus signal simulation method.The method comprises the following steps: acquiring device node topology, protocol types and historical load data; constructing a bus network abstract model; extracting a message flow timing template; generating a concurrent message scheduling sequence conforming to arbitration logic; fusing a high-fidelity signal base; superimposing physical layer interference signals based on measured data; and injecting a measured system through a hardware-in-the-loop interface.The system comprises bus topology analysis, network modeling, timing template extraction, scheduling generation, signal fusion, interference injection and hardware output modules.The method significantly improves test authenticity, coverage and platform universality through joint modeling of logic and physical layers.

Description

Technical Field

[0001] This invention belongs to the field of computer technology, specifically relating to a method for simulating bus signals in a general-purpose launch control system. Background Technology

[0002] Against the backdrop of the rapid development of the Industrial Internet of Things (IIoT) and intelligent measurement and control systems, general-purpose launch control systems, as key signal interaction platforms, are widely used in high-reliability scenarios such as aerospace launch and measurement, weapon testing, and complex equipment integration testing. These systems typically connect multiple heterogeneous devices via a bus architecture to achieve command issuance, status feedback, and real-time collaborative control. With the expansion of system scale and the increase in device density, the number of signals transmitted concurrently on the bus surges, leading to non-orthogonal aliasing of multi-source signals in the time domain, frequency domain, and even code domain, creating a complex interference environment. Traditional bus signal simulation methods are mostly based on idealized assumptions, using orthogonal or isolated channels to generate signals for individual devices, making it difficult to reproduce the dynamic aliasing effects caused by factors such as device response delays, protocol conflicts, and electrical crosstalk under real-world operating conditions.

[0003] The concept of Non-Orthogonal Multiple Access (NOMA) has been introduced into the field of industrial signal simulation in recent years, giving rise to the NOMA-SST (Non-Orthogonal Multiple Access - Signal Superposition Testing) technology. This technology aims to synchronously simulate the concurrent signal behavior of multiple devices within a limited bandwidth through superposition coding and power domain differentiation mechanisms. The core objective of this technology is to reconstruct the signal interaction scenario of multiple devices coexisting with high fidelity without increasing the number of physical channels, thereby supporting the robustness verification and fault diagnosis capabilities of the control system under strong interference conditions.

[0004] Existing bus signal simulation schemes generally suffer from three major limitations: First, the signal generation model is overly simplified, supporting only static, independent signal sequence outputs and failing to dynamically couple the interaction logic and response timing between devices. Second, they lack effective modeling capabilities for non-orthogonal aliased signals, making it difficult to accurately control the power distribution, phase relationship, and burst characteristics of superimposed signals, resulting in significant deviations between simulation results and measured data. Third, in complex electromagnetic environments, traditional methods cannot distinguish and separate the effective components from the interference components in aliased signals, causing subsequent signal analysis, fault injection, or performance evaluation to lack a reliable benchmark. These deficiencies make it difficult for existing simulation methods to provide test records with practical engineering value when facing high-density, highly dynamic, and strongly coupled general transmission control scenarios. Therefore, a new simulation method capable of realistically reproducing and controllably separating non-orthogonal aliased bus signals is urgently needed. Summary of the Invention

[0005] This invention provides a general-purpose launch control system bus signal simulation method, aiming to solve the communication interference problem caused by signal aliasing from multiple devices and overcome the technical deficiency of traditional signal simulation techniques in failing to realistically reproduce complex electromagnetic and logical interaction scenarios. The method constructs a high-fidelity spatiotemporal coupling model of multi-source heterogeneous bus signals, combined with a dynamic topology reconstruction mechanism and a signal injection strategy based on physical layer characteristics, to achieve accurate simulation of the concurrent, asynchronous, and non-steady-state bus behavior of multiple devices in real combat or testing environments.

[0006] This invention provides a method for simulating bus signals in a general-purpose launch control system, comprising:

[0007] Obtain the physical connection topology, communication protocol type, message cycle characteristics, message priority allocation rules, and historical bus load data of all device nodes participating in communication in the target launch control system;

[0008] Based on the physical connection topology and communication protocol type, an initial bus network abstract model is constructed. The initial bus network abstract model includes the address identifier, message identifier set, transmission rate parameters and arbitration mechanism description of each device node.

[0009] The historical bus load data is segmented into time series and event trigger points are marked to extract message flow timing templates under typical working modes. The message flow timing templates include message sending time, duration, data frame length and the distribution pattern of verification fields.

[0010] Based on the message cycle characteristics and message priority allocation rules, a multi-device concurrent message scheduling sequence is generated. The multi-device concurrent message scheduling sequence ensures that within any time window, the message sending behavior of each device node conforms to its competition and arbitration logic in the real system.

[0011] The message flow timing template and the multi-device concurrent message scheduling sequence are spatiotemporally aligned and fused to generate a high-fidelity bus signal behavior base.

[0012] Based on the high-fidelity bus signal behavior substrate, a physical layer interference signal generated by an external environment disturbance model is superimposed. The physical layer interference signal includes voltage drop, signal reflection, common-mode noise and crosstalk components, and its amplitude, phase and duration are determined based on measured electromagnetic environment statistical data.

[0013] The superimposed composite signal is injected into the bus physical layer of the general-purpose launch control system under test through a hardware-in-the-loop interface to complete the closed-loop simulation of complex multi-device aliasing scenarios.

[0014] The present invention describes obtaining the physical connection topology of all communication-related device nodes in the target launch control system, specifically including:

[0015] The bus scanning tool is used to traverse all valid node addresses on the controller local area network bus and record the response latency and error frame reporting frequency of each node.

[0016] Parse the configuration description files of each node to extract its supported communication baud rates, filter mask settings, receive buffer depths, and error status register mappings;

[0017] Based on the above information, a bidirectional directed graph model containing logical dependencies between nodes and physical link impedance characteristics is constructed as a digital representation of the physical connection topology.

[0018] The construction of the initial bus network abstract model described in this invention specifically includes:

[0019] Each device node is assigned a unique logical identifier, which corresponds one-to-one with its hardware address in the real system;

[0020] Based on the communication protocol type, determine the encoding rules for the message arbitration field. For protocols that use identifier priority arbitration, map the message identifier to a binary priority code.

[0021] The message transmission rate parameter is defined as the number of bits transmitted per second, and its value range covers discrete levels from 10 kilobits per second to 1 megabit per second.

[0022] The arbitration mechanism is modeled as a finite state machine, and its state transition conditions are jointly determined by the current bus idle state, the priority of the messages to be sent by the node, and the collision detection results.

[0023] The present invention specifically includes time-series segmentation and event trigger point labeling of historical bus load data, which includes:

[0024] The continuously acquired raw bus data stream is sliced ​​using a preset time window of 100 milliseconds.

[0025] Within each time window, identify the start and end edges of all complete data frames and calculate the inter-frame interval time.

[0026] When the inter-frame interval is less than a preset threshold, it is determined to be a continuous message within the same event trigger sequence;

[0027] Each event trigger sequence is labeled with its corresponding system operation event type, which includes weapon unlocking, fire control calculation start-up, seeker activation, and launch command issuance.

[0028] The generation of multi-device concurrent message scheduling sequences described in this invention specifically includes:

[0029] Establish a scheduling engine based on a hybrid time-triggered and event-triggered approach;

[0030] Configure an independent message queue for each device node, and sort the messages in the queue according to their generation logic in the real system;

[0031] Within each scheduling cycle of the scheduling engine, all pending messages are globally sorted according to the message priority allocation rules;

[0032] If multiple messages have the same priority, they are sorted in ascending order by the physical address of the device node to which they belong;

[0033] Output the sorted message sending time sequence as a multi-device concurrent message scheduling sequence.

[0034] The spatiotemporal alignment and fusion of message stream timing templates and multi-device concurrent message scheduling sequences as described in this invention specifically includes:

[0035] Convert the relative time offset in the message flow timing template into an absolute timestamp, with the time of sending the first message in the scheduling sequence as the time zero point;

[0036] For message types that are missing in the template, insert placeholders in the scheduling sequence and mark them as optional messages;

[0037] For high-priority interrupt messages that exist in the template but are not included in the scheduling sequence, force them to be inserted into the nearest bus idle gap;

[0038] Generate a high-fidelity bus signal behavior base containing complete message content, precise sending time, and expected response behavior.

[0039] The construction of the external environment disturbance model described in this invention specifically includes:

[0040] Collect the bus differential signal waveforms of the real transmission platform under different operating conditions, and extract its rise time, fall time, overshoot amplitude and eye diagram closure parameters.

[0041] The frequency, duration, and amplitude distribution of voltage dip events were statistically analyzed to establish a voltage dip probability density function.

[0042] Based on transmission line theory, the signal reflection coefficient is calculated under different combinations of cable length and terminal matching resistor, and a reflection waveform library is generated.

[0043] Measure the induced noise spectrum on the bus when adjacent high-power devices start and stop, and construct a time-frequency joint distribution model of common-mode noise and crosstalk components;

[0044] The above interference components are weighted and superimposed according to their joint occurrence probability in the real environment to form a composite physical layer interference signal.

[0045] The hardware-in-the-loop interface described in this invention specifically includes:

[0046] Programmable logic devices are used to generate differential signal levels that conform to the controller area network protocol specification in real time.

[0047] A high-precision digital-to-analog converter circuit with a resolution of no less than 12 bits and an update rate of no less than 10 MHz is used to convert digital interference signals into analog voltage waveforms.

[0048] The differential signal synthesis unit vector superimposes the clean bus signal and the analog interference signal and outputs them to the bus physical layer;

[0049] The real-time monitoring feedback loop is used to sample the injected bus signal and compare it with the expected waveform, dynamically adjusting the interference injection intensity to maintain analog fidelity.

[0050] According to another aspect of the present invention, a universal transmit control system bus signal simulation system is provided, comprising:

[0051] The bus topology and protocol parsing module is used to obtain the physical connection topology, communication protocol type, message cycle characteristics, message priority allocation rules, and historical bus load data of all device nodes participating in communication in the target launch control system.

[0052] The bus network abstract modeling module is used to construct an initial bus network abstract model based on the physical connection topology and communication protocol type.

[0053] The message flow timing template extraction module is used to perform time-series segmentation and event trigger point labeling on the historical bus load data, and extract the message flow timing template under typical working mode.

[0054] The concurrent message scheduling generation module is used to generate a multi-device concurrent message scheduling sequence based on the message periodicity characteristics and message priority allocation rules.

[0055] The high-fidelity signal substrate fusion module is used to perform spatiotemporal alignment and fusion of the message flow timing template and the multi-device concurrent message scheduling sequence to generate a high-fidelity bus signal behavior substrate.

[0056] The physical layer interference injection module is used to superimpose a physical layer interference signal generated by an external environment disturbance model onto the high-fidelity bus signal behavior substrate.

[0057] The hardware-in-the-loop signal output module is used to inject the superimposed composite signal into the bus physical layer of the general-purpose transmission control system under test through the hardware-in-the-loop interface.

[0058] The bus topology and protocol parsing module described in this invention specifically includes:

[0059] The bus node scanning unit is used to traverse all valid node addresses on the bus and record their response characteristics.

[0060] The protocol feature extraction unit is used to parse the configuration description files of each node to obtain communication parameters;

[0061] Topology graph building unit, used to generate bidirectional directed graph models that include logical dependencies and physical link characteristics.

[0062] The physical layer interference injection module of this invention specifically includes:

[0063] An interference feature database stores parameterized models of voltage dips, signal reflections, common-mode noise, and crosstalk components.

[0064] The interference signal synthesis engine selects the corresponding interference components and performs weighted superposition based on the current simulation scenario.

[0065] A real-time feedback adjustment unit is used to monitor the quality of the injected signal and dynamically correct interference parameters.

[0066] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0067] This invention addresses the fundamental flaw of traditional bus signal simulation, which focuses solely on the protocol layer while neglecting the influence of the electromagnetic environment, by constructing a composite signal model that integrates logic layer behavior and physical layer characteristics. The method can accurately reproduce signal aliasing phenomena across multiple devices under high load and strong interference conditions, including cascading failures caused by priority inversion, arbitration failure, bit stuffing anomalies, and physical layer distortion. This is achieved by introducing an external environmental disturbance model based on measured data.

[0068] This invention represents a leap from "ideal logic simulation" to "real physical reproduction," significantly improving the test coverage and confidence level of general-purpose launch control systems in the integration testing, fault diagnosis, and robustness verification phases. Simultaneously, the dynamic topology reconstruction and hybrid scheduling mechanism ensures the flexibility and scalability of the simulation scenario, adapting to the differences in bus architecture among different launch platforms. This eliminates the need to develop dedicated simulators for each platform, greatly reducing testing costs and timelines. Attached Figure Description

[0069] Figure 1 This is a schematic diagram of the overall technical solution architecture of the present invention;

[0070] Figure 2 This is a schematic diagram of the core principle framework of the high-fidelity multi-source heterogeneous bus signal spatiotemporal coupling model in this invention;

[0071] Figure 3This is a logical flow diagram of the bus topology parsing and network abstraction modeling stage in this invention;

[0072] Figure 4 This is a logical flow framework diagram of the message flow timing template extraction and concurrent scheduling sequence generation stage in this invention;

[0073] Figure 5 This is a flowchart illustrating the logic flow of the high-fidelity signal substrate fusion and physical layer interference injection stages in this invention.

[0074] Figure 6 This is a schematic diagram of the multi-level interaction relationship and data flow between the hardware-in-the-loop interface and the external environment disturbance model in this invention. Detailed Implementation

[0075] This invention provides a general-purpose launch control system bus signal simulation method. Its core lies in constructing a high-fidelity composite signal model that integrates logical behavior and physical layer characteristics to accurately reproduce the concurrent communication behavior of multiple devices in complex electromagnetic environments. The method achieves closed-loop simulation of bus signal aliasing, interference, and unsteady dynamics in real combat or testing scenarios through five systematic stages: acquisition, modeling, scheduling, fusion, and injection. The following will be combined with the appendix... Figure 1 To be continued Figure 6 This section provides a detailed implementation description of each functional module of the system, expanding upon it layer by layer.

[0076] The general-purpose launch control system bus signal simulation method includes steps S1 to S7.

[0077] S1 is used to obtain the physical connection topology, communication protocol type, message cycle characteristics, message priority allocation rules, and historical bus load data of all device nodes participating in communication in the target launch control system.

[0078] S2 is to construct an initial bus network abstract model based on the physical connection topology and communication protocol type;

[0079] S3 involves performing time-series segmentation and event trigger point labeling on the historical bus load data to extract message flow timing templates under typical working modes;

[0080] S4 generates a multi-device concurrent message scheduling sequence based on the message periodicity characteristics and message priority allocation rules;

[0081] S5 involves spatiotemporally aligning and fusing the message flow timing template with the multi-device concurrent message scheduling sequence to generate a high-fidelity bus signal behavior base.

[0082] S6 is to superimpose a physical layer interference signal generated by an external environment disturbance model on the basis of the high-fidelity bus signal behavior.

[0083] S7 is used to inject the superimposed composite signal into the bus physical layer of the general-purpose launch control system under test through the hardware-in-the-loop interface.

[0084] In step S1, the physical connection topology, communication protocol type, message cycle characteristics, message priority allocation rules, and historical bus load data of all communication-related device nodes in the target launch control system are acquired. This step is the data foundation for the entire simulation process, and its completeness and accuracy directly determine the fidelity of subsequent modeling and injection.

[0085] Specifically, the physical connection topology is obtained by traversing all valid node addresses on the controller area network bus using a bus scanning tool, recording the response latency and error frame reporting frequency of each node. Each node has a unique hardware address on the bus. The scanning process attempts communication handshakes sequentially at a preset baud rate, and nodes that successfully establish a connection are considered valid nodes. Response latency reflects the node's processing capability and link quality, while the error frame reporting frequency characterizes its stability under high load. Simultaneously, the configuration description files of each node are parsed to extract its supported communication baud rates, filter mask settings, receive buffer depths, and error status register mappings. These parameters constitute a complete profile of the node's communication capabilities.

[0086] Based on the above information, a bidirectional directed graph model is constructed, incorporating logical dependencies between nodes and physical link impedance characteristics, as a digital representation of the physical connection topology. Each vertex in the graph represents a device node, and each directed edge represents the message flow direction, along with physical attributes such as link length, terminal resistance value, and signal propagation delay. Communication protocol types include Controller Area Network 2.0B extended frame format, time-triggered Controller Area Network, or custom military bus protocols, with differences in arbitration mechanisms, frame structures, and error handling strategies. Message periodicity characteristics refer to the time pattern of message transmission by each node within a typical task cycle, categorized into periodic messages such as status heartbeats, event-triggered messages such as fault alarms, and mixed messages such as fire control commands. Message priority allocation rules define the arbitration order of messages during bus contention, typically determined by the numerical value of the message identifier. Historical bus load data is continuously collected for at least 72 hours using a high-sampling-rate logic analyzer, covering all operational stages including cold start, hot standby, weapon preparation, launch execution, and fault recovery, ensuring the representativeness and completeness of the dataset.

[0087] In step S2, an initial bus network abstract model is constructed based on the physical connection topology and communication protocol type. This model is a logical mirror of the real bus system, used to support subsequent scheduling and simulation. Specifically, this includes: assigning a unique logical identifier to each device node, which corresponds one-to-one with its hardware address in the real system, ensuring that simulated behavior is strictly bound to physical entities; and determining the encoding rules for the message arbitration field according to the communication protocol type.

[0088] For protocols employing identifier priority arbitration, message identifiers are mapped to binary priority codes, with the high-order bit being zero indicating high priority. The message transmission rate parameter is defined as the number of bits transmitted per second, ranging from 10 kilobits per second to 1 megabit per second. Each node can support multiple rate levels, but only one can be active at a time. The arbitration mechanism is modeled as a finite state machine, with states including idle, listening, sending, collision detection, and backoff. State transition conditions are determined by the current bus idle state, the priority of the node's pending messages, and the collision detection result. For example, when the bus is idle and a node has pending messages, it enters the listening state; if a higher-priority message is detected during listening, it immediately backs off; if it successfully wins arbitration, it enters the sending state. This finite state machine is embedded in the virtual communication engine of each node to ensure its behavior conforms to the protocol specifications.

[0089] In step S3, the historical bus load data is segmented into time series and event trigger points are marked to extract message flow timing templates under typical operating modes. This step aims to extract representative communication behavior patterns from massive amounts of raw data. Specifically, the continuously acquired raw bus data stream is sliced ​​using a preset time window length of 100 milliseconds with a step size of 50 milliseconds to ensure event integrity. Within each time window, the start and end edges of all complete data frames are identified, and the inter-frame interval is calculated. The start edge is determined by detecting dominant level transitions, and the end edge is identified by the frame tail delimiter.

[0090] When the inter-frame interval is less than a preset threshold (e.g., 200 microseconds), it is determined to be a continuous message within the same event trigger sequence because it logically belongs to the same operational atom. Each event trigger sequence is labeled with its corresponding system operation event type, which includes weapon unlocking, fire control calculation initiation, seeker activation, and launch command issuance. The labeling is based on operation logs or human-machine interaction command streams recorded synchronously. Finally, each event type corresponds to a message flow timing template. The template content includes a message identifier sequence, the relative sending time of each message, data frame length, the distribution pattern of the verification field, and the expected response behavior. The distribution pattern of the verification field refers to the statistical characteristics of the cyclic redundancy check value changing with the data content, used to verify the validity of the simulated message.

[0091] In step S4, a multi-device concurrent message scheduling sequence is generated based on the message periodicity characteristics and message priority allocation rules. This sequence is the core scheduling instruction of the simulated system, ensuring the consistency of multi-node behavior in time and logic. Specifically, this includes: establishing a scheduling engine based on a hybrid time-triggered and event-triggered approach. The time-triggered part runs at a fixed period (e.g., 1 millisecond) to process periodic messages; the event-triggered part responds to external instructions or internal state changes to process sudden messages. An independent message queue is configured for each device node, and the messages in the queue are ordered according to their generation logic in the real system, such as the generation of guidance instructions triggered after fire control calculation is completed.

[0092] Within each scheduling cycle of the scheduling engine, all messages to be sent are globally sorted according to message priority allocation rules. Priority comparison is first based on the message identifier value, with smaller values ​​taking precedence; if identifiers are the same, the data frame length is compared, with shorter frames taking precedence to reduce bus usage. If multiple messages have the same priority, they are arranged in ascending order according to the physical address of their respective device nodes to break symmetry. The sorted message sending time sequence is output as a multi-device concurrent message scheduling sequence. This sequence is accurate to the microsecond level, ensuring high-precision timing control.

[0093] In step S5, the message flow timing template and the multi-device concurrent message scheduling sequence are spatiotemporally aligned and fused to generate a high-fidelity bus signal behavior base. This step unifies logical behavior and scheduling instructions. Specifically, it includes: converting the relative time offset in the message flow timing template into an absolute timestamp, with the first message transmission time in the scheduling sequence as the time zero point; inserting placeholders in the scheduling sequence for message types missing in the template and marking them as optional messages, allowing them to be skipped when resources are scarce; for high-priority interruption messages (such as emergency stop-fire instructions) that exist in the template but are not included in the scheduling sequence, forcibly inserting them into the nearest bus idle gap, even if it causes a delay in low-priority messages; and generating a high-fidelity bus signal behavior base containing complete message content, precise transmission time, and expected response behavior. This base is stored in the form of an event list, with each event containing a timestamp, source node, target node, message identifier, data field, and checksum.

[0094] In step S6, a physical layer interference signal generated by the external environment disturbance model is superimposed on the high-fidelity bus signal behavior substrate. This step imparts realistic physical distortion characteristics to the simulated signal. The construction of the external environment disturbance model includes: acquiring the bus differential signal waveforms of the real transmission platform under different operating conditions, recording the differential voltage using an oscilloscope at a sampling rate of not less than 5 GHz, and extracting its rise time, fall time, overshoot amplitude, and eye diagram closure parameters. The frequency, duration, and amplitude distribution of voltage sag events are statistically analyzed to establish a voltage sag probability density function.

[0095] Based on transmission line theory, the signal reflection coefficient is calculated under different combinations of cable lengths and terminal matching resistors, generating a reflection waveform library. The induced noise spectrum on the bus during the start-up and shutdown of adjacent high-power devices is measured, constructing a time-frequency joint distribution model of common-mode noise and crosstalk components. The aforementioned interference components are weighted and superimposed according to their joint occurrence probability in a real environment to form a composite physical layer interference signal. The mathematical expression of the interference signal is as follows:

[0096] ;

[0097] in, , , , These are weighting coefficients, summing to 1, determined based on the co-occurrence probability of various interferences in the measured environment. (Clean bus signal) The final composite signal is generated by protocol encoding from a high-fidelity signal behavior substrate: ;

[0098] In step S7, the superimposed composite signal is injected into the bus physical layer of the general-purpose transmit control system under test through a hardware-in-the-loop interface. The hardware-in-the-loop interface includes a programmable logic device for real-time generation of differential signal levels conforming to the Controller Area Network (CAN) protocol specification; a high-precision digital-to-analog converter circuit with a resolution of at least 12 bits and an update rate of at least 10 MHz for converting digital interference signals into analog voltage waveforms; a differential signal synthesis unit for vector superimposing the clean bus signal and the analog interference signal, and outputting the result to the bus physical layer; and a real-time monitoring feedback loop for sampling the injected bus signal and comparing it with the expected waveform, dynamically adjusting the interference injection intensity to maintain analog fidelity. The feedback loop uses a mean square error criterion; when the error exceeds a threshold, it automatically reduces the interference amplitude or suspends injection to prevent damage to the device under test.

[0099] The general-purpose launch control system bus signal simulation system includes a bus topology and protocol parsing module, a bus network abstract modeling module, a message flow timing template extraction module, a concurrent message scheduling generation module, a high-fidelity signal substrate fusion module, a physical layer interference injection module, and a hardware-in-the-loop signal output module. The bus topology and protocol parsing module performs the function of step S1, including a bus node scanning unit, a protocol feature extraction unit, and a topology graph construction unit. The bus network abstract modeling module performs step S2, constructing an abstract model including node identifiers, arbitration mechanisms, and transmission parameters. The message flow timing template extraction module performs step S3, realizing event labeling and timing template generation. The concurrent message scheduling generation module performs step S4, outputting a globally consistent scheduling sequence. The high-fidelity signal substrate fusion module performs step S5, completing the fusion of logic and scheduling. The physical layer interference injection module performs step S6, including an interference feature database, an interference signal synthesis engine, and a real-time feedback adjustment unit. The hardware-in-the-loop signal output module performs step S7, realizing precise injection and closed-loop control of physical signals.

[0100] This embodiment achieves high-fidelity simulation of multi-device signal aliasing scenarios through the above-described method and system, solving the problem that traditional technologies cannot reproduce complex electromagnetic and logical interactions, and significantly improving the authenticity and effectiveness of the test.

Claims

1. A method for simulating bus signals in a general-purpose launch control system, characterized in that, include: Obtain the physical connection topology, communication protocol type, message cycle characteristics, message priority allocation rules, and historical bus load data of all device nodes participating in communication in the target launch control system; Based on the physical connection topology and communication protocol type, an initial bus network abstract model is constructed. The initial bus network abstract model includes the address identifier, message identifier set, transmission rate parameters and arbitration mechanism description of each device node. The historical bus load data is segmented into time series and event trigger points are marked to extract message flow timing templates under typical working modes. The message flow timing templates include message sending time, duration, data frame length and the distribution pattern of verification fields. Based on the message cycle characteristics and message priority allocation rules, a multi-device concurrent message scheduling sequence is generated. The multi-device concurrent message scheduling sequence ensures that within any time window, the message sending behavior of each device node conforms to its competition and arbitration logic in the real system. The message flow timing template and the multi-device concurrent message scheduling sequence are spatiotemporally aligned and fused to generate a high-fidelity bus signal behavior base. Based on the high-fidelity bus signal behavior substrate, a physical layer interference signal generated by an external environment disturbance model is superimposed. The physical layer interference signal includes voltage drop, signal reflection, common-mode noise and crosstalk components, and its amplitude, phase and duration are determined based on measured electromagnetic environment statistical data. The superimposed composite signal is injected into the bus physical layer of the general-purpose transmission control system under test through the hardware-in-the-loop interface to complete the closed-loop simulation of complex multi-device aliasing scenarios. Constructing an initial bus network abstract model includes: Each device node is assigned a unique logical identifier, which corresponds one-to-one with its hardware address in the real system; Based on the communication protocol type, determine the encoding rules for the message arbitration field. For protocols that use identifier priority arbitration, map the message identifier to a binary priority code. The message transmission rate parameter is defined as the number of bits transmitted per second, and its value range covers discrete levels from 10 kilobits per second to 1 megabit per second. The arbitration mechanism is modeled as a finite state machine, and its state transition conditions are jointly determined by the current bus idle state, the priority of the messages to be sent by the node, and the collision detection results.

2. The method for simulating bus signals of a universal transmission control system according to claim 1, characterized in that, Obtain the physical connection topology of all communication-related device nodes in the target launch control system, including: The bus scanning tool is used to traverse all valid node addresses on the controller local area network bus and record the response latency and error frame reporting frequency of each node. Parse the configuration description files of each node to extract its supported communication baud rates, filter mask settings, receive buffer depths, and error status register mappings; Based on the above information, a bidirectional directed graph model containing logical dependencies between nodes and physical link impedance characteristics is constructed as a digital representation of the physical connection topology.

3. The method for simulating bus signals of a universal transmission control system according to claim 2, characterized in that, The historical bus load data is segmented into time series and event trigger points are labeled, including: The continuously acquired raw bus data stream is sliced ​​using a preset time window of 100 milliseconds. Within each time window, identify the start and end edges of all complete data frames and calculate the inter-frame interval time. When the inter-frame interval is less than a preset threshold, it is determined to be a continuous message within the same event trigger sequence; Each event trigger sequence is labeled with its corresponding system operation event type, which includes weapon unlocking, fire control calculation start-up, seeker activation, and launch command issuance.

4. The method for simulating bus signals of a universal transmission control system according to claim 3, characterized in that, The generation of the multi-device concurrent message scheduling sequence includes: Establish a scheduling engine based on a hybrid time-triggered and event-triggered approach; Configure an independent message queue for each device node, and sort the messages in the queue according to their generation logic in the real system; Within each scheduling cycle of the scheduling engine, all pending messages are globally sorted according to the message priority allocation rules; If multiple messages have the same priority, they are sorted in ascending order by the physical address of the device node to which they belong; Output the sorted message sending time sequence as a multi-device concurrent message scheduling sequence.

5. The method for simulating bus signals of a universal transmit control system according to claim 4, characterized in that, The message flow timing template and the multi-device concurrent message scheduling sequence are spatiotemporally aligned and fused, including: Convert the relative time offset in the message flow timing template into an absolute timestamp, with the time of sending the first message in the scheduling sequence as the time zero point; For message types that are missing in the template, insert placeholders in the scheduling sequence and mark them as optional messages; For high-priority interrupt messages that exist in the template but are not included in the scheduling sequence, force them to be inserted into the nearest bus idle gap; Generate a high-fidelity bus signal behavior base containing complete message content, precise sending time, and expected response behavior.

6. The method for simulating bus signals of a universal transmit control system according to claim 5, characterized in that, The construction of the external environment disturbance model includes: Collect the bus differential signal waveforms of the real transmission platform under different operating conditions, and extract its rise time, fall time, overshoot amplitude and eye diagram closure parameters. The frequency, duration, and amplitude distribution of voltage dip events were statistically analyzed to establish a voltage dip probability density function. Based on transmission line theory, the signal reflection coefficient is calculated under different combinations of cable length and terminal matching resistor, and a reflection waveform library is generated. Measure the induced noise spectrum on the bus when adjacent high-power devices start and stop, and construct a time-frequency joint distribution model of common-mode noise and crosstalk components; The above interference components are weighted and superimposed according to their joint occurrence probability in the real environment to form a composite physical layer interference signal.

7. The method for simulating bus signals of a universal transmit control system according to claim 6, characterized in that, The hardware-in-the-loop interface includes: Programmable logic devices are used to generate differential signal levels that conform to the controller area network protocol specification in real time. A high-precision digital-to-analog converter circuit with a resolution of no less than 12 bits and an update rate of no less than 10 MHz is used to convert digital interference signals into analog voltage waveforms. The differential signal synthesis unit vector superimposes the clean bus signal and the analog interference signal and outputs them to the bus physical layer; The real-time monitoring feedback loop is used to sample the injected bus signal and compare it with the expected waveform, dynamically adjusting the interference injection intensity to maintain analog fidelity.

8. The method for simulating bus signals of a universal transmission control system according to claim 7, characterized in that, The message periodicity characteristics include periodic messages, event-triggered messages, and hybrid messages. The message priority allocation rule determines the arbitration order based on the numerical value of the message identifier.

9. The method for simulating bus signals of a universal transmit control system according to claim 8, characterized in that, The distribution pattern of the verification field refers to the statistical characteristics of the cyclic redundancy check value as the data content changes, which is used to verify the validity of the simulated message.

Images