Lightweight readout circuit for real-time data compression of large array spad
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV HANGZHOU RES INST
- Filing Date
- 2026-02-11
- Publication Date
- 2026-05-12
Smart Images
Figure CN121691956B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of digital image processing technology, specifically relating to a lightweight readout circuit for real-time data compression of large SPAD arrays. Background Technology
[0002] In high-resolution, high-frame-rate applications, the amount of data generated per second by large-scale SPAD (Single-Photon Avalanche Diode) arrays is excessive, even exceeding the bandwidth of data buses such as USB (Universal Serial Bus) and PCIe (Peripheral Component Interconnect Express) by an order of magnitude. To address this bottleneck, existing technologies employ wavelet transform to compress histogram data and supplement it with Gaussian filtering for noise reduction and smoothing. However, implementing wavelet transform and Gaussian filtering in traditional hardware has limitations: traditional wavelet transforms (such as multi-stage filter architectures) suffer from significant computational redundancy due to their inherent downsampling mechanism, and their serial structure is difficult to parallelize efficiently; simultaneously, traditional Gaussian filtering relies on computationally intensive two-dimensional convolution kernels, which consumes computational resources and increases processing latency, making it difficult to meet real-time processing requirements. Furthermore, under extreme conditions, such as extremely low signal-to-background ratio or low photon flux levels, SPAD detectors are highly susceptible to ambient light noise interference, making it difficult to distinguish between target signals and background light signals, thus hindering accurate reconstruction. Excessive compression can also lead to a significant increase in reconstruction errors. Summary of the Invention
[0003] To address the aforementioned problems in existing technologies, this invention provides a lightweight readout circuit for real-time data compression of large-array SPADs. At the hardware level, to address the computational redundancy of traditional wavelet transform, this invention employs convolution operations to replace redundant calculations in traditional wavelet transform, thereby improving computational efficiency. To address the massive computational cost of traditional Gaussian filtering, this invention uses a method of decoupling two one-dimensional vectors (i.e., separating the two-dimensional convolution), reducing the computational and memory access overhead caused by the two-dimensional convolution kernel. At the processing level, after performing wavelet transform on the SPAD histogram data, this invention first uses Gaussian filtering to smooth the transform coefficients, optimizing signal characteristics and suppressing noise, thus improving the effect after compression and reconstruction; then, a sliding window truncation unit is used to define the signal interval.
[0004] The technical problem to be solved by this invention is specifically achieved through the following technical solution:
[0005] This invention provides a lightweight readout circuit for real-time data compression of large SPAD arrays, comprising: a reconfigurable computation unit, a wavelet transform unit, a Gaussian filter unit, and a sliding window truncation unit.
[0006] The reconfigurable computing unit is a distributed arithmetic computing unit based on a lookup table, configured to serve the wavelet transform unit and the Gaussian filtering unit, and used to transform multiplication operations into lookup table lookups and pipelined accumulation operations.
[0007] The wavelet transform unit is used to receive the serial real-time data stream output by the SPAD array, convert the serial real-time data stream into a parallel continuous data stream, and perform wavelet decomposition calculation to extract low-frequency approximation coefficients.
[0008] The Gaussian filtering unit is connected after the wavelet transform unit and is used to perform Gaussian kernel convolution filtering on the low-frequency approximation coefficients.
[0009] The sliding window truncation unit, connected after the Gaussian filtering unit, is used to perform sliding window summation on the filtered data stream and extract peak features and their position indices as compressed output data.
[0010] In one embodiment of the present invention, the distributed arithmetic computation unit is a multi-path bit-by-bit lookup table computation unit, used to process multi-path parallel SPAD pixel data; the bit-by-bit lookup table computation unit includes a number of lookup tables corresponding to the bit width of the input data, a pipelined adder, and multiple bit computation units; wherein, each bit computation unit is configured to extract bits with the same weight from the multi-path parallel input data respectively, combine them to form a lookup address to query the lookup table; the lookup table pre-stores the coefficient part sum calculated based on the algorithm coefficients; after the query result is shifted according to the weight of the bit, it is accumulated by the pipelined adder to obtain the multiplication result.
[0011] In one embodiment of the present invention, by configuring the contents of the lookup table, the reconfigurable computing unit performs the multiplication operations required in the wavelet decomposition calculation and Gaussian kernel convolution filtering process, respectively.
[0012] In one embodiment of the present invention, the wavelet transform unit includes a data rearrangement module, a parallel processing pipeline, and an addition tree; wherein, the data rearrangement module is used to rearrange serial data into a parallel data stream; the parallel processing pipeline is composed of multiple cascaded reconfigurable computing units; and the addition tree is used to accumulate the output results of the parallel processing pipeline to obtain the low-frequency approximation coefficients.
[0013] In one embodiment of the present invention, the data rearrangement module is further configured to perform zero-padding between the input data of adjacent pixels to isolate the influence of adjacent pixels on the low-frequency approximation coefficient.
[0014] In one embodiment of the present invention, the Gaussian filtering unit includes a row buffer module, a column buffer module, a row transformation processing module, and a column transformation processing module. The row buffer module is used to cache multi-row coefficient data and provide parallel row sliding window data to the row transformation processing module. The column buffer module is used to cache multi-column intermediate results after row transformation and provide parallel column sliding window data to the column transformation processing module, thereby implementing Gaussian kernel convolution filtering in a separable convolution manner. Both the row transformation processing module and the column transformation processing module use the reconfigurable computing unit as their computing component.
[0015] In one embodiment of the present invention, the row buffer module is composed of multi-level registers for storing the low-frequency approximation coefficients and reorganizing them into the parallel row sliding window data to achieve one-dimensional convolution in the row direction; the column buffer module is composed of multi-level registers for storing the intermediate results after row transformation and reorganizing them into the parallel column sliding window data to achieve one-dimensional convolution in the column direction.
[0016] In one embodiment of the present invention, the sliding window interception unit includes a sliding window register chain, an adder tree, a comparator, and an index register; the sliding window register chain is used to cache continuous data; the adder tree is used to calculate the cumulative sum of the data within the sliding window in parallel; the comparator is used to compare and obtain the maximum value of the cumulative sum, and use it as the peak feature; the index register is used to record the position index corresponding to the peak feature.
[0017] In one embodiment of the present invention, the wavelet transform unit, the Gaussian filter unit, the sliding window truncation unit, and the reconfigurable computing unit all adopt a pipelined architecture and are integrated into a programmable gate array.
[0018] Compared with the prior art, the beneficial effects of the present invention are as follows:
[0019] This invention presents a lightweight readout circuit for real-time data compression of large-array SPADs. It integrates wavelet transform, Gaussian filtering, and sliding window truncation into a deeply parallel pipeline, enabling direct processing of high-speed real-time data streams from SPAD sensors. Compared to traditional serial or software-based processing methods, the circuit architecture of this invention matches hardware processing power with the sensor output rate, reducing integration complexity while achieving a systemic improvement in high throughput and low latency, thus meeting the real-time compression requirements of SPADs.
[0020] This invention employs a 4-way 8-bit lookup table as the core computational unit to replace the traditional high-overhead multiplier, thereby reducing logic resource consumption and shortening the critical path cycle in terms of hardware. Algorithmically, by adjusting the lookup table configuration, two different operations—wavelet transform and Gaussian filtering—can be executed flexibly and efficiently, achieving high efficiency and versatility of the computational core while maintaining accuracy.
[0021] The Gaussian filtering unit of this invention adopts an efficient data flow and feature compression mechanism. It performs two-level optimization for data flow. In intermediate processing, row buffering module and column buffering module are used to cache and reorganize wavelet coefficients into parallel sliding window data windows, providing seamless pipelined data for the Gaussian filtering unit. At the same time, the Gaussian filtering unit also uses a 4-way 8-bit lookup table as the core calculation unit, giving full play to the advantages of the 4-way 8-bit lookup table as a configurable, multiplier-free general-purpose calculation core.
[0022] In the final output, the present invention uses a sliding window truncation unit to efficiently locate the peak and index of the smoothed data, and extracts them as key signal features, thereby achieving high-rate effective compression.
[0023] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0024] Figure 1 This is a block diagram of a lightweight readout circuit for real-time data compression of large SPAD arrays provided in an embodiment of the present invention.
[0025] Figure 2 This is a flowchart illustrating the workflow of the 4-way 8-bit bit-by-bit lookup table provided in an embodiment of the present invention.
[0026] Figure 3 This is a flowchart illustrating the workflow of the wavelet transform unit provided in an embodiment of the present invention.
[0027] Figure 4 This is a flowchart illustrating the workflow of the Gaussian filter unit provided in an embodiment of the present invention.
[0028] Figure 5 This is a flowchart of the workflow of the sliding window capture unit provided in an embodiment of the present invention. Detailed Implementation
[0029] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description of the lightweight readout circuit for real-time data compression of large array SPADs, in conjunction with the accompanying drawings and specific embodiments, is provided.
[0030] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.
[0031] Example 1
[0032] like Figures 1 to 5 As shown, Figure 1 This is a block diagram of a lightweight readout circuit for real-time data compression of large SPAD arrays provided in an embodiment of the present invention. Figure 2 This is a flowchart illustrating the workflow of the 4-way 8-bit bit-by-bit lookup table provided in an embodiment of the present invention. Figure 3 This is a flowchart illustrating the workflow of the wavelet transform unit provided in an embodiment of the present invention. Figure 4 This is a flowchart illustrating the workflow of the Gaussian filter unit provided in an embodiment of the present invention. Figure 5 This is a flowchart illustrating the workflow of the sliding window truncation unit provided in this embodiment of the invention. In this embodiment, the lightweight readout circuit for real-time data compression of large-array SPADs includes: a reconfigurable computation unit, a wavelet transform unit, a Gaussian filtering unit, and a sliding window truncation unit. The readout circuit is designed for SPAD active imaging applications in extremely low light conditions, and realizes a complete hardware pipeline processing procedure for multi-level wavelet decomposition, Gaussian filtering, and sliding window truncation of the one-dimensional signal of the sensor's real-time readout data stream.
[0033] The reconfigurable computing unit, a lookup-table-based distributed arithmetic computing unit, is configured to serve the wavelet transform unit and the Gaussian filtering unit, transforming multiplication operations into lookup table lookups and pipelined accumulation operations. In practice, the reconfigurable computing unit processes each bit of the input data in parallel each clock cycle, looking up pre-calculated coefficients and accumulating them in a pipelined adder, thus efficiently completing the required multiplication operations without using traditional multipliers. The pre-calculated coefficients are algorithm coefficients based on wavelet transform and Gaussian filtering, obtained by summing the coefficients corresponding to all possible combinations of input bits beforehand and storing them in a lookup table.
[0034] In one optional implementation, the distributed arithmetic computation unit is a multi-path bit-by-bit lookup table computation unit used to process multi-path parallel SPAD pixel data. The bit-by-bit lookup table computation unit includes a number of lookup tables corresponding to the bit width of the input data, a pipelined adder, and multiple bit computation units. Each bit computation unit is configured to extract bits with the same weight from the multi-path parallel input data, combine them to form a lookup address, and then query the lookup table. The lookup table pre-stores the coefficients calculated based on the algorithm coefficients. After shifting the query result according to the weights of the bits, the pipelined adder accumulates the results to obtain the multiplication result.
[0035] Preferably, the reconfigurable computing unit is specifically implemented as a 4-way 8-bit lookup table computing unit, which serves as the core of wavelet transform and Gaussian filtering calculations, capable of performing a multiplication operation with 4 inputs and fixed-point coefficients. Its innovation lies in not employing traditional multiplier hardware, but rather a more efficient distributed algorithm architecture. This involves transforming the multiplication operation into a series of lookup table, shift, and accumulation operations, using a pre-calculated partial sum of filter coefficients, and then selecting the appropriate coefficients through a lookup table to achieve high-speed processing.
[0036] The wavelet transform unit receives the serial real-time data stream output from the SPAD array, transforms it into a parallel continuous data stream, and performs wavelet decomposition calculations to extract low-frequency approximation coefficients. Specifically, the wavelet transform unit first acts as a data rearrangement unit, transforming the serial data block processing task into a parallel continuous data stream, improving the parallelism of the hardware system. Simultaneously, it performs zero-padding between input data of two pixels to ensure that the output of the wavelet transform is not affected by adjacent pixels. It then provides data to the wavelet transform computation unit to perform the core wavelet multiplication and addition operations, realizing multi-level decomposition and feature compression of the SPAD time-series histogram data.
[0037] The Gaussian filtering unit is connected after the wavelet transform unit and is used to perform Gaussian kernel convolution filtering on the low-frequency approximation coefficients. Specifically, the Gaussian filtering unit includes a row buffer module and a column buffer module. In Gaussian filtering, a large amount of pixel data is stored through the row buffer module and the column buffer module to provide parallel data input to the computation unit in each clock cycle. This allows for the parallel and pipelined implementation of multiple multiply-add terms in the Gaussian kernel convolution operation, completing feature smoothing and feature enhancement without introducing a data processing bottleneck.
[0038] The sliding window truncation unit, connected after the Gaussian filtering unit, is used to perform sliding window summation on the filtered data stream, and extract the peak feature and its position index as the compressed output data. Specifically, the sliding window truncation unit sums multiple pixel data according to channels, finds the peak and its index, and uses the multiple pixel data and its index as the final output of the compressed pixel point represented by this window, thus achieving efficient compression.
[0039] In an optional implementation, the reconfigurable computing unit is specifically a 4-way 8-bit bit-by-bit lookup table computing unit. This unit uses the principle of distributed algorithm to convert complex multiplication operations into efficient lookup table operations. Specifically, the lookup table pre-stores the pre-computed coefficient partial sums, that is, according to the distributed algorithm, the results obtained by linearly accumulating the filter coefficients for all possible combinations of input bit positions. By configuring different lookup table contents, the reconfigurable computing unit can perform the operations required in wavelet decomposition calculation and Gaussian kernel convolution filtering processing respectively, so as to achieve high parallelism and efficient processing of data. This unit internally contains i (for example, i = 8) parallel bit computing units, and the number of i corresponds to the bit width of the input data; each bit computing unit is used to extract the bits with the same weight from the multiple input data as the address, and through parallel query of the lookup table, all bit computing units can perform parallel calculations.
[0040] As Figure 2 shown, the circuit of this embodiment completes the core operation through a 4-way bit-by-bit lookup table. For the i-th bit computing unit, its input is composed of the i-th bit combinations of 4-way parallel data (x0, x1, x2, x3). This combined address (composed of the bits of x and the coefficient selection signal y, and coeff is the pre-computed coefficient partial sum output by the lookup table) is used to query a pre-computed lookup table (LUT), which stores all possible coefficient sums. Further, the lookup table output of each bit computing unit, after a shift operation (<<i) corresponding to its bit weight, is sent to a pipelined adder composed of multiple levels of adders and registers. The pipelined adder is used to accumulate all parallel bit contribution values to finally obtain the complete multiply-accumulate operation result.
[0041] The Gaussian filtering unit in this embodiment is serially connected after the wavelet transform unit and is used to further smooth and enhance features of the wavelet coefficients. In this embodiment, the Gaussian filtering unit is a separable two-dimensional convolution architecture, which serially cascades two core processing modules, a row buffer module and a column buffer module, in hardware. Its function is to cache multiple rows of coefficient data from the wavelet transform unit, so as to provide a parallel two-dimensional sliding window data window for the subsequent row transformation processing module in each clock cycle to achieve high-speed pipelined parallel calculation.
[0042] As Figure 3As shown, in this embodiment, the input data is first rearranged by a wavelet transform unit, combining the original data stream (Data, D) with zero-padding data used for filter boundary processing. The combined data is then reshaped into an 8-channel parallel output data stream, which serves as the input to the parallel processing pipeline. Further, the 8-channel parallel data stream is fed into the wavelet transform unit, which contains two parallel processing pipelines. Each pipeline consists of four serially cascaded 4-way bit-by-bit lookup table modules. The 4-way 8-bit lookup tables perform the multiplication operations required by the wavelet filter. Finally, the outputs of the two parallel pipelines are fed into an addition tree. This addition tree, implemented using multi-stage adders and registers, is used to pipeline the sum of all parallel parts to calculate the final result.
[0043] In one optional implementation, the wavelet transform unit includes a data rearrangement module, a parallel processing pipeline, and an addition tree; wherein, the data rearrangement module is used to rearrange serial data into a parallel data stream; the parallel processing pipeline consists of multiple cascaded reconfigurable computing units; and the addition tree is used to accumulate the output of the parallel processing pipeline to obtain low-frequency approximation coefficients. For example, the data rearrangement module is also used to perform zero-padding between the input data of adjacent pixels to isolate the influence of adjacent pixels on the low-frequency approximation coefficients.
[0044] like Figure 4 As shown, the Gaussian filtering unit includes a row buffer module, a column buffer module, a row transformation processing module, and a column transformation processing module. The row buffer module is used to cache multi-row coefficient data and provide parallel row sliding window data to the row transformation processing module. The column buffer module is used to cache multi-column intermediate results after row transformation and provide parallel column sliding window data to the column transformation processing module. Gaussian kernel convolution filtering is implemented in a separable convolution manner.
[0045] Both the row transformation processing module and the column transformation processing module are implemented using reconfigurable computing units as computing components. Specifically, the computing module, which consists of a Gaussian filter unit composed of a 4-way 8-bit lookup table, performs row and column transformations on the data respectively. The Gaussian filter is formed by these two transformations, which is equivalent to splitting the filter kernel into two one-dimensional vectors, which are used to perform row and column transformations respectively. The two constitute a complete Gaussian filter. The operation circuits perform multiplication operations, which results in a low resource consumption on the FPGA (Field-Programmable Gate Array), making the circuit of this embodiment very suitable for deployment on an FPGA.
[0046] For example, both the row buffer module and the column buffer module consist of multi-level registers. The row buffer module stores low-frequency approximation coefficients and reassembles them into parallel row sliding window data to achieve one-dimensional convolution in the row direction. The column buffer module stores intermediate results after row transformation and reassembles them into parallel column sliding window data to achieve one-dimensional convolution in the column direction. Specifically, the Gaussian filter unit buffers the coefficient data stream output after the wavelet transform unit and provides a parallel two-dimensional sliding window data window for the subsequent row transform processing module. The wavelet transform result enters the row buffer module in a pipelined manner. This module buffers one or more rows of coefficients, and when a new row of data enters, it can output the current data point and its corresponding neighboring coefficients in the previous row in parallel in each clock cycle. The Gaussian filter kernel consists of filter coefficients. The parallel sliding window data window and the Gaussian kernel coefficients are multiplied and added, and the result also enters the column buffer module in a pipelined manner, performing the same operation as the row buffer.
[0047] The principle behind this is that the row transform processing module contains three parallel processing pipelines, each with a core of a 4-way 8-bit lookup table. The lookup table computation unit consists of 4 lookup tables and pipelined adders. This architecture efficiently performs Gaussian kernel convolution operations without using traditional multipliers. These lookup tables store the coefficients of the Gaussian kernel, and their data type is managed by external control signals (signed and unsigned). Specifically, when processing wavelet transforms involving negative coefficients, this unit uses two's complement logic to extend and accumulate the sign bits of the lookup table outputs to ensure the algebraic correctness of the results; while processing unsigned SPAD raw data, conventional logic operations are performed.
[0048] Furthermore, the column transformation processing module receives the processing results from the row transformation processing module and performs convolution operations in the column direction. The hardware architecture of the column transformation processing module is similar to that of the row transformation processing module, also containing multiple parallel processing units consisting of 4-way bit-by-bit lookup tables and pipelined adders. These output results are then subjected to specific shift operations (such as <<8 and <<16, used for weight adjustment or bit width alignment) before being finally summed by adders.
[0049] Furthermore, in the row transformation processing module, the outputs of the three parallel processing pipelines are combined through an adder tree; the outputs of two pipelines are added directly, while the output of the third pipeline undergoes a specific shift operation (such as <<8) before merging to achieve weighted summation. These partial sums are then fed into a final adder to complete the final accumulation of the row transformation.
[0050] Next, the column transformation processing module receives the output data stream from the row transformation processing module and performs convolution operations in the column direction. The hardware architecture of the column transformation processing module is similar to that of the row transformation processing module, also containing three parallel processing pipelines, each consisting of a 4-way bit-by-bit lookup table and a 4-way 24-bit multiply-accumulate unit. The weighted summation of its outputs employs different shift operations and is aggregated in the final adder to output the result of the entire Gaussian filtering unit. This embodiment utilizes this separable parallel pipeline architecture to efficiently decompose the two-dimensional Gaussian convolution into two one-dimensional convolutions, significantly improving the system's real-time filtering performance.
[0051] In this example, the sliding window truncation unit achieves final data compression and feature (peak) localization by performing efficient sliding window processing on the data stream processed by the Gaussian filter unit.
[0052] like Figure 5 As shown, the sliding window cropping unit, as the final data processing module, performs sliding window accumulation on the data within a pixel as the Gaussian filtering result is written. The result is obtained by calculating the sum of continuous data, and the accumulated sum corresponding to the peak value is used as the compressed data of this pixel. At the same time, the index position is marked, providing a basis for subsequent image restoration and reconstruction.
[0053] In one optional implementation, the sliding window interception unit includes a sliding window register chain, an adder tree, a comparator, and an index register; the sliding window register chain is used to cache continuous data; the adder tree is used to calculate the cumulative sum of the data within the sliding window in parallel; the comparator is used to compare and obtain the maximum value of the cumulative sum, and use it as the peak feature; the index register is used to record the position index corresponding to the peak feature.
[0054] The sliding window extraction unit in this embodiment completes its core computation by processing the data within the sliding window in parallel. For each clock cycle (corresponding to a new sliding window position), the sliding window register group outputs multiple coefficient values within the window in parallel. These parallel coefficient values are fed into an adder tree, which is implemented by multiple stages of adders and comparison logic, forming a pipeline structure for feature extraction. This pipeline structure is used to calculate the accumulation of coefficients within the window and determine the maximum peak value and its corresponding index, ultimately efficiently obtaining compressed data representing that pixel.
[0055] In an optional implementation, the wavelet transform unit, Gaussian filter unit, sliding window truncation unit, and reconfigurable computation unit all adopt a pipelined architecture and are integrated into a programmable gate array.
[0056] It is worth noting that this invention employs a 4-way 8-bit lookup table as the core computational unit to replace the traditional high-overhead multiplier. In terms of hardware, this reduces logic resource consumption, particularly avoiding the occupation of expensive and limited DSP Slice (Digital Signal Processing Slice) resources in the FPGA, and shortening the critical path cycle. Algorithmically, by adjusting the lookup table configuration, wavelet transform and Gaussian filtering can be executed flexibly and efficiently, achieving high efficiency and versatility of the computational core while maintaining accuracy. The Gaussian filtering unit employs an efficient data flow and feature compression mechanism, with two-level optimization for data flow. In intermediate processing, row and column buffer modules are used to cache and reassemble wavelet coefficients into parallel sliding window data windows, providing seamless pipelined data for the Gaussian filtering unit. Simultaneously, the Gaussian filtering unit also uses a 4-way 8-bit lookup table as its core computational unit, fully leveraging the advantages of the 4-way 8-bit lookup table as a configurable, multiplier-free, general-purpose computational core. Furthermore, in the final output, the present invention employs a sliding window truncation unit to efficiently locate the peaks and indices of the smoothed data, extracting them as key signal features, thereby achieving high-rate effective compression.
[0057] Please refer to Table 1, which shows a performance comparison between this embodiment and existing solutions. This invention, based on FPGA (Xilinx XCZU9EG) hardware implementation, demonstrates real-time processing advantages: throughput reaches 2.52 GB / s, far exceeding the 0.23 GB / s achieved by a CPU (Central Processing Unit); processing latency is reduced to 29.11 ms, a significant reduction compared to the CPU's 316.79 ms; and the effective processing frame rate is increased to 34.34 fps, far exceeding the CPU's 3.16 fps. Simultaneously, this invention achieves higher bit compression ratio and lower power consumption. These performance data fully demonstrate the superiority of the FPGA parallel pipeline architecture and 4-way 8-bit lookup table used in this invention for real-time SPAD data compression applications.
[0058] Table 1 Performance Comparison of This Embodiment and Existing Solutions
[0059]
[0060] It is worth noting that this invention proposes a lightweight readout circuit for real-time data compression of large-array SPADs based on FPGA. It employs a pipelined architecture, cascading wavelet transform, Gaussian filtering, and sliding window truncation units. The core computation unit consists of a 4-way 8-bit lookup table, used to efficiently perform the core multiplication operations in the wavelet decomposition and Gaussian filtering processes. The wavelet transform unit utilizes the parallel pipeline of this computational circuit to perform real-time decomposition and compression of the input data; the Gaussian filtering unit adopts a separable convolutional architecture and uses row / column buffer modules in conjunction with the 4-way 8-bit lookup table to smooth the wavelet decomposition results; finally, the sliding window truncation unit locates and extracts peak features on the filtered data stream. Compared to other hardware systems, this embodiment upgrades the traditional serial or software processing architecture to a high-efficiency parallel hardware architecture capable of matching the real-time data rate of the sensor by deploying the complete processing flow in an FPGA pipeline. At the algorithm level, distributed algorithms and separable convolutions are used to optimize computation; at the hardware level, the 4-way 8-bit lookup table improves resource utilization and computational efficiency. This design reduces end-to-end processing latency and hardware complexity, achieving high-throughput, low-power real-time compression processing of SPAD data while ensuring compression quality.
[0061] This invention presents a lightweight readout circuit for real-time data compression of large-array SPADs. It integrates wavelet transform, Gaussian filtering, and sliding window truncation into a deeply parallel pipeline, enabling direct processing of high-speed real-time data streams from SPAD sensors. Compared to traditional serial or software-based processing methods, the circuit architecture of this invention matches hardware processing power with the sensor output rate, reducing integration complexity while achieving a systemic improvement in high throughput and low latency, thus meeting the real-time compression requirements of SPADs.
[0062] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.
Claims
1. A lightweight readout circuit for real-time data compression of large SPAD arrays, characterized in that, include: Reconfigurable computation unit, wavelet transform unit, Gaussian filter unit, and sliding window truncation unit; The reconfigurable computing unit is a distributed arithmetic computing unit based on a lookup table, configured to serve the wavelet transform unit and the Gaussian filtering unit, and used to transform multiplication operations into lookup table lookups and pipelined accumulation operations. The wavelet transform unit is used to receive the serial real-time data stream output by the SPAD array, convert the serial real-time data stream into a parallel continuous data stream, and perform wavelet decomposition calculation to extract low-frequency approximation coefficients. The Gaussian filtering unit is connected after the wavelet transform unit and is used to perform Gaussian kernel convolution filtering on the low-frequency approximation coefficients. The sliding window truncation unit is connected after the Gaussian filtering unit. It is used to perform sliding window summation on the filtered data stream and extract peak features and their position indices as compressed output data. The distributed arithmetic computation unit is a multi-path bit-by-bit lookup table computation unit used to process multi-path parallel SPAD pixel data; the bit-by-bit lookup table computation unit includes a number of lookup tables corresponding to the bit width of the input data, a pipelined adder, and multiple bit computation units; Each bit calculation unit is configured to extract bits with the same weight from multiple parallel input data, combine them to form a lookup address to query the lookup table; the lookup table pre-stores the coefficients calculated by the algorithm based on wavelet transform and Gaussian filtering. The query result is shifted according to the weight of the bits, and then accumulated by the pipeline adder to obtain the multiplication result.
2. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 1, characterized in that, By configuring the contents of the lookup table, the reconfigurable computing unit can perform the multiplication operations required in the wavelet decomposition calculation and Gaussian kernel convolution filtering process, respectively.
3. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 1, characterized in that, The wavelet transform unit includes a data rearrangement module, a parallel processing pipeline, and an addition tree; wherein, the data rearrangement module is used to rearrange serial data into a parallel data stream; the parallel processing pipeline is composed of multiple cascaded reconfigurable computing units; and the addition tree is used to accumulate the output results of the parallel processing pipeline to obtain the low-frequency approximation coefficients.
4. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 3, characterized in that, The data rearrangement module is also used to perform zero-padding between the input data of adjacent pixels to isolate the influence of adjacent pixels on the low-frequency approximation coefficient.
5. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 1, characterized in that, The Gaussian filtering unit includes a row buffer module, a column buffer module, a row transformation processing module, and a column transformation processing module. The row buffer module is used to cache multi-row coefficient data and provide parallel row sliding window data to the row transformation processing module. The column buffer module is used to cache multi-column intermediate results after row transformation and provide parallel column sliding window data to the column transformation processing module, thereby realizing Gaussian kernel convolution filtering in a separable convolution manner. Both the row transformation processing module and the column transformation processing module use the reconfigurable computing unit as their computing component.
6. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 5, characterized in that, The row buffer module consists of multi-level registers, used to store the low-frequency approximation coefficients and reassemble them into the parallel row sliding window data to achieve one-dimensional convolution in the row direction; The column buffer module consists of multi-level registers, used to store the intermediate results after row transformation and reassemble them into the parallel column sliding window data to achieve one-dimensional convolution in the column direction.
7. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 1, characterized in that, The sliding window truncation unit includes a sliding window register chain, an adder tree, a comparator, and an index register; the sliding window register chain is used to cache continuous data; the adder tree is used to calculate the cumulative sum of the data within the sliding window in parallel; the comparator is used to compare and obtain the maximum value of the cumulative sum, and use it as the peak feature; The index register is used to record the position index corresponding to the peak feature.
8. The lightweight readout circuit for real-time data compression of large-array SPADs according to claim 1, characterized in that, The wavelet transform unit, the Gaussian filter unit, the sliding window truncation unit, and the reconfigurable computing unit all adopt a pipelined architecture and are integrated into a programmable gate array.