Field effect transistor and method for manufacturing a field effect transistor

Abstract

This application belongs to the field of semiconductor devices, specifically relating to a field-effect transistor (FET) and a method for fabricating the FET. The FET includes an N+ type substrate, an N- type drift region, a P- type base region, a gate oxide layer, a split gate module, an interlayer dielectric layer, a source, and a drain. The N-type drift region is formed on one side of the N+ type substrate, and the P-type base region is formed on the side of the N-type drift region away from the N+ type substrate. At least two gate trenches are formed on the P-type base region, and two split gate units are disposed in each gate trench. At least one split gate unit is a control gate. The gate oxide layer fills the gate trench and surrounds the split gate unit. The source is formed on the side of the P-type base region away from the N+ type substrate. The interlayer dielectric layer is formed between the gate oxide layer and the source. The drain is formed on the side of the N+ type substrate away from the N-type drift region. Multiple split gate units can form multiple combinations of 1 to 4 control gates and 0 to 3 shield gates. The parasitic capacitances Cgd and Cgs of different combinations are different.

Description

Technical Field

[0001] This application belongs to the field of semiconductor devices, specifically relating to a field-effect transistor and a method for manufacturing a field-effect transistor. Background Technology

[0002] Power semiconductor devices, including silicon carbide (SiC) field-effect transistors, are particularly suitable for high-voltage power conversion systems that require high-frequency operation, high efficiency, and high reliability, including but not limited to key power electronic devices such as electric drive systems for new energy vehicles, on-board chargers, DC-DC converters, industrial motor drives, rail transit traction, renewable energy power generation, and smart grids.

[0003] A field-effect transistor (FET) consists of a gate, a source, and a drain. There is a parasitic capacitance Cgs between the gate and source, and a parasitic capacitance Cgd between the gate and drain. Reducing the parasitic capacitance Cgd between the gate and drain can improve the switching speed of the FET, but at the cost of gate control capability. Increasing the parasitic capacitance Cgs between the gate and source can enhance noise immunity, but at the cost of reduced switching speed and increased drive losses.

[0004] In the prior art, the parasitic capacitance Cgd between the gate and drain of the field-effect transistor and the parasitic capacitance Cgs between the gate and source are fixed, resulting in rigid switching characteristics and making it impossible to achieve dynamic performance optimization in different application scenarios. Summary of the Invention

[0005] The purpose of this application is to provide a field-effect transistor and a method for manufacturing a field-effect transistor, which enables active control of parasitic capacitance and can achieve dynamic performance optimization in different application scenarios.

[0006] To achieve the above objectives, this application provides a field-effect transistor, comprising:

[0007] N+ type substrate;

[0008] An N-type drift region is formed on one side of the N+ type substrate;

[0009] A P-type base region is formed on the side of the N-type drift region away from the N+ type substrate, and at least two gate trenches are formed on the P-type base region, the gate trenches extending to the N-type drift region;

[0010] A split gate module includes multiple split gate units, with two split gate units disposed in each gate trench. The split gate units in each gate trench overlap and are spaced apart. At least one split gate unit in the split gate module is a control gate.

[0011] A gate oxide layer fills the gate trench and surrounds the split gate cell;

[0012] The source electrode is formed on the side of the P-type base region away from the N+ type substrate.

[0013] An interlayer dielectric layer is formed between the gate oxide layer and the source electrode;

[0014] The drain is formed on the side of the N+ type substrate away from the N- type drift region.

[0015] Optionally, the field-effect transistor further includes an N+ type buffer layer, an N- type carrier storage layer, an N+ type source region, and a P+ type contact region. The N+ type buffer layer is formed between the N+ type substrate and the N- type drift region. The N- type carrier storage layer is formed between the N- type drift region and the P- type base region. The N+ type source region is formed on the side of the P-type base region away from the N+ type substrate. The N+ type source region is disposed in a one-to-one correspondence with the gate trench. The gate trench extends through the N+ type source region to the N-type drift region. The P+ type contact region is formed on the side of the P-type base region away from the N+ type substrate and is located between two adjacent N+ type source regions. The source is connected to the P+ type contact region and the N+ type source regions on both sides of the P+ type contact region.

[0016] Optionally, the split gate module includes four split gate units, and the spacing between the split gate unit closest to the source and the N+ type substrate is smaller than the spacing between the P type base region and the N+ type substrate.

[0017] Optionally, one of the two split gate units closest to the source electrode is the control gate, and the other three split gate units are shielding gates.

[0018] Optionally, the split gate module includes two control gates and two shielding gates, wherein at least one of the two split gate units closest to the source is the control gate.

[0019] Optionally, both of the split gate units near the source side are the control gates, or both of the split gate units in one of the gate trenches are the control gates, or the split gate unit near the source side in one of the gate trenches is the control gate and the split gate unit away from the source side in the other gate trench is the control gate.

[0020] Optionally, the split gate module includes three control gates and one shielding gate, with one of the two split gate units closest to the source being the shielding gate, and the remaining split gate units being control gates.

[0021] Optionally, the split gate module includes three control gates and one shielding gate, with one of the two split gate units on the side away from the source being the shielding gate, and the remaining split gate units being control gates.

[0022] Optionally, all four split gate units are control gates.

[0023] This application also provides a method for fabricating a field-effect transistor, comprising:

[0024] An N-type drift region is formed on an N+ type substrate;

[0025] A P-type base region is formed on the side of the N-type drift region away from the N+ type substrate;

[0026] The P-type base region and the N-type drift region are etched to form two gate trenches extending to the N-type drift region, and the two gate trenches are spaced apart.

[0027] Two spaced and overlapping split gate units are formed in each gate trench, and a gate oxide layer is filled in the gate trench and covers the split gate units;

[0028] An interlayer dielectric layer is formed on the side of the gate oxide layer away from the N+ type substrate, and the interlayer dielectric layer at least covers the gate oxide layer;

[0029] A source electrode is formed in the P-type base region and on the side of the gate oxide layer away from the N+ type substrate;

[0030] A drain electrode is formed on the side of the N+ type substrate away from the N- type drift region.

[0031] The field-effect transistor and its fabrication method disclosed in this application have the following advantages:

[0032] In this application, the field-effect transistor includes an N+ type substrate, an N- type drift region, a P- type base region, a gate oxide layer, a split gate module, an interlayer dielectric layer, a source, and a drain. The N- type drift region is formed on one side of the N+ type substrate, and the P- type base region is formed on the side of the N- type drift region away from the N+ type substrate. At least two gate trenches are formed on the P-type base region, and two split gate units are disposed in each gate trench. At least one split gate unit is a control gate. The gate oxide layer fills the gate trench and surrounds the split gate unit. The source is formed on the side of the P-type base region away from the N+ type substrate. The interlayer dielectric layer is formed between the gate oxide layer and the source. The drain is formed on the side of the N+ type substrate away from the N- type drift region. Multiple split gate units can form at least 1 to 4 control gates and 0 to 3 shield gates in multiple combinations. The parasitic capacitances Cgd and Cgs of different combinations are different. By actively controlling the parasitic capacitances, dynamic performance optimization can be achieved in different application scenarios, that is, selecting appropriate switching speed, drive loss and anti-interference performance at the device level.

[0033] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0036] Figure 1 This is a schematic diagram of the structure of a field-effect transistor in an embodiment of this application.

[0037] Figure 2 This is a schematic diagram of the dual-control gate and dual-channel arrangement of the transistor in the embodiments of this application.

[0038] Figure 3 This is a schematic diagram of the transistor with dual control gates and single-channel off-site arrangement in an embodiment of this application.

[0039] Figure 4 This is a schematic diagram of the transistor with dual control gates and single-channel off-site arrangement in an embodiment of this application.

[0040] Figure 5 This is a schematic diagram of a transistor with a three-control gate and dual-channel arrangement in an embodiment of this application.

[0041] Figure 6 This is a schematic diagram of a transistor with a three-control gate and single-channel arrangement in an embodiment of this application.

[0042] Figure 7 This is a schematic diagram of a transistor with a four-control gate and dual-channel arrangement in an embodiment of this application.

[0043] Figure 8 This is a schematic flowchart of the manufacturing method of the field-effect transistor in the embodiments of this application.

[0044] Explanation of reference numerals in the attached figures:

[0045] 110, N+ type substrate; 120, N+ type buffer layer; 130, N- type drift region; 140, N- type carrier storage layer; 150, P-type base region; 161, N+ type source region; 162, P+ type contact region; 101, gate trench;

[0046] 210 Gate oxide layer; 220 Split gate module; 221 Control gate; 222 Shielding gate; 300 Interlayer dielectric layer; 410 Source; 420 Drain. Detailed Implementation

[0047] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0048] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0049] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0050] See Figure 1As shown, in this embodiment, the field-effect transistor includes an N+ type substrate 110, an N-type drift region 130 (N-Drift), a P-type base region 150 (P-Well), a gate oxide layer 210, a split gate module 220, an interlayer dielectric layer 300, a source 410, and a drain 420. The N-type drift region 130 is formed on one side of the N+ type substrate 110, and the P-type base region 150 is formed on the side of the N-type drift region 130 away from the N+ type substrate 110. At least two gate trenches 101 are formed on the P-type base region 150, and the gate trenches 101 extend into the N-type drift region 130. It should be noted that the gate trenches 101 extend into the N-type drift region 130, that is, in the vertical direction perpendicular to the N+ type substrate 110, the bottom surface of the gate trenches 101 is located between the top and bottom surfaces of the N-type drift region 130.

[0051] The split-gate module 220 includes multiple split-gate units, which are respectively disposed in multiple gate trenches 101. Two split-gate units are disposed in each gate trench 101, and the two split-gate units in each gate trench 101 overlap and are spaced apart. At least one split-gate unit in the split-gate module 220 is a control gate 221. If the split-gate module 220 includes 1 to 3 control gates 221, the remaining split-gate units are shield gates 222. The control gate 221 is used to apply a gate control signal to form a conductive channel. The shield gate 222 is connected to the source 410, and serves to reduce parasitic capacitance Cgd, optimize electric field distribution, suppress dv / dt mis-conduction, reduce drive current and drive loss, and improve switching efficiency.

[0052] The gate oxide layer 210 fills the gate trench 101 and surrounds the split gate cell. That is, the gate oxide layer 210 completely fills the gate trench 101, the split gate cell is buried in the gate oxide layer 210, and the gate oxide layer 210 is present between two overlapping split gate cells, and between the split gate cell and the inner wall of the gate trench 101. The source 410 is formed on the side of the P-type base region 150 away from the N+ type substrate 110, the interlayer dielectric layer 300 is formed between the gate oxide layer 210 and the source 410, and the drain 420 is formed on the side of the N+ type substrate 110 away from the N- type drift region 130.

[0053] In the prior art, the parasitic capacitance Cgd between the gate and drain of the field-effect transistor and the parasitic capacitance Cgs between the gate and source are fixed, resulting in rigid switching characteristics and making it impossible to achieve dynamic performance optimization in different application scenarios.

[0054] In this embodiment, the field-effect transistor includes an N+ type substrate 110, an N- type drift region 130, a P- type base region 150, a gate oxide layer 210, a split gate module 220, an interlayer dielectric layer 300, a source 410, and a drain 420. The N-type drift region 130 is formed on one side of the N+ type substrate 110, and the P-type base region 150 is formed on the side of the N-type drift region 130 away from the N+ type substrate 110. At least two gate trenches 101 are formed on the P-type base region 150. Two split gate units are disposed in each gate trench 101. At least one split gate unit in the split gate module 220 is a control gate 221. The gate oxide layer 210 fills the gate trench 101 and surrounds the split gate unit. The source 410 is formed on the side of the P-type base region 150 away from the N+ type substrate 110. The interlayer dielectric layer 300 is formed between the gate oxide layer 210 and the source 410. The drain 420 is formed on the side of the N+ type substrate 110 away from the N-type drift region 130. Multiple split gate units can form at least 1 to 4 combinations of control gates 221 and 0 to 3 shield gates 222. The parasitic capacitances Cgd and Cgs of different combinations are different. By actively controlling the parasitic capacitances, dynamic performance optimization can be achieved in different application scenarios, that is, selecting appropriate switching speed, drive loss and anti-interference performance at the device level.

[0055] In some embodiments, the field-effect transistor further includes an N+ type buffer layer 120 (N+Buffer), an N-type carrier storage layer 140 (N CSL), an N+ type source region 161, and a P+ type contact region 162. The N+ type buffer layer 120 is formed between the N+ type substrate 110 and the N-type drift region 130, and the N-type carrier storage layer 140 is formed between the N-type drift region 130 and the P-type base region 150. The N+ type source region 161 is formed on the side of the P-type base region 150 away from the N+ type substrate 110, and the N+ type source region 161 is correspondingly disposed with the gate trench 101, which extends through the N+ type source region 161 to the N-type drift region 130. P+ type contact region 162 is formed on the side of P-type base region 150 away from N+ type substrate 110 and is located between two adjacent N+ type source regions 161. Source 410 is connected to P+ type contact region 162 and N+ type source regions 161 on both sides of P+ type contact region 162.

[0056] An N+ type buffer layer 120 is formed between the N+ type substrate 110 and the N- type drift region 130. The N+ type buffer layer 120 can reduce the on-resistance of the device, increase the breakdown voltage of the device, suppress defects in subsequent epitaxial film formation, and improve device reliability. An N-type carrier storage layer 140 is formed between the N-type drift region 130 and the P-type base region 150. The N-type carrier storage layer 140 can optimize the electric field, increase the breakdown voltage of the device, and reduce the on-resistance of the device. The N+ type source region 161 provides a low-resistance electron channel, reducing the contact resistance of the source 410; the P+ type contact region 162 provides a low-resistance contact for the P-type base region 150, ensuring the potential stability of the P-type base region 150 and improving device reliability.

[0057] In some embodiments, the split gate module 220 includes four split gate units. Two gate trenches 101 are formed on the P-type base region 150, and two split gate units are disposed in each gate trench 101. The spacing between the split gate unit near the source 410 and the N+ type substrate 110 is smaller than the spacing between the P-type base region 150 and the N+ type substrate 110; the spacing between the split gate unit near the source 410 and the interlayer dielectric layer 300 is smaller than the spacing between the P-type base region 150 and the N+ type substrate 110. That is, the upper surface of the upper split gate unit is higher than the P-type base region 150 and the lower surface is lower than the P-type base region 150. The distance between the surface of the split gate unit near the source 410 and the N+ type substrate 110 is greater than the distance between the N-type carrier storage layer 140 and the N+ type substrate 110. That is, the upper surface of the lower split gate unit is higher than the upper surface of the N-type carrier storage layer 140.

[0058] The upper surface of the upper split gate unit is higher than the P-type base region 150 and the lower surface is lower than the P-type base region 150. When the upper split gate unit is the control gate 221, channels are formed on both sides of it. The lower split gate unit is used to optimize the electric field.

[0059] In some embodiments, one of the two split gate units near the source 410 is a control gate 221, and the other three split gate units are shielding gates 222, such as... Figure 1 As shown.

[0060] One of the two split gate units near the source 410 is the control gate 221, which has the smallest parasitic capacitance Cgd.

[0061] In some embodiments, the split gate module 220 includes two control gates 221 and two shielding gates 222, and at least one of the two split gate units closest to the source 410 is a control gate 221.

[0062] The upper surface of the uppermost split gate unit is higher than the P-type base region 150 and the lower surface is lower than the P-type base region 150. At least one of the two uppermost split gate units is a control gate 221, which ensures that channels are formed in the P-type base regions 150 on both sides of the control gate 221.

[0063] In some embodiments, the two split gate units closest to the source 410 are both control gates 221, and the other two split gate units are shielding gates 222, such as... Figure 2 As shown. Alternatively, both split gate units in one gate trench 101 may be control gates 221, and both split gate units in the other gate trench 101 may be shield gates 222, as shown. Figure 3 As shown. Alternatively, in one gate trench 101, the split gate cell on the side closer to the source 410 is the control gate 221, and in the other gate trench 101, the split gate cell on the side farther from the source 410 is also the control gate 221, as shown. Figure 4 As shown.

[0064] In one gate trench 101, both split gate units near the source 410 are control gates 221, forming two channels. This arrangement of control gates 221 and shielding gates 222 results in moderate parasitic capacitances Cgd and Cgs compared to other combinations of control gates 221 and shielding gates 222. In another gate trench 101, both split gate units are control gates 221, forming one channel, resulting in a smaller parasitic capacitance Cgs. In yet another gate trench 101, one split gate unit near the source 410 is a control gate 221, and the other gate trench 101, the split gate unit away from the source 410, is also a control gate 221. The upper control gate 221 forms one channel, resulting in a smaller parasitic capacitance Cgd.

[0065] In some embodiments, the split gate module 220 includes three control gates 221 and one shielding gate 222. One of the two split gate units closest to the source 410 is the shielding gate 222, and the remaining split gate units are control gates 221. Figure 5 As shown.

[0066] One of the two split gate units near the source 410 is a shield gate 222, and the other split gate units are control gates 221. With the control gates 221 and shield gates 222 arranged in this way, the two control gates 221 near the source 410 form two channels, resulting in higher transconductance of the device.

[0067] In some embodiments, the split gate module 220 includes three control gates 221 and one shielding gate 222. One of the two split gate units on the side away from the source 410 is the shielding gate 222, and the remaining split gate units are control gates 221. Figure 6 As shown.

[0068] One of the two split gate units on the side away from the source 410 is a shield gate 222, and the other split gate units are control gates 221. This arrangement of control gates 221 and shield gates 222, with one control gate 221 on the side closer to the source 410 forming a channel, can better optimize the electric field and improve the breakdown voltage of the device.

[0069] In some embodiments, all four split gate units are control gates 221, such as Figure 7 As shown.

[0070] All four split gate units are control gates 221. The two control gates 221s closest to the source 410 form two channels. This arrangement of control gates 221 and shielding gates 222 results in the device having the lowest on-resistance and the strongest conduction capability.

[0071] In this embodiment, the four split gate units can form multiple combinations of 1 to 4 control gates 221 and 0 to 3 shield gates 222. Under each combination of control gate 221 and shield gate 222: when the device is turned on, the control gate 221 forms an electronic channel, and the shield gate 222 optimizes the potential distribution; when the device is turned off, the split gate module 220 modulates the peak electric field and increases the breakdown voltage; during the device switching transient, the parasitic capacitance is different under different combinations of control gate 221 and shield gate 222, and the charge injection / extraction process can be controlled by adjusting the capacitance.

[0072] The field-effect transistor of this application achieves active adjustment of parasitic capacitances Cgd and Cgs at the device level. By optimizing parasitic capacitance Cgd, switching losses are reduced, switching frequency is increased, the controllable range of dynamic dV / dt is expanded, and EMI characteristics are significantly improved.

[0073] This application also provides a method for fabricating a field-effect transistor (FET), used to fabricate the FET disclosed above. See also... Figure 1 and Figure 8 As shown, the fabrication method of a field-effect transistor includes:

[0074] S100: An N-type drift region 130 is formed on an N+ type substrate 110;

[0075] S200: A P-type base region 150 is formed on the side of the N-type drift region 130 away from the N+ type substrate 110;

[0076] S300: Etching the P-type base region 150 and the N-type drift region 130 forms two gate trenches 101 extending to the N-type drift region 130, with the two gate trenches 101 spaced apart;

[0077] S400: Two spaced and overlapping split gate units are formed in each gate trench 101 and a gate oxide layer 210 is filled in the gate trench 101 and covers the split gate units;

[0078] S500: An interlayer dielectric layer 300 is formed on the side of the gate oxide layer 210 away from the N+ type substrate 110, and the interlayer dielectric layer 300 at least covers the gate oxide layer 210.

[0079] S600: A source electrode 410 is formed on the side of the interlayer dielectric layer 300 away from the N+ type substrate 110;

[0080] S700: Drain 420 is formed on the side of N+ type substrate 110 away from N- type drift region 130.

[0081] Specifically, before forming the N-type drift region 130, an N+ type buffer layer 120 can be formed on the N+ type substrate 110. Both the N+ type buffer layer 120 and the N-type drift region 130 can be fabricated using epitaxial growth processes. It should be understood that while the N+ type buffer layer 120 and the N-type drift region 130 can be fabricated using epitaxial growth processes, they are not limited to this. Other deposition processes can also be used to fabricate the N+ type buffer layer 120 and the N-type drift region 130, depending on the specific circumstances.

[0082] Before forming the P-type base region 150, an N-type carrier storage layer 140 can be formed on the N-type drift region 130. The N-type carrier storage layer 140 and the P-type base region 150 can be fabricated using an ion implantation process. After forming the P-type base region 150, an N+ type source region 161 and a P+ type contact region 162 can be formed on the P-type base region 150. The N+ type source region 161 is formed on the side of the P-type base region 150 away from the N+ type substrate 110. The N+ type source region 161 is configured in a one-to-one correspondence with the gate trench 101, and the gate trench 101 extends through the N+ type source region 161 to the N-type drift region 130. P+ type contact region 162 is formed on the side of P-type base region 150 away from N+ type substrate 110 and is located between two adjacent N+ type source regions 161. Source 410 is connected to P+ type contact region 162 and N+ type source regions 161 on both sides of P+ type contact region 162.

[0083] When forming the source 410 on the side of the interlayer dielectric layer 300 away from the N+ type substrate 110, the interlayer dielectric layer 300 is first etched to form a first via. The source 410 is connected to the P+ type contact region 162 and the N+ type source regions 161 on both sides of the P+ type contact region 162 through the first via. When the field-effect transistor includes at least one shielding gate 222, a second via extending to the upper surface of the shielding gate 222 is formed before forming the source 410. When forming the source 410, the source 410 is connected to the shielding gate 222 through the second via.

[0084] When fabricating field-effect transistors (FETs), combinations of 1 to 4 control gates 221 and 0 to 3 shield gates 222 can be selected based on the device performance requirements such as switching speed, drive loss, and anti-interference performance under different application scenarios. This results in devices with different values ​​for parasitic capacitance Cgd and parasitic capacitance Cgs. The combinations of 1 to 4 control gates 221 and 0 to 3 shield gates 222 can be as follows: one of the two split gate units near the source 410 is a control gate 221, and the other three are shield gates 222; or both split gate units near the source 410 are control gates 221, and the other two are shield gates 222; or both split gate units in one gate trench 101 are control gates 221, and both split gate units in the other gate trench 101 are shield gates 222; or the split gate unit near the source 410 in one gate trench 101 is a control gate 221. The control gate 221 and the split gate unit on the side away from the source 410 in another gate trench 101 are control gates 221, or the split gate module 220 includes three control gates 221 and one shield gate 222, one of the two split gate units on the side near the source 410 is the shield gate 222, and the remaining split gate units are control gates 221, or the split gate module 220 includes three control gates 221 and one shield gate 222, one of the two split gate units on the side away from the source 410 is the shield gate 222, and the remaining split gate units are control gates 221, or all four split gate units are control gates 221.

[0085] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0086] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0087] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0088] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A field-effect transistor, characterized in that, include: N+ type substrate; An N-type drift region is formed on one side of the N+ type substrate; A P-type base region is formed on the side of the N-type drift region away from the N+ type substrate, and at least two gate trenches are formed on the P-type base region, the gate trenches extending to the N-type drift region; A split gate module includes multiple split gate units, with two split gate units disposed in each gate trench. The split gate units in each gate trench overlap and are spaced apart. At least one split gate unit in the split gate module is a control gate. A gate oxide layer fills the gate trench and surrounds the split gate cell; The source electrode is formed on the side of the P-type base region away from the N+ type substrate. An interlayer dielectric layer is formed between the gate oxide layer and the source electrode; The drain is formed on the side of the N+ type substrate away from the N- type drift region; The field-effect transistor further includes an N+ type buffer layer, an N- type carrier storage layer, an N+ type source region, and a P+ type contact region. The N+ type buffer layer is formed between the N+ type substrate and the N- type drift region. The N- type carrier storage layer is formed between the N- type drift region and the P- type base region. The N+ type source region is formed on the side of the P-type base region away from the N+ type substrate. The N+ type source region is disposed in a one-to-one correspondence with the gate trench. The gate trench extends through the N+ type source region to the N- type drift region. The P+ type contact region is formed on the side of the P-type base region away from the N+ type substrate and is located between two adjacent N+ type source regions. The source is connected to the P+ type contact region and the N+ type source regions on both sides of the P+ type contact region.

2. The field-effect transistor according to claim 1, characterized in that, The split gate module includes four split gate units, and the spacing between the split gate unit closest to the source and the N+ type substrate is smaller than the spacing between the P type base region and the N+ type substrate.

3. The field-effect transistor according to claim 1 or 2, characterized in that, One of the two split gate units closest to the source electrode is the control gate, and the other three split gate units are shielding gates.

4. The field-effect transistor according to claim 1 or 2, characterized in that, The split gate module includes two control gates and two shielding gates, and at least one of the two split gate units closest to the source is the control gate.

5. The field-effect transistor according to claim 4, characterized in that, Both of the split gate cells near the source side are control gates, or both of the split gate cells in one of the gate trenches are control gates, or the split gate cell near the source side in one of the gate trenches is the control gate and the split gate cell away from the source side in the other gate trench is the control gate.

6. The field-effect transistor according to claim 1 or 2, characterized in that, The split gate module includes three control gates and one shielding gate. One of the two split gate units closest to the source is the shielding gate, and the other split gate units are control gates.

7. The field-effect transistor according to claim 1 or 2, characterized in that, The split gate module includes three control gates and one shielding gate. One of the two split gate units on the side away from the source is the shielding gate, and the other split gate units are control gates.

8. The field-effect transistor according to claim 1 or 2, characterized in that, All four of the split gate units are control gates.

9. A method for fabricating a field-effect transistor, characterized in that, include: An N+ type buffer layer is formed on an N+ type substrate, and an N- type drift region is formed on the side of the N+ type buffer layer away from the N+ type substrate; An N-type carrier storage layer is formed on the side of the N-type drift region away from the N+ type substrate. A P-type base region is formed on the side of the N-type carrier storage layer away from the N+ type substrate. An N+ type source region and a P+ type contact region are formed on the side of the P-type base region away from the N+ type substrate. The P+ type contact region is located between two adjacent N+ type source regions. The N+ type source region, the P type base region, the N type carrier storage layer and the N- type drift region are etched to form two gate trenches extending to the N- type drift region, and the two gate trenches are spaced apart; Two spaced and overlapping split gate units are formed in each gate trench, and a gate oxide layer is filled in the gate trench and covers the split gate units; An interlayer dielectric layer is formed on the side of the gate oxide layer away from the N+ type substrate, and the interlayer dielectric layer at least covers the gate oxide layer; A source electrode is formed on the side of the interlayer dielectric layer away from the N+ type substrate; A drain electrode is formed on the side of the N+ type substrate away from the N- type drift region.

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