Back contact solar cell and photovoltaic module

Abstract

The invention provides a back contact solar cell and a photovoltaic module, the back contact solar cell comprises a substrate, the substrate is provided with a backlight surface, and the backlight surface comprises a first polarity area, a second polarity area and an isolation area arranged between the first polarity area and the second polarity area; a first doped layer and a second doped layer, the first doped layer is arranged in the first polarity region, the second doped layer is arranged in the second polarity region, and the doping types of the first doped layer and the second doped layer are opposite; the isolation layer is arranged in the isolation region, the isolation layer comprises an intrinsic polycrystalline silicon layer, a first passivation layer and a third doping layer which are sequentially stacked in the direction away from the substrate, and the doping type of the third doping layer is the same as that of the first doping layer or the second doping layer. The main isolation effect is achieved through the intrinsic polycrystalline silicon layer, the composite passivation effect can be achieved through combination of the first passivation layer and the third doping layer, composite passivation with chemical passivation and field passivation is achieved in the isolation area, and the surface recombination rate is greatly reduced.

Description

Technical Field

[0001] This application relates to the field of photovoltaic technology, and in particular to a back-contact solar cell and photovoltaic module. Background Technology

[0002] As a clean energy technology, solar cells are fundamentally about efficiently converting light energy into electrical energy. Back-contact solar cells, because they fabricate all the metal electrodes on the back side of the cell, completely eliminate the shading of incident light by the front electrodes of traditional cells, making them an important technological route for achieving higher conversion efficiency.

[0003] In back-contact solar cells, the back surface needs to be fabricated with alternating first polarity regions (e.g., P-type doped regions) and second polarity regions (e.g., N-type doped regions) of opposite doping types. To prevent short circuits between these two polarity regions due to direct contact, an electrical isolation region needs to be set between them.

[0004] In existing technologies, only a single passivation film, such as silicon nitride or aluminum oxide, is used to cover the silicon substrate surface in the isolation region. Although this approach is simple to implement, its passivation effect is often insufficient, making it difficult to meet the requirements of high-efficiency cells for low surface recombination rates. Summary of the Invention

[0005] This application provides a back-contact solar cell and photovoltaic module, which can solve the problem that the passivation effect in the prior art is not ideal and it is difficult to meet the requirements of high-efficiency cells for low surface recombination rate.

[0006] In a first aspect, this application provides a back-contact solar cell, comprising:

[0007] The substrate has a backlight surface, the backlight surface including a first polar region, a second polar region, and an isolation region disposed between the first polar region and the second polar region;

[0008] A first doped layer and a second doped layer, wherein the first doped layer is disposed in the first polar region and the second doped layer is disposed in the second polar region, and the doping types of the first doped layer and the second doped layer are opposite;

[0009] An isolation layer is disposed in the isolation region. The isolation layer includes an intrinsic polysilicon layer, a first passivation layer and a third doped layer stacked sequentially in a direction away from the substrate. The doping type of the third doped layer is the same as that of the first doped layer or the second doped layer.

[0010] In some embodiments, the material of the third doped layer is doped amorphous silicon that has been annealed and crystallized.

[0011] In some embodiments, the doping concentration of the third doped layer is higher than that of the first or second doped layer, which has the same doping type.

[0012] In some embodiments, the doping concentration of the third doped layer is 1×10⁻⁶. 18 cm -3 Up to 1×10 21 cm -3 .

[0013] In some embodiments, the thickness of the third doped layer is 10 nm to 200 nm.

[0014] In some embodiments, the first passivation layer is a tunneling oxide layer.

[0015] In some embodiments, a second passivation layer is further included, which is disposed between the back surface of the substrate and the first doped layer, the second doped layer and the intrinsic polysilicon layer.

[0016] In some embodiments, the thickness of the first passivation layer is greater than the thickness of the second passivation layer.

[0017] In some embodiments, the thickness of the first passivation layer is 4nm-20nm.

[0018] In some embodiments, the thickness of the second passivation layer is 0.5 nm to 4 nm.

[0019] In some embodiments, the thickness of the intrinsic polysilicon layer is greater than or equal to the thickness of the first doped layer and greater than or equal to the thickness of the second doped layer.

[0020] In some embodiments, the difference between the thickness of the first doped layer and the thickness of the second doped layer is within 30%.

[0021] In some embodiments, the intrinsic polysilicon layer has a first doped portion and a second doped portion, wherein the first doped portion is formed by the lateral diffusion of a dopant used to prepare the first doped layer into the intrinsic polysilicon layer; and the second doped portion is formed by the lateral diffusion of a dopant used to prepare the second doped layer into the intrinsic polysilicon layer.

[0022] In some embodiments, the first polar region, the isolation region, and the second polar region are sequentially disposed along a first direction, the intrinsic polysilicon layer has a first length along the first direction; the first doped portion has a second length along the first direction; and the second doped portion has a third length along the first direction.

[0023] The first length is greater than the sum of the second length and the third length.

[0024] In some embodiments, the second length is greater than 0 μm and less than or equal to 2 μm.

[0025] In some embodiments, the third length is greater than 0 μm and less than or equal to 2 μm.

[0026] Secondly, this application provides a photovoltaic module including at least one battery string, the battery string including at least two back-contact solar cells provided in this application as described above.

[0027] The embodiments provided in this application utilize an intrinsic polysilicon layer to provide primary isolation, achieving physical barrier properties. Building upon this, the application employs a combination of a first passivation layer and a third doped layer to create a composite passivation effect, achieving a composite passivation in the isolation region that combines both chemical and field passivation, significantly reducing the surface recombination rate.

[0028] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0029] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the embodiments of the present application to explain the application and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed example embodiments described with reference to the accompanying drawings, in which:

[0030] Figure 1 A partial cross-sectional view of a back-contact solar cell provided in an embodiment of this application;

[0031] Figure 2 This is a dimensioning diagram of the first and second doped portions of a back-contact solar cell provided in an embodiment of this application. Detailed Implementation

[0032] To enable those skilled in the art to better understand the technical solutions of this application, exemplary embodiments of this application are described below in conjunction with the accompanying drawings, including various details of the embodiments of this application to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this application. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0033] Where there is no conflict, the various embodiments of this application and the features thereof may be combined with each other.

[0034] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0035] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, they specify the presence of features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. Words such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0036] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this application, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0037] Please refer to the following: Figure 1 and Figure 2 The back-contact solar cell provided in this application includes a substrate 1, a first doped layer 31, a second doped layer 32, and an isolation layer 4. The substrate 1 is, for example, a silicon substrate, and has a backlight surface. This backlight surface includes a first polar region A1, a second polar region A2, and an isolation region B disposed between the first polar region A1 and the second polar region A2. There can be multiple first polar regions A1 and second polar regions A2, which are spaced apart and alternately arranged along a direction parallel to the substrate 1. An isolation region B is provided between each adjacent pair of first polar regions A1 and second polar regions A2. The alternating direction of the first polar regions A1 and second polar regions A2 is, for example, parallel to the width direction of the electrode 6.

[0038] A first doped layer 31 is disposed in a first polar region A1, and a second doped layer 32 is disposed in a second polar region A2. The doping types of the first doped layer 31 and the second doped layer 32 are opposite. For example, one of the first doped layer 31 and the second doped layer 32 is an N-type doped layer, and the other is a P-type doped layer. An isolation layer 4 is disposed in an isolation region B. The isolation layer 4 includes an intrinsic polysilicon layer 41, a first passivation layer 42, and a third doped layer 43 sequentially stacked along a direction away from the substrate 1. The doping type of the third doped layer 43 is the same as the doping type of the first doped layer 31 or the second doped layer 32. That is, the third doped layer 43 can be an N-type doped layer or a P-type doped layer.

[0039] In some embodiments, the back-contact solar cell may further include a third passivation layer 5 and an electrode 6. The third passivation layer 5 covers the first doped layer 31, the second doped layer 32, and the isolation layer 4, and is provided with an opening region. The electrode 6 is electrically connected to the first doped layer 31 or the second doped layer 32 through the opening region.

[0040] Specifically, the intrinsic polysilicon layer 41 disposed in isolation region B is used for electrical isolation between the first doped layer 31 and the second doped layer 32. The intrinsic polysilicon layer 41 is composed of undoped (intrinsic) polysilicon material, which has a high resistivity, thereby forming an insulating layer between the first polar region A1 and the second polar region A2, cutting off the direct current leakage path between the first doped layer 31 and the second doped layer 32.

[0041] The first passivation layer 42 is, for example, a tunneling oxide layer, used to provide interfacial chemical passivation and improve the open-circuit voltage of the battery.

[0042] The third doped layer 43 is used to provide effective field passivation. By making the doping type of the third doped layer 43 the same as that of the first doped layer 31 or the second doped layer 32, it is easy to understand that the doping type of the third doped layer 43 is opposite to the doping type of the substrate 1 below the isolation region B, thereby providing a field passivation effect through the electric field formed between the third doped layer 43 and the substrate 1. The difference between the doping type of the third doped layer 43 and the substrate 1 induces an electrostatic field (i.e., a field effect) near the substrate 1. This electric field can repel minority carriers (e.g., electrons near the p-type substrate) away from the substrate surface, thereby preventing them from reaching the surface and recombinating with the interface states.

[0043] Existing technologies employ simple dielectric layer isolation schemes, which only provide limited chemical passivation. During high-temperature processes or long-term operation, this can easily lead to short circuits (i.e., "parasitic channel" leakage) between polar regions due to lateral diffusion of dopants. To address this issue, this application utilizes an intrinsic polysilicon layer 41 to provide primary isolation, achieving physical barrier properties. Building upon this, the application leverages the combination of a first passivation layer 42 and a third doped layer 43 to create a composite passivation effect, achieving a composite passivation in isolation region B that combines both "chemical passivation" and "field passivation," significantly reducing the surface recombination rate.

[0044] Specifically, the first passivation layer 42 saturates the dangling bonds on the crystalline silicon surface, reducing the interface state density and thus decreasing the probability of carrier recombination through surface defects, thereby achieving chemical passivation. The third doped layer 43 is further away from the substrate 1 than the intrinsic polycrystalline silicon layer 41 and the first passivation layer 42, and its doping type is the same as that of the first doped layer 31 or the second doped layer 32. This creates an electrostatic field (i.e., a "field effect") between the third doped layer 43 and the substrate 1, thereby achieving field passivation. The synergistic effect of the first passivation layer 42 and the third doped layer 43 effectively improves the passivation effect.

[0045] Furthermore, the first passivation layer 42 is a tunneling oxide layer, which, together with the third doped layer 43, constitutes a tunneling passivation contact structure. This structure allows majority carriers to pass through via the tunneling effect, forming a low-resistance ohmic contact, thereby reducing series resistance and heat loss. Simultaneously, it forms a barrier for minority carriers and, in conjunction with the field passivation effect of the third doped layer 43, achieves excellent surface passivation. In addition, the first passivation layer 42 acts as an effective diffusion barrier layer, preventing dopants in the third doped layer 43 from contaminating the silicon substrate 1 during the manufacturing process.

[0046] In some embodiments, the material of the third doped layer 43 is annealed and crystallized doped amorphous silicon. During the deposition process of preparing the third doped layer 43, the doped amorphous silicon material exhibits excellent fluidity and coverage, enabling it to better cover the underlying first passivation layer 42, forming a continuous and dense thin film. This ensures the structural integrity of the third doped layer 43, avoiding localized passivation failures or potential leakage channels caused by film discontinuities, thus improving product yield and reliability. Compared to directly depositing polycrystalline silicon, the initial amorphous silicon film possesses inherently smooth surface characteristics. This provides an ideal high-flatness substrate 1 for subsequent patterning processes such as photolithography and etching, ensuring process windows and consistency. Simultaneously, it exhibits excellent thickness and doping uniformity when deposited on large-area substrates, thereby ensuring the uniformity of battery performance. Furthermore, the annealing process activates the dopant, giving it the required electrical properties, and drives the amorphous silicon to undergo solid-phase crystallization into polycrystalline silicon.

[0047] In some embodiments, the doping concentration of the third doped layer 43 is higher than that of the first doped layer 31 or the second doped layer 32, which have the same doping type. Since the third doped layer 43 functions as a field passivation layer, the strength of the electrostatic field formed between it and the substrate 1 is positively correlated with the doping concentration. A higher doping concentration means more ionized impurities, resulting in a stronger space charge region and a steeper bandgap. This strong electric field effectively repels minority carriers (e.g., electrons near the p-type substrate 1) away from regions with high surface defect density, thus greatly suppressing surface recombination. Moreover, the higher doping concentration reduces the sensitivity of the third doped layer 43 to process fluctuations (such as temperature and time). Even with slight process variations, its high concentration ensures a robust field passivation effect, improving manufacturing robustness and yield.

[0048] To achieve the aforementioned effects of the third doped layer 43, in some embodiments, the doping concentration of the third doped layer 43 is 1×10⁻⁶. 18 cm -3 Up to 1×10 21 cm -3 .

[0049] In some embodiments, the thickness of the third doped layer 43 is 10 nm to 200 nm. The third doped layer 43 must reach a certain thickness to ensure its continuity and density. If the thickness is too thin, the film may grow in an island-like pattern, forming discontinuous networks or islands, leading to problems such as electrical short circuits and field passivation failure. If the thickness of the third doped layer is too thick, there is a risk of warping or peeling, which will impair the mechanical reliability and yield of the device. Moreover, beyond a certain thickness, further increasing the thickness contributes almost nothing to improving the field passivation effect, constituting performance overkill, resulting in material waste, increased costs, and potentially increasing unnecessary absorption or recombination of photogenerated carriers. Therefore, this application controls the thickness of the third doped layer 43 within the range of 10 nm to 200 nm, ensuring that the third doped layer 43 is a continuous and dense functional film, guaranteeing the reliable realization of the field passivation effect and ensuring the reliability of electrical isolation. At the same time, by limiting the maximum thickness, the risk of film peeling and microcracks in the battery is reduced, avoiding unnecessary cost increases caused by performance overkill.

[0050] In some embodiments, the back-contact solar cell further includes a second passivation layer 2, which is disposed between the back surface of the substrate 1 and the first doped layer 31, the second doped layer 32, and the intrinsic polycrystalline silicon layer 41. That is, the second passivation layer 2 covers the first polar region A1, the second polar region A2, and the isolation region B. The second passivation layer 2 is, for example, a tunneling oxide layer, used to bond with silicon atoms, saturating the dangling bonds across the entire silicon surface, and providing interfacial chemical passivation for the cell. The portion of the second passivation layer 2 located in the first polar region A1 and the second polar region A2 serves as a quantum tunneling layer, allowing majority carriers to pass through through the quantum tunneling effect, enter the upper doped polycrystalline silicon, and be collected by the electrode 6. The portion of the second passivation layer 2 located in the isolation region B can be used as a passivation and buffer layer. That is, it provides chemical passivation for the intrinsic polycrystalline silicon layer 41, maintaining a low recombination rate at the silicon interface. At the same time, it separates the intrinsic polycrystalline silicon layer 41 from the single-crystal silicon substrate, avoiding additional interface defects that may be introduced by direct contact between two materials with different crystal structures, thus playing a buffering and isolation role.

[0051] Furthermore, in some embodiments, the thickness of the first passivation layer 42 is greater than the thickness of the second passivation layer 2. As previously mentioned, the portion of the second passivation layer 2 located in the first polar region A1 and the second polar region A2 serves as a quantum tunneling layer, which needs to be relatively thin to allow majority carriers to tunnel through, forming a low-resistance ohmic contact. Preferably, the thickness of the second passivation layer 2 is 0.5 nm to 4 nm.

[0052] The first passivation layer 42, acting as a diffusion barrier and protective layer in isolation region B, is disposed between the intrinsic polysilicon layer 41 and the third doped layer 43. Since the third doped layer 43 is heavily doped, the dopant atoms (such as phosphorus or boron) exhibit a strong tendency to diffuse laterally and vertically during subsequent high-temperature processes such as annealing. If the first passivation layer 42 is too thin, the dopant can easily diffuse through it, entering and compensating for the underlying intrinsic polysilicon layer 41. Once the intrinsic polysilicon is compensated into a conductive layer, its insulating isolation function will completely fail, leading to leakage between the first polar region A1 and the second polar region A2. Therefore, a sufficiently thick first passivation layer 42 must be used to form an effective diffusion barrier. Preferably, the thickness of the first passivation layer 42 is 4nm-20nm. By using this thickness range, the contamination of the underlying intrinsic polysilicon layer 41 by the dopant in the third doped layer 43 can be effectively prevented, ensuring the reliability of isolation region B.

[0053] In some embodiments, the thickness of the intrinsic polysilicon layer 41 is greater than or equal to the thickness of the first doped layer 31 and greater than or equal to the thickness of the second doped layer 32. Leakage channels in back-contact solar cells exist not only laterally (along the surface direction) but also longitudinally. If the intrinsic polysilicon layer 41 is too thin, dopants may penetrate longitudinally through the entire intrinsic polysilicon layer 41 during the deposition of the upper third doped layer 43 or subsequent annealing. To avoid this problem, by making the thickness of the intrinsic polysilicon layer 41 greater than or equal to the thickness of the first doped layer 31 and greater than or equal to the thickness of the second doped layer 32, a safe thickness margin can be provided to block the diffusion of dopants from top to bottom. This ensures the insulation reliability of the intrinsic polysilicon layer 41 and prevents current leakage in the vertical direction. Meanwhile, the first doped layer 31 and the second doped layer 32 diffuse laterally into the intrinsic polysilicon layer 41 during the fabrication process. If the intrinsic polysilicon layer 41 is too thin, these two regions diffusing from opposite directions are likely to meet and connect in the middle, forming a parasitic conductive channel penetrating the isolation region B, leading to leakage. To avoid this problem, by using a relatively thick intrinsic polysilicon layer 41, the risk of forming parasitic conductive channels can be reduced, ensuring that effective electrical isolation is maintained.

[0054] Preferably, the thickness of the intrinsic polycrystalline silicon layer 41 is equal to the thickness of the first doped layer 31 and equal to the thickness of the second doped layer 32. If there is a height difference between the first polar region A1, the isolation region B, and the second polar region A2, steps will form at their boundaries. These steps will become stress concentration points when the cell is subjected to stress (such as stress transmission during manufacturing, pressure during module lamination, or daily thermal expansion and contraction). This stress concentration can easily cause microcracks or even breakage of the cell at the step, seriously damaging the mechanical reliability and long-term service life of the module. Moreover, printing or photolithography of the electrode 6 on a surface with a height difference increases the process difficulty. When the metal paste flows over the step, it is easy to cause broken lines, incomplete printing, or uneven thickness due to uneven flow. The height difference will cause distortion of the exposure pattern, inconsistent line width, and even breakage of the metal interconnect at the step. This directly leads to an increase in series resistance, a decrease in fill factor, and even short circuit or open circuit failure of the cell. To address the aforementioned issues, this application makes the thickness of the intrinsic polycrystalline silicon layer 41 equal to the thickness of the first doped layer 31 and equal to the thickness of the second doped layer 32. This allows the substrate 1 to be flatter on the backlight side, enabling the solar cell to uniformly distribute and withstand external stress, significantly improving its resistance to microcracks. Furthermore, it provides a flatter substrate 1 for subsequent metallization processes (whether screen printing, electroplating, or photolithography), allowing the electrodes 6 to achieve more uniform patterns with lower resistance. The flat surface ensures highly consistent performance across all areas of the cell, avoiding current mismatch caused by uneven topography.

[0055] In other embodiments, the difference between the thickness H1 of the first doped layer 31 and the thickness H2 of the second doped layer 32 is within 30%. A difference within 30% means that the relative difference between the thickness H1 of the first doped layer 31 and the thickness H2 of the second doped layer 32 does not exceed 30%. Specifically, the calculation is: |H1-H2| / reference value ≤ 30%, where the reference value can be the average of the thickness H1 of the first doped layer 31 and the thickness H2 of the second doped layer 32, i.e., (H1+H2) / 2; or, the reference value can be either the thickness H1 of the first doped layer 31 or the thickness H2 of the second doped layer 32. This 30% is an empirical tolerance range, meaning that the thicknesses of the two doped layers cannot differ too much to ensure a relatively flat back surface of the battery, thereby uniformly distributing stress and improving mechanical reliability; simultaneously, it makes the subsequent electrode 6 process easier to implement, resulting in a more precise and consistent electrode 6 pattern, thus optimizing electrical performance. Based on this, by keeping the difference between the thickness H1 of the first doped layer 31 and the thickness H2 of the second doped layer 32 within 30%, some process fluctuations (such as deposition inhomogeneity) are allowed, while ensuring that the thickness difference is not large enough to cause significant problems. In other words, if the tolerance is too large, the height difference problem may still exist; if the tolerance is too small, the process requirements may be too high, affecting the yield. 30% is a typical value that achieves the best balance between reliability and manufacturability.

[0056] In some embodiments, such as Figure 2 As shown, the intrinsic polysilicon layer 41 has a first doped portion 411 and a second doped portion 412. The first doped portion 411 is formed by the lateral diffusion of the dopant used to prepare the first doped layer 31 into the intrinsic polysilicon layer 41; the second doped portion 412 is formed by the lateral diffusion of the dopant used to prepare the second doped layer 32 into the intrinsic polysilicon layer 41. If the interface between the first doped layer 31 and the intrinsic polysilicon layer 41, and the interface between the second doped layer 32 and the intrinsic polysilicon layer 41, is a steep interface, a large doping concentration gradient and bandgap will be generated at the interface. This will lead to a high interface state density, becoming a strong recombination center for charge carriers; it will also generate local electric field concentration, which may induce non-ideal effects such as tunnel breakdown, increasing the risk of leakage. Moreover, it is difficult to achieve in terms of process that the dopants used to prepare the first doped layer 31 and the dopants used to prepare the second doped layer 32 are completely prevented from diffusing into the intrinsic polycrystalline silicon layer 41. Therefore, the lateral lengths of the first doped portion 411 and the second doped portion 412 can be controlled by controlling the parameters of the diffusion process to balance process feasibility and isolation effect.

[0057] The first doped region 411 and the second doped region 412 are formed during the annealing process by the diffusion of dopant atoms (such as boron or phosphorus) from the first polar region A1 and the second polar region A2, respectively, from the interface between them and the isolation region B into the intrinsic polysilicon layer 41. Due to thermal diffusion, the concentrations of the first doped region 411 and the second doped region 412 decrease gradually from the interface into the intrinsic polysilicon layer 41, thus forming a gradually changing transition region of doping concentration. This gradient-doped, gradually changing junction effectively mitigates band bending at the interface, smooths the local electric field, and significantly reduces the carrier recombination rate and tunnel breakdown risk at the interface.

[0058] Furthermore, in some embodiments, the first polarity region A1, the isolation region B, and the second polarity region A2 are along a first direction (i.e., parallel to...). Figure 1 and Figure 2 The intrinsic polysilicon layer 41 and the second doped layer 32 are arranged laterally (for example, parallel to the width direction of electrode 6). The intrinsic polysilicon layer 41 has a length of L1 along the first direction; the first doped portion 411 has a length of L2 along the first direction; and the second doped portion 412 has a length of L3 along the first direction. The first length L1 is greater than the sum of the second length L2 and the third length L3. In the high-temperature process, the dopants of the first doped layer 31 and the second doped layer 32 will inevitably diffuse laterally into the middle isolation region B, forming the first doped portion 411 and the second doped portion 412. If the original width (i.e., the first length L1) of the isolation region B (also the intrinsic polysilicon layer 41) is insufficient, the two doped portions that diffuse from the left and right sides will meet and connect in the middle. Once connected, a doped conductive channel connecting the P-region and the N-region is physically formed, causing a short circuit and leakage between the first polar region A1 and the second polar region A2, which causes a sharp drop in the open-circuit voltage and fill factor of the battery, which may lead to battery failure. Based on this, by making the first length L1 greater than the sum of the second length L2 and the third length L3, a safety buffer can be established to ensure that an intrinsic region (i.e., an undoped central region that maintains intrinsic high resistivity) exists between the first doped portion 411 and the second doped portion 412 in the intrinsic polysilicon layer 41. This intrinsic region blocks the possibility of connection between doped portions from both sides, thereby ensuring the reliability of electrical isolation. Preferably, the second length L2 is greater than 0 μm and less than or equal to 2 μm. The third length L3 is greater than 0 μm and less than or equal to 2 μm.

[0059] If the lateral diffusion of the first doped layer 31 and the second doped layer 32 is uncontrolled (e.g., > 2 μm), the doped portion will excessively erode the intrinsic polysilicon layer 41. Even if the total length of the intrinsic polysilicon layer 41 (the first length L1) meets the requirements, excessive diffusion will significantly reduce the effective width of the intermediate intrinsic region, increasing the risk of connection (bridging) between the first doped portion 411 and the second doped portion 412, leading to leakage. This application reduces the risk of leakage due to isolation failure caused by lateral diffusion by making the second length L2 greater than 0 μm and less than or equal to 2 μm; and the third length L3 greater than 0 μm and less than or equal to 2 μm, thus ensuring the parallel resistance and high fill factor of the battery.

[0060] As another technical solution, this application embodiment also provides a photovoltaic module, including at least one battery string, the battery string including at least two back-contact solar cells provided in this application embodiment.

[0061] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this application as set forth by the appended claims.

Claims

1. A back contact solar cell, characterized by, The back contact solar cell comprises: a substrate having a back surface, the back surface comprising a first polarity region, a second polarity region, and an isolation region disposed between the first polarity region and the second polarity region; a first doped layer disposed in the first polarity region and a second doped layer disposed in the second polarity region, the first doped layer and the second doped layer having opposite doping types; an isolation layer disposed in the isolation region, the isolation layer comprising, in order from a direction away from the substrate, an intrinsic polysilicon layer, a first passivation layer, and a third doped layer, the third doped layer having a same doping type as the first doped layer or the second doped layer.

2. The back contact solar cell of claim 1, wherein, The third doped layer is made of annealed and crystallized doped amorphous silicon.

3. The back contact solar cell of claim 1, wherein, The third doped layer has a higher doping concentration than the first doped layer or the second doped layer having the same doping type.

4. The back contact solar cell according to claim 1 or 3, characterized in that, The third doped layer has a doping concentration of 1 x 10 18 cm -3 to 1 x 10 21 cm -3 .

5. The back contact solar cell of claim 1, wherein, The third doped layer has a thickness of 10 nm to 200 nm.

6. The back contact solar cell of claim 1, wherein, The first passivation layer is a tunneling oxide layer.

7. The back contact solar cell of claim 1 wherein, The back contact solar cell further comprises a second passivation layer disposed between the back surface of the substrate and the first doped layer, the second doped layer, and the intrinsic polysilicon layer.

8. The back contact solar cell of claim 7, wherein, The first passivation layer has a thickness greater than a thickness of the second passivation layer.

9. The back contact solar cell of claim 8, wherein, The first passivation layer has a thickness of 4 nm to 20 nm.

10. The back contact solar cell of claim 8, wherein, The second passivation layer has a thickness of 0.5 nm to 4 nm.

11. The back contact solar cell of claim 1 wherein, The intrinsic polysilicon layer has a thickness greater than or equal to a thickness of the first doped layer and greater than or equal to a thickness of the second doped layer.

12. The back contact solar cell of claim 1 or 11, wherein, A difference between the thickness of the first doped layer and the thickness of the second doped layer is within 30%.

13. The back contact solar cell of claim 1 wherein, The intrinsic polysilicon layer has a first doped portion and a second doped portion, the first doped portion being formed by lateral diffusion of a dopant used to prepare the first doped layer into the intrinsic polysilicon layer, and the second doped portion being formed by lateral diffusion of a dopant used to prepare the second doped layer into the intrinsic polysilicon layer.

14. The back contact solar cell of claim 13, wherein, The first polarity region, the isolation region, and the second polarity region are arranged in order along a first direction, the intrinsic polysilicon layer has a first length along the first direction, the first doped portion has a second length along the first direction, and the second doped portion has a third length along the first direction. The first length is greater than a sum of the second length and the third length.

15. The back contact solar cell of claim 14, wherein, The second length is greater than 0 μm and less than or equal to 2 μm.

16. The back contact solar cell of claim 14, wherein, The third length is greater than 0 μm and less than or equal to 2 μm.

17. A photovoltaic module, characterized by The back contact solar cell comprises at least one cell string, the cell string comprising at least two back contact solar cells according to any one of claims 1-16.

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