TBC crystalline silicon cell with back surface doped step by step and region and preparation method of TBC crystalline silicon cell

Abstract

The invention discloses a TBC crystalline silicon cell doped on the back step by step and region and a preparation method of the TBC crystalline silicon cell. The preparation method comprises the steps that an N-type monocrystalline silicon substrate is provided, the substrate comprises a front face and a back face, annealing treatment is carried out on the back face in a partitioned and step-by-step mode, and doping activation of independent areas is carried out; preparing a textured structure with pyramid morphology on the front surface of the N-type monocrystalline silicon substrate to enhance the light trapping effect; and performing a metal slurry screen printing process on the first region and the second region, performing high-temperature sintering, forming a metal electrode in contact with the first doping layer in the first region, forming a metal electrode in contact with the second doping layer in the second region, and preparing the TBC crystalline silicon battery. According to the invention, the technical problems of incompatibility of boron and phosphorus doped region doping processes, increase of the complexity of a process route, influence on the cell performance and the like in the prior art can be solved, the open-circuit voltage and the fill factor of the cell can be effectively improved, and the photoelectric conversion efficiency of the TBC crystalline silicon cell is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic cells, in particular to a structure of a tunnel oxide passivated contact (TBC) crystalline silicon solar cell and a preparation method thereof. BACKGROUND

[0002] With the increasing demand for cell conversion efficiency in the photovoltaic industry, N-type crystalline silicon cells have become the mainstream direction of high-efficiency cell technology development due to their high minority carrier lifetime, no light-induced degradation, and good weak light effect.

[0003] TBC cells combine the excellent passivation performance of the tunnel oxide passivated contact technology and the advantage of no grid line shading on the front of the interdigitated back contact (IBC) cell, and are considered as one of the potential technologies to achieve higher conversion efficiency.

[0004] The core structure of a TBC cell is to prepare P-type doped regions (usually boron-doped to form emitters) and N-type doped regions (usually phosphorus-doped to form back surface fields) in an interdigital and spaced arrangement on the back of the cell.

[0005] In the traditional TBC cell preparation process, high-temperature doping is usually required for P-type and N-type doped regions to achieve activation of the doping elements, crystallization of the polysilicon layer, and formation of a high-quality passivation contact interface. However, there is a long-standing technical bottleneck that has not been effectively solved in this process, which is the significant difference or even conflict between the doping process windows required for boron (B) and phosphorus (P) doping elements. Specifically, due to its relatively low solid solubility and diffusion coefficient in silicon, boron requires a very high thermal budget to achieve effective electrical activation, and a high annealing or diffusion temperature of more than 1000℃ is usually required for boron doping to form a good emitter. After completing this high-temperature step, the phosphorus-doped region needs to be prepared and activated, and the doping and activation temperature of phosphorus is significantly lower than that of the boron-doped region. In the existing technology, a one-step co-doping or co-annealing process is used, which simplifies the process flow, but in actual operation, in order to activate both elements simultaneously, compromises need to be made in the doping concentration, junction depth, and annealing temperature of boron and phosphorus, making it difficult to achieve optimal performance for both P and N regions simultaneously, and there is a risk of cross-contamination. Using a two-step furnace tube high-temperature annealing method, on the one hand, both doped regions need a long annealing time (at least 10 minutes to achieve doping), and on the other hand, in order to avoid cross-contamination, a mask layer needs to be prepared before doping, and multiple steps of laser patterning of the mask layer are required, increasing the complexity of the process flow.

[0006] Therefore, the existing technical route generally faces the problem of being unable to compatibly process two high-quality doped regions.

[0007] In summary, developing a TBC cell fabrication method that can decouple the doping processes of the P-type and N-type doped regions, allowing for independent doping optimization of the two regions while reducing the risks of process flow and cross-contamination, is of great significance for overcoming the performance bottlenecks of existing TBC cells and enhancing their market competitiveness. Summary of the Invention

[0008] To address the aforementioned technical problems and shortcomings in the field, this invention provides a TBC crystalline silicon solar cell with back-side stepwise partitioned doping and its preparation method. This invention solves the technical problems in the background art, such as incompatibility of boron and phosphorus doping processes, increased complexity of process routes, and impact on cell performance. This technology can effectively improve the open-circuit voltage and fill factor of the cell, thereby increasing the photoelectric conversion efficiency of the TBC crystalline silicon solar cell.

[0009] A method for fabricating a TBC crystalline silicon solar cell with back-side stepwise partitioning doping includes: An N-type monocrystalline silicon substrate is provided, comprising a front side and a back side, wherein the following operations are performed on the back side: S1, a tunneling oxide layer and an intrinsic polycrystalline silicon layer are deposited sequentially; S2, etching out forked grooves to form alternating first and second regions with gaps between adjacent regions; S3, deposit a boron source layer; perform a first annealing process on the first region to activate boron doping and form a first doped layer; remove the boron source layer in the second region; S4, deposit phosphorus source layer; perform second annealing process on the second region to activate phosphorus doping and form second doped layer; remove all boron source layer and phosphorus source layer; A textured structure with a pyramidal morphology is prepared on the front side of an N-type monocrystalline silicon substrate to enhance the light trapping effect; a metal paste screen printing process is performed on the first and second regions, followed by high-temperature sintering, to form a metal electrode in contact with the first doped layer in the first region and a metal electrode in contact with the second doped layer in the second region, thus preparing a TBC crystalline silicon cell.

[0010] This invention performs annealing in sections and steps, independently activating the doping in each region. During the first and second laser annealing processes, the precise laser alignment process ensures that there is no substantial negative impact on the electrical properties and passivation quality of the other doped region, whether already formed or yet to be formed. Furthermore, the second furnace tube annealing temperature is significantly lower than the doping temperature of the first region, thus avoiding any thermal impact of the second annealing on the already doped first region.

[0011] Before depositing the tunneling oxide layer and the intrinsic polycrystalline silicon layer in S1, the process also includes cleaning and polishing the N-type monocrystalline silicon substrate.

[0012] S1 uses chemical vapor deposition to prepare a tunneling oxide layer and an intrinsic polycrystalline silicon layer. Furthermore, the preparation temperature for chemical vapor deposition is 300-700℃.

[0013] Furthermore, the thickness of the tunneling oxide layer is 0.5-2 nm.

[0014] Furthermore, the thickness of the intrinsic polycrystalline silicon layer is 50-300 nm.

[0015] The method for preparing the first and second regions with gaps using S2 is a laser film removal method. Further, the laser film removal method uses a picosecond laser with a wavelength range of 300-600 nm, a laser power of 1-20 W, and a laser energy density of 0.1-2 J·cm⁻¹. -2 Pulse width 10-100 ps, ​​laser scanning speed set to 1-50 m / s.

[0016] The S3 boron source layer and S4 phosphorus source layer are silicide layers containing doped impurities, which can be prepared by chemical vapor deposition (CVD). The CVD preparation temperature can be 300-700℃, and the preparation time can be 5-15 min. The raw materials for forming the boron and phosphorus source layers can be gas sources. The gas source for forming the doped impurities in the boron source layer can be one of boron tribromide or boron trichloride, and the gas source for forming the doped impurities in the phosphorus source layer can be one of phosphorus tribromide or phosphorus trichloride. The formation process of the boron and phosphorus source layers may also include other reaction gas sources and carrier gases, such as a mixture of one or more gases selected from nitrogen, argon, silane, nitrous oxide, ammonia, and oxygen.

[0017] The thickness of the boron source layer and the phosphorus source layer is preferably 20-200 nm. The thickness of the boron source layer is further preferably 50-150 nm. If the boron source layer is too thin, less than 20 nm, it cannot effectively serve as a protective layer for the subsequent back-side laser patterning stage, causing laser-induced damage, increasing the probability of non-radiative recombination, and affecting the photoelectric conversion efficiency. If the boron source layer is too thick, greater than 200 nm, it may cause significant diffusion of other impurity elements in the source layer, mainly oxygen impurities, leading to Auger recombination, which will also affect the photoelectric conversion efficiency.

[0018] The S3 first annealing process is a transient laser high-temperature process, with an annealing temperature higher than 1000 ℃, a laser wavelength set to 300-1100 nm, a pulse width of 0.1-1 ms, and a laser energy density set to 0.1-5 J·cm. -2 The laser power is set to 1-100W, and the laser scanning speed is set to 1-60m / s.

[0019] S3 removes the boron source layer in the second region using preset laser conditions or wet etching methods.

[0020] The S4 second annealing process can be a transient laser high-temperature process, with the annealing temperature controlled between 600-900℃.

[0021] In this invention, the instantaneous laser high-temperature process used in the first and second annealing processes has the following parameters: laser wavelength set to 300-1100 nm, pulse width to 0.1-1 ms, and laser energy density to 0.1-5 J·cm⁻¹. -2 Laser power is set to 1-100W, and laser scanning speed is set to 1-60m / s. The second annealing process for S4 can be a furnace tube high-temperature annealing process, with the annealing temperature set at 600-900℃ and the processing time at 10-30 minutes. The furnace tube high-temperature annealing process has a significantly lower processing temperature than the first annealing process and will not affect the already formed first doped layer.

[0022] This invention decouples the doping steps of the two doping regions by configuring different doping processes for the first and second regions, enabling independent doping of each region. This solves the technical problem of incompatible doping process windows in the first and second regions on the back of TBC crystalline silicon solar cells, significantly improving the open-circuit voltage and fill factor of the cell, and enhancing the photoelectric conversion efficiency.

[0023] The present invention also provides a TBC crystalline silicon solar cell with back-side stepwise partitioning doping prepared by the above-described preparation method.

[0024] TBC crystalline silicon solar cells include an N-type monocrystalline silicon substrate; the front side of the N-type monocrystalline silicon substrate, from the outside to the inside, includes a silicon nitride antireflective coating, an aluminum oxide film, a texturing structure, and the N-type monocrystalline silicon substrate; the back side of the N-type monocrystalline silicon substrate includes three regions: a back field region, an emitter region, and a gap region; the back field region, from the outside to the inside, includes a metal electrode, a silicon nitride antireflective coating, an aluminum oxide film, a first doped polycrystalline silicon layer, a first tunneling oxide layer, and the N-type monocrystalline silicon substrate; the emitter region, from the outside to the inside, includes a metal electrode, a silicon nitride antireflective coating, an aluminum oxide film, a second doped polycrystalline silicon layer, a second tunneling oxide layer, and the N-type monocrystalline silicon substrate; the gap region, from the outside to the inside, includes a silicon nitride antireflective coating, an aluminum oxide film, a texturing structure, and the N-type monocrystalline silicon substrate.

[0025] Fabricating a textured structure with a pyramidal morphology on the front side can enhance the light-trapping effect. While fabricating the first and second regions on the back side, a first and second mask layer are formed on the front side. The front mask layer is removed through wet etching and cleaning steps, resulting in the textured structure and further enhancing the light-trapping effect.

[0026] Metal paste screen printing is performed on the first and second regions, followed by high-temperature sintering. A metal electrode in contact with the first doped layer is formed in the first region, and a metal electrode in contact with the second doped layer is formed in the second region, thus preparing a TBC crystalline silicon solar cell.

[0027] Compared with the prior art, the beneficial effects of this invention are as follows: This invention decouples the doping steps of the two doping regions, which can independently optimize the doping activation and contact passivation quality of each region, solve the technical problem of incompatibility of doping process windows of the first and second doped polycrystalline silicon layers on the back of TBC crystalline silicon solar cells, and reduce the number of masking and etching steps required in traditional processes. This simplifies the overall process flow, reduces manufacturing costs, and significantly improves the open-circuit voltage and fill factor of the cell, thereby increasing photoelectric conversion efficiency. Attached Figure Description

[0028] Figure 1 This is a flowchart of a TBC crystalline silicon solar cell fabrication method.

[0029] Figure 2 This is a schematic diagram of the cross-sectional structure of a TBC crystalline silicon solar cell after some fabrication steps are completed.

[0030] Figure 3 This is a schematic diagram of the final structure of a TBC crystalline silicon solar cell. Detailed Implementation

[0031] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Operating methods not specifically specified in the following embodiments are generally performed under conventional conditions or as recommended by the manufacturer.

[0032] Combination Figure 1 A method for fabricating TBC crystalline silicon solar cells with stepwise partitioning doping on the back side, comprising the following steps: S10: Provides an N-type single-crystal silicon substrate 1, with a thickness of 100-200 µm and a resistivity of 0.1-20 Ω·cm. The substrate 1 undergoes standard chemical cleaning to remove surface damage from cutting, organic matter, and metallic impurities. Optionally, a texturing process can be performed on the front side (light-receiving surface) of the substrate 1 to form a pyramid-shaped textured structure 12 to enhance light-harvesting capabilities, such as... Figure 2 As shown.

[0033] S11: Using methods such as low-pressure chemical vapor deposition (LPCVD) or plasma-enhanced chemical vapor deposition (PECVD), tunneling oxide layers 2 and 4 and intrinsic polycrystalline silicon layers 3 and 5 are grown on the entire back side of substrate 1; wherein, the first region includes an ultrathin tunneling oxide layer 2 (such as silicon oxide) with a thickness of 1-2 nm, and subsequently, an intrinsic polycrystalline silicon layer 3 with a thickness of 50-300 nm is deposited on the tunneling oxide layer 2; the second region is similar to the first region, such as... Figure 2 As shown.

[0034] S12: Using high-precision laser ablation technology for patterning or employing mask lithography combined with plasma etching, interdigitated trenches are etched on the polysilicon layer and tunneling oxide layer on the back side, thereby dividing the back side into a first region for subsequent formation of the first impurity doping and a second region for formation of the second impurity doping, such as... Figure 2 As shown. Laser coating removal method conditions: laser type is picosecond laser, laser wavelength range is 300-600nm, laser power is set to 1-100W, and laser energy density is set to 1-5J·cm⁻¹. -2 Pulse width 10-100 ps, ​​laser scanning speed set to 1-50 m / s.

[0035] S13: After patterning in S12, the silicon wafer is placed in a PECVD apparatus, and a boron-rich first doped source layer, such as a borosilicate glass (BSG) layer, is deposited on the back side. Subsequently, the first region is subjected to transient high-temperature laser treatment. A pulsed laser is used to scan the first region, with laser parameters selected from the following range: laser wavelength 300-1100 nm, pulse width 0.1-1 ms, and laser energy density 0.1-5 J·cm⁻¹. -2 The laser power was set to 1-100W, and the laser scanning speed was set to 1-60m / s. The laser energy was absorbed by the BSG layer and the first region polycrystalline silicon layer 3, generating an instantaneous high temperature exceeding 1000°C. This caused boron atoms to rapidly diffuse from the BSG layer into the polycrystalline silicon layer, heavily doping it into a P-type boron-doped polycrystalline silicon layer 6. Simultaneously, the electrical activation of boron was achieved, such as... Figure 3 As shown. The key is that the instantaneous high-temperature annealing of the laser can be precisely applied only to the first region, preventing the doping elements in the BSG from diffusing into the second doped region.

[0036] S14: Remove the first doped source layer in the second region by a preset laser process and wet chemical cleaning (such as HF solution).

[0037] S15: A second thermal treatment process is performed, involving the deposition of a phosphorus-rich second doped source layer, such as a phosphorus silicate glass (PSG) layer, followed by a transient high-temperature laser treatment of the second region. The second region is scanned using a pulsed laser. Laser parameters are selected from the following ranges: laser wavelength 300-1100 nm, pulse width 0.1-1 ms, and laser energy density 0.1-5 J·cm⁻¹. -2 The laser power is set to 1-100W, and the laser scanning speed is set to 1-60m / s. The laser energy is absorbed by the PSG layer and the second polycrystalline silicon layer 5, generating an instantaneous high temperature of 600-900℃. This causes phosphorus atoms to rapidly diffuse from the PSG layer into the polycrystalline silicon layer, heavily doping it into an N-type phosphorus-doped polycrystalline silicon layer 7, while simultaneously achieving the electrical activation of phosphorus. The difference lies in the laser processing technology of the second region, which differs from the laser processing technology of the first region through different parameter settings, such as laser wavelength, power, and energy density. This ensures that the processing temperature and time of the second doped region are lower than those required for the first doped region. Crucially, the instantaneous high-temperature annealing by the laser can precisely act only on the second region, without affecting the passivation performance and electrical properties of the already stabilized P-type boron-doped polycrystalline silicon layer in the first region.

[0038] S16: All doped source layers are removed using a pre-defined laser process and wet cleaning. Then, passivation and antireflection films (protective layers) are deposited on the front and back sides of the cell using PECVD or atomic layer deposition (ALD) techniques. For example, the front side may be an Al₂O₃ / silicon nitride stack, and the back side may be a silicon nitride or silicon oxide / silicon nitride stack. See [link to relevant documentation]. Figure 3 .

[0039] S17: Using screen printing technology, a first electrode (such as silver paste) 9 is printed on the protective layer 8 of the first region on the back side, and a second electrode (such as silver paste) 11 is printed on the protective layer 10 of the second region. After high-temperature sintering, the metal electrode penetrates the passivation layer and forms a good ohmic contact with the underlying doped polycrystalline silicon layer, ultimately producing a TBC crystalline silicon solar cell product, such as... Figure 3 As shown.

[0040] Another embodiment of the present invention is to replace the second heat treatment process in step S15 in the above embodiment, specifically as follows: S10-S14: The preparation process is the same as in the above cases.

[0041] S15: Deposit a second phosphorus-rich doped source layer, such as a phosphorus silicate glass (PSG) layer, followed by a second heat treatment process of high-temperature furnace tube annealing of the second region, with the temperature set at 600-900℃ and the treatment time at 10-30min; the key is that the treatment temperature is significantly lower than the temperature required by the first doping process, so as not to affect the passivation quality and electrical properties of the already formed first doped region.

[0042] S16-S17: The preparation process is the same as the above cases.

[0043] Through the above embodiments, the present invention successfully decouples the doping processes of the P-region and N-region on the back side of the TBC crystalline silicon cell, which can effectively avoid the thermal damage problem in the traditional process and provide a feasible technical path for independently optimizing the performance of each doped region, thus laying a solid foundation for the preparation of higher efficiency TBC crystalline silicon solar cells.

[0044] Furthermore, it should be understood that after reading the above description of the present invention, those skilled in the art can make various alterations or modifications to the present invention, and these equivalent forms also fall within the scope defined by the appended claims.

Claims

1. A method for fabricating a back surface step and zone doped TBC crystalline silicon cell, characterized by, The preparation method comprises the following steps: An N-type monocrystalline silicon substrate is provided, and the substrate comprises a front surface and a back surface, and the following operations are performed on the back surface: S1, a tunneling oxide layer and an intrinsic polysilicon layer are sequentially deposited; S2, interdigital grooves are etched to form first regions and second regions which are alternately arranged and have gaps between adjacent regions; S3, a boron source layer is deposited; a first annealing process is performed on the first regions to activate boron doping and form a first doped layer; The boron source layer of the second regions is removed; S4, a phosphorus source layer is deposited; A second annealing process is performed on the second regions to activate phosphorus doping and form a second doped layer; All the boron source layer and the phosphorus source layer are removed; A pyramidal textured structure is prepared on the front surface of the N-type monocrystalline silicon substrate to enhance the light trapping effect; A metal paste screen printing process is performed on the first regions and the second regions, and high-temperature sintering is performed, so that a metal electrode in contact with the first doped layer is formed in the first regions, and a metal electrode in contact with the second doped layer is formed in the second regions, thereby preparing a TBC crystalline silicon cell.

2. The production method according to claim 1, characterized by, S1 is to prepare the tunneling oxide layer and the intrinsic polysilicon layer by chemical vapor deposition, and the preparation temperature of the chemical vapor deposition is 300-700°C.

3. The preparation method according to claim 1, characterized in that, The thickness of the tunneling oxide layer in S1 is 0.5-2 nm, and the thickness of the intrinsic polysilicon layer is 50-300 nm.

4. The method of claim 1, wherein, S2 The method for preparing the first region and the second region with gaps is a laser demolding method, the laser type is a picosecond laser, the laser wavelength range is 300-600 nm, the laser power is set to 1-20 W, the laser energy density is set to 0.1-2 J·cm -2 , the pulse width is 10-100 ps, and the laser scanning speed is set to 1-50 m / s.

5. The preparation method according to claim 1, characterized in that, The boron source layer in S3 and the phosphorus source layer in S4 are silicide layers containing doping impurities, which are prepared by chemical vapor deposition, and the preparation temperature of the chemical vapor deposition is 300-700°C, the preparation time is 5-15 min, the formation raw material of the boron source layer and the phosphorus source layer is a gas source, the gas source for forming the doping impurities of the boron source layer is one of boron tribromide and boron trichloride, the gas source for forming the doping impurities of the phosphorus source layer is one of phosphorus tribromide and phosphorus trichloride, and the thickness of the boron source layer and the phosphorus source layer is 20-200 nm.

6. The method of claim 1, wherein, The first annealing process in S3 is a transient laser high-temperature process, and the annealing temperature is higher than 1000°C.

7. The preparation method according to claim 1, characterized in that, The boron source layer of the second regions is removed by preset laser conditions or a wet etching method.

8. The method of claim 1, wherein, The second annealing process in S4 is a transient laser high-temperature process, and the annealing temperature is controlled to be 600-900°C.

9. The method of claim 1, wherein, The second annealing process in S4 is a furnace tube high-temperature annealing process, the annealing temperature is set to be 600-900°C, and the processing time is 10-30 min.

10. A TBC crystalline silicon cell prepared by the preparation method in any one of claims 1-9.

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