Solar cell, preparation method thereof and photovoltaic module

Abstract

The invention provides a solar cell, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaic cells. The solar cell comprises a semiconductor substrate, and a first surface of the semiconductor substrate comprises a first polarity region, a second polarity region and a spacer region arranged between the first polarity region and the second polarity region; a first doping part is arranged in the semiconductor substrate in the first polarity region, a second doping part is arranged in the semiconductor substrate in the second polarity region, and a third doping part is arranged in the semiconductor substrate in the interval region; a fourth doping part is arranged at the position, close to the third doping part, of the first doping part, and a fifth doping part is arranged at the position, close to the third doping part, of the second doping part. The five doping parts of the solar cell are in direct contact, so that the reverse turn-on voltage of a bypass channel is reduced, and the risk caused by the hot spot effect is reduced.

Description

Technical Field

[0001] This invention relates to the technical field of solar cells, and in particular to a solar cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Back contact batteries (BC batteries) have no grid lines obstructing their front surface, eliminating optical losses caused by front metal grid lines. Moreover, their back grid line design has a wider window, resulting in higher conversion efficiency. The grid-free design on the front makes them more aesthetically pleasing and applicable to a wider range of scenarios.

[0003] In a back-contact battery structure, the P-region and N-region on the back are arranged alternately. When a cell or part of the battery is blocked, the blocked PN junction will be subjected to reverse bias. This bias will rise rapidly and cause breakdown. When current concentrates through the tiny breakdown point, it will generate extremely high local temperatures, which can easily burn out the battery and packaging materials, and may also cause serious safety hazards such as fires. Therefore, a bypass channel needs to be constructed inside the back-contact battery. When the battery is blocked and reverse biased, this channel will conduct before the main PN junction avalanche breakdown, providing a non-destructive discharge path for the reverse current, thereby avoiding concentrated energy release and preventing local high temperatures and burnout.

[0004] In existing technologies, bypass channels are typically constructed using a process that involves overlapping semiconductor layers, such as polycrystalline silicon or amorphous silicon, with polar doped substrate surfaces. However, due to limitations in actual processing precision, dielectric isolation inevitably exists between semiconductor layers with different polar doping, directly restricting the optimization space for the reverse turn-on voltage of the bypass channel. This technological bottleneck means that even under partial shading conditions, solar cells still face the risk of high-temperature burnout due to reverse breakdown, posing a potential threat to the reliability of photovoltaic modules.

[0005] In view of this, the present invention is hereby proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a solar cell, a method for its fabrication, and a photovoltaic module, in order to solve at least one of the problems in the prior art.

[0007] In order to achieve the above-mentioned objectives of the present invention, the following technical solution is adopted: In a first aspect, the present invention provides a solar cell, including a semiconductor substrate, the semiconductor substrate including a first surface and a second surface disposed opposite to each other, and the first surface including a first polar region and a second polar region, and a spacer region disposed between the first polar region and the second conductive region. Wherein, the semiconductor substrate in the first polar region includes at least one first doped portion, and the semiconductor substrate in the second polar region includes at least one second doped portion; the first doped portion and the second doped portion have opposite conductivity types; The semiconductor substrate in the spacer region includes at least one third doped portion; the third doped portion is disposed between the first doped portion and the second doped portion; At least a portion of the third doped portion has the same conductivity type as the first doped portion; And / or, at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of the second doped portion.

[0008] Furthermore, at least a portion of the conductivity type of the third doped portion is the same as that of the first doped portion, and the ratio of the doping concentration of the third doped portion to the doping concentration of the first doped portion is (1.1~20):1.

[0009] Furthermore, the difference between the junction depth of the third doped portion and the junction depth of the first doped portion is 200~1000 nm.

[0010] Furthermore, at least a portion of the conductivity type of the third doped portion is the same as that of the second doped portion, and the ratio of the doping concentration of the third doped portion to the doping concentration of the second doped portion is (1.1~30):1.

[0011] Furthermore, the difference between the junction depth of the third doped portion and the junction depth of the second doped portion is 200~1000nm.

[0012] Furthermore, the conductivity type of the third doped portion is P-type, or the conductivity type of the third doped portion is N-type.

[0013] Furthermore, relative to the semiconductor substrate surfaces of the first polar region and the second polar region, the semiconductor substrate surface of the spacer region is recessed along the thickness direction of the semiconductor substrate to form a groove structure.

[0014] Furthermore, the ratio of the junction depth of the third doped portion to the depth of the groove structure is (0.3~10):1.

[0015] Furthermore, the depth of the groove structure is 5 nm or more; the width of the groove structure is 0.01~15 μm.

[0016] Furthermore, the semiconductor substrate surface of the spacer region is coplanar with at least one of the semiconductor substrate surfaces of the first polar region and the second polar region.

[0017] Furthermore, the solar cell also includes a fourth doped portion disposed between the first doped portion and the third doped portion, and the fourth doped portion is at least partially located in the first polarity region; the fourth doped portion has the same conductivity type as the first doped portion.

[0018] Furthermore, the doping concentration of the fourth doped portion is greater than that of the first doped portion, and the ratio between the doping concentration of the fourth doped portion and the doping concentration of the first doped portion is (1.01~50):1.

[0019] Furthermore, along the thickness direction of the semiconductor substrate, the junction depth of the fourth doped portion is greater than that of the first doped portion.

[0020] Furthermore, the difference between the junction depth of the fourth doped portion and the junction depth of the first doped portion is 200~1000nm.

[0021] Furthermore, the solar cell also includes a fifth doped portion disposed between the second doped portion and the third doped portion, the fifth doped portion having the same conductivity type as the third doped portion, and the fifth doped portion being at least partially located in the spacer region.

[0022] Furthermore, the doping concentration of the fifth doped portion is less than that of the third doped portion, and the ratio between the doping concentration of the third doped portion and the doping concentration of the fifth doped portion is (1.01~10):1.

[0023] Furthermore, along the thickness direction of the semiconductor substrate, the junction depth of the fifth doped portion is greater than that of the second doped portion.

[0024] Furthermore, the difference between the junction depth of the fifth doped portion and the junction depth of the second doped portion is 200~1000nm.

[0025] Furthermore, the fourth doped section contains at least two doping elements of different conductivity types; or, the fifth doped section contains at least two doping elements of different conductivity types.

[0026] Furthermore, the solar cell also includes a fourth doped portion and a fifth doped portion, wherein the fourth doped portion is disposed between the first doped portion and the third doped portion, and the fourth doped portion has the same conductivity type as the first doped portion.

[0027] Furthermore, the fifth doped portion is disposed between the second doped portion and the third doped portion, and the conductivity type of the fifth doped portion is the same as that of the third doped portion.

[0028] Furthermore, the first doped portion, the fourth doped portion, the third doped portion, the fifth doped portion, and the second doped portion are connected in sequence.

[0029] Furthermore, the first doped portion, the third doped portion, and the second doped portion electrically form a bypass channel.

[0030] Furthermore, the first polar region and the second polar region are spaced apart, and at least a portion of the substrate in the spacer region between the first polar region and the second polar region is provided with a third doped portion.

[0031] Furthermore, the third doped portion includes at least two third doped portions, which are discontinuously arranged along a direction intersecting the first polar region and the second polar region, and the distance between adjacent third doped portions is 1~10 mm.

[0032] Furthermore, the second polar region is disposed around the first polar region, and at least a portion of the substrate in the spacer region between the first polar region and the second polar region is provided with a third doped portion.

[0033] Furthermore, the first polar region includes a first polar functional stack, the first polar functional stack includes a first dielectric layer and a first polar doped layer, and the first dielectric layer is disposed between the first surface of the semiconductor substrate and the first polar doped layer.

[0034] Furthermore, the second polar region includes a second polar functional stack, which includes a second dielectric layer and a second polar doped layer, and the second dielectric layer is disposed between the first surface of the semiconductor substrate and the second polar doped layer.

[0035] Furthermore, the first dielectric layer is only disposed in the first polarity region.

[0036] Furthermore, the second dielectric layer is disposed only in the second polarity region.

[0037] Furthermore, a passivation layer is provided on the first surface of the solar cell, the passivation layer covering the spacer region and in direct contact with the third doped portion.

[0038] Secondly, the present invention provides a method for preparing a solar cell, comprising: Take a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other, and a first polar region and a second polar region are disposed on the first surface; A spacer region is formed on the first surface of the semiconductor substrate, the spacer region being disposed between the first polarity region and the second polarity region; At least one first doped portion is formed in the first polar region; at least one third doped portion is formed in the interval region; At least one second doped portion is formed in the second polar region to obtain the solar cell; The third doped portion is disposed between the first doped portion and the second doped portion; at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of either the first doped portion or the second doped portion. That is, at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of the first doped portion; and / or, at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of the second doped portion.

[0039] Further, the preparation method includes: After the spacer region is formed, a first doped portion is formed in the first polar region; a third doped portion is formed in the spacer region. And / or, the first doped portion and the third doped portion are formed simultaneously.

[0040] Further, the preparation method includes: A dielectric layer, an intrinsic polysilicon layer, and a mask functional layer are sequentially deposited on the first surface of a semiconductor substrate; The mask functional layer, dielectric layer, and intrinsic polysilicon layer at the corresponding positions of the spacer region are removed to form the spacer region; Remove the mask functional layer at the corresponding position of the first conductive region, and allow the first doping element to diffuse into the polysilicon layer and semiconductor substrate corresponding to the first conductive region to form the first doped portion; at the same time, allow the first doping element to diffuse into the semiconductor substrate to form the third doped portion and the fourth doped portion. A second doping element diffusion process is performed to diffuse the second doping element into the semiconductor substrate of the second conductive region, forming a second doped portion, thereby obtaining the solar cell.

[0041] Furthermore, the fabrication method includes: the solar cell further includes a fourth doped portion and / or a fifth doped portion; the fourth doped portion is formed simultaneously with the formation of the first doped portion.

[0042] Furthermore, the fifth doped portion is formed simultaneously with the formation of the second doped portion.

[0043] Thirdly, the present invention provides a photovoltaic module, the photovoltaic module comprising a solar cell as described in the first aspect, or a solar cell obtained by the preparation method described in the second aspect.

[0044] Compared with the prior art, the present invention has the following beneficial effects: The solar cell of the present invention dops at least a portion of the spacer region of the semiconductor substrate to form a third doped portion. The third doped portion, together with the doped portion (the first doped portion and the second doped portion) below the first conductive region and the second conductive region, constitutes a bypass channel. The bypass channel is completely disposed within the semiconductor substrate. The different doped portions of the bypass channel are in direct contact without a dielectric layer, thereby significantly reducing the reverse turn-on voltage of the bypass channel and reducing the risk of hot spot effect. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a structural schematic diagram of a cross-section of a solar cell provided in an embodiment of the present invention.

[0047] Figure 2 This is a structural schematic diagram of a cross-section of a solar cell provided in another embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of the structure of a solar cell plane provided in an embodiment of the present invention.

[0049] Figure 4 This is a schematic diagram of the structure of a solar cell plane provided in another embodiment of the present invention.

[0050] Figure 5 This is a process flow diagram of the method for preparing a solar cell provided by the present invention; wherein A~H represent the structures of the solar cells obtained in each step of the process flow diagram.

[0051] Wherein, 1 is a semiconductor substrate, 10 is a first polar region, 20 is a second polar region, 30 is a spacer region, 11 is a first doped portion, 111 is a fourth doped portion, 21 is a second doped portion, 211 is a fifth doped portion, 31 is a third doped portion, 101 is a first dielectric layer, 102 is a first polar doped layer, 201 is a second dielectric layer, 202 is a second polar doped layer, 601 is a dielectric layer, 602 is an intrinsic polysilicon layer, 603 is a mask functional layer, and 604 is a first doping source layer. Detailed Implementation

[0052] Unless otherwise defined herein, the scientific and technical terms used in conjunction with this invention shall have the meanings commonly understood by one of ordinary skill in the art. The meaning and scope of terms shall be clear; however, in any case of potential ambiguity, the definitions provided herein shall prevail over any dictionary or foreign definitions. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms is non-limiting.

[0053] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] In a first aspect, the present invention provides a solar cell that solves the problem that solar cells, particularly back-contact solar cells, generate localized high temperatures under partial shading conditions, thereby causing damage to the device or system.

[0055] like Figure 1 or Figure 2 As shown, the solar cell includes a semiconductor substrate 1, the semiconductor substrate 1 includes a first surface and a second surface disposed opposite to each other, and the first surface includes a first polar region 10 and a second polar region 20, and a spacer region 30 disposed between the first polar region 10 and the second polar region 20. Wherein, the semiconductor substrate of the first polar region 10 includes at least one first doped portion 11, and the semiconductor substrate of the second polar region 20 includes at least one second doped portion 21; the first doped portion 11 and the second doped portion 21 have opposite conductivity types. The semiconductor substrate of the spacer region 30 includes a third doped portion 31; the third doped portion 31 is disposed between the first doped portion 11 and the second doped portion 21; At least a portion of the conductivity type of the third doped portion 31 is the same as that of the first doped portion 11. And / or, at least a portion of the conductivity type of the third doped portion 31 is the same as the conductivity type of the second doped portion 21.

[0056] It should be noted that this invention constructs a bypass channel located inside the silicon substrate without dielectric layer isolation by setting a third doped region within the semiconductor substrate in the spacer region, and making it have the same conductivity type as the first or second doped region but with a higher doping concentration ratio. Since the doped regions are in direct contact, the carrier transport barrier and contact resistance are significantly reduced, allowing the bypass channel to conduct earlier at a lower reverse bias voltage. This provides a non-destructive discharge path for reverse current when the battery is partially blocked, effectively preventing avalanche breakdown and concentrated energy release in the main PN junction. This significantly reduces the risk of localized high temperatures caused by hot spot effects, improving component safety and long-term reliability. Simultaneously, the reasonable doping concentration gradient design balances current conduction efficiency and material interface stability, preventing lattice defects or increased leakage current due to abrupt doping changes. This optimizes the overall performance and process feasibility of the bypass structure, solving the technical bottleneck of excessively high bypass turn-on voltage caused by dielectric layer isolation in traditional back-contact batteries.

[0057] As an optional implementation, at least a portion of the conductivity type of the third doped portion 31 is the same as that of the first doped portion 11, and the ratio of the doping concentration of the third doped portion to the doping concentration of the first doped portion is (1.1~20):1, for example, it can be 1.1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1, 13:1, 14:1, 15:1, 16:1, 17:1, 18:1, 19:1, 20:1, etc.

[0058] As an optional implementation, the difference between the junction depth of the third doped portion 31 and the junction depth of the first doped portion 11 is 200~1000 nm, for example, it can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, etc.

[0059] In a preferred embodiment, at least a portion of the conductivity type of the third doped portion 31 is the same as that of the first doped portion 11; and the difference between the junction depth of the third doped portion 31 and the junction depth of the first doped portion 11 is 300~800 nm, for example, it can be 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, etc.

[0060] It should be noted that by controlling the junction depth difference between the third doped region and the first doped region within 200–1000 nm (preferably 300–800 nm), good electrical connection and stress balance between the doped regions in the bypass channel are achieved. An appropriate junction depth difference helps to increase the contact area between the two regions within the substrate, reduce interface resistance, and improve reverse current conduction capability; simultaneously, it avoids lattice mismatch or increased carrier recombination caused by abrupt junction depth changes. This structure optimizes the bandgap transition, making carrier transport smoother, which is beneficial for reducing the turn-on voltage of the bypass channel and improving shunt efficiency during hot spot occurrence. Furthermore, a reasonable junction depth difference can reduce stress concentration caused by doping diffusion during the process, enhance structural stability, prevent leakage or performance degradation, thereby improving the reliability and yield of the battery.

[0061] As an optional implementation, at least a portion of the conductivity type of the third doped portion 31 is the same as that of the second doped portion 21, and the ratio of the doping concentration of the third doped portion to the doping concentration of the second doped portion is (1.1~30):1, for example, it can be 1.1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, 11:1, 12:1, 13:1, 14:1, 15:1, 16:1, 17:1, 18:1, 19:1, 20:1, 21:1, 22:1, 23:1, 24:1, 25:1, 26:1, 27:1, 28:1, 29:1, 30:1, etc.

[0062] As an optional implementation, at least a portion of the conductivity type of the third doped portion 31 is the same as that of the second doped portion 21; and the difference between the junction depth of the third doped portion 31 and the junction depth of the second doped portion 21 is 200~1000 nm, for example, it can be 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, etc.

[0063] In a preferred embodiment, at least a portion of the conductivity type of the third doped portion 31 is the same as that of the second doped portion 21; and the difference between the junction depth of the third doped portion 31 and the junction depth of the second doped portion 21 is 300~800 nm, for example, it can be 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, etc.

[0064] It should be noted that by controlling the junction depth difference between the two components within 200~1000 nm (preferably 300~800 nm), this invention achieves a good electrical connection between them within the semiconductor substrate, expands the contact interface, and reduces the carrier transport barrier. This structure helps to smooth the bandgap transition, improves the conduction efficiency of reverse current in the bypass channel, and enables the cell to conduct the shunt path earlier and more uniformly when partially shaded, effectively suppressing the hot spot effect. The reasonable junction depth difference avoids increased resistance or stress concentration caused by excessive overlap or separation of doped regions, reducing interface defects and recombination losses. Simultaneously, this design considers process stability, prevents performance fluctuations caused by excessive or insufficient diffusion, improves device consistency and reliability, ensures stable triggering of the bypass function, and enhances the safety and durability of back-contact solar cells under reverse bias.

[0065] As an optional implementation, the third doped portion 31 has a P-type conductivity or an N-type conductivity.

[0066] As an optional implementation method, such as Figure 1 As shown, the semiconductor substrate surface of the interval region 30 is opposite to the semiconductor substrate surfaces of the first polar region 10 and the second polar region 20, and the semiconductor substrate surface of the interval region is recessed along the thickness direction of the semiconductor substrate to form a groove structure.

[0067] As an optional implementation, the ratio of the junction depth of the third doped portion 31 to the depth of the groove structure is (0.3~10):1, for example, it can be 0.3:1, 1:1, 2:1, 3:1, 4:1, 5:1, 6:1, 7:1, 8:1, 9:1, 10:1, etc.

[0068] As an optional implementation, the depth of the groove structure is 5 nm or more, for example, it can be 5 nm, 10 nm, 50 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, 1000 nm, etc.

[0069] As an optional implementation, the width of the groove structure is 0.01~15 μm, for example, it can be 0.01 μm, 0.05 μm, 0.1 μm, 0.5 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, 12 μm, 13 μm, 14 μm, 15 μm, etc.

[0070] As an optional implementation method, such as Figure 2As shown, the surface of the semiconductor substrate 1 of the spacing region 30 is coplanar with at least one of the surfaces of the semiconductor substrate 1 of the first polar region 10 and the second polar region 20.

[0071] As an optional implementation, the solar cell includes a back-contact solar cell.

[0072] As an optional implementation, the first surface is the back side of the solar cell.

[0073] As an optional implementation, the second surface is the front side of the solar cell.

[0074] As an optional implementation, the semiconductor substrate includes a silicon semiconductor substrate.

[0075] As an optional implementation method, such as Figure 1 or Figure 2 As shown, The solar cell further includes a fourth doped portion 111, which is disposed between the first doped portion 11 and the third doped portion 31. The fourth doped portion 111 is at least partially located in the first polar region 10. The fourth doped portion 111 has the same conductivity type as the first doped portion 11.

[0076] It should be noted that by placing a fourth doped section with a higher doping concentration adjacent to the third doped section, and ensuring that it is at least partially located within the first polarity region, the contact resistance of the critical connection region in the bypass channel is effectively reduced. The fourth doped section, acting as a highly doped "bridging region," enhances the current conduction capability between the first and third doped sections, reduces the barrier region width, and improves carrier transport efficiency, enabling the bypass channel to conduct at lower voltages and significantly suppressing hot spot effects. The layout within the first polarity region further ensures the continuity and integrity of the bypass channel structure, ensuring the uniformity of the reverse turn-on voltage of the bypass channel between different regions and different cells, thereby improving the battery's safety, reliability, and mass production adaptability.

[0077] As an optional implementation, the doping concentration of the fourth doped portion 111 is greater than the doping concentration of the first doped portion 11, and the ratio between the doping concentration of the fourth doped portion 111 and the doping concentration of the first doped portion 11 is (1.01~50):1, for example, it can be 1.01:1, 2:1, 4:1, 6:1, 8:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, 40:1, 45:1, 50:1, etc.

[0078] In a preferred embodiment, the doping concentration of the fourth doped portion 111 is greater than the doping concentration of the first doped portion 11, and the ratio between the doping concentration of the fourth doped portion 111 and the doping concentration of the first doped portion 11 is (1.1~15):1.

[0079] It should be noted that the doping concentration ratio between the fourth doped part and the first doped part needs to be maintained within a certain range. A moderate difference in doping concentration can balance current conduction and stress control. An appropriate concentration gradient ensures efficient carrier transport while maintaining material stability and optimizing the conductivity and reliability of the bypass channel.

[0080] As an optional implementation, when the doping type of the first doped portion and the fourth doped portion is P-type, the doping concentration of the fourth doped portion is 1 E19~1 E20 atm. cm. -3 For example, it could be 1 E19 atm. cm -3 2 E19atm. cm -3 3 E19 atm. cm -3 4 E19 atm. cm -3 5 E19 atm. cm -3 6 E19 atm. cm -3 7 E19atm. cm -3 8 E19 atm. cm -3 9 E19 atm. cm -3 1 E20 atm. cm -3 And so on; and the doping concentration of the first doped portion is 5 E18~1 E20 atm. cm. -3 For example, it could be 5 E18 atm. cm -3 6 E18 atm. cm -3 7 E18atm. cm -3 8 E18 atm. cm -3 9 E18 atm. cm -3 1 E19 atm. cm -3 2 E19 atm. cm -3 3 E19atm. cm -3 4 E19 atm. cm -3 5 E19 atm. cm -3 6 E19 atm. cm -3 7 E19 atm. cm -3 8 E19atm. cm -39 E19 atm. cm -3 1 E20 atm. cm -3 wait.

[0081] As an optional implementation, when the doping type of the first doped portion and the fourth doped portion is N-type, the doping concentration of the fourth doped portion is 1 E20~1 E21 atm. cm. -3 For example, it could be 1 E20 atm. cm -3 2 E20atm. cm -3 3 E20 atm. cm -3 4 E20 atm. cm -3 5 E20 atm. cm -3 6 E20 atm. cm -3 7 E20atm. cm -3 8 E20 atm. cm -3 9 E20 atm. cm -3 1 E21 atm. cm -3 And so on; and the doping concentration of the first doped portion is 5 E18~3 E20 atm. cm. -3 For example, it could be 5 E18 atm. cm -3 6 E18 atm. cm -3 7 E18atm. cm -3 8 E18 atm. cm -3 9 E18 atm. cm -3 1 E19 atm. cm -3 2 E19 atm. cm -3 3 E19atm. cm -3 4 E19 atm. cm -3 5 E19 atm. cm -3 6 E19 atm. cm -3 7 E19 atm. cm -3 8 E19atm. cm -3 9 E19 atm. cm -3 1 E20 atm. cm -3 2 E20 atm. cm -3 3 E20 atm. cm -3 wait.

[0082] As an optional implementation, in the thickness direction of the semiconductor substrate, the junction depth of the fourth doped portion 111 is greater than the junction depth of the first doped portion 11.

[0083] It should be noted that the junction depth of the fourth doped part is greater than that of the first doped part, which can increase the contact area with the third doped part, widen the reverse current path, and reduce the current density and on-resistance. At the same time, it helps to reduce the concentration of local electric field, improve the thermal stability of the bypass channel, and enable the integrated bypass structure to conduct earlier and more uniformly under reverse bias, effectively suppressing the hot spot effect and improving battery safety and durability.

[0084] As an optional implementation, the difference between the junction depth of the fourth doped portion 111 and the junction depth of the first doped portion 11 is 200~1000 nm, for example, it can be 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc.

[0085] It should be noted that the difference in junction depth between the fourth doped part and the first doped part needs to be maintained within a certain range. A moderate junction depth difference can balance the conduction performance and process reliability, avoid stress concentration or uneven doping caused by excessive steepness, ensure stable conduction of the bypass channel, and improve the reverse voltage withstand capability and yield of the battery.

[0086] As an optional implementation, the thickness of the fourth doped portion 111 is 400~800 nm, for example, it can be 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, etc.

[0087] As an optional implementation, the thickness of the first doped portion 11 is 10~200 nm, for example, it can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, etc.

[0088] As an optional implementation method, such as Figure 1 and Figure 2 As shown, the solar cell further includes a fifth doped portion 211, which is disposed between the second doped portion 21 and the third doped portion 31. The fifth doped portion 211 and the third doped portion 31 have the same conductivity type, and the fifth doped portion 211 is at least partially located in the spacing region 30.

[0089] It should be noted that by setting a fifth doped part on the side adjacent to the third doped part of the second doped part, with the same conductivity type and lower doping concentration as the third doped part, a gradient transition structure from the third doped part to the second doped part is constructed. During normal operation of the solar cell, the fifth doped part increases the width of the equivalent diode junction depletion layer of the bypass channel, reduces the saturation current density of the junction, and avoids the bypass channel negatively impacting the cell conversion efficiency. When the solar cell is shaded, the band gradient causes the bypass channel to open "layer by layer" under reverse bias, reducing the carrier transport barrier at the interface and improving the uniformity and efficiency of reverse current conduction in the bypass channel. The fifth doped part acts as a "buffer layer," mitigating lattice stress and defect generation caused by abrupt changes in doping levels (high-low doping), reducing interface recombination and leakage risks, and improving device reliability. The fifth doped part is at least partially located in the spacer region, ensuring direct contact with the third doped part, strengthening electrical connection, and improving the overall conductivity of the bypass channel. This structure optimizes the electrical continuity of the bypass path, enabling the battery to activate the shunt mechanism earlier and more stably when partially shaded, significantly reducing the reverse turn-on voltage and the highest local temperature, thereby effectively suppressing the hot spot effect and enhancing the safety, durability, and mass production stability of back-contact solar cells.

[0090] As an optional implementation, the doping concentration of the fifth doped portion 211 is less than the doping concentration of the third doped portion 31, and the ratio between the doping concentration of the third doped portion 31 and the doping concentration of the fifth doped portion 211 is (1.01~10):1, for example, it can be 1.01:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1, 5.5:1, 6:1, 6.5:1, 7:1, 7.5:1, 8:1, 8.5:1, 9:1, 9.5:1, 10:1, etc.

[0091] It should be noted that maintaining the concentration ratio of the third and fifth doped portions within a certain range can optimize the band transition, reduce the carrier transport barrier, and improve the conduction uniformity of the bypass channel. At the same time, it avoids lattice mismatch and defects caused by abrupt doping changes, reduces the risk of leakage, ensures stable current shunting, effectively suppresses hot spot effects, and improves the reverse voltage withstand performance and long-term reliability of the battery.

[0092] As an optional implementation, when the third and fifth doped portions are p-type, the doping concentration of the third doped portion is 1 E19~1 E20 atm.cm. -3 For example, it could be 1 E19 atm. cm -3 2 E19 atm.cm -3 3 E19 atm. cm -34 E19 atm. cm -3 5 E19 atm. cm -3 6 E19 atm. cm -3 7 E19 atm.cm -3 8 E19 atm. cm -3 9 E19 atm. cm -3 1 E20 atm. cm -3 And so on, and the doping concentration of the fifth doped portion is 5 E18~5 E19 atm.cm -3 For example, it could be 5 E18 atm.cm -3 6 E18 atm.cm -3 7 E18 atm.cm -3 8 E18 atm.cm -3 9 E18 atm.cm -3 1 E19 atm.cm -3 2 E19 atm.cm -3 3 E19 atm.cm -3 4 E19atm.cm -3 5 E19 atm.cm -3 wait.

[0093] As an optional implementation, when the third and fifth doped portions are N-type, the doping concentration of the third doped portion is 1 E20~1 E21 atm.cm. -3 For example, it could be 1 E20 atm. cm -3 2 E20 atm.cm -3 3 E20 atm. cm -3 4 E20 atm. cm -3 5 E20 atm. cm -3 6 E20 atm. cm -3 7 E20 atm.cm -3 8 E20 atm. cm -3 9 E20 atm. cm -3 1 E21 atm. cm -3 And the doping concentration of the fifth doped portion is 5 E19~1 E21 atm.cm -3 For example, it could be 5 E19 atm.cm -3 6 E19 atm.cm -3 7 E19 atm.cm-3 8 E19 atm.cm -3 9 E19 atm.cm -3 1 E20 atm. cm -3 2 E20 atm. cm -3 3 E20 atm. cm -3 4E20 atm. cm -3 5 E20 atm. cm -3 6 E20 atm. cm -3 7 E20 atm. cm -3 8 E20 atm. cm -3 9E20 atm. cm -3 1 E21 atm.cm -3 wait.

[0094] As an optional implementation, the junction depth of the fifth doped portion 211 is greater than the junction depth of the second doped portion 21 along the thickness direction of the semiconductor substrate.

[0095] It should be noted that the fifth doped region has a greater junction depth than the second doped region, which increases the contact area with the third doped region, widens the reverse current conduction path, and reduces current density and on-resistance. This helps to disperse the local electric field, reduce heat concentration, improve the conductivity and thermal stability of the bypass channel, and enable the battery to form non-destructive shunt earlier under shaded conditions, effectively suppressing the hot spot effect.

[0096] As an optional implementation, the difference between the junction depth of the fifth doped portion 211 and the junction depth of the second doped portion 21 is 200~1000 nm, for example, it can be 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, etc.

[0097] It should be noted that the junction depth difference between the fifth doped part and the second doped part needs to be maintained within a certain range. A moderate junction depth difference can ensure a smooth current transition and avoid stress concentration or interface defects caused by sudden changes. This ensures the conduction efficiency of the bypass channel, maintains structural stability, prevents local overheating or leakage, and improves the reliability and yield of the battery under reverse bias.

[0098] As an optional implementation, the thickness of the fifth doped portion 211 is 400~800 nm, for example, it can be 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, etc.

[0099] As an optional implementation, the thickness of the second doped portion 21 is 10~200 nm, for example, it can be 10 nm, 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, etc.

[0100] As an optional implementation, the doping concentration of the second doped portion 21 is 5 E18~3 E20 atm.cm. -3 For example, it could be 5 E18 atm.cm -3 6 E18 atm.cm -3 7 E18 atm.cm -3 8 E18 atm.cm -3 9 E18atm.cm -3 1 E19 atm.cm -3 2 E19 atm.cm -3 3 E19 atm. cm -3 4 E19 atm. cm -3 5 E19atm. cm -3 6 E19 atm. cm -3 7 E19 atm. cm -3 8 E19 atm. cm -3 9 E19 atm. cm -3 1 E20atm. cm -3 2 E20 atm. cm -3 3 E20 atm. cm -3 wait.

[0101] As an optional implementation, the thickness of the third doped portion 31 is 400~800 nm, for example, it can be 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, etc.

[0102] As an optional implementation, a fifth doped portion 211 is provided adjacent to the third doped portion 31, and the fifth doped portion 211 has the same conductivity type as the third doped portion 31; the fifth doped portion 211 contains at least two doping elements with different conductivity types, and the fifth doped portion 211 is at least partially disposed in the interval region.

[0103] As an optional implementation, the fourth doping section 111 contains at least two doping elements of different conductivity types; or, the fifth doping section 211 contains at least two doping elements of different conductivity types.

[0104] As an optional embodiment, the solar cell further includes a fourth doped part 111 and a fifth doped part 211, wherein the fourth doped part 111 is disposed between the first doped part 11 and the third doped part 31, and the fourth doped part 111 has the same conductivity type as the first doped part 11. The fifth doped portion 211 is disposed between the second doped portion 21 and the third doped portion 31, and the conductivity type of the fifth doped portion 211 is the same as that of the third doped portion 31. The first doped portion 11, the fourth doped portion 111, the third doped portion 31, the fifth doped portion 211, and the second doped portion 21 are connected sequentially. As an optional implementation, such as... Figure 1 and Figure 2 As shown, the first doped part 11, the third doped part 31, and the second doped part 21 electrically form a bypass channel.

[0105] As an optional implementation method, such as Figure 1 or Figure 2 As shown, the first doped part 11, the fourth doped part 111, the third doped part 31, the fifth doped part 211, and the second doped part 21 form a bypass channel.

[0106] As an optional implementation method, such as Figure 3 As shown, the first polar region 10 and the second polar region 20 are spaced apart, and at least a portion of the substrate in the spacer region between the first polar region 10 and the second polar region 20 is provided with a third doped portion 31.

[0107] As an optional implementation, the third doped portion 31 includes at least two third doped portions 31, which are discontinuously arranged along a direction intersecting the first polar region 10 and the second polar region 20. The distance between adjacent third doped portions is 1 to 10 mm, for example, it can be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.

[0108] As an optional implementation method, such as Figure 4 As shown, the second polar region 20 is disposed around the first polar region 10, and at least a portion of the substrate in the spacer region between the first polar region 10 and the second polar region 20 is provided with a third doped portion 31.

[0109] As an optional implementation, when the doping type of the first doped portion, the fourth doped portion, the third doped portion, and the fifth doped portion is P-type, the doping elements in the first doped portion, the fourth doped portion, the third doped portion, and the fifth doped portion include any one or a combination of at least two of boron, aluminum, gallium, and indium; and the doping element in the third doped portion includes any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0110] As an optional implementation, when the doping type of the first doped portion, the fourth doped portion, the third doped portion, and the fifth doped portion is N-type, the doping element in the first doped portion, the fourth doped portion, the third doped portion, and the fifth doped portion includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth; and the doping element in the third doped portion includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0111] As an optional implementation method, such as Figure 1 or Figure 2 As shown, the first polar region 10 includes a first polar functional stack, which includes a first dielectric layer 101 and a first polar doped layer 102, and the first dielectric layer 101 is disposed between the first surface of the semiconductor substrate 1 and the first polar doped layer 102.

[0112] As an optional implementation, the first dielectric layer 101 is disposed only in the first polarity region 10.

[0113] As an optional implementation, the material of the first dielectric layer 101 includes any one or a combination of at least two of silicon oxide, silicon nitride, aluminum oxide, and titanium oxide.

[0114] As an optional implementation, the thickness of the first dielectric layer 101 is 0.5~2 nm, for example, it can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc.

[0115] As an optional implementation, when the first polar doped layer is P-type, the first polar doped layer 102 is a doped polycrystalline silicon layer; wherein the doping element includes any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0116] As an optional implementation, when the first polar doped layer is N-type, the first polar doped layer 102 is a doped polycrystalline silicon layer; wherein, the doping element includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0117] As an optional implementation, the thickness of the first polar doped layer 102 is 100~500 nm, for example, it can be 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 400 nm, 500 nm, etc.

[0118] As an optional implementation method, such as Figure 1 or Figure 2 As shown, the second polar region 20 includes a second polar functional stack, which includes a second dielectric layer 201 and a second polar doped layer 202, and the second dielectric layer 201 is disposed between the first surface of the semiconductor substrate 1 and the second polar doped layer 202.

[0119] As an optional implementation, the second dielectric layer 201 is disposed only in the second polarity region 20.

[0120] As an optional implementation, the material of the second dielectric layer 201 includes any one or a combination of at least two of silicon oxide, silicon nitride, aluminum oxide, and titanium oxide.

[0121] As an optional implementation, the thickness of the second dielectric layer 201 is 0.5~2 nm, for example, it can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc.

[0122] As an optional implementation, when the second polar doped layer is P-type, the second polar doped layer 202 is a doped polycrystalline silicon layer; wherein the doping element includes any one or a combination of at least two of boron, aluminum, gallium, and indium.

[0123] As an optional implementation, when the second polar doped layer is N-type, the second polar doped layer 202 is a doped polycrystalline silicon layer; wherein the doping element includes any one or a combination of at least two of phosphorus, arsenic, antimony, and bismuth.

[0124] As an optional implementation, the thickness of the second polar doped layer 202 is 100~500 nm, for example, it can be 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 400 nm, 500 nm, etc.

[0125] As an optional implementation, the first polar doped layer 102 and the second polar doped layer 202 have different doping types.

[0126] As an optional implementation, when the first polar doped layer is P-type and the second polar doped layer is N-type, the doping concentration of the first polar doped layer is 1 E19~1 E20 atm / cm². -3 The doping concentration of the second polar doped layer is 1 E20~1 E21 atm.cm -3 .

[0127] As an optional implementation, when the first polar doped layer is N-type and the second polar doped layer is P-type, the doping concentration of the first polar doped layer is 1 E20~1 E21 atm.cm. -3 The doping concentration of the second polar doped layer is 1 E19~1 E20 atm.cm. -3 .

[0128] The doping concentration described in this invention is the peak doping concentration of the doped portion obtained by testing the doped portion using known methods such as TOF-SIMS or ECV; the junction depth is the distance along the substrate thickness direction from the first surface of the substrate corresponding to the doped portion to the point where the doping element concentration of the doped portion is 1E17 atm cm. -3 Distance of location.

[0129] As an optional implementation, the first surface of the solar cell is further provided with a passivation layer, which covers the spacer region and is in direct contact with the third doped portion.

[0130] Secondly, the present invention provides a method for preparing a solar cell as described in the first aspect, such as... Figure 5 As shown, the preparation method includes: Take a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface disposed opposite to each other, and a first polar region and a second polar region are disposed on the first surface; A spacer region is formed on the first surface of the semiconductor substrate, the spacer region being disposed between the first polarity region and the second polarity region; At least one first doped portion is formed in the first polar region; at least one third doped portion is formed in the interval region; At least one second doped portion is formed in the second polar region to obtain the solar cell; The third doped portion is disposed between the first doped portion and the second doped portion; at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of either the first doped portion or the second doped portion. That is, at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of the first doped portion; and / or, at least a portion of the conductivity type of the third doped portion is the same as the conductivity type of the second doped portion.

[0131] As an optional implementation, the solar cell fabrication method includes: After the spacer region is formed, a first doped portion is formed in the first polar region; a third doped portion is formed in the spacer region. And / or, the first doped portion and the third doped portion are formed simultaneously.

[0132] As an optional implementation, the solar cell fabrication method includes: A dielectric layer, an intrinsic polysilicon layer, and a mask functional layer are sequentially deposited on the first surface of a semiconductor substrate; The mask functional layer, dielectric layer, and intrinsic polysilicon layer at the corresponding positions of the spacer region are removed to form the spacer region; Remove the mask functional layer at the corresponding position of the first conductive region, and allow the first doping element to diffuse into the polysilicon layer and semiconductor substrate corresponding to the first conductive region to form the first doped portion; at the same time, allow the first doping element to diffuse into the semiconductor substrate to form the third doped portion and the fourth doped portion. A second doping element diffusion process is performed to diffuse the second doping element into the semiconductor substrate of the second conductive region, forming a second doped portion, thereby obtaining the solar cell.

[0133] As an optional implementation, the solar cell fabrication method includes: the solar cell further includes a fourth doped portion and / or a fifth doped portion; the fourth doped portion is formed simultaneously with the formation of the first doped portion.

[0134] As an optional implementation, the solar cell fabrication method includes forming the fifth doped portion while forming the second doped portion.

[0135] As an optional implementation method, such as Figure 5 As shown, the method for preparing the solar cell includes A~G: (A) A dielectric layer 601, an intrinsic polysilicon layer 602, and a mask functional layer 603 are sequentially deposited on the first surface of the semiconductor substrate 1 to obtain the following: Figure 5 The intermediate battery cell in the structure shown in Figure A; (B) Remove the mask functional layer 603 at the position corresponding to the spacing region of the intermediate battery cell obtained in step (A), to obtain as shown. Figure 5 The intermediate battery cell in the structure shown in B; (C) Remove the dielectric layer 601 and intrinsic polysilicon layer 602 at the positions corresponding to the spacer region of the intermediate solar cell obtained in step (B) to form the spacer region 30, resulting in the following: Figure 5 The intermediate battery cell in the structure shown in C; (D) Remove the mask functional layer 603 at the position corresponding to the first polarity region of the intermediate battery cell obtained in step (C), to obtain as shown in the figure. Figure 5 The intermediate battery cell in the structure shown in D; (E) A first doped source layer 604 containing the first doped element is deposited on the first surface of the intermediate cell obtained in step (D), resulting in the following: Figure 5 The intermediate battery cell in the structure shown in E; (F) The intermediate solar cell obtained in step (E) is subjected to heat treatment to diffuse the first dopant element into the polycrystalline silicon layer and semiconductor substrate corresponding to the first polar region, forming the first polar doped layer 102 and the first doped portion 11; simultaneously, the first dopant element is diffused into the semiconductor substrate to form the third doped portion 31 and the fourth doped portion 111, resulting in the following: Figure 5 The intermediate battery cell in the structure shown in Figure F; (G) Remove the first doped source layer 604 and mask functional layer 603 at the corresponding positions of the second polar region of the intermediate cell obtained in step (F) to obtain the following: Figure 5 The intermediate battery cell in the structure shown in G; (H) The intermediate cell obtained in step (G) undergoes a second doping element diffusion treatment, causing the second doping element to diffuse into the polycrystalline silicon layer and semiconductor substrate corresponding to the second polar region, forming a second polar doped layer 202, a second doped portion 21, and a fifth doped portion 211, to obtain the solar cell (e.g., Figure 5 (Structure shown in H).

[0136] As an optional implementation, in step (A), the semiconductor substrate 1 is a silicon semiconductor substrate.

[0137] As an optional implementation, in step (A), the silicon semiconductor substrate is a silicon semiconductor substrate that has been cleaned, texturized, or alkaline polished.

[0138] As an optional implementation, in step (A), the deposition method includes any one or a combination of at least two of PECVD, LPCVD, or ALD.

[0139] As an optional implementation, in step (A), the mask functional layer 603 includes a silicon oxide layer and / or a silicon nitride layer.

[0140] As an optional implementation, in step (A), the mask functional layer 603 can also be other films and stacks with similar functions.

[0141] As an optional implementation, in step (A), the dielectric layer 601 is a tunneling oxide layer.

[0142] As an optional implementation, in step (A), the thickness of the dielectric layer 601 is 0.5~2 nm, for example, it can be 0.5 nm, 0.6 nm, 0.8 nm, 1 nm, 1.2 nm, 1.4 nm, 1.6 nm, 1.8 nm, 2 nm, etc.

[0143] As an optional implementation, in step (A), the thickness of the intrinsic polycrystalline silicon layer 602 is 100~500 nm, for example, it can be 100 nm, 120 nm, 140 nm, 150 nm, 160 nm, 180 nm, 200 nm, 220 nm, 240 nm, 260 nm, 280 nm, 300 nm, 400 nm, 500 nm, etc.

[0144] As an optional implementation, in step (A), the thickness of the mask functional layer 603 is 50~100 nm, for example, it can be 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, etc.

[0145] As an optional implementation, in step (B), the removal process is laser etching.

[0146] As an optional implementation, in step (B), the laser etching uses a laser source with etching function, which can be an ultraviolet picosecond or femtosecond laser with a wavelength of 355 nm, or a green picosecond or femtosecond laser with a wavelength of 532 nm.

[0147] As an optional implementation, in step (C), the removal process is alkaline etching.

[0148] As an optional implementation, in step (C), the base includes potassium hydroxide (KOH).

[0149] As an optional implementation, in step (D), the removal process is laser etching.

[0150] As an optional implementation, in step (D), the laser etching uses a laser source with etching function, which can be an ultraviolet picosecond or femtosecond laser with a wavelength of 355 nm, or a green picosecond or femtosecond laser with a wavelength of 532 nm.

[0151] As an optional implementation, step (D) further includes an acid washing step after removing the mask functional layer 603 at the position corresponding to the first polar region.

[0152] As an optional implementation, in step (D), the pickling is performed using an HF acid solution.

[0153] As an optional implementation, in step (D), the acid washing removes the silicon oxide residue remaining on the surface of the spacer region and the first polar region after steps (C) and (D).

[0154] As an optional implementation, in step (E), the first doped source layer 604 is a BSG layer.

[0155] As an optional implementation, in step (E), the deposition process includes PECVD or APCVD.

[0156] As an optional implementation, in step (E), the thickness of the first doped source layer 604 is 10~100 nm, for example, it can be 10 nm, 20 nm, 30 nm, 40 nm, 50 nm, 60 nm, 70 nm, 80 nm, 90 nm, 100 nm, etc.

[0157] As an optional implementation, in step (F), the temperature of the heat treatment is 850~1000℃, for example, it can be 850℃, 860℃, 880℃, 900℃, 920℃, 940℃, 950℃, 960℃, 980℃, 1000℃, etc., and the time of the heat treatment is 60~150 min, for example, it can be 60 min, 70 min, 80 min, 90 min, 100 min, 110 min, 120 min, 130 min, 140 min, 150 min, etc.

[0158] As an optional implementation, in step (G), the removal process is laser etching.

[0159] As an optional implementation, in step (G), the laser etching uses a laser source with etching function, which can be an ultraviolet picosecond or femtosecond laser with a wavelength of 355 nm, or a green picosecond or femtosecond laser with a wavelength of 532 nm.

[0160] As an optional implementation, in step (H), the diffusion treatment of the second dopant element can be carried out by using a solid dopant source containing the second dopant element, which is applied to the surface of the polycrystalline silicon layer in the second polar region by printing or spraying, and then heat treatment is performed to complete the diffusion of the second dopant element.

[0161] As an optional implementation, in step (H), the diffusion process of the second doped element can be carried out by using a gaseous dopant source carrying the second doped element in nitrogen gas. In this case, the first doped source layer 604 on the surface of the first polar region and the spacer region serves as a diffusion barrier layer, which can effectively prevent the diffusion of the second doped element.

[0162] As an optional implementation, in step (H), after the second dopant diffusion treatment, an oxide film layer containing the second dopant and / or an oxide film layer containing both the first and second dopant will be formed on the surface of the silicon wafer.

[0163] As an optional implementation, in step (H), the oxide film layer containing the second dopant element is a PSG layer.

[0164] As an optional implementation, in step (H), the oxide film layer containing both the first dopant element and the second dopant element is a BPSG layer.

[0165] As an optional implementation, in step (H), the oxide film layer containing the second dopant element and the oxide film layer containing both the first and second dopant elements are removed by acid washing.

[0166] As an optional implementation, in step (H), the acid used for pickling includes HF.

[0167] As an optional implementation, step (H) further includes depositing a passivation film layer such as alumina or silicon nitride after pickling.

[0168] As an optional implementation, in step (H), after the second doping element diffusion treatment, a second doping element doping layer and / or a co-doped layer of the first and second doping elements will be formed on the surface of the silicon wafer, which will be retained as a surface insulating layer without acid washing.

[0169] The present invention will be further illustrated by the following examples. Unless otherwise specified, the materials in the examples are prepared according to existing methods or purchased directly from the market.

[0170] Example 1 This embodiment provides a back-contact solar cell, including a silicon semiconductor substrate. The silicon semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first polar region and a second polar region, and a spacer region disposed between the first polar region and the second polar region. The first polar region includes a first polar functional stack, which comprises a first dielectric layer and a first polar doped layer. The first dielectric layer is disposed between the first surface of the semiconductor substrate and the first polar doped layer. The first dielectric layer is a first tunneling oxide layer made of silicon oxide with a thickness of 1.5 nm. The first polar doped layer is a boron-doped polycrystalline silicon layer with a thickness of 200 nm and a doping concentration of 5.3E19 atm / cm². -3 ; The second polar region includes a second polar functional stack, which comprises a second dielectric layer and a second polar doped layer. The second dielectric layer is disposed between the first surface of the semiconductor substrate and the second polar doped layer. The second dielectric layer is a second tunneling oxide layer made of silicon oxide with a thickness of 1.5 nm. The second polar doped layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 200 nm and a doping concentration of 3.1 E20 atm / cm². -3 ; The semiconductor substrate in the first polar region includes a first doped portion, the semiconductor substrate in the second polar region includes a second doped portion, and the semiconductor substrate in the spacer region includes a third doped portion; a fourth doped portion is disposed adjacent to the third doped portion, and a fifth doped portion is disposed adjacent to the third doped portion; the first doped portion, the fourth doped portion, the third doped portion, the second doped portion, and the fifth doped portion form a bypass channel; The first doped portion is doped with boron, and the doping concentration is 1.1 E19 atm.cm. -3 The thickness is 110 nm; the fourth doped part is doped with boron, and the doping concentration is 5.3 E19 atm / cm. -3 The width is 420 nm and the thickness is 600 nm; the third doped part is doped with boron at a concentration of 5.3 E19 atm / cm². -3 The width is 4000 nm and the thickness is 600 nm; the fifth doped part is doped with boron at a concentration of 3.6 E19 atm / cm². -3 The width is 370 nm and the thickness is 600 nm; the second doped part is doped with phosphorus at a concentration of 4.3 E19 cm⁻¹.-3 The thickness is 70nm; Wherein, the semiconductor substrate surface of the interval region is recessed along the thickness direction of the semiconductor substrate relative to the semiconductor substrate surfaces of the first polar region and the second polar region, and the interval region forms a groove structure; the depth of the groove structure is 550 nm.

[0171] The method for preparing the solar cell described in this embodiment includes the following steps: (A) On a silicon semiconductor substrate that has been cleaned and texturized, a multilayer electrolyte film is deposited by PECVD, including a tunneling oxide layer, an intrinsic polycrystalline silicon layer, and a mask functional layer deposited sequentially; wherein the mask functional layer is a silicon nitride layer, the thickness of the tunneling oxide layer is 1.5 nm, the thickness of the intrinsic polycrystalline silicon layer is 200 nm, and the thickness of the mask functional layer is 80 nm. (B) The mask functional layer at the position corresponding to the interval region of the intermediate battery cell obtained in step (A) is removed by laser etching; wherein the laser source with etching effect is an ultraviolet picosecond laser with a wavelength of 355 nm. (C) Perform KOH etching on the intermediate cell obtained in step (B) to remove the dielectric layer and intrinsic polysilicon layer at the corresponding positions of the spacer region to form the spacer region; (D) The mask functional layer at the corresponding position of the first polar region of the intermediate cell obtained in step (C) is removed by laser etching; wherein, the laser source with etching effect is a 355 nm ultraviolet picosecond laser; then, HF acid solution is used for cleaning to remove the silicon oxide remaining on the surface of the spacer region and the first polar region after steps (C) and (D). (E) A BSG layer is deposited on the first surface of the intermediate cell obtained in step (D) by PECVD; wherein the thickness of the BSG layer is 40 nm; (F) The silicon wafer after depositing the BSG layer in the intermediate solar cell obtained in step (E) is subjected to heat treatment. Boron in the BSG diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the first polar region through heat treatment, forming the first polar doped layer and the first doped part. The heat treatment process causes the boron in the BSG layer in the spacer region to diffuse into the semiconductor substrate to form the third doped part and the fourth doped part. Due to the diffusion blocking effect of the surface mask functional layer 603, the boron in the BSG cannot diffuse into the intrinsic polycrystalline silicon layer corresponding to the second polar region. The relevant process parameters of the heat treatment include: heat treatment temperature 930℃ and heat treatment time 120 min. (G) The first doped source layer and mask functional layer at the corresponding position of the second polar region of the intermediate cell obtained in step (F) are removed by laser etching to expose the underlying intrinsic polysilicon layer; wherein, the laser source with etching function is an ultraviolet picosecond laser with a wavelength of 355 nm. (H) The intermediate cell obtained in step (G) is subjected to phosphorus diffusion treatment, so that the second doping element diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the second polar region, forming a second polar doped layer, a second doped part and a fifth doped part, to obtain the solar cell; wherein, the relevant process parameters of the phosphorus diffusion treatment include: diffusion temperature 860℃ and diffusion time 90 min.

[0172] Example 2 This embodiment provides a back-contact solar cell, including a silicon semiconductor substrate. The silicon semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first polar region and a second polar region, and a spacer region disposed between the first polar region and the second polar region. The first polar region includes a first polar functional stack, which comprises a first dielectric layer and a first polar doped layer. The first dielectric layer is disposed between the first surface of the semiconductor substrate and the first polar doped layer. The first dielectric layer is a first tunneling oxide layer made of silicon oxide with a thickness of 0.5 nm. The first polar doped layer is a boron-doped polycrystalline silicon layer with a thickness of 100 nm and a doping concentration of 1 E19 atm / cm². -3 ; The second polar region includes a second polar functional stack, which comprises a second dielectric layer and a second polar doped layer. The second dielectric layer is disposed between the first surface of the semiconductor substrate and the second polar doped layer. The second dielectric layer is a second tunneling oxide layer made of silicon oxide with a thickness of 0.5 nm. The second polar doped layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 100 nm and a doping concentration of 1 E20 atm / cm². -3 ; The semiconductor substrate in the first polar region includes a first doped portion, the semiconductor substrate in the second polar region includes a second doped portion, and the semiconductor substrate in the spacer region includes a third doped portion; a fourth doped portion is disposed adjacent to the third doped portion, and a fifth doped portion is disposed adjacent to the third doped portion; the first doped portion, the fourth doped portion, the third doped portion, the second doped portion, and the fifth doped portion form a bypass channel; The first doped portion is doped with boron at a concentration of 5 E18 atm.cm. -3The thickness is 10 nm; the fourth doped part is doped with boron, and the doping concentration is 1 E19 atm.cm. -3 The width is 260 nm and the thickness is 400 nm; the dopant element of the third doped part is boron, and the doping concentration is 1 E19 atm.cm. -3 The width is 1500 nm and the thickness is 400 nm; the fifth doped part is doped with boron at a concentration of 8E18 atm.cm. -3 The width is 200 nm and the thickness is 400 nm; the dopant element of the second doped part is phosphorus, and the doping concentration is 5 E18 atm.cm. -3 The thickness is 10nm; Wherein, the semiconductor substrate surface of the interval region is recessed along the thickness direction of the semiconductor substrate relative to the semiconductor substrate surfaces of the first polar region and the second polar region, and the interval region forms a groove structure; the depth of the groove structure is 5 nm.

[0173] The method for preparing the solar cell described in this embodiment includes the following steps: (A) On a silicon semiconductor substrate that has been cleaned and texturized, a multilayer electrolyte film is deposited by PECVD, including a tunneling oxide layer, an intrinsic polycrystalline silicon layer, and a mask functional layer deposited sequentially; wherein the mask functional layer is a silicon nitride layer, the thickness of the tunneling oxide layer is 0.5 nm, the thickness of the intrinsic polycrystalline silicon layer is 100 nm, and the thickness of the mask functional layer is 50 nm. (B) The mask functional layer at the position corresponding to the interval region of the intermediate battery cell obtained in step (A) is removed by laser etching; wherein the laser source with etching effect is an ultraviolet picosecond laser with a wavelength of 355 nm. (C) Perform KOH etching on the intermediate cell obtained in step (B) to remove the dielectric layer and intrinsic polysilicon layer at the corresponding positions of the spacer region to form the spacer region; (D) The mask functional layer at the corresponding position of the first polar region of the intermediate cell obtained in step (C) is removed by laser etching; wherein, the laser source with etching effect is a 355 nm ultraviolet picosecond laser; then, HF acid solution is used for cleaning to remove the silicon oxide remaining on the surface of the spacer region and the first polar region after steps (C) and (D). (E) A BSG layer is deposited on the first surface of the intermediate cell obtained in step (D) by PECVD; wherein the thickness of the BSG layer is 10 nm; (F) The silicon wafer after depositing the BSG layer in the intermediate solar cell obtained in step (E) is subjected to heat treatment. Boron in the BSG diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the first polar region through heat treatment, forming the first polar doped layer and the first doped part. The heat treatment process causes the boron in the BSG layer in the spacer region to diffuse into the semiconductor substrate to form the third doped part and the fourth doped part. Due to the diffusion blocking effect of the surface mask functional layer 603, the boron in the BSG cannot diffuse into the intrinsic polycrystalline silicon layer corresponding to the second polar region. The relevant process parameters of the heat treatment include: heat treatment temperature 850℃, heat treatment time 60 min. (G) The first doped source layer and mask functional layer at the corresponding position of the second polar region of the intermediate cell obtained in step (F) are removed by laser etching to expose the underlying intrinsic polysilicon layer; wherein, the laser source with etching function is an ultraviolet picosecond laser with a wavelength of 355 nm. (H) The intermediate cell obtained in step (G) is subjected to phosphorus diffusion treatment, so that the second doping element diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the second polar region, forming a second polar doped layer, a second doped part and a fifth doped part, to obtain the solar cell; wherein, the relevant process parameters of the phosphorus diffusion treatment include: diffusion temperature 820℃ and diffusion time 60 min.

[0174] Example 3 This embodiment provides a back-contact solar cell, including a silicon semiconductor substrate. The silicon semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first polar region and a second polar region, and a spacer region disposed between the first polar region and the second polar region. The first polar region includes a first polar functional stack, which comprises a first dielectric layer and a first polar doped layer. The first dielectric layer is disposed between the first surface of the semiconductor substrate and the first polar doped layer. The first dielectric layer is a first tunneling oxide layer made of silicon oxide with a thickness of 2 nm. The first polar doped layer is a boron-doped polycrystalline silicon layer with a thickness of 500 nm and a doping concentration of 1 E20 atm / cm². -3 ; The second polar region includes a second polar functional stack, which comprises a second dielectric layer and a second polar doped layer. The second dielectric layer is disposed between the first surface of the semiconductor substrate and the second polar doped layer. The second dielectric layer is a second tunneling oxide layer made of silicon oxide with a thickness of 2 nm. The second polar doped layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 500 nm and a doping concentration of 1 E21 atm / cm². -3 ; The semiconductor substrate in the first polar region includes a first doped portion, the semiconductor substrate in the second polar region includes a second doped portion, and the semiconductor substrate in the spacer region includes a third doped portion; a fourth doped portion is disposed adjacent to the third doped portion, and a fifth doped portion is disposed adjacent to the third doped portion; the first doped portion, the fourth doped portion, the third doped portion, the second doped portion, and the fifth doped portion form a bypass channel; The first doped portion is doped with boron, and the doping concentration is 5 E19 atm.cm. -3 The thickness is 200 nm; the fourth doped part is doped with boron, and the doping concentration is 1 E20 atm.cm. -3 The width is 550 nm and the thickness is 800 nm; the dopant element of the third doped part is boron, and the doping concentration is 1 E20 atm.cm. -3 The width is 50,000 nm and the thickness is 800 nm; the fifth doped part is doped with boron at a concentration of 9 E19 atm.cm. -3 The width is 480 nm and the thickness is 800 nm; the dopant element of the second doped part is phosphorus, and the doping concentration is 3 E20 atm.cm. -3 The thickness is 200nm; Wherein, the semiconductor substrate surface of the interval region is recessed along the thickness direction of the semiconductor substrate relative to the semiconductor substrate surfaces of the first polar region and the second polar region, and the interval region forms a groove structure; the depth of the groove structure is 2000 nm.

[0175] The method for preparing the solar cell described in this embodiment includes the following steps: (A) On a silicon semiconductor substrate that has been cleaned and texturized, a multilayer electrolyte film is deposited by PECVD, including a tunneling oxide layer, an intrinsic polycrystalline silicon layer, and a mask functional layer deposited sequentially; wherein the mask functional layer is a silicon nitride layer, the thickness of the tunneling oxide layer is 2 nm, the thickness of the intrinsic polycrystalline silicon layer is 500 nm, and the thickness of the mask functional layer is 100 nm. (B) The mask functional layer at the position corresponding to the interval region of the intermediate battery cell obtained in step (A) is removed by laser etching; wherein the laser source with etching effect is an ultraviolet picosecond laser with a wavelength of 355 nm. (C) Perform KOH etching on the intermediate cell obtained in step (B) to remove the dielectric layer and intrinsic polysilicon layer at the corresponding positions of the spacer region to form the spacer region; (D) The mask functional layer at the corresponding position of the first polar region of the intermediate cell obtained in step (C) is removed by laser etching; wherein, the laser source with etching effect is a 355 nm ultraviolet picosecond laser; then, HF acid solution is used for cleaning to remove the silicon oxide remaining on the surface of the spacer region and the first polar region after steps (C) and (D). (E) A BSG layer is deposited on the first surface of the intermediate cell obtained in step (D) by PECVD; wherein the thickness of the BSG layer is 100 nm; (F) The silicon wafer after depositing the BSG layer in the intermediate solar cell obtained in step (E) is subjected to heat treatment. Boron in the BSG diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the first polar region through heat treatment, forming the first polar doped layer and the first doped part. The heat treatment process causes the boron in the BSG layer in the spacer region to diffuse into the semiconductor substrate to form the third doped part and the fourth doped part. Due to the diffusion blocking effect of the surface mask functional layer 603, the boron in the BSG cannot diffuse into the intrinsic polycrystalline silicon layer corresponding to the second polar region. The relevant process parameters of the heat treatment include: heat treatment temperature 1000℃ and heat treatment time 150 min. (G) The first doped source layer and mask functional layer at the corresponding position of the second polar region of the intermediate cell obtained in step (F) are removed by laser etching to expose the underlying intrinsic polysilicon layer; wherein, the laser source with etching function is an ultraviolet picosecond laser with a wavelength of 355 nm. (H) The intermediate cell obtained in step (G) is subjected to phosphorus diffusion treatment, so that the second doping element diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the second polar region, forming a second polar doped layer, a second doped part and a fifth doped part, to obtain the solar cell; wherein, the relevant process parameters of the phosphorus diffusion treatment include: diffusion temperature 880℃ and diffusion time 120 min.

[0176] Example 4 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in that the semiconductor substrate surface of the spacer region is coplanar with the semiconductor substrate surfaces of the first polar region and the second polar region; other configurations are the same as in Embodiment 1.

[0177] Example 5 This embodiment provides a back-contact solar cell, differing from Embodiment 1 only in that the doping concentration of the fourth doped portion is 4 E19 atm.cm. -3 The doping concentration of the first doped region is 5 E19 atm.cm. -3 Other settings are the same as in Example 1.

[0178] Example 6 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in that the thickness of the fourth doped portion is 300 nm and the thickness of the first doped portion is 200 nm. Other settings are the same as in Embodiment 1.

[0179] Example 7 This embodiment provides a back-contact solar cell, differing from Embodiment 1 only in that the doping concentration of the fifth doped portion is 2.5 E19 atm.cm. -3 The doping concentration of the third doped region is 1 E19 atm.cm. -3 Other settings are the same as in Example 1.

[0180] Example 8 This embodiment provides a back-contact solar cell, which differs from Embodiment 1 only in that the thickness of the fifth doped part is 300 nm and the thickness of the second doped part is 200 nm, while the other settings are the same as in Embodiment 1.

[0181] Example 9 This embodiment provides a back-contact solar cell, differing from Embodiment 1 only in that the doping concentration of the fourth doped portion is 5.5 E19 atm.cm. -3 The doping concentration of the first doped region is 5.1 E19 atm / cm. -3 Other settings are the same as in Example 1.

[0182] Example 10 This embodiment provides a back-contact solar cell, differing from Embodiment 1 only in that the doping concentration of the fourth doped portion is 1 E20 atm.cm. -3 The doping concentration of the first doped region is 5 E18 atm.cm. -3 Other settings are the same as in Example 1.

[0183] Example 11 This embodiment provides a back-contact solar cell, including a silicon semiconductor substrate. The silicon semiconductor substrate includes a first surface and a second surface disposed opposite to each other. The first surface includes a first polar region and a second polar region, and a spacer region disposed between the first polar region and the second polar region. The first polar region includes a first polar functional stack, which comprises a first dielectric layer and a first polar doped layer. The first dielectric layer is disposed between the first surface of the semiconductor substrate and the first polar doped layer. The first dielectric layer is a first tunneling oxide layer made of silicon oxide with a thickness of 1.5 nm. The first polar doped layer is a phosphorus-doped polycrystalline silicon layer with a thickness of 255 nm and a doping concentration of 2.95E20 atm / cm². -3 ; The second polar region includes a second polar functional stack, which comprises a second dielectric layer and a second polar doped layer. The second dielectric layer is disposed between the first surface of the semiconductor substrate and the second polar doped layer. The second dielectric layer is a second tunneling oxide layer made of silicon oxide with a thickness of 1.5 nm. The second polar doped layer is a boron-doped polycrystalline silicon layer with a thickness of 255 nm and a doping concentration of 4.72 E19 atm / cm². -3 ; The semiconductor substrate in the first polar region includes a first doped portion, the semiconductor substrate in the second polar region includes a second doped portion, and the semiconductor substrate in the spacer region includes a third doped portion; a fourth doped portion is disposed adjacent to the third doped portion, and a fifth doped portion is disposed adjacent to the third doped portion; the first doped portion, the fourth doped portion, the third doped portion, the second doped portion, and the fifth doped portion form a bypass channel; The first doped portion is doped with phosphorus, and the doping concentration is 3.98 E19 atm / cm². -3 The thickness is 90 nm; the fourth doped part is doped with phosphorus, and the doping concentration is 2.95 E20 atm / cm. -3 The width is 430 nm and the thickness is 700 nm; the dopant element of the third doped part is phosphorus, and the doping concentration is 2.95 E20 atm.cm. -3 The width is 5200 nm and the thickness is 700 nm; the fifth doped part is doped with phosphorus at a concentration of 1.5 E19 atm / cm³. -3 The width is 310 nm and the thickness is 700 nm; the second doped part is doped with boron, and the doping concentration is 2.1 E19 cm⁻¹. -3 The thickness is 120 nm; Wherein, the semiconductor substrate surface of the interval region is recessed along the thickness direction of the semiconductor substrate relative to the semiconductor substrate surfaces of the first polar region and the second polar region, and the interval region forms a groove structure; the depth of the groove structure is 410 nm.

[0184] The method for preparing the solar cell described in this embodiment includes the following steps: (A) On a silicon semiconductor substrate that has been cleaned and texturized, a multilayer electrolyte film is deposited by PECVD, including a tunneling oxide layer, an intrinsic polycrystalline silicon layer, and a mask functional layer deposited sequentially; wherein the mask functional layer is a silicon nitride layer, the thickness of the tunneling oxide layer is 1.5 nm, the thickness of the intrinsic polycrystalline silicon layer is 255 nm, and the thickness of the mask functional layer is 70 nm. (B) The mask functional layer at the position corresponding to the interval region of the intermediate battery cell obtained in step (A) is removed by laser etching; wherein the laser source with etching effect is an ultraviolet picosecond laser with a wavelength of 355 nm. (C) Perform KOH etching on the intermediate cell obtained in step (B) to remove the dielectric layer and intrinsic polysilicon layer at the corresponding positions of the spacer region to form the spacer region; (D) The mask functional layer at the corresponding position of the first polar region of the intermediate cell obtained in step (C) is removed by laser etching; wherein, the laser source with etching effect is a 355 nm ultraviolet picosecond laser; then, HF acid solution is used for cleaning to remove the silicon oxide remaining on the surface of the spacer region and the first polar region after steps (C) and (D). (E) A PSG layer is deposited on the first surface of the intermediate cell obtained in step (D) by PECVD; wherein the thickness of the PSG layer is 70 nm; (F) The silicon wafer after depositing the PSG layer in the intermediate solar cell obtained in step (E) is subjected to heat treatment. Phosphorus in the PSG diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the first polar region through heat treatment, forming the first polar doped layer and the first doped part. The heat treatment process causes phosphorus in the PSG layer in the spacer region to diffuse into the semiconductor substrate to form the third doped part and the fourth doped part. Due to the diffusion blocking effect of the surface mask functional layer 603, phosphorus in the PSG cannot diffuse into the intrinsic polycrystalline silicon layer corresponding to the second polar region. The relevant process parameters of the heat treatment include: heat treatment temperature 870℃ and heat treatment time 100 min. (G) The first doped source layer and mask functional layer at the corresponding position of the second polar region of the intermediate cell obtained in step (F) are removed by laser etching to expose the underlying intrinsic polysilicon layer; wherein, the laser source with etching function is an ultraviolet picosecond laser with a wavelength of 355 nm. (H) The intermediate cell obtained in step (G) is subjected to boron diffusion treatment, so that the second doping element diffuses into the polycrystalline silicon layer and semiconductor substrate corresponding to the second polar region, forming a second polar doped layer, a second doped part and a fifth doped part, to obtain the solar cell; wherein, the relevant process parameters of the boron diffusion treatment include: diffusion temperature 910℃ and diffusion time 120 min.

[0185] Comparative Example 1 This comparative example provides a back-contact solar cell, which differs from Example 1 only in that the silicon semiconductor substrate region of the spacer area is not diffused and doped, that is, the third doped part is no longer provided. Other settings are the same as in Example 1.

[0186] Comparative Example 2 This comparative example provides a back-contact solar cell, which differs from Example 1 only in that the fourth and fifth doped portions are no longer provided, the first and third doped portions are in direct contact, and the third and second doped portions are in direct contact. Other settings are the same as in Example 1.

[0187] Test case Test samples: back-contact solar cells provided in Examples 1-11 and back-contact solar cells provided in Comparative Examples 1-2.

[0188] Test method: Using a light source that meets the BBB level spectral distribution, at an irradiance of 800 W / m² 2 ~1100 W / m 2 Under certain conditions, the unshaded area of ​​the test sample is irradiated, and the IV characteristics of the sample are tested using an IV tester. After continuous irradiation for more than 1 hour or after the sample reaches thermal stability, the temperature of each area is tested using an infrared thermal imager.

[0189] The specific test results are shown in Table 1 below: Table 1

[0190] As shown in Table 1, the solar cell of the present invention forms a third doped portion by doping at least a portion of the spacer region of the semiconductor substrate. The third doped portion, together with the doped portions (first doped portion and second doped portion) below the first polar region and the second polar region, and the sub-doped portions (fourth doped portion and fifth doped portion) arranged adjacent to each other, constitute a bypass channel. The bypass channel is completely disposed within the semiconductor substrate. The different doped portions of the bypass channel are in direct contact without a dielectric layer, thereby significantly reducing the reverse turn-on voltage of the bypass channel and reducing the risk of hot spot effect.

[0191] The comparison between Examples 1 and 5 shows that the doping concentration of the fourth doped part is higher than that of the first doped part, and the ratio needs to be maintained within a certain range to form a suitable concentration gradient, which can better ensure efficient carrier transport, maintain material stability, and optimize the conduction performance and reliability of the bypass channel.

[0192] The comparison between Example 1 and Example 6 shows that the thickness of the fourth doped part is greater than that of the first doped part, and the thickness difference needs to be maintained within a certain range. This can better avoid stress concentration or uneven doping caused by the steep transition, ensure stable conduction of the bypass channel, and improve the reverse voltage withstand capability and yield of the battery.

[0193] The comparison between Examples 1 and 7 shows that the doping concentration of the fifth doping part is lower than that of the third doping part, and the ratio needs to be maintained within a certain range to form a suitable concentration gradient, optimize the band transition, reduce the carrier transport barrier, and improve the conduction uniformity of the bypass channel. At the same time, it avoids lattice mismatch and defects caused by abrupt doping changes, reduces the risk of leakage, ensures stable current shunting, effectively suppresses hot spot effects, and improves the reverse voltage withstand performance and long-term reliability of the battery.

[0194] The comparison between Example 1 and Example 8 shows that the thickness of the fifth doped part is greater than that of the second doped part, and the thickness difference needs to be maintained within a certain range. This can better ensure a smooth current transition and avoid stress concentration or interface defects caused by sudden changes. It can both ensure the conduction efficiency of the bypass channel and maintain structural stability, prevent local overheating or leakage, and improve the reliability and yield of the battery under reverse bias.

[0195] A comparison of Examples 1 and 9-10 shows that the ratio between the doping concentration of the fourth doped part and the doping concentration of the first doped part is (1.1-15):1. However, whether the ratio is too small in Example 9 or too large in Example 10, under an unsuitable concentration gradient, the reverse turn-on voltage of the bypass channel cannot be reduced effectively, and the generation of hot spots cannot be suppressed. Therefore, the local temperature rises significantly compared to Example 1.

[0196] The comparison between Example 1 and Comparative Example 1 shows that without the third doping section, the reverse turn-on voltage of the bypass channel increases significantly, and the risk caused by the hot spot effect becomes serious.

[0197] As can be seen from the comparison between Example 1 and Comparative Example 2, even without the fourth and fifth doping portions, the reverse turn-on voltage of the bypass channel will still increase significantly, and the risk caused by the hot spot effect will be serious.

[0198] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A solar cell, characterized by, The solar cell comprises a semiconductor substrate, the semiconductor substrate comprises a first surface and a second surface arranged oppositely, the first surface comprises a first polarity region and a second polarity region, and a spacing region arranged between the first polarity region and the second polarity region; The semiconductor substrate of the first polarity region comprises at least one first doped part, and the semiconductor substrate of the second polarity region comprises at least one second doped part; the conductive type of the first doped part is opposite to that of the second doped part; The semiconductor substrate of the spacing region comprises at least one third doped part; the third doped part is arranged between the first doped part and the second doped part; At least part of the conductive type of the third doped part is the same as that of one of the first doped part and the second doped part.

2. The solar cell according to claim 1, characterized in that, At least part of the conductive type of the third doped part is the same as that of the first doped part, and the ratio of the doping concentration of the third doped part to that of the first doped part is (1.1-20):1; And / or, the difference between the junction depth of the third doped part and that of the first doped part is 200-1000 nm.

3. The solar cell according to claim 1, characterized in that, At least part of the conductive type of the third doped part is the same as that of the second doped part, and the ratio of the doping concentration of the third doped part to that of the second doped part is (1.1-30):1; And / or, the difference between the junction depth of the third doped part and that of the second doped part is 200-1000 nm.

4. The solar cell according to any one of claims 1 to 3, wherein The conductive type of the third doped part is P type, or the conductive type of the third doped part is N type.

5. The solar cell of claim 1, wherein The semiconductor substrate surface of the spacing region is recessed along the thickness direction of the semiconductor substrate to form a groove structure relative to the semiconductor substrate surfaces of the first polarity region and the second polarity region; And / or, the ratio of the junction depth of the third doped part to the depth of the groove structure is (0.3-10):1; And / or, the depth of the groove structure is 5 nm or more; the width of the groove structure is 0.01-15 μm; And / or, the semiconductor substrate surface of the spacing region is coplanar with at least one of the semiconductor substrate surfaces of the first polarity region and the second polarity region.

6. The solar cell of claim 1, wherein The solar cell further comprises a fourth doped part arranged between the first doped part and the third doped part, the fourth doped part is at least partially located in the first polarity region; the conductive type of the fourth doped part is the same as that of the first doped part; And / or, the doping concentration of the fourth doped part is greater than that of the first doped part, and the ratio of the doping concentration of the fourth doped part to that of the first doped part is (1.01-50):1; And / or, along the thickness direction of the semiconductor substrate, the junction depth of the fourth doped part is greater than that of the first doped part; And / or, the difference between the junction depth of the fourth doped part and that of the first doped part is 200-1000 nm.

7. The solar cell of claim 1, wherein The solar cell further comprises a fifth doped portion, which is arranged between the second doped portion and the third doped portion, and has the same conductive type as the third doped portion, and at least part of the fifth doped portion is located in the interval region; The doping concentration of the fifth doped portion is less than that of the third doped portion, and the ratio between the doping concentration of the third doped portion and the doping concentration of the fifth doped portion is (1.01-10):1; In the thickness direction of the semiconductor substrate, the junction depth of the fifth doped portion is greater than that of the second doped portion; The difference between the junction depth of the fifth doped portion and the junction depth of the second doped portion is 200-1000 nm.

8. The solar cell of claim 6, wherein, There are at least two different conductive types of doped elements in the fourth doped portion.

9. The solar cell of claim 7, wherein, There are at least two different conductive types of doped elements in the fifth doped portion.

10. The solar cell of claim 1, wherein, The solar cell further comprises a fourth doped portion and a fifth doped portion, the fourth doped portion is arranged between the first doped portion and the third doped portion, and has the same conductive type as the first doped portion; The fifth doped portion is arranged between the second doped portion and the third doped portion, and has the same conductive type as the third doped portion; The first doped portion, the fourth doped portion, the third doped portion, the fifth doped portion and the second doped portion are sequentially connected.

11. The solar cell of claim 1, wherein, The first doped portion, the third doped portion and the second doped portion form a bypass channel in electrical property; The first polarity region and the second polarity region are arranged at intervals, and at least part of the base of the interval region between the first polarity region and the second polarity region is provided with a third doped portion; The third doped portion includes at least two third doped portions, the third doped portions are discontinuously arranged along the direction intersecting the interval arrangement of the first polarity region and the second polarity region, and the distance between adjacent third doped portions is 1-10 mm; The second polarity region surrounds the first polarity region, and at least part of the base of the interval region between the first polarity region and the second polarity region is provided with a third doped portion.

12. The solar cell of claim 1, wherein, The first polarity region comprises a first polarity functional stack, the first polarity functional stack comprises a first dielectric layer and a first polarity doped layer, and the first dielectric layer is arranged between the first surface of the semiconductor substrate and the first polarity doped layer; The second polarity region comprises a second polarity functional stack, the second polarity functional stack comprises a second dielectric layer and a second polarity doped layer, and the second dielectric layer is arranged between the first surface of the semiconductor substrate and the second polarity doped layer; The first dielectric layer is only arranged in the first polarity region; The second dielectric layer is only arranged in the second polarity region.

13. The solar cell of claim 1, wherein, The first surface of the solar cell is further provided with a passivation layer, which covers the interval region and directly contacts the third doped portion.

14. A method of producing a solar cell according to any one of claims 1 to 13, characterized by, Comprise: Taking one of the semiconductor substrates, the semiconductor substrate comprises a first surface and a second surface arranged oppositely, and the first surface is provided with a first polarity region and a second polarity region; forming a spacing region on the first surface of the semiconductor substrate, the spacing region is arranged between the first polarity region and the second polarity region; forming at least one first doped part on the first polarity region; and forming at least one third doped part on the spacing region; forming at least one second doped part on the second polarity region, thereby obtaining the solar cell; the third doped part is arranged between the first doped part and the second doped part; and at least part of the third doped part has the same conductive type as one of the first doped part and the second doped part.

15. The preparation method according to claim 14, characterized in that, The preparation method comprises: forming the first doped part on the first polarity region after forming the spacing region; and forming the third doped part on the spacing region; And / or, the first doped part and the third doped part are formed simultaneously.

16. The method of claim 15, wherein, The preparation method comprises: sequentially depositing a dielectric layer, an intrinsic polysilicon layer and a mask functional layer on the first surface of the semiconductor substrate; removing the mask functional layer, the dielectric layer and the intrinsic polysilicon layer at the position corresponding to the spacing region, thereby forming the spacing region; removing the mask functional layer at the position corresponding to the first conductive region, so that the first doped element diffuses into the polysilicon layer and the semiconductor substrate corresponding to the first conductive region, thereby forming the first doped part; at the same time, the first doped element diffuses into the semiconductor substrate, thereby forming the third doped part and the fourth doped part; performing a second doped element diffusion treatment, so that the second doped element diffuses into the semiconductor substrate corresponding to the second conductive region, thereby forming the second doped part, thereby obtaining the solar cell.

17. The preparation method according to claim 16, characterized in that, The preparation method comprises: the solar cell further comprises a fourth doped part and / or a fifth doped part; and the fourth doped part is formed simultaneously with the first doped part; And / or, the fifth doped part is formed simultaneously with the second doped part.

18. A photovoltaic module, characterized by, The photovoltaic module comprises the solar cell according to any one of claims 1-13, or the solar cell obtained by the preparation method according to any one of claims 14-17.

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