Manufacturing method of semiconductor device and semiconductor device
By creating grooves on the bonding substrate and forming a cavity with a third substrate, the process flow is simplified, the edge planarization problem is solved, the heat dissipation effect is improved, and thus the performance of semiconductor devices is enhanced.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-25
- Publication Date
- 2026-03-17
AI Technical Summary
In existing semiconductor devices, bonding the die to the substrate results in complex processes, low efficiency, difficulty in solving edge planarization problems, and impact on heat dissipation, which in turn affects performance.
Grooves are formed on the bonding substrate and the grains are bonded together. A cavity is formed by combining it with a third substrate, which simplifies the process and increases the heat dissipation area.
This improved process efficiency, solved the edge flattening problem, and enhanced heat dissipation, thereby improving the performance of semiconductor devices.
Smart Images
Figure CN121693255A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor, in particular to a manufacturing method of semiconductor device and semiconductor device. BACKGROUND
[0002] In current semiconductor devices, in order to improve performance, a bonding technology is usually used to bond the die and the to-be-bonded substrate to realize efficient interconnection between the dies. However, after the current die and the to-be-bonded substrate are bonded, a virtual die is used to fill the gap between adjacent dies, which is complex and low in efficiency, and it is difficult to solve the problem caused by edge planarization. Moreover, after the die and the to-be-bonded substrate are bonded, a high-density structure is formed, which affects heat dissipation and further affects the performance of the semiconductor device. SUMMARY
[0003] The technical problem solved by the present application is to provide a manufacturing method of semiconductor device and semiconductor device, which is simple in process, high in efficiency, solves the problem caused by edge planarization, effectively improves heat dissipation, and further improves the performance of the semiconductor device.
[0004] To solve the above technical problem, one technical solution adopted by the present application is a manufacturing method of semiconductor device, comprising: providing a bonding substrate, wherein the bonding substrate comprises a bonded first substrate and a second substrate; opening at least one first groove from a first surface of the second substrate away from the first substrate to the first substrate, the first groove exposing the first substrate, the first substrate comprising a first region exposed by the first groove and a second region other than the first region, wherein the first substrate in the second region is bonded with the remaining second substrate; bonding a die to the first substrate in the first region, a second groove being formed between the die and the remaining second substrate; and bonding a third substrate to a first support portion, the first support portion being the remaining second substrate above the edge region of the first substrate, the third substrate being formed with a first opening, the first opening being in communication with the second groove to form a cavity.
[0005] In an embodiment of the present application, the third substrate comprises a second opening and a third opening, both of which are in communication with the cavity, the second opening being located on a side of the third substrate away from the first support portion, and the third opening being located on a side edge of the third substrate and / or on the bonding substrate.
[0006] In an embodiment of the present application, the first groove is one, and a third groove is formed between adjacent dies, the third groove being in communication with the first opening.
[0007] In an embodiment of the present application, the first recesses are at least two, and the adjacent dies are separated by a spacing part, the spacing part being the remaining second substrate between the adjacent two first recesses, and the die surface being higher than the spacing part surface.
[0008] In an embodiment of the present application, the method for providing a bonded substrate comprises: providing the first substrate and the second substrate, wherein the first substrate comprises a first semiconductor substrate and a first dielectric layer disposed on the first semiconductor substrate, and the first dielectric layer is provided with a first bonding structure; the second substrate comprises a second semiconductor substrate and a second dielectric layer disposed on the second semiconductor substrate; and bonding the first dielectric layer to the second dielectric layer, wherein the first bonding structure is in contact with the second dielectric layer.
[0009] In an embodiment of the present application, the first recess exposes the first bonding structure, and the die is formed with a second bonding structure bonded to the first bonding structure.
[0010] In an embodiment of the present application, before the first recess is opened, the method further comprises: thinning the second substrate.
[0011] To solve the above technical problems, another technical solution adopted by the present application is to provide a semiconductor device, comprising: a bonded substrate, wherein the bonded substrate comprises a bonded first substrate and a second substrate, at least one first recess is opened from a first surface of the second substrate away from the first substrate to the first substrate, the first recess exposes the first substrate, the first substrate comprises a first region exposed by the first recess and a second region other than the first region, wherein the first substrate in the second region is bonded to the remaining second substrate; a die bonded to the first substrate in the first region, and a second recess is formed between the die and the remaining second substrate; a third substrate bonded to a first support part, the first support part being the remaining second substrate above the edge region of the first substrate, the third substrate is formed with a first opening, and the first opening communicates with the second recess to form a cavity.
[0012] In an embodiment of the present application, the third substrate comprises a second opening and a third opening both communicating with the cavity, the second opening is located on a side of the third substrate away from the first support part, and the third opening is located on a side edge of the third substrate and / or the bonded substrate.
[0013] In an embodiment of the present application, the first recess is one, and a third recess is formed between the adjacent dies, the third recess communicating with the first opening.
[0014] In one embodiment of this application, there are at least two first grooves, and adjacent grains are separated by a spacer. The spacer is the remaining second substrate between two adjacent first grooves, and the surface of the grain is higher than the surface of the spacer.
[0015] Unlike existing technologies, the semiconductor device manufacturing method and semiconductor device provided in this application involve bonding a die to a bonding substrate with a first groove, then bonding a third substrate to a first support portion, and creating a cavity between the third substrate, the die, and the remaining second substrate. This method is simpler and more efficient than using virtual dies to fill the gaps between adjacent dies, and it also solves the problem of edge flattening. Furthermore, it increases the heat dissipation area, effectively improving heat dissipation and reducing the impact of heat on the performance of the semiconductor device, thereby improving the performance of the semiconductor device. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein: Figure 1 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application; Figure 2 This is a schematic diagram of the structure of an embodiment of the bonding substrate in this application; Figure 3 This is a schematic diagram of the structure of the first embodiment in which the first groove is formed in this application; Figure 4 This is a schematic diagram of the structure of the first embodiment of the bonded grains in this application; Figure 5 This is a schematic diagram of the structure of the second embodiment in which the first groove is formed in this application; Figure 6 This is a schematic diagram of the structure of the second embodiment of the bonded grains in this application; Figure 7 This is a schematic diagram of a structure of an embodiment of bonding a third substrate in this application; Figure 8 This is a top view schematic diagram of an embodiment of the semiconductor device in this application.
[0017] In the attached drawings, the components are: first substrate 100, first semiconductor substrate 110, first dielectric layer 120, first bonding structure 130, second substrate 200, second semiconductor substrate 210, second dielectric layer 220, first groove 201, remaining second substrate 202 (204 (including first support portion 202 and spacer portion 204)), second groove 203, third groove 205, die 300, third semiconductor substrate 310, third dielectric layer 320, second bonding structure 330, third substrate 400, first opening 401, second opening 402, third opening 403, first protective layer 500, second protective layer 600, first region A, and second region B. Detailed Implementation
[0018] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.
[0019] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.
[0020] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0021] The present application will now be described in detail with reference to the accompanying drawings and embodiments.
[0022] After the die is bonded to the substrate through a bonding process, virtual dies are used to fill the gaps between adjacent dies. This process is complex and inefficient, and it is difficult to solve the problems caused by edge planarization. Furthermore, after the die is bonded to the substrate, a high-density structure is formed, which affects heat dissipation and thus affects the performance of semiconductor devices.
[0023] Therefore, this application provides a method for manufacturing a semiconductor device that can effectively reduce the gap between adjacent dies, reduce the difficulty of subsequent planarization processes, and effectively improve heat dissipation, thereby improving the performance of the semiconductor device.
[0024] Please see Figure 1 , Figure 1 This is a schematic flowchart of an embodiment of the semiconductor device manufacturing method in this application.
[0025] like Figure 1 As shown, the method for manufacturing the semiconductor device in this application includes the following steps: S10. A bonding substrate is provided, wherein the bonding substrate includes a first substrate and a second substrate that are bonded together; S20. At least one first groove is formed from the first surface of the second substrate away from the first substrate toward the first substrate. The first groove exposes the first substrate. The first substrate includes a first region exposed by the first groove and a second region other than the first region. The remaining second substrate is bonded to the first substrate located in the second region. S30. The die is bonded to a first substrate located in the first region, and a second groove is formed between the die and the remaining second substrate. S40. The third substrate is joined to the first support portion, the first support portion being the remaining second substrate located above the edge region of the first substrate, the third substrate having a first opening, the first opening communicating with the second groove to form a cavity.
[0026] Furthermore, combined Figures 2 to 8 The method for manufacturing the semiconductor device of this application is described.
[0027] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an embodiment of the bonding substrate in this application.
[0028] The bonding substrate includes a first substrate 100 and a second substrate 200 bonded together. The first substrate 100 or the second substrate 200 can be a single-layer substrate or a multilayer substrate formed of the same or different materials. The shapes of the first substrate 100 and the second substrate 200 can be the same or different. For example, both the first substrate 100 and the second substrate 200 can be circular or square, and the size of the second substrate 200 can be smaller than, greater than, or equal to the size of the first substrate 100. Alternatively, the first substrate 100 can be circular, and the second substrate 200 can be square. In some embodiments, the first substrate 100 or the second substrate 200 can be a wafer or a die formed by dicing a wafer; this application does not impose specific limitations.
[0029] Furthermore, a bonding substrate is provided, comprising a first substrate 100 and a second substrate 200, such as... Figure 2 As shown, the first substrate 100 includes a first semiconductor substrate 110 and a first dielectric layer 120 disposed on the first semiconductor substrate 110, wherein a first bonding structure 130 is disposed in the first dielectric layer 120. The second substrate 200 includes a second semiconductor substrate 210 and a second dielectric layer 220 disposed on the second semiconductor substrate 210, wherein the second dielectric layer 220 may or may not have a bonding structure for bonding with the first bonding structure 130. In some embodiments, the first dielectric layer 120 is bonded to the second dielectric layer 220, wherein the first bonding structure 130 is in contact with the second dielectric layer 220.
[0030] The first semiconductor substrate 110 or the second semiconductor substrate 210 includes any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III / V compound semiconductors, and also includes multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). The first dielectric layer 120 or the second dielectric layer 220 includes any suitable dielectric layer known in the art, including but not limited to oxide layers and nitride layers. The first bonding structure 130 includes but is not limited to hybrid bonding structures, bump bonding structures, and pads.
[0031] In some embodiments, prior to forming the first groove 201, the following may also be included: The second substrate 200 is thinned. For example, a portion of the second semiconductor substrate 210 may be removed, or all of the second semiconductor substrate 210 may be removed, or a portion of the second dielectric layer 220 may be further removed, as needed. Here, the thickness of the thinned second substrate 200 can be designed according to the thickness of the die 300 to be bonded subsequently.
[0032] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of the first embodiment in which the first groove is formed in this application.
[0033] like Figure 3 As shown, after obtaining the bonding substrate, at least one first groove 201 is formed from the first surface of the second substrate 200, that is, the side surface of the second substrate 200 away from the first substrate 100, toward the first substrate 100. The first groove 201 is described as one. The first groove 201 exposes the first substrate 100. The first substrate 100 includes a first region A exposed by the first groove 201 and a second region B other than the first region A. The remaining second substrate 202 is bonded to the first substrate 100 located in the second region B.
[0034] In this context, the first region A refers to the area of the first substrate 100 exposed by the first groove 201; the second region B refers to the area of the first substrate 100 other than the first region A. The first region A is generally located in the middle region of the first substrate 100, and the second region B may be located in the edge region of the first substrate 100, or in the middle region of the first substrate 100 to separate adjacent first regions A.
[0035] In some embodiments, there is one first groove 201. A first groove 201 can be formed by removing all of the second substrate 200 above the middle region of the first substrate 100, leaving the remaining second substrate 202 above the edge region of the first substrate 100. In this case, the remaining second substrate 200 above the edge region of the first substrate 100 can be referred to as the first support portion 202. The remaining second substrate 202 (first support portion 202) above the edge region of the first substrate 100 matches the size and shape of the edge region of the first substrate 100, thus preventing the edge region from being affected during the subsequent planarization process when the die 300 is bonded to the first substrate 100.
[0036] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of the first embodiment of the bonded grains in this application.
[0037] like Figure 4 As shown, in Figure 3Based on this, in the first groove 201, the die 300 is bonded to the first substrate 100 located in the first region A. A second groove 203 is formed between the die 300 and the remaining second substrate 202. Here, the second groove 203 is the gap between the die 300 and the remaining second substrate 202 (first support portion 202).
[0038] In some embodiments, the die 300 is formed by dicing a wafer. The die 300 includes a third semiconductor substrate 310 and a third dielectric layer 320. A second bonding structure 330 is formed in the third dielectric layer 320. A first groove 201 exposes the first bonding structure 130. The second bonding structure 330 in the die 300 is bonded to the first bonding structure 130. The second bonding structure 330 includes, but is not limited to, hybrid bonding, bump bonding, and pads.
[0039] In some embodiments, a third groove 205 is formed between adjacent grains 300.
[0040] In some embodiments, the top surface of the bonded die 300 is higher than, lower than or flush with, the top surface of the remaining second substrate 202, that is, the top surface of the bonded die 300 is higher than, lower than or flush with, the top surface of the first support portion 202. In this application, the top surface refers to the surface away from the first substrate 100.
[0041] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of the second embodiment in which the first groove is formed in this application.
[0042] It is understood that the parts of this embodiment that are the same as those in the previous embodiments should be referred to the foregoing, and will not be repeated here.
[0043] like Figure 5 As shown, there are at least two first grooves 201. The at least two first grooves 201 can be arranged in an array according to certain rules, which can be set according to the actual situation.
[0044] In some embodiments, a portion of the second substrate 200 above the middle region of the first substrate 100 may be removed to form at least two first grooves 201. Two adjacent first grooves 201 are separated by the remaining second substrate 204. The remaining second substrates 202 (204) are retained above the edge region and the middle region of the first substrate 100, which correspond to the first support portion 202 and the spacer portion 204, respectively. The first support portion 202 is the remaining second substrate 202 located above the edge region of the first substrate 100, and the spacer portion 204 is the remaining second substrate 204 between two adjacent first grooves 201. The width of the spacer portion 204 is less than, equal to or greater than the width of the first support portion 202, and the top surface of the spacer portion 204 is lower than, higher than or flush with the top surface of the first support portion 202. The remaining second substrate 204 (spacer 204) above the middle region of the first substrate 100 prevents the gap between adjacent dies 300 from being too large and affecting the planarization process. The remaining second substrate 202 (first support 202) above the edge region of the first substrate 100 matches the size and shape of the edge region of the first substrate 100 to prevent the edge region from being affected when the dies 300 are bonded to the first substrate 100 and the planarization process is performed.
[0045] In other embodiments, at least two first grooves 201 can be formed by removing a portion of the second substrate 200 above the middle region of the first substrate 100 and removing all of the second substrate 200 above the edge region of the first substrate 100. That is, the remaining second substrate 204 (spacer 204) is retained above the middle region of the first substrate 100, and the remaining second substrate 202 (first support 202) is not retained above the edge region of the first substrate 100. It is understood that combinations of features between different embodiments also fall within the scope of protection of this application.
[0046] Please see Figure 6 , Figure 6 This is a schematic diagram of the structure of the second embodiment of the bonded grains in this application.
[0047] like Figure 6 As shown, in Figure 5 Based on this, in the first groove 201, the dies 300 are bonded to the first substrate 100 located in the first region A, and adjacent dies 300 are separated by the remaining second substrate 204 (spacer 204) between two adjacent first grooves 201.
[0048] A second groove 203 is formed between the die 300 and the remaining second substrate 202. In some embodiments, the die 300 and the spacer 204 may not be in contact, i.e., a gap may be formed. Here, the second groove 203 includes a first gap between the die 300 and the remaining second substrate 202 (first support portion 202) and a second gap between the die 300 and the remaining second substrate 202 (spacer 204); or, the die 300 and the spacer 204 may be in contact. Here, the second groove 203 includes a first gap between the die 300 and the remaining second substrate 202 (first support portion 202).
[0049] Please see Figure 7 , Figure 7 This is a schematic diagram of a structure of an embodiment of bonding a third substrate in this application.
[0050] like Figure 7 As shown, in Figure 6 Based on this, the third substrate 400 is joined to the first support portion 202. The third substrate 400 has a first opening 401, which communicates with the second groove 203 to form a cavity.
[0051] The third substrate 400 can be a single-layer substrate or a multilayer substrate formed of the same or different materials. The third substrate 400 can include any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI). Preferably, the third substrate 400 is a blank wafer or the third substrate includes a metallic material.
[0052] In some embodiments, the first opening 401 is formed by removing a portion of the third substrate 400 from the surface of the third substrate 400 toward the interior of the third substrate 400. Further, at least one sub-opening (not shown) is also formed at the bottom of the first opening 401, and the at least one sub-opening is formed by removing a portion of the third substrate 400 from the bottom of the first opening 401 toward the interior of the third substrate 400.
[0053] In some embodiments, before the third substrate 400 is bonded to the first support portion 202, a first protective layer 500 is formed, the first protective layer 500 being located on the remaining surface of the second substrate 202, the surface of the grain 300, and the surface of the first substrate 100 exposed by the second groove 203.
[0054] In some embodiments, before bonding the third substrate 400 to the first support portion 202, a second protective layer 600 is formed, the second protective layer 600 being located on the surface of the first opening 401, or the second protective layer 600 being formed on the side of the third substrate 400 near the bonding substrate.
[0055] In some embodiments, when the third substrate is bonded to the first support portion, the second protective layer 600 formed on the third substrate is bonded to the first protective layer 500 formed on the first support portion.
[0056] The first protective layer 500 and / or the second protective layer 600 include any suitable dielectric layer known in the art, including but not limited to oxide layers and nitrided layers.
[0057] In some embodiments, the orthographic projection of the first opening 401 onto the surface of the first substrate 100 covers the orthographic projection of the grain 300 and the second groove 203 onto the surface of the first substrate 100.
[0058] In some embodiments, there is one first groove 201, and the third groove 205 is connected to the first opening 401.
[0059] In some embodiments, there are at least two first grooves 201, and the surface of the grain 300 is higher than the surface of the spacer 204.
[0060] In some embodiments, the third substrate 400 further includes a second opening 402 communicating with the cavity, the second opening 402 being located on the side of the third substrate 400 away from the first support portion 202; the third substrate 400 also includes a third opening 403 communicating with the cavity, the third opening 403 being located on the sidewall of the third substrate 400 and / or on the bonding substrate. The number of second openings 402 or third openings 403 can be at least one, and the positions of the second openings 402 or third openings 403 are set at different locations on the third substrate 400 or the bonding substrate as needed. While ensuring reliability and enabling directional fluid flow, the second openings 402 or third openings 403 are positioned as close as possible to the grains, wherein the fluid includes, but is not limited to, gas or liquid.
[0061] In this embodiment, after the die is bonded to the bonding substrate with the first groove, the third substrate is bonded to the first support portion. A cavity is formed between the third substrate, the die, and the remaining second substrate. On the one hand, compared with using virtual dies to fill the gaps between adjacent dies, the process is simple and efficient, and it solves the problem caused by edge flattening. On the other hand, it can also increase the heat dissipation area, which can effectively improve the heat dissipation effect, thereby reducing the impact of heat on the performance of semiconductor devices and improving the performance of semiconductor devices.
[0062] Please see Figure 8 , Figure 8 This is a top view schematic diagram of an embodiment of the semiconductor device in this application.
[0063] like Figure 8 As shown, a first groove 201 ( Figure 8 The area enclosed by the thick black line in the diagram will be used as an example. Multiple grains 300 are bonded to the middle region of the first substrate 100. These grains 300 are located in the region where the first groove 201 is located, and adjacent grains 300 are separated by a third groove 205. The edge region of the first substrate 100 (…) Figure 8 Region B) retains the remaining second substrate 202, the die 300, and the remaining second substrate 202 adjacent to the die 300. Figure 8 The area between region B is the second groove 203 ( Figure 8 The area between the outer and inner boundaries of the thick black line in the image.
[0064] This application also provides a semiconductor device.
[0065] Please see Figures 4 to 8 The semiconductor device 10 includes a bonding substrate, a die 300, and a third substrate 400. The bonding substrate includes a first substrate 100 and a second substrate 200 bonded together. The second substrate 200 has at least one first groove 201 formed on a first surface away from the first substrate 100 facing the first substrate 100. The first groove 201 exposes the first substrate 100. The first substrate 100 includes a first region A exposed by the first groove 201 and a second region B other than the first region A. The first substrate 100 located in the second region B is bonded with the remaining second substrate 202 (204).
[0066] The grain 300 is bonded to the first substrate 100 located in the first region A, and a second groove 203 is formed between the grain 300 and the remaining second substrate 202 (204).
[0067] The third substrate 400 is joined to the first support portion 202. The first support portion 202 is the second substrate 202 remaining above the edge region of the first substrate 100. The third substrate 400 has a first opening 401, which communicates with the second groove 203 to form a cavity.
[0068] In some embodiments, the third substrate 400 further includes a second opening 402 communicating with the cavity, the second opening 402 being located on the side of the third substrate 400 away from the first support portion 202; the third substrate 400 also includes a third opening 403 communicating with the cavity, the third opening 403 being located on the sidewall of the third substrate 400 and / or on the bonding substrate. The number of second openings 402 or third openings 403 can be at least one, and the positions of the second openings 402 or third openings 403 are set at different locations on the third substrate 400 or the bonding substrate according to actual needs, ensuring reliability and enabling directional fluid flow, so that the second openings 402 or third openings 403 are as close as possible to the grains.
[0069] In some embodiments, there is one first groove 201, see [link / reference]. Figure 4 A third groove 205 is formed between adjacent grains 300, and the third groove 205 is connected to the first opening.
[0070] In some embodiments, there are at least two first grooves 201, see [link to relevant documentation]. Figure 6 Adjacent grains 300 are separated by a spacer 204, which is the remaining second substrate between two adjacent first grooves 201, and the surface of the grain 300 is higher than the surface of the spacer 204.
[0071] In some embodiments, a first bonding structure 130 is provided in the first substrate 100, and a second bonding structure 330 is provided in the die 300. Then, when the die 300 is bonded to the first substrate 100 in the first groove 201, the first bonding structure 130 and the second bonding structure 330 are connected.
[0072] In this embodiment, after the die is bonded to the bonding substrate with the first groove, the third substrate is bonded to the first support portion. A cavity is formed between the third substrate, the die, and the remaining second substrate. On the one hand, compared with using virtual dies to fill the gaps between adjacent dies, the process is simple and efficient, and it solves the problem caused by edge flattening. On the other hand, it can also increase the heat dissipation area, which can effectively improve the heat dissipation effect, thereby reducing the impact of heat on the performance of semiconductor devices and improving the performance of semiconductor devices.
[0073] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A method of manufacturing a semiconductor device, characterized by, Comprising: providing a bonded substrate, wherein the bonded substrate comprises a first substrate and a second substrate bonded together; opening at least one first recess from a first surface of the first substrate toward the second substrate, the first recess exposing the first substrate, the first substrate comprising a first region exposed by the first recess and a second region other than the first region, wherein the first substrate at the second region is bonded with a remaining portion of the second substrate; bonding a die to the first substrate at the first region, a second recess formed between the die and the remaining portion of the second substrate; bonding a third substrate to a first support portion of the remaining portion of the second substrate above an edge region of the first substrate, the third substrate formed with a first opening, the first opening in communication with the second recess to form a cavity.
2. The method of claim 1, wherein: the third substrate comprises a second opening and a third opening in communication with the cavity, the second opening on a side of the third substrate away from the first support portion, and the third opening on a side edge of the third substrate and / or on the bonded substrate.
3. The method of claim 2, wherein: the first recess is one, and a third recess is formed between adjacent dies, the third recess in communication with the first opening.
4. The method of claim 2, wherein: the first recess is at least two, and adjacent dies are separated by a spacer portion, the spacer portion being a remaining portion of the second substrate between adjacent first recesses, and a surface of the die is higher than a surface of the spacer portion.
5. The method of claim 1, wherein: providing the bonded substrate comprises: providing the first substrate and the second substrate, wherein the first substrate comprises a first semiconductor substrate and a first dielectric layer disposed on the first semiconductor substrate, the first dielectric layer having a first bonding structure disposed therein, and the second substrate comprises a second semiconductor substrate and a second dielectric layer disposed on the second semiconductor substrate; bonding the first dielectric layer to the second dielectric layer, wherein the first bonding structure is in contact with the second dielectric layer.
6. The method of claim 5, wherein: the first recess exposes the first bonding structure, and a second bonding structure is formed in the die, the second bonding structure bonded to the first bonding structure.
7. The method of claim 1, wherein: prior to opening the first recess, the method further comprises: thinning the second substrate.
8. A semiconductor device, characterized by, Comprising: a bonded substrate, wherein the bonded substrate comprises a first substrate and a second substrate bonded together, the second substrate having at least one first recess opened from a first surface of the first substrate toward the first substrate, the first recess exposing the first substrate, the first substrate comprising a first region exposed by the first recess and a second region other than the first region, wherein the first substrate at the second region is bonded with a remaining portion of the second substrate. a die bonded to a first substrate at a first region, a second recess formed between the die and a remaining second substrate; a third substrate bonded to a first support portion of the remaining second substrate above a first substrate edge region, the third substrate formed with a first opening, the first opening in communication with the second recess to form a cavity.
9. The semiconductor device of claim 8, wherein: the third substrate includes a second opening and a third opening in communication with the cavity, the second opening located on a side of the third substrate distal to the first support portion, and the third opening located on a side edge of the third substrate and / or the bonded substrate.
10. The semiconductor device of claim 8, wherein: the first recess is one, and a third recess is formed between adjacent dies, the third recess in communication with the first opening.
11. The semiconductor device of claim 8, wherein: the first recess is at least two, and a spacing portion separates adjacent dies, the spacing portion being the remaining second substrate between adjacent first recesses, and a surface of the die is higher than a surface of the spacing portion.