Method and apparatus for monitoring electromechanical brake actuator health

Abstract

The present disclosure provides a method and apparatus for monitoring electromechanical brake actuator health. Disclosed examples include measuring, via a sensor, a brake torque generated by a brake of a brake system; providing a first current to a motor to actuate the brake, the first current for causing the measured brake torque to meet a target brake torque; determining a residual value based on the first current and a second current of the motor associated with a first gap between a friction material of the brake and a braking surface; detecting a condition of the braking system based on the residual value and a difference between the second current and a third current of the motor, the third current being associated with a second gap between the friction material and the braking surface; and outputting an indication representative of the detected condition.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to vehicles, and more particularly to methods and apparatus for monitoring electromechanical brake actuator health. BACKGROUND

[0002] Some vehicles include a brake-by-wire system. Unlike hydraulic brakes, the electric brakes of a brake-by-wire system slow the rotation of a vehicle’s wheels via an electric actuator. Some electric brake systems (EBS) are configured such that when a driver activates a brake (e.g., via a brake pedal, etc.), an electrical command is sent to the actuator of the brake, thereby causing a braking force to be applied to the wheel. SUMMARY

[0003] An example apparatus includes machine-readable instructions and at least one processor circuit programmed by the machine-readable instructions to: measure, via a sensor, a brake torque generated by a brake of a brake system; provide a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determine a residual value based on the first current and a second current of the motor associated with a first gap between a friction material and a braking surface of the brake; detect a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the braking surface; and output an indication representative of the detected condition.

[0004] At least one example non-transitory machine-readable medium includes machine- readable instructions to cause at least one processor circuit to at least: measure, via a sensor, a brake torque generated by a brake of a brake system; provide a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determine a residual value based on the first current and a second current of the motor associated with a first gap between a friction material and a braking surface of the brake; detect a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the braking surface; and output an indication representative of the detected condition.

[0005] An example method includes measuring, via a sensor, a brake torque generated by a brake of a brake system; providing a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determining, by at least one processing circuit programmed by at least one instruction, a residual value based on the first current and a second current of the motor associated with a first gap between a friction material and a braking surface of the brake; detecting, by one or more of the at least one processing circuit, a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the braking surface; and outputting an indication representative of the detected condition. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a perspective view of a vehicle in which examples disclosed herein can be implemented.

[0007] Figure 2 is a front view of an example drum brake assembly of Figure 1

[0008] Figure 3 is a rear view of an example drum brake assembly of Figure 2

[0009] Figure 4 is an example electromechanical brake (EMB) actuator system of the drum brake assembly of Figure 2 Figure 3

[0010] Figure 5 is a block diagram of an example drum brake assembly of Figure 2 Figure 3

[0011] Figure 6 is a graph of an example target brake torque versus input motor current.

[0012] Figure 7 is a block diagram of an example implementation of a brake controller of Figure 1 Figure 5

[0013] Figure 8 is a flowchart representative of example machine readable instructions and / or example operations that can be executed, instantiated, and / or performed by example programmable circuitry to implement a brake controller of Figure 7

[0014] Figure 9 ​​​​​​​​​is a block diagram of an exemplary processing platform including programmable circuitry structured to execute, instantiate, and / or perform exemplary machine-readable instructions and / or perform exemplary operations to implement a brake controller of Figure 8 Figure 7

[0015] Figure 10 is a block diagram of an exemplary embodiment of programmable circuitry of Figure 9

[0016] Figure 11 is a block diagram of another exemplary embodiment of programmable circuitry of Figure 9

[0017] Generally, throughout the drawings and accompanying written description, like reference numerals will be used to refer to like or similar portions. The drawings are not necessarily to scale. DETAILED DESCRIPTION

[0018] Examples disclosed herein relate to EMB systems in a drive-by-wire brake method. Examples disclosed herein can be used to monitor the health of a motor (e.g., a brushless direct current (BLDC) motor) of an actuator (e.g., a brake actuator motor) used as a brake pad in a drive brake system.

[0019] Examples disclosed herein can be used to perform out-of-range condition detection in motor performance to detect degradation of a brake actuator motor. In examples disclosed herein, an out-of-range condition of a brake actuator motor means that an amount of current drawn by the brake actuator motor to generate a particular brake torque is greater than a maximum current value (e.g., a threshold current value) that the brake actuator motor is expected to draw. A drive-by-wire brake system uses a closed loop control in which a requested “brake torque target” (e.g., relative to a press force on a brake pedal) is input into the drive-by-wire closed loop. The closed loop generates a current input (i_in) to the brake actuator motor based on the “brake torque target” and uses the current input (i_in) to cause a spread unit or brake caliper to generate a brake torque between a brake pad and a brake surface (e.g., a brake drum, a brake disc, etc.).

[0020] ​​​​Examples disclosed herein use two target trend lines of brake torque versus motor current. A maximum static gap target trend line reflects the amount of current input (i_in) to the brake actuator motor to generate a particular target brake torque through the expansion unit when the static brake shoe-brake drum gap is at a maximum distance. In examples disclosed herein, “static” refers to a position state of the friction material on the brake shoe or pad during which the brake shoe or pad is not being driven toward the braking surface (e.g., brake drum or brake disc), regardless of whether the vehicle is moving. A minimum static gap target trend line reflects the amount of current input (i_in) to the brake actuator motor to generate a particular target brake torque through the expansion unit when the static brake shoe-brake drum gap is at a minimum distance. Both trend lines are plotted on the same graph so that a minimum-maximum gap current difference (Δmax) between the current inputs of the two trend lines can be determined for different target brake torques.

[0021] For a particular target brake torque, examples disclosed herein determine a current residual (r i ) of motor current as a difference between an actual motor current (i 实际 _ 马达 ) of the brake actuator motor and an expected motor current obtained from the minimum gap trend line (i min_曲线 _ 马达 ) (e.g., r i = i 实际_马达 - i min_曲线_马达 ). Examples disclosed herein compare the current residual (r i ) to a sum of the minimum-maximum gap current difference (Δmax) and an experimental current tolerance deviation (Δs) for the particular target brake torque. When the current residual (r i ) is less than or equal to the sum (e.g., r i ≤ Δ max + Δ s ), an in-range condition of the brake actuator motor (e.g., normal operation) is detected. However, when the current residual (r i ) is greater than the sum (e.g., r i > Δ max + Δ s) the flag remains active for a threshold number of brake cycles, the examples disclosed herein activate a maintenance due notification or alert. As used herein, a brake cycle is a braking event initiated by a request to generate a target brake torque. For example, a vehicle operator stepping on a brake pedal initiates a brake cycle, which ends when the operator releases or stops stepping on the brake pedal. A brake cycle or braking event can include multiple iterations of a feedback control loop to achieve the requested target brake torque by controlling an amount of actual brake torque applied by a brake shoe.

[0022] Figure 1 is a perspective view of an example vehicle 100 in which examples disclosed herein can be implemented. In the illustrated example of Figure 1 , the vehicle 100 includes an example brake system 102, an example brake controller 104, an example first wheel 106a, an example second wheel 106b, an example third wheel 106c, and an example fourth wheel 106d.

[0023] The vehicle 100 is a motorized wheeled vehicle. In the illustrated example of Figure 1 , the vehicle 100 is a pickup truck. In other examples, the vehicle 100 can be any type of vehicle having brakes (e.g., sedan, coupe, van, pickup truck, sport utility vehicle, all-terrain vehicle (ATV), agricultural equipment, etc.). The vehicle 100 can be a pure electric vehicle, a hybrid vehicle including an internal combustion engine and electric drive components, or an internal combustion engine (e.g., non-electrified vehicle, partially electrified vehicle, etc.).

[0024] In the illustrated example of Figure 1 , the brake system 102 is implemented as an EMB system that uses a brake-by-wire system. The brake system 102 includes mechanical and electrical components that slow the rotation of the wheels 106a, 106b, 106c, 106d. The brake system 102 can receive user input (e.g., via a brake pedal, a park brake lever / switch / pedal, etc.) or machine input (e.g., an automated command of a vehicle automation system, etc.) and cause activation of one or more brakes of the brake system 102.

[0025] The wheels 106a, 106b, 106c, 106d include a rim and a corresponding tire. While in the illustrated example of Figure 1 , the vehicle 100 has two axles and four wheels, in other examples, the vehicle 100 can have any number of axles and wheels. In the illustrated example of Figure 1 , the first wheel 106a and the second wheel 106b are front wheels, and the third wheel 106c and the fourth wheel 106d are rear wheels. In the illustrated example of Figure 1In the illustrated example of FIG. 1, the first wheel 106a and the third wheel 106c are driver-side wheels, and the second wheel 106b and the fourth wheel 106d are passenger-side wheels.

[0026] During operation of the vehicle 100, the brake system 102 is controlled via the brake controller 104. For example, in response to user input (e.g., depression of a brake pedal, etc.) and / or machine input (e.g., an automation command of a vehicle automation system, etc.), the brake controller 104 can cause the brake system 102 to slow rotation of some or all of the wheels 106a, 106b, 106c, 106d, thereby slowing the vehicle 100.

[0027] Figure 2 The vehicle 100 can be used to implement Figure 1 A front view of an example drum brake assembly 200 of the brake system 102 of the vehicle 100. The drum brake assembly 200 corresponds to one of the wheels 106a-106d of the vehicle 100. Although the examples disclosed herein are described with respect to the drum brake assembly 200, the examples disclosed herein can additionally or alternatively be used in conjunction with a disc brake assembly. In some examples, each of the wheels 106a-106d includes a drum brake assembly that is substantially similar or identical to the drum brake assembly 200. In other examples, only some of the wheels 106a-106d include a drum brake assembly, while other ones of the wheels 106a-106d include a disc brake assembly. For example, the rear wheels 106c, 106d can include drum brake assemblies, and the front wheels 106a, 106b can include disc brake assemblies. In such a brake configuration, the examples disclosed herein can be implemented for both drum brake assemblies and disc brake assemblies. In other examples, all of the wheels 106a-106d include disc brake assemblies, and the examples disclosed herein can be implemented for disc brake assemblies.

[0028] The drum brake assembly 200 includes a drum 202 that rotates in unison with a corresponding wheel (e.g., one of the wheels 106a-106d). Accordingly, rotational acceleration and speed of the drum 202 matches that of the corresponding wheel. Thus, a deceleration force applied on an inner surface (e.g., a braking surface) of the drum 202 translates to a commensurate deceleration of the wheel. Similarly, in a disc brake assembly, a disc brake rotor operates substantially similar to the drum 202 in that it rotates in unison with a corresponding wheel (e.g., one of the wheels 106a-106d) such that rotational acceleration and speed of the disc matches that of the corresponding wheel. Thus, a deceleration force applied on a disc surface (e.g., a braking surface) of the disc brake rotor translates to a commensurate deceleration of the wheel. The inner surface of the drum 202 in the drum brake assembly 200 and the disc surface of the disc brake rotor in the disc brake assembly can generally be referred to as a braking surface.

[0029] Drum brake assembly 200 includes exemplary opposing brake shoes identified as first brake shoe 204a and second brake shoe 204b. Brake shoes 204a, 204b have respective friction material surfaces that generate a deceleration force when the friction material surfaces engage an inner surface of drum 202 based on an applied brake torque. In a disc brake assembly, opposing brake pads in a brake caliper assembly also have respective friction material surfaces. A deceleration force is generated when the brake pads are squeezed together by the brake caliper assembly such that their friction material surfaces engage opposing disc surfaces of a disc brake based on an applied brake torque.

[0030] Drum brake assembly 200 also includes exemplary expansion unit 206. Expansion unit 206 is mechanically coupled to opposing brake shoes 204a, 204b. Expansion unit 206 includes two opposing pistons 208a, 208b. In operation, expansion unit 206 is activated to push pistons 208a, 208b away from each other in opposite directions. As a result, pistons 208a, 208b push brake shoes 204a, 204b Figure 2 ) away from each other to engage the inner surface of drum 202. As expansion unit 206 pushes brake shoes 204a, 204b toward the inner surface of drum 202, the friction material surfaces of brake shoes 204a, 204b engage the inner surface of drum 202 to generate an applied brake torque between brake shoes 204a, 204b and drum 202 (e.g., the actual brake torque between the friction material surfaces of brake shoes 204a, 204b and the braking surface of drum 202). This action slows the rotation of a corresponding one of wheels 106a-106d by a frictional force.

[0031] In a disc brake assembly, a brake caliper includes one or more brake caliper pistons that push one brake pad toward an opposing brake pad to engage opposing disc surfaces of a disc brake. The brake caliper and brake caliper pistons operate in a disc brake assembly to generate an applied brake torque between the opposing brake pads and the disc brake. Thus, an applied brake torque can be generated by expansion unit 206 in drum brake assembly 200 and by a brake caliper in a disc brake assembly. The pistons 208a, 208b of expansion unit 206 in drum brake assembly 200 and the brake caliper pistons of a brake caliper in a disc brake assembly can generally be referred to as brake pistons.

[0032] The drum brake assembly 200 includes an example abutment force sensor 210. The abutment force sensor 210 measures the amount of torque actually applied by the brake shoes 204a, 204b on the drum 202. For example, the expansion unit 206 can be actuated based on an applied or requested target brake torque (e.g., by a depression of a brake pedal, by an automated command of a vehicle automation system, etc.). However, the actual torque applied by the brake shoes 204a, 204b on the drum 202 can be different than the requested target brake torque. This difference can be caused by wear of the brake actuator motor (e.g., the BLDC motor 402 of Figure 4 and Figure 5 As the brake actuator motor wears over time, the amount of input current required by the brake actuator motor to generate the requested target brake torque at the brake shoes 204a, 204b also increases. Thus, the actual brake torque is measured by the abutment force sensor 210 and used in a feedback control loop to more accurately control the amount of actual brake torque applied by the brake shoes 204a, 204b based on the requested target brake torque.

[0033] The drum brake assembly 200 includes an example wear self-adjuster 212. The wear self-adjuster 212 compensates for wear of the friction material on the brake shoes 204a, 204b over time. As this friction material wears over the life of the brake shoes 204a, 204b, the static clearance between the brake shoes 204a, 204b and the inner surface of the drum 202 also increases. As the friction material wears, the wear self-adjuster 212 mitigates some of the friction material wear by pushing the brake shoes 204a, 204b closer to the drum 202. However, a difference in the static clearance between the brake shoes 204a, 204b and the inner surface of the drum 202 can still occur relative to a new condition of the brake shoes 204a, 204b (e.g., little or no friction material wear) and a worn condition of the brake shoes 204a, 204b (e.g., significant friction material wear). This difference in static clearance is described below in connection with a minimum static clearance trend line (e.g., the minimum static clearance trend line 602 of Figure 6 and a maximum static clearance trend line (e.g., the static clearance trend line 604 of Figure 6 .

[0034] Figure 3 is a rear view of the example drum brake assembly 200 of Figure 2 In the example of Figure 3 , the drum brake assembly 200 includes an example EMB actuator system 302 mounted thereto. Additionally, the abutment force sensor 210 is engaged with the EMB actuator system 302 (e.g., the EMB actuation chain). The EMB actuator system 302 is communicatively coupled to Figure 1brake controller 104. In operation, the brake controller 104 sends a brake actuation signal (e.g., a current input (i_in)) to the EMB actuator system 302, and the EMB actuator system 302 generates an actual brake torque between the brake shoes 204a, 204b and the drum 202. A measurement feedback signal of the actual brake torque is provided by the carrier force sensor 210 to the brake controller 104. The brake controller 104 uses the applied brake torque measurement feedback signal to provide a corrected brake actuation signal (e.g., a current input (i_in)) to the EMB actuator system 302. This feedback and correction process is repeatedly performed as target brake torques are requested by a vehicle operator or a vehicle automation system, such that target brake torques can be achieved at the drum brake assembly 200 by the EMB actuator system 302.

[0035] Figure 4 is Figure 3 an exemplary EMB actuator system 302. The EMB actuator system 302 includes an exemplary BLDC motor 402 operably coupled to the expansion unit 206 of the drum brake assembly 200 via an exemplary rotary-rotary gear train 404. Figure 2 The BLDC motor 402 includes an exemplary shaft 406 extending therefrom. The shaft 406 of the BLDC motor 402 provides a rotational force to drive the pistons 208a, 208b of the expansion unit 206 Figure 2 away from one another to increase a brake torque or closer to one another to decrease a brake torque or to end the brake event.

[0036] The BLDC motor 402 operates as an actuator for braking and is controlled by the brake controller 104 of Figure 1 and Figure 2 For example, in response to a target brake torque request from a vehicle operator or a vehicle automation system, the brake controller 104 sends a brake actuation signal (e.g., a current input (i_in)) to the EMB actuator system 302. In response, the EMB actuator system 302 causes rotation of the shaft 406 of the BLDC motor 402. The expansion unit 206 receives the rotational motion from the rotary-rotary gear train 404 and converts the rotational motion to linear motion. The linear motion drives the pistons 208a, 208b of the expansion unit 206 to push the brake shoes 204a, 204b into engagement with the inner surface of the drum 202. In this manner, the EMB actuator system 302 generates a desired brake torque (e.g., a target brake torque) at the drum 202 to slow down the wheels 106a-d of the vehicle 100. Figure 1

[0037] Figure 5 is a health monitoring system 500 for monitoring the health of the BLDC motor 402 in the EMB actuator system 302. Figure 2 and​Figure 3 FIG. 2 is a block diagram of an example embodiment of the example drum brake assembly 200. Motor health monitoring involves detection of out-of-range conditions of motor performance. Such motor health monitoring can be implemented during a braking operation to detect performance degradation of the BLDC motor 402. Figure 5 FIG. 3 is a block diagram representation of a closed-loop control system in which a target brake torque (brake torque target) is provided for a braking event and the actual applied brake torque (T brake) is measured (brake torque actual) to iteratively control the amount of applied brake torque until the applied brake torque matches the input target brake torque.

[0038] In Figure 5 In the example shown, Figure 1 The brake controller 104 of FIG. 1 is communicatively coupled to an example motor gear assembly 502 that is coupled to the expansion unit 206, and the expansion unit 206 is coupled to the brake shoes 204a, 204b. In the example of FIG. 2, the motor gear assembly 502 includes the BLDC motor 402 and a rotary-rotary gear train 404. Figure 5

[0039] In operation, the brake controller 104 receives a target brake torque value (brake torque target) based on, for example, depression of a brake pedal, an automated command of a vehicle automation system, and the like. In the example of FIG. 2, the drum brake assembly 200 includes an example current (I) versus torque change (AT) lookup table (LUT) 504. To drive the BLDC motor 402 based on the target brake torque value (brake torque target), the brake controller 104 accesses the I versus AT LUT 504 to retrieve a current value corresponding to a torque amount change to generate the target brake torque value. That is, the retrieved current value is intended to drive the BLDC motor 402 to cause the expansion unit 206 to produce an applied brake torque (T brake) that is substantially equal to the target brake torque value (brake torque target). To this end, the brake controller 104 generates a current input (i in) based on the current value retrieved from the I versus AT LUT 504 and uses the generated current input (i in) to drive the BLDC motor 402. Figure 5

[0040] When the expansion unit 206 is not actively pushing on the brake shoes 204a, 204b, the torque amount change (AT) to generate the target brake torque is equal to the target brake torque value (brake torque target). However, when the expansion unit 206 is actively pushing on the brake shoes 204a, 204b, the torque amount change (AT) to generate the target brake torque is equal to the additional torque amount needed to increase the current applied brake torque (T brake) to meet the target brake torque value (brake torque target).

[0041] ​​Based on the current input (i_in), the BLDC motor 402 generates a corresponding motor torque or rotational torque force (T_m) via its shaft 406 Figure 4 ) to the rotary-rotary gear train 404. The rotary-rotary gear train 404 operates as a torque multiplier to increase the rotational torque force (T_m) from the shaft 406. Thus, the rotary-rotary gear train 404 generates a rotary gear chain torque (T_gc) (e.g., torque output from the rotary-rotary gear train 404) based on the rotational torque force (T_m) and transmits the rotary gear chain torque (T_gc) to the expansion unit 206.

[0042] The expansion unit 206 includes a rotary-translation gear arrangement 506 that converts the rotary gear chain torque (T_gc) to a translational (linear) expansion unit force (F_su) (e.g., force output from the expansion unit 206). The expansion unit 206 uses the translational (linear) expansion unit force (F_su) to drive the opposing pistons 208a, 208b Figure 2 ) away from each other. In turn, the pistons 208a, 208b push against and engage the brake shoes 204a, 204b with the inner surface of the drum 202 to generate a brake torque (T_brake) (e.g., actual brake torque) between the brake shoes 204a, 204b and the drum 202. If the vehicle 100 is in motion, the brake shoes 204a, 204b rub against the drum 202 to slow the rotation of the drum 202. If the vehicle 100 is in a stationary state, the brake shoes 204a, 204b press against the drum 202 to prevent the drum 202 from rotating (e.g., in a park brake application).

[0043] The drum brake assembly 200 includes an example torque comparator circuitry 508 to compare a target brake torque (brake_torque_target) measurement to an actual brake torque (brake_torque_actual) measurement. For example, the backing plate force sensor 210 measures the actual brake torque (T_brake) applied by the brake shoes 204a, 204b to the drum 202 and transmits feedback of the actual brake torque value (brake_torque_actual) to the torque comparator circuitry 508. To ensure that the correct brake torque is generated, the torque comparator circuitry 508 compares the actual brake torque (brake_torque_actual) feedback to the target brake torque (brake_torque_target) and generates a torque difference value (d). The torque comparator circuitry 508 provides the torque difference value (d) to the brake controller 104, which uses the torque difference value (d) to adjust the current input (i_in) to the BLDC motor 402 until the actual brake torque (T_brake) meets the target brake torque (brake_torque_target). For example, the brake controller 104 can determine that the actual brake torque (T_brake) meets the target brake torque (brake_torque_target) when the torque difference value (d) is less than or equal to a torque difference tolerance value. The torque difference tolerance value can be selected as any suitable value (e.g., within 1%, 2%, etc.) that produces an acceptable actual brake torque (T_brake) relative to the target brake torque (brake_torque_target). The torque comparator circuitry 508 can be implemented solely in hardware or in hardware in combination with software and / or firmware.

[0044] To perform out-of-range condition detection of the motor performance of the BLDC motor 402, the brake controller 104 is programmed based on the premise that for a particular target brake torque, the BLDC motor 402 will draw a certain amount of current to achieve that target. The current draw will also depend on the gap between the brake shoes 204a, 204b and the inner surface of the drum 202. In some examples, the current draw also depends on the motor temperature of the BLDC motor 402. To model the target brake torque versus motor current for different stationary brake shoe-brake drum gaps, Figure 6 An example plot 600 of target brake torque versus input motor current is shown in FIG. 6.

[0045] In Figure 6In the illustrated example, a plot 600 of target brake torque versus input motor current illustrates two trend lines labeled an exemplary minimum static gap trend line 602 and an exemplary maximum static gap trend line 604. In examples disclosed herein, “static” refers to a state of the brake shoes 204a, 204b during which the BLDC motor 402 does not generate torque to expand or push the brake shoes 204a, 204b toward the drum 202. The minimum static gap trend line 602 represents the input current drawn by the BLDC motor 402 to achieve a corresponding target brake torque when the static brake shoe-brake drum gap is minimum (e.g., the wear self-adjuster 212 maintains a minimum gap size between the brake shoes 204a, 204b and the drum 202). The maximum static gap trend line 604 represents the input current drawn by the BLDC motor 402 to achieve a corresponding target brake torque when the static brake shoe-brake drum gap is maximum (e.g., the wear self-adjuster maintains a maximum gap size between the brake shoes 204a, 204b and the drum 202). Thus, the minimum static gap trend line 602 corresponds to a first gap size between the brake shoes 204a, 204b and the drum 202 when the brake shoes 204a, 204b are static (e.g., when the brake pistons 208a, 208b are static), and the maximum static gap trend line 604 corresponds to a second gap size between the brake shoes 204a, 204b and the drum 202 when the brake shoes 204a, 204b are static (e.g., when the brake pistons 208a, 208b are static). The second gap size is greater than the first gap size. For example, as described above, the first gap size can correspond to a minimum gap size between the brake shoes 204a, 204b and the drum 202 that the wear self-adjuster 212 maintains, and the second gap size can correspond to a maximum gap size between the brake shoes 204a, 204b and the drum 202 that the wear self-adjuster 212 maintains. In some examples, the minimum static gap trend line 602 corresponds to a relatively newer condition of the brake shoes 204a, 204b (e.g., little or no wear of the friction material), and the maximum static gap trend line 604 corresponds to a relatively worn condition of the brake shoes 204a, 204b (e.g., significant wear of the friction material).

[0046] More generally, the minimum static gap trend line 602 and the maximum static gap trend line 604 can apply to a drum brake assembly (e.g., the drum brake assembly 200) or a disc brake assembly. In either case, the maximum static gap trend line 604 can more generally correspond to a first gap size between a friction material surface (e.g., of a brake shoe 204a, 204b or brake pad) and a brake surface (e.g., an inner surface of a brake drum 202 or opposing disc surfaces of a disc brake rotor) when a brake piston 208a, 208b of the drum brake assembly 200 or a brake piston of the disc brake assembly is static, and the maximum static gap trend line 604 corresponds to a second gap size between the friction material surface and the brake surface when the brake piston 208a, 208b of the drum brake assembly 200 or the brake piston of the disc brake assembly is static.

[0047] Data for the trend lines 602, 604 can be determined through experimentation or empirical processes in a laboratory, field testing, or other testing environment. For example, a plurality of brake shoes and corresponding brake drums can be run through a plurality of brake cycles for both minimum static brake shoe-brake drum gap and maximum static brake shoe-brake drum gap conditions. During the brake cycles, current input and corresponding brake torque measurements can be recorded to generate the trend lines 602, 604.

[0048] Current input values (i_in) and target brake torque values (brake torque target) for the trend lines 602, 604 are stored in the I vs. AT LUT 504. For example, the minimum static gap trend line 602 is stored as minimum static gap torque-current data in the I vs. AT LUT 504, and the maximum static gap trend line 604 is stored as maximum static gap torque-current data in the I vs. AT LUT 504. In this way, the brake controller 104 can access or retrieve current input values (i_in) for corresponding input target brake torque values (brake torque target) from the minimum and / or maximum static gap torque-current data in the I vs. AT LUT 504 during a brake event. The brake controller 104 can then generate a corresponding input current to achieve a desired brake torque (T_brake) by the brake shoes 204a, 204b.

[0049] During operation of the vehicle 100, the brake controller 104 can perform out-of-range condition detection based on a current residual (r i ) of the motor current determined according to Equation 1 below.

[0050]

[0051] In Equation 1 above, is an actual motor current drawn by the BLDC motor 402 during operation, It is the target motor current obtained from the minimum stationary clearance trend line 602 in Figure 600 for the corresponding target braking torque, and r i This is the current residual. When the target braking torque (braking torque - target) is met, the actual motor current... It is the amount of current drawn by the BLDC motor 402 to generate the actual braking torque (T_braking) that meets the target braking torque (braking torque_target).

[0052] Brake controller 104 will transfer the current residual r i With minimum-maximum gap current difference Δ max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s The brake controller 104 compares the values ​​by determining the target motor current value from the minimum stationary clearance trend line 602 for the target braking torque. The minimum-maximum gap current difference Δ is determined by the difference between the maximum stationary gap motor current value and the maximum stationary gap trend line 604 for the same target braking torque. max Current tolerance deviation Δ s It is the amount of experimental deviation or fluctuation that can be observed between different brake shoes, and is used to account for this small difference when the brake controller 104 performs out-of-range condition detection of the motor performance of the BLDC motor 402. Tolerance deviation Δ s It can be set to any suitable value. In some examples, the tolerance deviation Δ s It is set to zero (e.g., no observed deviation or fluctuation between different brake shoes). In other examples, the tolerance deviation Δ s The value obtained from the experiment can be decreased or increased to any other suitable value.

[0053] Brake controller 104 uses current residual r i With minimum-maximum gap current difference Δ max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s The comparison between the two equations determines whether the BLDC motor 402 is operating within or outside its range. For example, the brake controller 104 uses Equation 2 below to determine whether the BLDC motor 402 is operating within its range.

[0054] r i ≤Δ max +Δ s (Equation 2)

[0055] According to Equation 2 above, if the current residual ri the sum of the minimum-maximum gap current difference Δ max and the current margin deviation Δ s (e.g., Δ max + Δ s ), the brake controller 104 determines that the BLDC motor 402 is operating in an in-range condition. In examples disclosed herein, an in-range condition for the BLDC motor 402 means that the amount of current drawn by the BLDC motor 402 (e.g., current input (i_in)) is less than or equal to a threshold current value. The threshold current value can be selected as a value that indicates that the BLDC motor 402 is operating at a particular power efficiency, better than or worse than a particular power efficiency. The brake controller 104 uses Equation 3 below to detect an out-of-range condition in the operation of the BLDC motor 402.

[0056] r i > Δ max + Δ s (Equation 3)

[0057] According to Equation 3 above, if the current residual r i is greater than the sum of the minimum-maximum gap current difference Δ max and the current margin deviation Δ s (e.g., Δ max + Δ s ), the brake controller 104 detects an out-of-range condition in the operation of the BLDC motor 402 (e.g., the BLDC motor 402 is not operating in an in-range condition). In examples disclosed herein, an in-range condition in the operation of the BLDC motor 402 means that the amount of current drawn by the BLDC motor 402 (e.g., current input (i_in)) is greater than a threshold current value. As described above, the threshold current value can be selected as a value that indicates whether the BLDC motor 402 is operating at a particular power efficiency, better than or worse than a particular power efficiency.

[0058] In some examples, the amount of actual motor current (e.g., current input (i_in)) drawn by the BLDC motor 402 to produce a target braking torque (braking torque_target) represents the efficiency of the BLDC motor 402. As the BLDC motor 402 ages, its efficiency decreases, which causes the BLDC motor 402 to draw a higher actual motor current to produce the same target braking torque (braking torque_target) that it previously produced based on a lower actual motor current .

[0059] In some implementations, the examples disclosed herein are selectively activated by the brake controller 104 to be performed in the vehicle after the BLDC motor 402 reaches a certain operational life. Such operational life can mark a point at which the BLDC motor can show signs of needing maintenance or replacement. In some examples, the operational life can be measured by a service distance (e.g., miles traveled, kilometers traveled, etc.) or a number of brake events (e.g., brake event count) that the BLDC motor 402 has used. The operational life that triggers the use or activation of the examples disclosed herein can be based on empirical observations of typical operational life metrics for a plurality of BLDC motors (e.g., in field testing or a laboratory environment). An example operational life of the BLDC motor 402 can be 160,000 miles or any other suitable distance. Selectively disabling the examples disclosed herein in the brake controller 104 conserves processing resources, which in turn reduces the amount of electrical power consumed by the brake controller 104 when the monitoring of the BLDC motor 402 as disclosed herein is less likely to detect a condition of the BLDC motor 402 that warrants a check for possible maintenance or replacement.

[0060] Figure 7 is an example embodiment of a brake controller 104 for performing out-of-range condition detection in a BLDC motor 402. Figure 1 and Figure 5 is a block diagram of an example embodiment of a brake controller 104. Figure 7 The brake controller 104 of Figure 7 The brake controller 104 of Figure 7 Some or all of the circuitry of Figure 7 Some or all of the circuitry of Figure 7 Some or all of the circuitry of

[0061] In Figure 7In the illustrated example, the brake controller 104 includes example interface circuitry 702, example current generator circuitry 704, example arithmetic circuitry 706, example comparator circuitry 708, and example maintenance detector circuitry 710. The interface circuitry 702 is provided to receive an input target brake torque value (brake torque target) (e.g., by a depression of a brake pedal, by an automated command of a vehicle automation system, etc.), to access the I vs. DT LUT 504 Figure 5 ), and to receive an actual brake torque value (brake torque actual) from the seat force sensor 210 Figure 2 and Figure 5 In some examples, the interface circuitry 702 is instantiated by programmable circuitry executing interface instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 8 .

[0062] The current generator circuitry 704 is provided to generate a current input (i in) for the BLDC motor 402 based on a current value obtained from the I vs. DT LUT 504 for a corresponding input target brake torque value (brake torque target). In some examples, the current generator circuitry 704 is instantiated by programmable circuitry executing current generator instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 8 .

[0063] The arithmetic circuitry 706 is provided to perform arithmetic operations such as determining a current residual value (r i ) according to Equation 1 above, and determining a sum of the minimum-maximum gap current difference Δ max and the current tolerance deviation Δ s (e.g., Δ max + Δ s ). In some examples, the arithmetic circuitry 706 is instantiated by programmable circuitry executing arithmetic instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 8 .

[0064] The comparator circuitry 708 is provided to perform comparisons between data values. For example, the comparator circuitry 708 compares the current residual value (r i ) to a sum of the minimum-maximum gap current difference Δ max and the current tolerance deviation Δ s (e.g., Δ max + Δ s) to detect in-range conditions and / or out-of-range conditions of the BLDC motor 402. In some examples, the comparator circuitry 708 is instantiated by programmable circuitry executing comparator instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 8

[0065] Maintenance detector circuitry 710 is provided to detect when maintenance in the EMB actuator system 302 Figure 3 and Figure 4 is due. For example, the maintenance detector circuitry 710 can include an example counter 712 that is incremented at each brake cycle in which an out-of-range condition of motor performance of the BLDC motor 402 is detected based on a comparison by the comparator circuitry 708. The comparator circuitry 708 can compare the value of the counter 712 to a threshold number of brake cycles. The threshold number of brake cycles represents the number of brake cycles in which an out-of-range condition must be active to activate a maintenance due alert of the EMB actuator system 302. The threshold number of brake cycles can be programmed into the brake controller 104 to be any suitable value that notifies a driver or technician of maintenance due in the braking system without generating false positive notifications. When the counter 712 exceeds the threshold number of brake cycles, the maintenance detector circuitry 710 activates a maintenance due notification or alert of the EMB actuator system 302 in the vehicle diagnostic system. The maintenance due alert can be used to indicate that maintenance is due on the brake actuator motor (e.g., the BLDC motor 402). In some examples, the maintenance detector circuitry 710 is instantiated by programmable circuitry executing maintenance detector instructions and / or is configured to perform operations such as those represented by the flowchart of Figure 8

[0066] As described above, Figure 5 the torque comparator circuitry 508 of the brake controller 104 of Figure 7 the interface circuitry 702, the current generator circuitry 704, the arithmetic circuitry 706, the comparator circuitry 708, and the maintenance detector circuitry 710 are structures. Such structures can embody means for performing the corresponding disclosed functions. Examples of such functions are described above in connection with the corresponding circuitry of the torque comparator circuitry 508, the interface circuitry 702, the current generator circuitry 704, the arithmetic circuitry 706, the comparator circuitry 708, and the maintenance detector circuitry 710, and are described below in connection with the flowchart of Figure 8

[0067] While an example manner of implementing the brake controller 104 of Figure 7 is shown in Figure 1 , one or more of the elements represented by the elements of Figure 7 ​​​One or more of the elements, processes and / or devices illustrated in FIG. 1 can be combined, divided, re-arranged, omitted, eliminated and / or implemented in any other way. Further, Figure 5 the torque comparator circuitry 508 of FIG. 1 and Figure 7 the interface circuitry 702, the current generator circuitry 704, the arithmetic circuitry 706, the comparator circuitry 708, and the maintenance detector circuitry 710 of FIG. 1 and / or more generally the brake controller 104 can be implemented individually by hardware or by a combination of hardware with software and / or firmware. Thus, for example, Figure 5 the torque comparator circuitry 508 of FIG. 1 and the interface circuitry 702, the current generator circuitry 704, the arithmetic circuitry 706, the comparator circuitry 708, and the maintenance detector circuitry 710 of FIG. 1 and / or more generally the brake controller 104 can be implemented by programmable circuitry in combination with machine-readable instructions (e.g., firmware or software), processor circuitry, analog circuitry, digital circuitry, logic circuitry, programmable processors, programmable microprocessors, digital signal processors (DSPs), ASICs, programmable logic devices (PLDs), and / or field programmable logic devices (FPLDs) such as FPGAs. Still further, as an adjunct to, or alternative to, those shown, Figure 7 the exemplary brake controller 104 of FIG. 1 can include one or more elements, processes and / or devices, and / or can include one or more of any or all of the illustrated elements, processes and devices. Figure 7

[0068] Figure 8 Flowcharts representative of example machine readable instructions (which can be executed by programmable circuitry to implement and / or instantiate the brake controller 104 of FIG. 1) and / or example operations (which can be performed by programmable circuitry to implement and / or instantiate the brake controller 104 of FIG. 1) are shown in FIG. 1. The machine readable instructions can be one or more executable programs or portions of programs, and / or can be one or more functions or portions of functions, executed by programmable circuitry (such as the programmable circuitry 912 shown in the example programmable circuitry platform 900 discussed below in connection with FIG. 9), and / or can be one or more functions or portions of functions executed by example programmable circuitry (e.g., FPGAs) discussed below in connection with FIGS. 10 and / or 11. In some examples, the machine readable instructions cause operations, tasks, etc. to be implemented and / or performed in the real world in an automated fashion. As used herein, “automated” means without human intervention. Figure 7 Figure 7 Figure 9 Figure 10

[0069] ​​​​​The programs can be embodied in instructions (e.g., software and / or firmware) stored in one or more non-transitory computer-readable storage media and / or machine-readable storage media, such as cache memory, magnetic storage, or disk (e.g., floppy disk, hard drive, etc.), optical storage, or any other storage device or storage disk. The instructions of the non-transitory computer-readable media and / or machine-readable media can be programmed and / or executed by programmable circuitry located in one or more hardware devices, although the entire program and / or portions of it can alternatively be executed and / or instantiated by one or more hardware devices instead of programmable circuitry and / or embodied in dedicated hardware. The machine-readable instructions can be distributed over multiple hardware devices and / or executed by two or more hardware devices (e.g., server and client hardware devices). For example, a client hardware device can be implemented by an endpoint client hardware device (e.g., a hardware device associated with a human and / or machine user) or an intermediary client hardware device gateway (e.g., a radio access network (RAN)) that can facilitate communications between a server and an endpoint client hardware device. Similarly, the non-transitory computer-readable storage media can comprise one or more media. Furthermore, although the exemplary embodiments are described in the context of a single client and server, the embodiments are equally applicable to a system with more than one client and / or server. Figure 8The illustrated flowchart describes an example procedure, but many other methods of implementing the example brake controller 104 can alternatively be used. For example, the order of execution of the blocks of the flowchart can be changed, and / or some of the described blocks can be changed, eliminated, or combined. Additionally or alternatively, any or all of the blocks of the flowchart can be implemented by one or more hardware circuits (e.g., processor circuitry, discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, op-amps, logic circuits, etc.) structured to perform the corresponding operations without executing software or firmware. Programmable circuitry can be distributed across different network locations and / or local to one or more hardware devices (e.g., single-core processors (e.g., single-core CPUs), multi-core processors (e.g., multi-core CPUs, XPU, etc.)). For example, programmable circuitry can be a CPU and / or FPGA located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings), one or more processors in a single machine, multiple processors distributed across multiple servers of a server rack, multiple processors distributed across multiple server racks, etc., and / or any combination thereof.

[0070] The machine-readable instructions described herein can be stored in one or more of a compressed format, an encrypted format, a segmented format, a compiled format, an executable format, a packaged format, etc. The machine-readable instructions as described herein can be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), a bitstream (e.g., a computer-readable bitstream, a machine-readable bitstream, etc.), etc.) or data structures (e.g., portions of instructions stored, representations of code, etc.) that can be used to create, manufacture, and / or produce machine-executable instructions. For example, the machine-readable instructions can be segmented and stored on one or more storage devices, storage disks, and / or computing devices (e.g., servers) located at the same or different locations of a network or collection of networks (e.g., in the cloud, in edge devices, etc.). The machine-readable instructions can need to be one or more of installed, modified, rewritten, updated, combined, supplemented, configured, decrypted, decompressed, unpacked, distributed, reassigned, compiled, etc. in order to be directly readable, interpretable, and / or executable by a computing device and / or other machine. For example, the machine-readable instructions can be stored in multiple portions that are individually compressed, encrypted, and / or stored on separate computing devices, where the portions, when decrypted, decompressed, and / or combined, form a set of computer-executable instructions and / or machine-executable instructions that implement one or more functions and / or operations of a program that together can form a program such as described herein.

[0071] In another example, machine-readable instructions can be stored in a state in which they can be read by programmable circuitry, but require addition of a library (e.g., a dynamic link library (DLL)), a software development kit (SDK), an application programming interface (API), etc., in order to execute the machine-readable instructions on a particular computing device or other apparatus. In another example, it can be necessary to configure the machine-readable instructions (e.g., store settings, input data, record network addresses, etc.) prior to all or part of the machine-readable instructions and / or corresponding program being executed. Thus, machine-readable, computer-readable medium, and / or machine-readable medium, as used herein, can include instructions and / or programs, regardless of the particular format or state of the machine-readable instructions and / or programs.

[0072] The machine-readable instructions described herein can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, the machine-readable instructions can be represented using any of the following languages: C, C++, Java, C#, Perl, Python, JavaScript, HyperText Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0073] As mentioned above, the executable instructions (e.g., computer-readable instructions and / or machine-readable instructions) stored on one or more non-transitory computer-readable and / or machine-readable media can be used to implement Figure 8example operations. As used herein, the terms non-transitory computer-readable medium, non-transitory computer-readable storage medium, non-transitory machine-readable medium, and / or non-transitory machine-readable storage medium are expressly defined to include any type of computer-readable storage, and to exclude propagating signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and / or non-transitory machine-readable storage media include optical storage, magnetic storage, HDDs, flash memories, ROMs, CDs, DVDs, caches, any type of RAM, registers, and / or any other storage devices or storage disks in which information is stored for any duration (e.g., for extended periods of time, permanently, for brief instances, for temporarily buffering, and / or for caching of the information). As used herein, the terms “non-transitory computer-readable storage device” and “non-transitory machine-readable storage device” are expressly defined to include any physical (mechanical, magnetic, and / or electrical) hardware that stores information for any duration, but excludes propagating signals and transmission media. Examples of non-transitory computer-readable storage devices and / or non-transitory machine-readable storage devices include any type of random access memory, any type of read only memory, solid state memory, flash memory, optical disks, magnetic disks, disk drives, and / or redundant array of independent disks (RAID) systems. As used herein, the term “device” refers to a physical structure that can or can not be configured by computer-readable instructions, machine-readable instructions, etc., and / or can or can not be manufactured to perform computer-readable instructions, machine-readable instructions, etc., such as mechanical and / or electrical equipment, hardware, and / or circuitry.

[0074] Figure 8 are example machine-readable instructions and / or example operations 800 that can be executed, instantiated, and / or performed by programmable circuitry (e.g., Figure 9 programmable circuitry 912 of the brake controller 104 Figure 1 , Figure 5 and Figure 7 to perform over-range condition detection in motor performance of a brake actuator motor (e.g., Figure 4 and Figure 5 BLDC motor 402) to detect motor degradation. The machine-readable instructions and / or operations 800 can be executed for one of the wheels 106a-d Figure 1 on which the EMB actuator system 302 is located. Substantially similar or identical instructions and / or operations can be executed for the other wheels 106a-d with their respective EMB actuator systems. Figure 8The example machine-readable instructions and / or example operations 800 begin at block 802, where the interface circuitry 702( Figure 7 ) obtains a target current value representing a target current input to the BLDC motor 402 (e.g., actuator motor) to drive the expansion unit 206 of the EMB actuator system 302 to a target brake torque (brake torque target). For example, the interface circuitry 702 obtains the target current value in the I vs. AT LUT 504 based on an input target brake torque (brake torque target) (e.g., received from a depression of a brake pedal, from an automated command of a vehicle automation system, etc.). The brake controller 104 uses the retrieved target current value to attempt to generate an actual brake torque (T brake) between the brake shoes 204a, 204b and the drum 202 that satisfies or matches the input target brake torque (brake torque target). In the illustrated example, the interface circuitry 702 references the input target brake torque value in the minimum static clearance trend line 602( Figure 6 ) to obtain a minimum static clearance between the brake shoes 204a, 204b and the drum 202 of the EMB actuator system 302.

[0075] The current generator circuitry 704( Figure 7 ) generates a current input (i in) for the BLDC motor 402 (e.g., actuator motor) (block 804). The BLDC motor 402 can use the current input (i in) to generate a motor torque (T m) to drive the expansion unit 206. The standoff force sensor 210( Figure 2 and Figure 5 ) measures an actual brake torque (T brake) generated by the expansion unit 206 between the brake shoes 204a, 204b and the drum 202 (block 805).

[0076] The torque comparator circuitry 508( Figure 5 ) determines whether the input target brake torque (brake torque target) is satisfied (block 806). For example, the torque comparator circuitry 508 receives a feedback measurement of the actual brake torque (T brake) from the standoff force sensor 210 (e.g., an actual brake torque value (brake torque actual)) generated by the expansion unit 206 between the brake shoes 204a, 204b and the drum 202 (e.g., based on the measurement at block 805). The torque comparator circuitry 508 compares the actual brake torque (T brake) to the input target brake torque (brake torque target) to determine whether the actual brake torque (T brake) satisfies the input target brake torque (brake torque target) (e.g., within a 1%, 2%, etc. tolerance threshold or any other suitable tolerance threshold).

[0077] If the torque comparator circuitry 508 determines that the actual brake torque (T_brake) does not satisfy the input target brake torque (brake_torque_target) (block 806: NO), control returns to block 804 where the current generator circuitry 704 adjusts (e.g., increases) the current input (i_in) to the BLDC motor 402 (e.g., actuator motor) to increase the actual brake torque (T_brake) generated by the expansion unit 206. Thus, the abutment force sensor 210, the torque comparator circuitry 508, and the current generator circuitry 704 implement a brake torque control loop until the actual brake torque (T_brake) generated by the expansion unit 206 satisfies the input target brake torque (brake_torque_target). When the current generator circuitry 704 adjusts the current input (i_in) to achieve the target brake torque (brake_torque_target), the current input (i_in) is no longer equal to the initial target current value obtained at block 802. Thus, a final current input (i_in) for achieving the target brake torque (brake_torque_target) is obtained at block 808 below.

[0078] When the torque comparator circuitry 508 determines that the actual brake torque (T_brake) satisfies the input target brake torque (brake_torque_target) (block 806: YES), control proceeds to block 808. At block 808, the interface circuitry 702 obtains a measured actual current value representing the current input (i_in) to the BLDC motor 402 (e.g., actuator motor). The measured actual current corresponds to the amount of current drawn by the BLDC motor 402 (e.g., actuator motor) to drive the expansion unit 206 to generate the actual brake torque (T_brake) between the brake shoes 204a, 204b and the drum 202 that satisfies the input target brake torque (brake_torque_target).

[0079] At block 810, the arithmetic circuitry 706 determines a current residual value (r Figure 7 ) by subtracting the measured actual current value from the target current value. For example, the arithmetic circuitry 706 uses Equation 1 above to determine a current residual value (r i ) for the current of the BLDC motor 402 based on the measured actual current value obtained at block 808 and the target current value obtained from the I vs. AT LUT 504 at block 802. i

[0080] At block 812, the arithmetic circuitry 706 determines a minimum-maximum gap current difference AT max ​The target current value corresponding to the minimum stationary clearance trend line 602 is the current input drawn by the BLDC motor 402 to drive the brake shoes 204a and 204b to generate the target braking torque value (braking torque_target) when there is a minimum stationary clearance between the brake shoes 204a and 204b and the drum 202. The second current value represents the second current input drawn by the BLDC motor 402 to drive the brake shoes 204a and 204b to generate the target braking torque value (braking torque_target) for the maximum stationary clearance between the brake shoes 204a and 204b and the drum 202.

[0081] At box 814, the arithmetic circuit system 706 determines the minimum-maximum gap current difference Δ. max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s At box 816, comparator circuit system 708 ( Figure 7 Determine the current residual value (r) i Is it greater than the minimum-maximum gap current difference Δ? max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s For example, the comparator circuit system 708 calculates the current residual value (r) according to Equation 3 above. i ) and the minimum-maximum gap current difference Δ max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s ) are compared to determine whether the current residual value (r) i () greater than the minimum-maximum gap current difference Δ max and current tolerance deviation Δ s (For example, Δ) max +Δ s The sum of ), or according to Equation 2 above, the current residual value (r) i Is it less than or equal to the minimum-maximum gap current difference Δ? max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s ).

[0082] If the comparator circuit system 708 determines the current residual value (r) i The difference between the minimum and maximum gap current Δ is not greater than the minimum-maximum gap current difference. max and current tolerance deviation Δ s The sum (e.g., Δ) max +Δ s) (block 816: NO), control proceeds to block 818. At block 818, the comparator circuitry 708 determines that the BLDC motor 402 (e.g., actuator motor) in the EMB actuator system 302 is operating in an in-range condition.

[0083] If the comparator circuitry 708 determines that the current residual value (r i ) is greater than the minimum-maximum gap current difference Δ max and the current tolerance offset Δ s (e.g., Δ max + Δ s ) (block 816: YES), the comparator circuitry 708 detects an out-of-range condition of the performance of the BLDC motor 402 (e.g., actuator motor) in the EMB actuator system 302 (block 820). The maintenance detector circuitry 710 determines whether the out-of-range condition has been active for a threshold number of brake cycles (block 824). For example, the comparator circuitry 708 can increment a value of a counter 712 ( Figure 7 ) at each brake cycle at which the out-of-range condition is detected at block 820, and compare the counter value to a threshold number of brake cycles.

[0084] If the maintenance detector circuitry 710 determines that the out-of-range condition has been active for the threshold number of brake cycles (block 824: YES), the maintenance detector circuitry 710 activates a maintenance due alert or notification in the vehicle diagnostic system (block 826). For example, the maintenance detector circuitry 710 can activate the maintenance due alert to output a message or other indication representative of the detected condition. Figure 8 The example instructions or operations 800 then end.

[0085] Otherwise, if the maintenance detector circuitry 710 determines that the out-of-range condition has not been active for the threshold number of brake cycles (block 824: NO), control proceeds to block 822. At block 822, the maintenance detector circuitry 710 determines whether to continue monitoring. For example, the maintenance detector circuitry 710 can determine to stop monitoring after the maintenance due alert is activated, after the brake event has ended, or after the vehicle 100 has been turned off. If the maintenance detector circuitry 710 determines to continue monitoring (block 822: YES), control returns to block 808. Otherwise, if the maintenance detector circuitry 710 determines not to continue monitoring (block 822: NO), the example instructions and / or operations 800 end. Figure 8

[0086] Figure 9 is a block diagram of an example programmable circuitry platform 900 structured to execute and / or instantiate the example instructions and / or operations 800.​Figure 8 example machine-readable instructions and / or example operations to implement Figure 7 The programmable circuitry platform 900 of the illustrated example includes programmable circuitry 912. The programmable circuitry 912 of the illustrated example is hardware. For example, the programmable circuitry 912 can be implemented by one or more integrated circuits from any desired family or manufacturer, logic circuits, FPGAs, microprocessors, CPUs, DSPs, and / or microcontrollers. The programmable circuitry 912 can be implemented by one or more semiconductor-based devices, e.g., semiconductor-based devices that include one or more processor cores, microprocessors, CPUs, DSPs, Figure 5 The programmable circuitry 912 of the illustrated example implements the torque comparator circuitry 508 of the brake controller 104. The programmable circuitry 912 of the illustrated example implements the arithmetic circuitry 706, the comparator circuitry 708, and the maintenance detector circuitry 710 of the brake controller 104. Figure 7

[0087] The programmable circuitry 912 of the illustrated example includes local memory 913 (e.g., cache, registers, etc.). The programmable circuitry 912 of the illustrated example communicates with main memory 914, 916 including volatile memory 914 and non-volatile memory 916 over a bus 918. The volatile memory 914 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), dynamic synchronous dynamic random access memory and / or any other type of RAM device. The non-volatile memory 916 can be implemented by flash memory and / or any other desired type of memory device. Accesses to the main memory 914, 916 of the illustrated example are controlled by a memory controller 917. In some examples, the memory controller 917 can be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuitry from any desired family or manufacturer to manage the flow of data to and from the main memory 914, 916. In the illustrated example, the I & DT LUT 504 is stored in the non-volatile memory 916. Additionally or alternatively, the I & DT LUT 504 can be stored in the volatile memory 914.

[0088] The programmable circuitry platform 900 of the illustrated example also includes interface circuitry 920. The interface circuitry 920 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a universal serial bus (USB) interface, an interface, a near field communication (NFC) interface, a peripheral component interconnect (PCI) interface, and / or a peripheral component interconnect express (PCIe) interface. In some examples, the interface circuitry 920 is in communication with an example network 926. In the illustrated example, the interface circuitry 920 implements the network interface 506 of the brake controller 104. Figure 7 ​interface circuitry 702.

[0089] In the illustrated example, one or more input devices 922 are connected to the interface circuitry 920. The input devices 922 permit a user (e.g., a human user, a machine user, etc.) to input data and / or commands into the programmable circuitry 912. The input devices 922 can be implemented by, for example, a brake pedal, a brake lever, a button, an in-vehicle graphical user interface, a vehicle automation system application programming interface (API), etc.

[0090] One or more output devices 924 are also connected to the interface circuitry 920 of the illustrated example. In the illustrated example, the output devices 924 implement the current generator circuitry 704 to generate and provide the current input (i_in) to the BLDC motor 402.

[0091] The programmable circuitry platform 900 of the illustrated example also includes one or more mass storage disks or devices 928 for storing firmware, software, and / or data. Examples of such mass storage disks or devices 928 include magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.) and / or solid-state storage disks or devices such as flash memory devices and / or SSDs. In some examples, the I & Delta T LUT 504 is stored in the mass storage device 928 in addition to or in lieu of the volatile memory 914 and / or the non-volatile memory 916.

[0092] The machine-readable instructions 932, which can be implemented by the machine- readable instructions of Figure 8 The machine-readable instructions 932, which can be implemented by the machine- readable instructions of

[0093] Figure 10 The machine-readable instructions 932, which can be implemented by the machine- readable instructions of Figure 9 A block diagram of an example implementation of the programmable circuitry 912 of Figure 9 The programmable circuitry 912 of is implemented by a microprocessor 1000. For example, the microprocessor 1000 can be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit). The microprocessor 1000 executes Figure 8 Some or all of the machine-readable instructions of the flowchart of are executed by the microprocessor 1000 to effectively instantiate the circuitry of as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such examples, Figure 7 Some or all of the machine-readable instructions of the flowchart of are executed by the microprocessor 1000 to effectively instantiate the circuitry of as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such examples, Figure 7Circuitry of the microprocessor 1000 is instantiated by hardware circuitry of the microprocessor 1000 in combination with machine-readable instructions. For example, the microprocessor 1000 can be implemented by multi-core hardware circuitry, such as a CPU, a DSP, and the like. While it can include any number of example cores 1002 (e.g., 1 core), the microprocessor 1000 of this example is a multi-core semiconductor device including N cores. The cores 1002 of the microprocessor 1000 can operate independently or can cooperate to execute machine-readable instructions. For example, machine code corresponding to a firmware program, an embedded software program, or a software program can be executed by one of the cores 1002 or can be executed by multiple ones of the cores 1002 at the same or different times. In some examples, machine code corresponding to a firmware program, an embedded software program, or a software program is split into threads and executed in parallel by two or more of the cores 1002. The software program can correspond to a program for implementing a method, such as the method represented by the flowchart of FIG. 1. Figure 8 machine-readable instructions and / or operations represented by the flowchart of FIG. 1.

[0094] The cores 1002 can communicate over a first example bus 1004. In some examples, the first bus 1004 can be implemented by a communication bus to perform communications associated with one or more of the cores 1002. For example, the first bus 1004 can be implemented by at least one of an Inter-Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Additionally or alternatively, the first bus 1004 can be implemented by any other type of computing or electrical bus. The cores 1002 can obtain data, instructions, and / or signals from one or more external devices through example interface circuitry 1006. The cores 1002 can output data, instructions, and / or signals to one or more external devices through the interface circuitry 1006. While the cores 1002 of this example include an example local memory 1020 (e.g., a level 1 (L1) cache that can be split into an L1 data cache and an L1 instruction cache), the microprocessor 1000 also includes an example shared memory 1010 that can be shared by the cores (e.g., a level 2 (L2 cache)) for high-speed access to data and / or instructions. Data and / or instructions can be communicated (e.g., shared) by writing to and / or reading from the shared memory 1010. The local memory 1020 of each of the cores 1002 and the shared memory 1010 can be part of a memory hierarchy that includes multiple levels of cache memory and main memory (e.g., the main memory 914, 916 of FIG. 9). Generally, higher levels of memory in the hierarchy exhibit shorter access times and have smaller storage capacities than lower levels of memory. Variations in the cache hierarchy of the respective levels are managed (e.g., coordinated) by a cache coherency policy. Figure 9 the main memory 914, 916 of FIG. 9). Generally, higher levels of memory in the hierarchy exhibit shorter access times and have smaller storage capacities than lower levels of memory. Variations in the cache hierarchy of the respective levels are managed (e.g., coordinated) by a cache coherency policy.

[0095] Each core 1002 can be referred to as a CPU, DSP, etc., or any other type of hardware circuitry. Each core 1002 includes control unit circuitry 1014, arithmetic and logic (AL) circuitry (sometimes referred to as an ALU) 1016, a plurality of registers 1018, local memory 1020, and a second exemplary bus 1022. Other structures can be present. Control unit circuitry 1014 includes semiconductor-based circuitry structured to control (e.g., coordinate) movement of data within a corresponding core 1002. AL circuitry 1016 includes semiconductor-based circuitry structured to perform one or more mathematical and / or logical operations on data within a corresponding core 1002. The AL circuitry 1016 of some examples performs integer-based operations. In other examples, the AL circuitry 1016 also performs floating point operations. In yet other examples, the AL circuitry 1016 can include first AL circuitry to perform integer-based operations and second AL circuitry to perform floating point operations. In some examples, the AL circuitry 1016 can be referred to as an arithmetic logic unit (ALU).

[0096] Registers 1018 are semiconductor-based structures used to store data and / or instructions, such as a result of one or more of the operations performed by the AL circuitry 1016 of a corresponding core 1002. For example, registers 1018 can include vector registers, general-purpose registers, flag registers, segment registers, machine-specific registers, instruction pointer registers, control registers, etc. Registers 1018 can be arranged in a bank as shown. Alternatively, registers 1018 can be organized in any other arrangement, format, or structure, such as by being distributed throughout core 1002 to shorten access time. Second bus 1022 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus. Figure 10 As shown. Alternatively, registers 1018 can be organized in any other arrangement, format, or structure, such as by being distributed throughout core 1002 to shorten access time. Second bus 1022 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0097] Each core 1002 and / or microprocessor 1000 more generally can include additional and / or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power sources, one or more power gates, one or more shifters (e.g., barrel shifters), and / or other circuitry can be present. Microprocessor 1000 is a semiconductor device fabricated to include many transistors interconnected to implement the above-described structures in one or more integrated circuits (ICs) contained in one or more packages.

[0098] Figure 11 is Figure 9a block diagram of another example implementation of programmable circuitry 912. In this example, the programmable circuitry 912 is implemented by FPGA circuitry 1100. For example, the FPGA circuitry 1100 can be implemented by an FPGA. The FPGA circuitry 1100 can be used, for example, to perform operations that otherwise can be performed by Figure 10 the example microprocessor 1000 executing corresponding machine-readable instructions. However, once configured, the FPGA circuitry 1100 instantiates in hardware the operations and / or functions corresponding to the machine-readable instructions, and thus can generally perform the operations / functions faster than a general-purpose microprocessor executing corresponding software.

[0099] More specifically, in contrast to the above-described Figure 10 microprocessor 1000 (which is a general-purpose device that can be programmed to perform operations represented by flowchart diagrams Figure 8 some or all machine-readable instructions represented by the flowchart diagrams, but the interconnects and logic circuitry of the general-purpose device are fixed once manufactured) in contrast, Figure 11 the example FPGA circuitry 1100 includes interconnects and logic circuitry that can be configured, structured, programmed, and / or interconnected in different ways after manufacture to instantiate, for example, some or all of the operations / functions corresponding to machine-readable instructions represented by the flowchart diagrams Figure 8 the flowchart diagrams. Specifically, the FPGA circuitry 1100 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change the way the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (unless and until the FPGA circuitry 1100 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by the input circuitry. Those operations can correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowchart diagrams. Thus, the FPGA circuitry 1100 can be configured and / or structured to effectively instantiate as special-purpose logic circuits some or all of the operations / functions corresponding to the machine-readable instructions of the flowchart diagrams. Figure 8 Figure 8 the flowchart diagrams. Specifically, the FPGA circuitry 1100 can be thought of as an array of logic gates, interconnects, and switches. The switches can be programmed to change the way the logic gates are interconnected by the interconnects, effectively forming one or more special-purpose logic circuits (unless and until the FPGA circuitry 1100 is reprogrammed). The configured logic circuits enable the logic gates to cooperate in different ways to perform different operations on data received by the input circuitry. Those operations can correspond to some or all of the instructions (e.g., software and / or firmware) represented by the flowchart diagrams. Thus, the FPGA circuitry 1100 can be configured and / or structured to effectively instantiate as special-purpose logic circuits some or all of the operations / functions corresponding to the machine-readable instructions of the flowchart diagrams. Figure 8

[0100] in Figure 11 ​​In some examples, the FPGA circuit system 1100 is configured and / or structured in response to being programmed (and / or reprogrammed once or multiple times) based on a binary file. In some examples, the binary file can be compiled and / or generated based on instructions in a hardware description language (HDL) such as Lucid, VHSIC Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) can write code or programs in the HDL corresponding to one or more operations / functions; the code / program can be translated into a low-level language as needed; and the code / program (e.g., low-level language code / program) can be converted into a binary file (e.g., through a compiler, software application, etc.). In some examples, Figure 11 The FPGA circuit system 1100 can access and / or load binary files to enable Figure 11 The FPGA circuit system 1100 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions, which may be provided by... Figure 11 Access to the FPGA circuit system 1100, so as to enable Figure 11 The configuration and / or structuring of the FPGA circuit system 1100 or its components.

[0101] In some examples, binary files are compiled, generated, transformed, and / or otherwise output from a unified software platform used for programming the FPGA. For instance, the unified software platform can translate first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in an HDL. In some such examples, binary files are compiled, generated, and / or otherwise output from the unified software platform based on the second instructions. In some examples, Figure 11 The FPGA circuit system 1100 can access and / or load binary files to enable Figure 11 The FPGA circuit system 1100 is configured and / or structured to perform one or more operations / functions. For example, a binary file may be implemented by a bit stream (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.), and / or machine-readable instructions, which may be provided by... Figure 11 Access to the FPGA circuit system 1100, so as to enable Figure 11 The configuration and / or structuring of the FPGA circuit system 1100 or its components.

[0102] Figure 10 The FPGA circuit system 1100 includes an example input / output (I / O) circuit system 1102 to obtain data from and / or output data to an exemplary configuration circuit system 1104 and / or external hardware 1106. For example, the configuration circuit system 1104 may be implemented by interface circuitry that can obtain a binary file, which may be implemented by bitstreams, data, and / or machine-readable instructions to configure the FPGA circuit system 1100 or portions thereof. In some such examples, the configuration circuit system 1104 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that may implement an artificial intelligence / machine learning (AI / ML) model to generate the binary file), and / or any combination thereof. In some examples, the external hardware 1106 may be implemented by an external hardware circuit system. For example, the external hardware 1106 may be... Figure 8 The microprocessor 1000 is implemented.

[0103] The FPGA circuit system 1100 also includes an array of exemplary logic gate circuit systems 1108, a plurality of exemplary configurable interconnects 1110, and an exemplary memory circuit system 1112. The logic gate circuit systems 1108 and the configurable interconnects 1110 can be configured to instantiate one or more operations / functions, which may correspond to... Figure 11 At least some of the machine-readable instructions and / or other desired operations. Figure 11 The logic gate system 1108 shown is manufactured in blocks or groups. Each block includes a semiconductor-based electrical structure that can be configured as a logic circuit. In some examples, the electrical structure includes logic gates (e.g., AND gates, OR gates, NOT gates, etc.) that provide basic building blocks for the logic circuit. Electrically controlled switches (e.g., transistors) are present in each of the logic gate system 1108 to support the configuration of the electrical structure and / or logic gates to form a circuit for performing a desired operation / function. The logic gate system 1108 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops), multiplexers, etc.

[0104] The configurable interconnect 1110 shown in the example is a conductive path, trace, via, etc., which may include an electrically controlled switch (e.g., a transistor) whose state can be changed (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit system 1108 to program the desired logic circuit.

[0105] The storage circuitry 1112 of the illustrated example is structured to store results of one or more of the operations performed by the corresponding logic gates. The storage circuitry 1112 can be implemented by registers or the like. In the illustrated example, the storage circuitry 1112 is distributed among the logic gate circuitry 1108 to facilitate access and improve execution speed.

[0106] Figure 10 The exemplary FPGA circuitry 1100 also includes exemplary special-purpose operation circuitry 1114. In this example, the special-purpose operation circuitry 1114 includes special-purpose circuitry 1116 that can be invoked to implement commonly used functions so that these functions do not need to be programmed in the field. Examples of such special-purpose circuitry 1116 include memory (e.g., DRAM) controller circuitry, PCIe controller circuitry, clock circuitry, transceiver circuitry, memory, and multiplier-accumulator circuitry. There can be other types of special-purpose circuitry. In some examples, the FPGA circuitry 1100 can also include exemplary general-purpose programmable circuitry 1118, such as exemplary CPUs 1120 and / or exemplary DSPs 1122. There can additionally or alternatively be other general-purpose programmable circuitry 1118 that can be programmed to perform other operations.

[0107] Although Figure 11 and Figure 9 shows two exemplary implementations of the programmable circuitry 912 of Figure 10 , many other approaches are also contemplated. For example, the FPGA circuitry can include an on-board CPU, such as Figure 9 one or more of the exemplary CPUs 1120 of Figure 10 . Thus, Figure 10 the programmable circuitry 912 of Figure 11 may additionally be implemented by combining at least Figure 11 the exemplary microprocessor 1000 with Figure 10 the exemplary FPGA circuitry 1100 of Figure 8 In some such hybrid examples, Figure 8 one or more cores 1002 of Figure 11 may execute a first portion of machine-readable instructions represented by the flowchart of Figure 8 the FPGA circuitry 1100 of Figure 8 may be configured and / or structured to perform a second operation / function corresponding to a second portion of machine-readable instructions represented by the flowchart of Figure 7 and / or the ASIC can be configured and / or structured to perform a third operation / function corresponding to a third portion of machine-readable instructions represented by the flowchart of

[0108] It will be appreciated that Figure 10Some or all of the circuitry of the microprocessor 1000 can thus be instantiated at the same or different times. For example, Figure 11 The same and / or different portions of the microprocessor 1000 of the microprocessor 1000 can be programmed to execute portions of machine-readable instructions at the same and / or different times. In some examples, Figure 7 The same and / or different portions of the FPGA circuitry 1100 of the FPGA circuitry 1100 can be configured and / or structured to perform operations / functions corresponding to portions of machine-readable instructions at the same and / or different times.

[0109] In some examples, Figure 10 Some or all of the circuitry of the circuitry can be instantiated, for example, in one or more threads that are executed concurrently and / or serially. For example, Figure 11 The microprocessor 1000 of the microprocessor 1000 can execute machine-readable instructions in one or more threads that are executed concurrently and / or serially. In some examples, Figure 7 The FPGA circuitry 1100 of the FPGA circuitry 1100 can be configured and / or structured to perform operations / functions concurrently and / or serially. Moreover, in some examples, Figure 10 Some or all of the circuitry can be implemented within one or more virtual machines and / or containers that are executed on Figure 9 The microprocessor 1000 of the microprocessor 1000.

[0110] In some examples, Figure 10 The programmable circuitry 912 of the programmable circuitry 912 can be in one or more packages. For example, Figure 11 The microprocessor 1000 of the microprocessor 1000 and / or ​ The FPGA circuitry 1100 of the FPGA circuitry 1100 can be in one or more packages.

[0111] “Comprise” and “contain” (and all forms of these terms, and tenses thereof) are used herein as open-ended terms. Thus, whenever a claim uses any form of “comprise” or “contain” (e.g., comprises, comprising, contained, contain, containing, etc.) as a preamble, it is understood that additional elements, items, etc. can be present in the corresponding claim or claims or statement without falling outside the scope of the corresponding claim or statement. As used herein, when the phrase “at least” is used as a transitional term in a preamble of a claim, it is an open term, in the same manner as the terms “comprise” and “contain” are open terms. The term “and / or” when used in the form, such as A, B, and / or C, means that any combination or subset of A, B, and C is permitted, such as (1) only A, (2) only B, (3) only C, (4) A with B, (5) A with C, (6) B with C, and (7) A with B with C. As used herein in the context of describing structures, components, articles, objects, and / or things, the phrase “at least one of A and B” is intended to refer to implementations including any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, articles, objects, and / or things, the phrase “at least one of A or B” is intended to refer to implementations including any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any one of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0112] As used herein, singular references (e.g., “a,” “an,” “one,” “the,” etc.) do not exclude multiple. As used herein, the term “one” (or “an”) object refers to one or more of the object. The terms “one,” “an,” “one or more,” and “at least one” are used interchangeably herein. Additionally, although separately listed, multiple components, elements or acts can be implemented by a single entity or object. Additionally, although features can be included in different examples or claims, these can be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and / or advantageous.

[0113] As used herein, unless otherwise indicated, a connection reference (e.g., attached, coupled, connected, and linked) can include an intermediate member between the connection reference and the element to which it connects and / or relative movement between the elements. As such, a connection reference does not necessarily infer a direct connection and / or fixed relationship between two elements. As used herein, a statement that a part is “contacted” by another part is defined as meaning that there are no intervening parts between the two parts.

[0114] Unless specifically stated otherwise, as employed herein, the description of a description such as “first,” “second,” “third,” etc., does not impose or otherwise connote any meaning to priority, physical order, arrangement in a list, and / or ordering and is merely used as a label and / or any arbitrary name to distinguish elements for the sake of understanding the disclosed examples. In some examples, a descriptor “first” can be used to refer to an element in the detailed description, while the same element can be referred to in a claim with a different descriptor such as “second” or “third.” In such cases, it is understood that such descriptors are used only to clearly identify those elements within the context of the discussion, e.g., within a claim, where those elements can otherwise share the same name, for example.

[0115] As used herein, the phrase “in communication” (including variations thereof) encompasses both direct communication and / or indirect communication through one or more intermediary components and does not require direct physical (e.g., wired) communication and / or continuous communication, but additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0116] As used herein, “programmable circuitry” is defined to include: (i) one or more special purpose circuits (e.g., application specific circuits (ASICs)) structured to perform specific operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors); and / or (ii) one or more general purpose semiconductor-based circuits programmable with instructions to perform specific functions and / or operations and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as central processing units (CPUs) that can execute first instructions to perform one or more operations and / or functions, FPGAs that can be programmed with second instructions to cause a configuration and / or structure of the FPGAs to be instantiated to instantiate one or more operations and / or functions corresponding to the first instructions, digital signal processors (DSPs) that can execute first instructions to perform one or more operations and / or functions, one or more microcontrollers that can execute first instructions to perform one or more operations and / or functions, and / or integrated circuits such as application specific integrated circuits (ASICs).

[0117] As used herein, integrated circuit / circuitry is defined as one or more semiconductor packages that contain one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupled with multiple circuit elements, a system on a chip (SoC), etc.

[0118] Disclosed herein are example methods, apparatuses, systems, and articles of manufacture for monitoring electromechanical brake actuator health. Additional examples and combinations thereof include the following:

[0119] Example 1 includes an apparatus comprising: machine readable instructions; and at least one processor circuit programmed by the machine readable instructions to: measure, via a sensor, a brake torque generated by a brake of a brake system; provide a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determine a residual value based on the first current and a second current of the motor associated with a first gap between a friction material of the brake and a brake surface; detect a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the brake surface; and output an indication representative of the detected condition.

[0120] Example 2 includes the apparatus of Example 1, wherein one or more of the at least one processor circuit is to output the indication after the condition is active for a threshold number of brake cycles, the condition being an out-of-range condition of the motor.

[0121] Example 3 includes the apparatus of Example 1 and / or Example 2, wherein one or more of the at least one processor circuit is to obtain the second current from minimum static gap torque-current data, the minimum static gap torque-current data representing an amount of current drawn by the motor to generate a corresponding target brake torque for the first gap between the friction material and the brake surface.

[0122] Example 4 includes the apparatus of any one or more of Examples 1-3, wherein one or more of the at least one processor circuit is to obtain the third current from maximum static gap torque-current data, the maximum static gap torque-current data representing an amount of current drawn by the motor to generate a corresponding target brake torque of the target brake torques for the second gap between the friction material and the brake surface.

[0123] Example 5 includes the apparatus of any one or more of Examples 1-4, wherein the second current is drawn by the motor to drive a brake piston from the first gap between the friction material and the brake surface, and the third current is drawn by the motor to drive the brake piston from the second gap between the friction material and the brake surface.

[0124] Example 6 includes the apparatus of any one or more of Examples 1-5, wherein one or more of the at least one processor circuit is to obtain the first current after a brake torque control loop using the brake torque control loop causes a brake piston to generate the measured brake torque that satisfies the target brake torque.

[0125] Example 7 includes the apparatus of any one or more of Examples 1-6, wherein the first gap is a minimum static gap size between the friction material and the brake surface when a brake piston is at rest, the second gap is a maximum static gap size between the friction material and the brake surface when the brake piston is at rest, the second gap being greater than the first gap.

[0126] Example 8 includes the apparatus of any one or more of Examples 1-7, wherein one or more of the at least one processor circuit is to determine the residual value by subtracting the first current from the second current, and detect the condition based on the residual value being greater than the difference between the second current and the third current.

[0127] Example 9 includes at least one non-transitory machine-readable medium comprising machine-readable instructions to cause at least one processor circuit to at least: measure, via a sensor, a brake torque generated by a brake of a brake system; provide a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determine a residual value based on the first current and a second current of the motor associated with a first gap between a friction material of the brake and a brake surface; detect a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the brake surface; and output an indication representative of the detected condition.

[0128] Example 10 includes the at least one non-transitory machine-readable medium of Example 9, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to output the indication after the condition is active for a threshold number of brake cycles, the condition being an out-of-range condition of the motor.

[0129] Example 11 includes the at least one non-transitory machine-readable medium of Example 9 and / or Example 10, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to determine the residual value by subtracting the first current from the second current, and detect the condition based on the residual value being greater than the difference between the second current and the third current.

[0130] Example 12 includes the at least one non-transitory machine-readable medium of any one or more of Examples 9-11, wherein the first gap is a minimum resting gap size between the friction material and the brake surface when a brake piston is at rest, the second gap is a maximum resting gap size between the friction material and the brake surface when the brake piston is at rest, the second gap being greater than the first gap.

[0131] Example 13 includes the at least one non-transitory machine-readable medium of any one or more of Examples 9-12, wherein the machine-readable instructions are to cause one or more of the at least one processor circuit to obtain the first current after a brake torque control loop is used to cause a brake piston to generate the measured brake torque that satisfies the target brake torque.

[0132] Example 14 includes a method comprising: measuring, via a sensor, a brake torque generated by a brake of a brake system; providing a first current to a motor to actuate the brake, the first current to cause the measured brake torque to satisfy a target brake torque; determining, by at least one processing circuit programmed by at least one instruction, a residual value based on the first current and a second current of the motor associated with a first gap between a friction material and a brake surface of the brake; detecting, by one or more of the at least one processing circuit, a condition of the brake system based on the residual value and a difference between the second current and a third current of the motor associated with a second gap between the friction material and the brake surface; and outputting an indication representative of the detected condition.

[0133] Example 15 includes the method of example 14, wherein the indication is outputted after the condition is active for a threshold number of brake cycles, the condition being an out-of-range condition of the motor.

[0134] Example 16 includes the method of example 14 and / or example 15, wherein the second current is obtained from minimum-stationary-gap torque-current data representative of a first amount of current drawn by the motor to generate a corresponding target brake torque for the first gap between the friction material and the brake surface.

[0135] Example 17 includes the method of any one or more of examples 14-16, further comprising obtaining the third current from maximum-stationary-gap torque-current data representative of an amount of current drawn by the motor to generate a corresponding one of the target brake torques for the second gap between the friction material and the brake surface.

[0136] Example 18 includes the method of any one or more of examples 14-17, wherein the second current is drawn by the motor to drive a brake piston from the first gap between the friction material and the brake surface, and the third current is drawn by the motor to drive the brake piston from the second gap between the friction material and the brake surface.

[0137] Example 19 includes the method of any one or more of examples 14-18, wherein the first current is obtained after a brake torque control loop causes a brake piston to generate the measured brake torque satisfying the target brake torque.

[0138] Example 20 includes the method described in any one or more of Examples 14 to 19, wherein the first gap is the minimum static gap size between the friction material and the braking surface when the brake piston is stationary, the second gap is the maximum static gap size between the friction material and the braking surface when the brake piston is stationary, and the second gap is greater than the first gap.

[0139] As can be understood from the foregoing, exemplary systems, apparatuses, articles, and methods for monitoring the health status of electromechanical brake actuators have been disclosed. The disclosed systems, apparatuses, articles, and methods monitor the health degradation of motors used as actuators (e.g., brake actuator motors) for operating brake shoes or brake pads in a vehicle braking system. Therefore, the disclosed systems, apparatuses, articles, and methods relate to the operation of machines such as computers or other electronic devices and / or mechanical devices.

[0140] The appended claims are hereby incorporated by reference into this specific embodiment. While certain example systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not limited thereto. Rather, this patent covers all systems, devices, articles of manufacture, and methods that fall fully within the scope of the claims of this patent.

Claims

1. An apparatus comprising: Machine-readable instructions; as well as At least one processor circuit, said at least one processor circuit being programmed by said machine-readable instructions to: The braking torque generated by the brakes in the braking system is measured via sensors; A first current is supplied to the motor to actuate the brake, the first current being used to cause the measured braking torque to meet the target braking torque; The residual value is determined based on the first current and a second current associated with the first gap between the friction material of the motor and the braking surface of the brake. The condition of the braking system is detected based on the residual value and the difference between the second current and the third current of the motor, wherein the third current is associated with the second gap between the friction material and the braking surface. as well as The output indicates the detected condition.

2. The device of claim 1, wherein one or more of the at least one processor circuitry is configured to output the indication after the condition is active for a threshold number of braking cycles, the condition being an out-of-range condition of the motor.

3. The device of claim 1, wherein one or more of the at least one processor circuit is configured to obtain the second current from minimum stationary gap torque-current data, the minimum stationary gap torque-current data representing a first current quantity drawn by the motor to generate a corresponding target braking torque for the first gap between the friction material and the braking surface.

4. The device of claim 3, wherein one or more of the at least one processor circuitry is configured to acquire the third current from maximum stationary gap torque-current data, the maximum stationary gap torque-current data representing the amount of current drawn by the motor to generate the target braking torque corresponding to the target braking torque for the second gap between the friction material and the braking surface.

5. The device according to claim 1 or any one or more of claim 2, wherein the second current is drawn by the motor to drive the brake piston from the first gap between the friction material and the brake surface, and the third current is drawn by the motor to drive the brake piston from the second gap between the friction material and the brake surface.

6. The device according to any one or more of claims 1 or 2, wherein one or more of the at least one processor circuit is configured to acquire the first current after the brake piston generates the measured braking torque that satisfies the target braking torque using a braking torque control circuit.

7. The device according to claim 1 or any one or more of claim 2, wherein the first gap is the minimum static gap size between the friction material and the braking surface when the brake piston is stationary, the second gap is the maximum static gap size between the friction material and the braking surface when the brake piston is stationary, and the second gap is greater than the first gap.

8. The device according to claim 1 or any one or more of claim 2, wherein one or more of the at least one processor circuitry is used for: The residual value is determined by subtracting the first current from the second current; and The condition is detected based on the residual value being greater than the difference between the second current and the third current.

9. At least one machine-readable medium comprising machine-readable instructions such that at least one processor circuitry at least: The braking torque generated by the brakes in the braking system is measured via sensors; A first current is supplied to the motor to actuate the brake, the first current being used to cause the measured braking torque to meet the target braking torque; The residual value is determined based on the first current and a second current associated with the first gap between the friction material of the motor and the braking surface of the brake. The condition of the braking system is detected based on the residual value and the difference between the second current and the third current of the motor, wherein the third current is associated with the second gap between the friction material and the braking surface. as well as The output indicates the detected condition.

10. The at least one machine-readable medium of claim 9, wherein the machine-readable instructions are used to cause one or more of the at least one processor circuitry to output the indication after the condition is active for a threshold number of braking cycles, the condition being an out-of-range condition of the motor.

11. At least one machine-readable medium according to claim 9 or claim 10, wherein the machine-readable instructions are used to cause one or more of the at least one processor circuitry to: The residual value is determined by subtracting the first current from the second current; and The condition is detected based on the residual value being greater than the difference between the second current and the third current.

12. The at least one machine-readable medium according to any one or more of claims 9 or 10, wherein the first gap is the minimum stationary gap size between the friction material and the braking surface when the brake piston is stationary, the second gap is the maximum stationary gap size between the friction material and the braking surface when the brake piston is stationary, and the second gap is greater than the first gap.

13. At least one machine-readable medium according to any one or more of claims 9 or 10, wherein the machine-readable instructions are used to cause one or more of the at least one processor circuitry to acquire the first current after using a braking torque control circuit to cause a brake piston to generate the measured braking torque that satisfies the target braking torque.

14. A method comprising: The braking torque generated by the brakes in the braking system is measured via sensors; A first current is supplied to the motor to actuate the brake, the first current being used to cause the measured braking torque to meet the target braking torque; The residual value is determined by at least one processing circuit programmed by at least one instruction based on the first current and a second current associated with the first gap between the friction material of the motor and the braking surface of the brake. The condition of the braking system is detected by one or more of the at least one processing circuits based on the residual value and the difference between the second current and the third current of the motor, wherein the third current is associated with a second gap between the friction material and the braking surface. as well as The output indicates the detected condition.

15. The method of claim 14, wherein the indication is output after the condition is in an active state for a threshold number of braking cycles, the condition being an out-of-range condition of the motor.

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