A memory management unit, method and apparatus

Abstract

The application provides a memory management unit, method and device, which comprises outputting to a page table cache from multiple source requests according to a preset strategy through a multiplexer, so as to avoid multiple requests from simultaneously competing for page table cache resources. The page table cache stores page table entries, and when a query hits, the hit page table entry is returned and the adapted query result is output, thereby reducing the pipeline stall caused by address translation delay. The query result based on the page table cache generates a prefetch request, and when the page table cache query misses, the prefetch operation is triggered, so that the page table entry that may be needed in the future can be more accurately predicted. The prefetch request is fed back to the multiplexer, the invalid page number of the page table cache is received, the first preset granularity page address is requested from the lower layer storage system and returned to the page table cache, and the page table query component also requests the second preset granularity page address from the lower layer storage system and returns it to the page table cache, so that multiple components work together to complete the acquisition and update of the page address.

Description

Technical Field

[0001] This application relates to the fields of computer architecture and program compilation technology, and in particular to a memory management unit, method and apparatus. Background Technology

[0002] The Memory Management Unit (MMU) is responsible for translating virtual addresses (Vaddr) into physical addresses (Paddr) based on page tables in memory. This translation requires multiple memory accesses, which reduces performance. Therefore, the processor uses an on-chip Translation Lookaside Buffer (TLB) for caching. However, the TLB is tightly coupled to the main memory pipeline and needs to respond quickly to address translation requests to ensure processor performance, limiting its capacity. As the virtual address space used by programs expands, the TLB struggles to cache all required page table entries, leading to more TLB failures. After a failure, the next level of memory with higher latency must be accessed to retrieve the page table entry, ultimately hindering overall processor performance. Summary of the Invention

[0003] The purpose of this application is to at least partially solve one of the technical problems in the related art.

[0004] To achieve the above objectives, a first aspect of this application provides a memory management unit connected to a first-level TLB, wherein the first-level TLB includes an instruction TLB coupled to an instruction fetch unit and a data TLB coupled to a data fetch / store execution unit, and the memory management device includes:

[0005] A multi-selector is used to receive page table query requests from the instruction TLB, the data TLB, the TLB failure queue, and the TLB prefetcher according to a preset strategy, and select one of them as the current request.

[0006] Page table caching is used to cache multi-level page table entries and respond to the current request to perform a query. If the query is successful, the successful page table entry is returned to the first-level TLB corresponding to the current request, and the successful access information is sent to the TLB prefetcher. If the query is unsuccessful, a miss result containing the failed virtual page number is sent to the TLB failure queue and page table query component, and the TLB prefetcher is triggered to start the prefetch operation based on the failed virtual page number.

[0007] The TLB failure queue is used to receive the miss result containing the failed virtual page number output by the page table cache, request the first preset granularity page address data block where the corresponding page table entry is located from the lower layer storage system based on the miss result, and send the obtained data block back to the page table cache for filling.

[0008] The page table lookup component is used to receive miss results from the page table cache, perform hardware page table traversal on the corresponding virtual address, and fill the page table entries obtained by the traversal into the page table cache. The corresponding virtual address is related to the miss result, and the hardware page table traversal operation is to access the second preset granularity page address page table mapped to the virtual address.

[0009] The TLB prefetcher is used to generate a prefetch request based on the hit access information or the miss invalid virtual page number provided by the page table cache, and to feed the prefetch request back to the multiselector.

[0010] To achieve the above objectives, a second aspect of this application provides a memory management method, the memory management method comprising:

[0011] The selector receives translation-related requests from the instruction TLB, data TLB, TLB failure queue, and TLB prefetcher, and selects one as the current request according to the pre-set control policy.

[0012] Use the page table cache to retrieve the page table entry corresponding to the current request;

[0013] If a page table cache lookup hits, the hit page table entry is returned to the instruction TLB or data TLB, and a prefetch request is generated based on the hit access information.

[0014] In the event of a page table cache miss, a miss result containing the invalid virtual page number is generated through the page table cache, and a first preset granularity page address data block corresponding to the invalid virtual page number is obtained based on the miss result for filling.

[0015] To achieve the above objectives, a third aspect of this application provides a memory management apparatus, comprising:

[0016] The acquisition module is used to receive translation-related requests from the instruction TLB, data TLB, TLB failure queue and TLB prefetcher through a multi-selector, and select one as the current request according to a pre-set control strategy.

[0017] The query module is used to query the page table entry corresponding to the current request using the page table cache; if the page table cache query is successful, the successful page table entry is returned to the instruction TLB or data TLB, and a prefetch request is generated based on the successful access information; if the page table cache query is unsuccessful, a miss result containing the invalid virtual page number is generated through the page table cache, and a first preset granularity page address data block corresponding to the invalid virtual page number and used for padding is obtained based on the miss result.

[0018] To achieve the above objectives, a fourth aspect of this application provides an electronic device, comprising: a processor; and a memory for storing processor-executable instructions; wherein the processor is configured to execute the instructions to implement the steps of the memory management method proposed in the second aspect of this application.

[0019] To achieve the above objectives, a fifth aspect of this application provides a computer-readable storage medium that, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform the steps of the memory management method proposed in the second aspect of this application.

[0020] To achieve the above objectives, a sixth aspect of this application provides a computer program product, including a computer program that, when executed by a processor in a communication device, implements the steps of the memory management method proposed in the second aspect of this application.

[0021] To achieve the above objectives, a seventh aspect of this application provides a chip that includes the memory management unit proposed in the first aspect of this application; or the chip includes a processing circuit and an interface circuit, wherein the interface circuit is used to acquire instructions and send the instructions to the processing circuit, and the processing circuit is used to execute the instructions to implement the steps of the memory management method proposed in the second aspect of this application.

[0022] In this embodiment, by deploying the TLB between the primary TLB and the underlying storage system, a connection can be established between the high-speed TLB and the low-speed underlying storage, bridging the performance gap. The multi-selector selects requests from multiple sources, including the instruction TLB, data TLB, TLB invalidation queue, and TLB prefetcher, and outputs them to the page table cache according to a preset strategy. This avoids multiple requests simultaneously competing for page table cache resources, reducing request conflicts and waiting time, and enabling the page table cache to respond to query requests more efficiently, thereby improving the overall cache access efficiency. By storing page table entries in the page table cache, when a query hits, the hit page table entry is returned to the primary TLB corresponding to the current request, and the hit access information is sent to the TLB prefetcher. This allows instructions and data to obtain the correct address translation information faster, reducing pipeline stalls caused by address translation delays and improving processor execution efficiency. The TLB invalidation queue receives invalidated virtual page numbers from the page table cache, requests page addresses with a first preset granularity from the lower-level storage system, and then sends these requests back to the page table cache. Simultaneously, the page table lookup unit requests page addresses with a second preset granularity from the lower-level storage system and sends these requests back to the page table cache. This collaborative process allows multiple components to work together to acquire and update page addresses, making TLB invalidation handling more orderly and efficient, avoiding the chaos and resource waste caused by processing multiple invalidation requests simultaneously. The TLB prefetcher generates prefetch requests based on provided hit access information or missing invalidated virtual page numbers. This allows for more accurate prediction of potentially needed page table entries and preloading them into the TLB, reducing the TLB miss rate during subsequent accesses and further improving memory access efficiency. The prefetch requests generated by the TLB prefetcher are fed back to the multiselector, participating in subsequent request processing. This allows for continuous optimization of the prefetch strategy based on actual operational conditions, improving the accuracy and effectiveness of prefetching.

[0023] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0024] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:

[0025] Figure 1 This is a schematic diagram illustrating address translation using a multi-level page table according to an embodiment of this application;

[0026] Figure 2 This is a schematic diagram of the RISC-V instruction set Sv39 virtual address provided according to an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the RISC-V 64-bit instruction set stap control register provided according to an embodiment of this application;

[0028] Figure 4 This is a schematic diagram of the address translation process in the RISC-V instruction set Sv39 provided according to an embodiment of this application;

[0029] Figure 5 This is a schematic diagram of the physical address of the RISC-V instruction set Sv39 according to an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of a RISC-V instruction set Sv39 three-level page table provided according to an embodiment of this application;

[0031] Figure 7 This is a schematic diagram of a RISC-V instruction set Sv39 page table entry provided according to an embodiment of this application;

[0032] Figure 8 This is a schematic diagram of the structure of a memory management unit provided in an embodiment of this application;

[0033] Figure 9 This is a flowchart illustrating a memory management method provided in an embodiment of this application.

[0034] Figure 10 This is a schematic diagram of the structure of a memory management device provided in an embodiment of this application;

[0035] Figure 11 This is a schematic diagram of the structure of an electronic device according to an embodiment of this application;

[0036] Figure 12 This is a schematic diagram of the structure of a chip according to an embodiment of this application. Detailed Implementation

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0038] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0039] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" and "suppose" as used herein can be interpreted as "when," "when," or "in response to a determination."

[0040] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0041] The Memory Management Unit (MMU) is a key component of the processor. Its responsibility is to translate virtual addresses (Vaddr) into physical addresses (Paddr) and perform memory access operations based on the translated physical addresses. Through this Vaddr-Paddr translation mechanism, physical memory resources can be dynamically allocated to various programs, allowing program development to focus solely on virtual addresses without needing to consider the actual limitations of the physical address space.

[0042] To achieve process isolation, each process is configured with an independent address space, and the addresses used during program execution are virtual addresses. Through the virtual-to-physical address translation mechanism, program security can be protected: even if two programs use the same virtual address, the MMU will map them to different physical addresses, effectively preventing unauthorized modification of the contents of a single program by other programs. By mapping the virtual addresses of different programs to the same physical address, resource sharing between programs can be achieved, improving the utilization efficiency of physical memory.

[0043] The page table is a key data structure for the MMU to implement address translation. Essentially, it is a translation table used to store the mapping relationship between virtual addresses and physical addresses. This translation table is stored in memory. In current technology, processors generally adopt a multi-level page table structure. Figure 1 This is a schematic diagram illustrating address translation using a multi-level page table according to an embodiment of this application.

[0044] like Figure 1As shown, the first-level virtual page number is used to index the first-level page table, the second-level virtual page number is used to index the second-level page table, and the third-level virtual page number is used to index the third-level page table. The page offset is the location of the virtual address within the basic storage unit of a "page" (the page offset of the physical address is exactly the same as the virtual address). The first-level page table is stored in physical memory, and its physical address is provided by the processor's registers (such as the SATA register of a RISC-V instruction set processor). The first-level page table entries store the physical base address of the second-level page table; the second-level page table entries store the physical base address of the third-level page table; and the third-level page table entries store the physical page number (i.e., the base address of the physical page where the target data is located).

[0045] In some scenarios, when performing virtual-to-physical address translation using a multi-level page table structure, it is necessary to access memory multiple times to query the page tables level by level to obtain the target mapping relationship. This process significantly increases the time overhead of address translation, resulting in a substantial decrease in the processor's memory access performance. To address the above technical shortcomings, existing technologies employ a Translation Lookaside Buffer (TLB) to build a high-speed cache mechanism on the processor chip. The TLB caches the entries (PTEs) in the page tables. When the processor issues an address translation request for a virtual address, the MMU first accesses and queries the TLB: if the TLB caches the virtual-to-physical address translation entry corresponding to the virtual address (i.e., TLB hit), the cached entry is directly invoked to complete the virtual-to-physical address translation; if the TLB does not cache the virtual-to-physical address translation entry corresponding to the virtual address (i.e., TLB miss), the MMU further accesses the underlying storage system or memory to query and obtain the virtual-to-physical address translation entry corresponding to the virtual address to complete the subsequent address translation operation.

[0046] In some scenarios, when using page tables to translate virtual addresses to physical addresses, if a process accesses the page table and finds that the corresponding Page Table Entry (PTE) is invalid, it means that the page to which this virtual address belongs has not yet been loaded into physical memory. Therefore, the page table does not store the mapping for this page, resulting in a Page Fault. The page needs to be retrieved from the underlying storage system, such as the hard drive, and loaded into physical memory. The starting address of this page in physical memory is then written into the page table. A Page Fault is a type of exception, and its handling is typically handled by software (the operating system) rather than hardware.

[0047] In some scenarios, the page tables supported by the MMU vary depending on the paging mechanism supported by the processor. Figure 2This is a schematic diagram of a RISC-V instruction set Sv39 virtual address provided according to an embodiment of this application. Figure 2 As shown, RISC-V (Fifth Generation Reduced Instruction Set Computing) processors support the Sv39 paging mechanism. The total length of the virtual address in Sv39 mode is 39 bits, with all bits divided into four fixed segments based on function. From the most significant bit to the least significant bit, these are VPN2 (Virtual Page Number 2), VPN1 (Virtual Page Number 1), VPN0 (Virtual Page Number 0), and Page Offset. VPN2, VPN1, and VPN0 each have 9 bits, forming a three-level page table; the lower 12 bits represent the Page Offset. Traversing the page table requires three memory accesses. To improve access efficiency, the page table needs to be cached; this is the main function of the TLB in the MMU.

[0048] The TLB (Translation Lookaside Buffer) is responsible for address translation. In Sv39 mode, the virtual address length is 39 bits, and the physical address length is 56 bits. Whether the virtual memory mechanism is enabled in a RISC-V instruction set processor depends on the STATP register. The STATP (Supervisor Address Translation and Protection) S-mode control status register controls the paging system. Figure 3 This is a schematic diagram of the RISC-V 64-bit instruction set stap control register provided according to an embodiment of this application, as shown below. Figure 3 As shown, SATAP has three fields. The MODE field enables paging and selects the page table level; the ASID (Address Space Identifier) ​​field is optional and can be used to reduce the overhead of context switching; the PPN field stores the physical address of the root page table, in units of 4KB page size.

[0049] In some scenarios, when paging is enabled in the SATAP register, virtual addresses in S-mode (Supervisor mode) and U-mode (User mode) are translated into physical addresses by traversing the page table from the root. The Sv39 page table contains 512 PTEs (page table entries), each PTE is 8 bytes, and each page table is 512 × 8 = 4096 bytes.

[0050] Figure 4 This is a schematic diagram of the address translation process in the RISC-V instruction set Sv39 provided according to an embodiment of this application. Figure 4As shown, the physical base address of the first-level page table is known (provided by the processor register). Combined with the "first-level virtual page number," the physical address of the first-level page table entry is calculated, and the entry is read (the entry stores the physical base address of the second-level page table). Using the "second-level page table physical base address" from the first-level page table entry, combined with the "second-level virtual page number," the physical address of the second-level page table entry is calculated, and the entry is read (the entry stores the physical base address of the third-level page table). Using the "third-level page table physical base address" from the second-level page table entry, combined with the "third-level virtual page number," the physical address of the third-level page table entry is calculated, and the entry is read (the entry stores the physical page number of the target data). The "physical page number" in the third-level page table entry is concatenated with the "page offset" of the virtual address to obtain the final physical address.

[0051] Figure 5 This is a schematic diagram of the physical address of the RISC-V instruction set Sv39 according to an embodiment of this application. Figure 5 As shown, the PPN field of the satp register gives the base address of the first-level page table, and Vaddr[38:30] gives the first-level page number. Therefore, the processor will read the page table entry located at address (satp.PPN×4096 + Vaddr[38:30]×8). This page table entry contains the base address of the second-level page table, and Vaddr[29:21] gives the second-level page number. Therefore, the processor will read the page table entry located at address (L1PTE.PPN×4096 + Vaddr[29:21]×8), where L1PTE represents the first-level page table entry (Level 1 Page Table Entry). This page table entry contains the base address of the third-level page table (which is also the leaf node page table; the leaf node is the lowest level of the effective mapping node in the multi-level page table), and Vaddr[20:12] gives the third-level page number. Therefore, the processor will read the page table entry located at address (L2PTE.PPN×4096 + Vaddr[29:21]×8). [20:12]×8) leaf node page table entries, where L2PTE represents a Level 2 Page Table Entry; the PPN field and the page offset (the lowest 12 significant bits of the original virtual address) of the leaf node page table entries constitute the final result: the physical address is LeafPTE.PPN×4096 + Vaddr[11:0], where LeafPTE represents a Leaf Page Table Entry.

[0052] Figure 6 This is a schematic diagram of a three-level page table for the RISC-V instruction set Sv39 provided according to an embodiment of this application. Figure 6 As shown, Sv39 uses base pages of 4KB. Page table entries are 8 bytes in size, allowing for larger physical addresses. To ensure the page table size matches the page size, the tree's radix is ​​reduced to 2.9 The tree also became three-level (three-level page table lookup). The 512GB address space of Sv39 was divided into 2... 9 Each gigabyte is 1GB in size. Each gigabyte is further divided into 2 9 Each of the following is a giant page. In Sv39, these giant pages are 2MB in size. Each giant page is further divided into 2... 9 A base page of 4KB size.

[0053] Figure 7 This is a schematic diagram of a RISC-V instruction set Sv39 page table entry provided according to an embodiment of this application. For example... Figure 7 As shown, the control information in a Page Table Entry (PTE) includes the V bit, RWX bit, U bit, G bit, A bit, and D bit. The V bit indicates whether the PTE is valid; if the V bit is 1, the PTE is valid.

[0054] The RWX bit is the permission bit, indicating whether the page is readable, writable, or executable; when all three are 0, the PTE is a pointer to the next lower page table; otherwise, it is a leaf page table entry.

[0055] The U bit indicates whether the page table can be used by user mode. When it is 1, it can be used by user mode.

[0056] The G bit represents the global mapping, which is a mapping that exists in all address spaces. For non-leaf PTEs, the global setting means that all mapping tables in subsequent levels of the page are global.

[0057] When the virtual address is read, written, or matched, the A bit of the corresponding PTE is set.

[0058] The D dirty bit is set when a virtual address is written to.

[0059] It should be noted that although the TLB effectively reduces address translation latency, its capacity cannot be significantly increased due to its tight coupling with the processor's main pipeline. As the program's virtual address space continues to expand, the probability of TLB misses (TLBMiss) increases significantly. After each TLB miss, the MMU needs to access the next-level cache or memory to retrieve page table entries, and the access latency of these storage components is much higher than that of the TLB, severely limiting processor performance. Therefore, how to further improve the TLB hit rate, or quickly retrieve the required page table entries from the nearest storage component when a TLB miss occurs, reducing the waiting time for the next-level storage, has become a critical problem that urgently needs to be solved in current MMU design.

[0060] A memory management apparatus and method according to an embodiment of this application are described below with reference to the accompanying drawings.

[0061] Figure 8 This is a schematic diagram of the structure of a memory management unit provided in an embodiment of this application.

[0062] like Figure 8 As shown, this memory management unit is connected to a Level 1 TLB. The Level 1 TLB includes an instruction TLB coupled to the instruction fetch unit and a data TLB coupled to the data fetch / store execution unit. This memory management unit includes:

[0063] A multi-selector is used to receive page table query requests from the instruction TLB, data TLB, TLB failure queue and TLB prefetcher according to a preset strategy, and select one of them as the current request.

[0064] Page Table Cache (TPCache) is used to cache multi-level page table entries and respond to current requests for queries. If the query is successful, the successful page table entry is returned to the first-level TLB (Instruction TLB or Data TLB) corresponding to the current request, and the successful access information is sent to the TLB prefetcher. If the query is unsuccessful, a miss result containing the failed virtual page number is sent to the TLB failure queue and page table query unit, and the TLB prefetcher is triggered to start a prefetch operation based on the failed virtual page number.

[0065] The TLB (Temporary Load Balancer) miss queue is used to receive miss results containing the missed virtual page number from the page table cache. Based on the miss result, it requests the data block of the first preset granularity page address where the corresponding page table entry is located from the lower storage system. The obtained data block is then sent back to the page table cache for filling. The lower storage system is a component of the processor architecture's "multi-level cache hierarchy". It is located between the first-level TLB and the main memory (i.e., main memory). It is a high-speed cache memory accessed based on physical address. It is a supplement and extension of the first-level TLB. Its capacity is usually larger than that of the first-level TLB. Its access latency is lower than that of the main memory but higher than that of the first-level TLB. It acts as a bridge between the first-level TLB and the main memory, reducing the frequency of the processor's direct access to high-latency memory.

[0066] The page table lookup unit is used to receive the miss result from the page table cache, perform hardware page table traversal on the corresponding virtual address, and fill the page table entries obtained by the traversal into the page table cache. The corresponding virtual address is related to the miss result, and the hardware page table traversal operation is to access the second preset granularity page address page table mapped to the virtual address.

[0067] The TLB prefetcher is used to generate a prefetch request based on the hit access information or the missed invalid virtual page number provided by the page table cache, and feeds the prefetch request back to the multiselector.

[0068] In one feasible implementation, the TLB failure queue is also used to receive page table query requests from the page table query unit that point to a first preset granularity page address, and to access the page table cache or the underlying storage system to continue the page table traversal process based on the physical address of the page table query request.

[0069] In one feasible implementation, the page table lookup component is also used for:

[0070] If a big page mapping or empty page mapping is hit while traversing the page table associated with the second preset granularity page address, the traversed page table entries are returned to the first-level TLB (instruction TLB or data TLB) corresponding to the current request.

[0071] If the traversal reaches a page table entry related to the first preset granularity page address, the page table entry related to the first preset granularity page address is used as a page table lookup request for the first preset granularity page address.

[0072] In some embodiments, the first preset granularity page address is a 4KB-level page address, the second preset granularity page address is a 1GB / 2MB-level page address, and the terminating node page table entry includes leaf nodes and empty pages. The leaf nodes include base pages (such as 4KB pages) and big pages (such as 2MB gigapages and 1GB gigapages).

[0073] In one feasible implementation, the memory access unit of the processor to which the memory management unit belongs includes at least one memory access pipeline, each memory access pipeline is configured with an independent data TLB, and the TLB in the pipeline used to execute data fetch instructions and the TLB in the pipeline used to execute data store instructions are configured to keep their contents consistent.

[0074] In some embodiments, the processor has at least one load / store pipeline, which can handle multiple memory access operations simultaneously, improving memory access parallelism. Each memory access pipeline is equipped with an independent data TLB to prevent the data TLB from becoming a performance bottleneck. Multiple memory access pipelines can perform virtual address to physical address translation queries simultaneously without being blocked due to port contention. The TLB in the pipeline executing fetch instructions and the TLB in the pipeline executing store instructions maintain consistency, avoiding memory access errors or data inconsistency issues caused by using incorrect or outdated address mappings.

[0075] In some embodiments, when any TLB needs to free up space to insert a new item, all TLBs use the same algorithm (such as LRU, pseudo-LRU, etc.) to decide which item to evict, ensuring that under the same conditions, all TLBs will choose to evict the same item. By using a unified replacement algorithm and backfill information, multiple TLBs maintain identical content, and mutual prefetching is achieved through content consistency.

[0076] In some embodiments, when a TLB miss occurs, after the page table lookup component obtains a new page table entry, backfill information, including the virtual page number, physical page frame number, and permission bits, is broadcast or written to all data TLBs simultaneously, instead of only writing to the TLB that triggered the miss, ensuring that the new mapping is established simultaneously in the data TLBs.

[0077] In one feasible implementation, the page table lookup component is configured to process page table access requests serially for accessing a first preset level structure of the page table; the TLB failure queue is configured to process multiple page table access requests in parallel for accessing a second preset level structure of the page table.

[0078] In some embodiments, if it is a three-level page table, the first preset level structure is the first two levels of the structure, and the second preset level structure is the last level of the structure.

[0079] In one feasible implementation, the page table cache is also used to store page table entries that meet preset conditions, and the page table cache access width is set according to the processor's cache line width. For example, the page table cache access width can be set to be equal to the processor's cache line width.

[0080] In some embodiments, a page table entry that meets preset conditions refers to a page table entry that can be used to successfully and securely translate a virtual address into a physical address.

[0081] In particular, according to embodiments of this application, the functions described in the above reference structural schematic diagram can be implemented as a chip, which includes the memory management unit provided in embodiments of this application.

[0082] Figure 9 This is a flowchart illustrating a memory management method provided in an embodiment of this application.

[0083] like Figure 9 As shown, this memory management method includes, but is not limited to, the following steps:

[0084] S901 receives translation-related requests from the instruction TLB, data TLB, TLB failure queue, and TLB prefetcher via a multiplexer, and selects one as the current request according to a pre-set control policy.

[0085] In one feasible implementation, the specific sorting rules of the pre-set control strategy include: treating translation-related requests from the instruction TLB or data TLB as the first priority (highest priority); treating translation-related requests from the TLB failure queue as the second priority; and treating translation-related requests from the TLB prefetcher as the third priority (lowest priority). The multi-selector outputs translation-related requests based on the pre-set control strategy, prioritizing higher-priority requests; when there are no higher-priority requests, or when there are at least two requests of the same priority, the requests are selected sequentially according to their timing.

[0086] In one feasible implementation, the pre-controlled control strategy also includes a round-robin strategy, in which the selector selects requests in a fixed order of “TLB failure queue request → instruction TLB request → data TLB request → TLB prefetcher request”, and outputs only one translation-related request in each round, ensuring that these four types of requests can be scheduled fairly.

[0087] In one feasible implementation, the pre-controlled strategy further includes a hybrid scheduling strategy. This hybrid scheduling strategy is as follows: when an instruction TLB or data TLB request exists, the highest priority translation-related request is selected according to a specific sorting rule (i.e., priority rule); when there is no instruction TLB or data TLB request, a round-robin strategy is used to select translation-related requests for the TLB failure queue and the TLB prefetcher; when there are no instruction TLB requests, data TLB requests, or TLB failure queue requests, the TLB prefetcher request is selected by the multiplexer.

[0088] S902, use the page table cache to query the page table entry corresponding to the current request.

[0089] In one feasible implementation, during the memory address translation process, the page table cache is divided into three independent sub-cache regions, wherein the sub-cache regions are used to store the data of each of the three levels of page tables, and each level of data contains the page table entries of the corresponding level.

[0090] In some embodiments, the three independent sub-cache regions include a first-level sub-cache region, a second-level sub-cache region, and a third-level sub-cache region. The first-level sub-cache region stores all valid page table entries of the first-level page table (e.g., a 1GB-level page table in the Sv39 architecture), including the mapping relationship between the virtual page number (VPN) of that level and the base address of the next-level page table, level permission identifiers, and other information. The second-level sub-cache region stores valid page table entries of the second-level page table (e.g., a 2MB-level page table in the Sv39 architecture), containing the mapping relationship between the corresponding VPN level and the base address of the third-level page table, as well as access control and caching attributes for that level. The third-level sub-cache region stores valid page table entries of the third-level page table (i.e., a 4KB-level page table in the Sv39 architecture), directly containing the final mapping relationship from virtual address to physical address, as well as complete attribute information such as read / write / execute (RWX) permissions, user-mode / global mapping (U / G) identifiers, access bit (A), and dirty bit (D).

[0091] In one feasible implementation, after receiving a translation-related request from the multiselector output, the page table cache completes a query operation of the three-level page table information within a single clock cycle based on a parallel query path, wherein the parallel query path is based on three independent sub-cache regions.

[0092] In some embodiments, page table cache lookup operations are triggered by translation-related requests output by a selector, with input signals including the complete virtual address (e.g., ...). Figure 4 (As shown) and request type identifiers (such as TLB invalidation queue request, instruction TLB request, data TLB request, TLB prefetcher request). The virtual address carries the virtual page number (VPN) after being split according to the page table hierarchy, providing basic data support for parallel queries.

[0093] In some embodiments, the parallel query path depends on three independent sub-cache regions. The sub-cache regions are completely independent in terms of physical storage, query control logic, and data output ports, and store valid page table entries (PTEs) of the first-level page table, second-level page table, and third-level page table, respectively. Each sub-cache region is equipped with a dedicated address decoding module and hit detection circuit.

[0094] In some embodiments, if the query operation results in a query hit, the page table cache returns the corresponding hit page table entry to the instruction TLB or data TLB, and outputs the adapted query result to the TLB prefetcher, TLB failure queue, or page table query unit, respectively. This includes: outputting an indication to the TLB prefetcher indicating whether the hit page table entry is a prefetch entry, and outputting decision feedback on the page table level hit status to the TLB failure queue or page table query unit. If the query operation results in a query miss, a miss query result containing the failed virtual page number is output to the TLB failure queue and page table query unit, and a query status is output to the TLB prefetcher to trigger a prefetch operation. This includes: determining the address of the page table entry to be prefetched in the contiguous address space based on the miss query result, and generating a prefetch request carrying the address of the page table entry to be prefetched, wherein the contiguous address space is related to the virtual address space to which the failed virtual page number belongs, and the prefetch request is used to trigger the prefetch operation.

[0095] In some embodiments, after receiving a translation-related request, the address decoding module completes the splitting of the virtual address within the same clock cycle, extracts the virtual page numbers (VPN[2], VPN[1], VPN[0]) of the first-level page table, second-level page table, and third-level page table, and synchronously sends the three virtual page numbers to the query port of the corresponding sub-cache area, while triggering the synchronous start of the three query paths. The three independent sub-cache areas synchronously perform hit judgment and data reading operations based on the received exclusive virtual page numbers. Each sub-cache area indexes its own cache entries through the virtual page number to determine whether there is a matching page table entry. If a hit is found, the complete information of the page table entry (including the base address of the next-level page table, access permissions, mapping identifier, etc.) is read; if a hit is found, the invalidation status is marked.

[0096] In some embodiments, at the end of the same clock cycle, the page table cache receives the query results (hit status + page table entry data) returned by the three sub-cache areas, completes the result summary and validity judgment, and forms the final three-level page table query feedback information (e.g., whether a certain level / multi-level page table is hit, the complete data of the hit page table entry, whether it is a leaf node mapping, etc.).

[0097] S903, when a page table cache lookup is successful, returns the successful page table entry to the instruction TLB or data TLB, and generates a prefetch request based on the successful access information.

[0098] In one feasible implementation, the page table cache includes a request source identifier decoding unit for parsing the source identifier sent by the selector along with the current request. This source identifier explicitly indicates the initiator of the current request. If the source identifier indicates that the current request originates from the instruction TLB, the hit page table entry and corresponding virtual page number are sent to the instruction TLB via the instruction TLB fill bus. If the source identifier indicates that the current request originates from the data TLB, the hit page table entry and corresponding virtual page number are sent to the data TLB via the data TLB fill bus. It should be noted that the instruction TLB fill bus and the data TLB fill bus can be physically independent to achieve parallel updates.

[0099] In one feasible implementation, when a page table cache query hits, the page table cache outputs an adapted query result to the TLB prefetcher, the TLB failure queue, or the page table query unit, respectively. In some embodiments, the page table cache outputs an indication to the TLB prefetcher indicating whether the hit page table entry is a prefetched entry, and outputs decision feedback on the page table hierarchy hit status to the TLB failure queue or the page table query unit.

[0100] In one feasible implementation, a pre-set prefetch algorithm is used to predict the page table entries that the processor will access, based on the hit access information, and the page table entries are pre-loaded into the page table cache.

[0101] In some embodiments, a next-row prefetch algorithm is used. When the page table cache access misses or the hit item is a prefetch item, a next prefetch request is generated. The prefetch request is sent to the page table cache for querying. If the prefetch request misses in the page table cache, the prefetch request is sent to the TLB invalidation queue for processing. The prefetch request is configured not to enter the page table query component for processing. The result obtained by prefetching is stored in the page table cache and is not returned to the first-level TLB.

[0102] In some embodiments, the execution flow of the pre-set prefetch algorithm includes: obtaining the starting address and fixed length of the page table entry that the processor will access; determining the address to be prefetched based on the starting address and fixed length of the page table entry; and, if the address to be prefetched has passed the validity check, reading the page table entry corresponding to the address to be prefetched from the lower storage system and writing it into the page table cache.

[0103] In one feasible implementation, if a prefetch request initiated by the TLB prefetcher enters the TLB invalidation queue, it is determined whether the first preset level structure of the page table to be accessed by the prefetch request is missing; if the first preset level structure is missing, the prefetch request is discarded to prevent it from occupying the processing resources of the page table cache and page table lookup unit.

[0104] In one feasible implementation, the prefetch granularity is set according to the width of the data returned by the underlying storage system, and the width of the returned data corresponds to the width of a cache line. During the prefetching process, if the retrieved data contains a page table entry with an invalid valid bit, a refetch operation is initiated based on hardware. If the valid bit of the page table entry is still invalid after the refetch operation, page fault exception handling is triggered based on software.

[0105] In some embodiments, the cache line width is 512 bits to allow multiple consecutive page table entries to be retrieved in a single prefetch operation. Hardware refetch operations involve re-accessing the underlying storage system to retrieve the data for the corresponding page table entry.

[0106] S904, if the page table cache query fails, generate a miss result containing the invalid virtual page number through the page table cache, and obtain a first preset granularity page address data block corresponding to the invalid virtual page number and used for filling based on the miss result.

[0107] In one feasible implementation, when a page table cache lookup fails, the page type to which the failed virtual page number belongs is identified, and the corresponding first preset granularity is matched. The acquisition of the first preset granularity page address data block is dominated by the TLB failure queue. In some embodiments, the first preset granularity page address is a 4KB-level page address.

[0108] After obtaining the first preset granularity page address, the page address is sent back to the page table cache. The page table cache then stores this page address in the corresponding sub-cache area, completing cache backfilling and providing fast query support for subsequent similar requests. The sent-back data includes complete page table entry information (Physical Page Number (PPN), RWX permission bits, U / G / A / D attribute bits, and V bit), ensuring the validity and integrity of the page table cache storage.

[0109] In one feasible implementation, the corresponding virtual address is obtained based on the miss result, a hardware page table traversal is performed on the corresponding virtual address, and the traversed page table entries are filled into the page table cache. The hardware page table traversal operation involves accessing the second preset granularity page address page table mapped to the virtual address. In some embodiments, the second preset granularity page address is a 1GB / 2MB level page address.

[0110] In some embodiments, the operation of performing hardware page table traversal on the corresponding virtual address includes: if a big page mapping or an empty page mapping is hit when traversing the page table associated with the second preset granularity page address, the traversed page table entry is returned to the first-level TLB corresponding to the current request; if a page table entry pointing to the first preset granularity page address is reached, the page table entry associated with the first preset granularity page address is used as a page table query request for the first preset granularity page address; or, if the page table query component still fails to find a page table entry after traversing to the last-level page table address, a query failure signal is output to trigger an exception handling process.

[0111] In one feasible implementation, the TLB failure queue receives the failed virtual page number output by the page table cache, requests a first preset granularity page address from the lower-level storage system based on the failed virtual page number, and sends the obtained first preset granularity page address back to the page table cache.

[0112] In one feasible implementation, a page table query request from the page table query unit and pointing to a first preset granularity page address is received through the TLB failure queue. Based on the physical address of the page table query request, the page table cache or the underlying storage system is accessed to continue the page table traversal process. If the page table query request for the first preset granularity page address is not ready, the page table query request for the first preset granularity page address is restarted through a multi-selector.

[0113] In some embodiments, the first preset granularity is the last-level page table (leaf node page table, i.e., 4KB-level page table) of the multi-level page table. The corresponding page table entries directly carry the final mapping relationship from virtual address to physical address, and this is the exclusive access granularity of the TLB failure queue. Because the Page Table Walker (PTW) is responsible for accessing terminating node page tables, the TLB failure queue focuses on the last-level page table to avoid hierarchical access conflicts and improve parallel efficiency. If the target page table entry exists in the lower-level storage system, it is read directly from the lower-level storage system; if the lower-level storage system does not find the entry, it is retrieved from main memory.

[0114] In one feasible implementation, if the query of the instruction TLB or data TLB fails, a page table query request is sent to the page table cache; if the page table cache is hit, the corresponding page table entry is returned to the instruction TLB or data TLB; if the page table cache fails, the request is assigned to the page table query unit or the TLB failure queue for processing according to the busy / idle status of the page table query unit.

[0115] In some embodiments, if the page table lookup unit is idle, a request is sent to the page table lookup unit to traverse multi-level page tables, wherein the multi-level page tables are related to the underlying storage system; if the page table lookup unit is busy, the request is sent to the TLB invalidation queue for buffering.

[0116] In summary, the memory management unit and method provided in this application, by deploying between the first-level TLB and the underlying storage system, can bridge the performance gap between the high-speed TLB and the low-speed underlying storage. The multi-selector selects one request from multiple sources, including the instruction TLB, data TLB, TLB invalidation queue, and TLB prefetcher, and outputs it to the page table cache according to a preset strategy. This avoids multiple requests simultaneously competing for page table cache resources, reduces request conflicts and waiting time, and enables the page table cache to respond to query requests more efficiently, thereby improving the overall cache access efficiency. By storing page table entries in the page table cache, when a query hits, the hit page table entry is returned to the first-level TLB corresponding to the current request, and the hit access information is sent to the TLB prefetcher. This allows instructions and data to obtain the correct address translation information faster, reducing pipeline stalls caused by address translation delays and improving processor execution efficiency. The TLB invalidation queue receives invalidated virtual page numbers from the page table cache, requests page addresses with a first preset granularity from the lower-level storage system, and then sends these requests back to the page table cache. Simultaneously, the page table lookup unit requests page addresses with a second preset granularity from the lower-level storage system and sends these requests back to the page table cache. This collaborative process allows multiple components to work together to acquire and update page addresses, making TLB invalidation handling more orderly and efficient, avoiding the chaos and resource waste caused by processing multiple invalidation requests simultaneously. The TLB prefetcher generates prefetch requests based on provided hit access information or missing invalidated virtual page numbers. This allows for more accurate prediction of potentially needed page table entries and preloading them into the TLB, reducing the TLB miss rate during subsequent accesses and further improving memory access efficiency. The prefetch requests generated by the TLB prefetcher are fed back to the multiselector, participating in subsequent request processing. This allows for continuous optimization of the prefetch strategy based on actual operational conditions, improving the accuracy and effectiveness of prefetching.

[0117] Corresponding to the memory management method described above, this application also provides a memory management device. Since the embodiments of the memory management device in this application correspond to the embodiments of the memory management method described above, details not disclosed in the embodiments of the memory management device can be found in the embodiments of the memory management method, and will not be repeated here.

[0118] Figure 10 This is a schematic diagram of the structure of a memory management device provided in an embodiment of this application.

[0119] like Figure 10 As shown, the memory management device 1000 includes:

[0120] The acquisition module 1001 is used to receive translation-related requests from the instruction TLB, data TLB, TLB failure queue and TLB prefetcher through a multi-selector, and select one as the current request according to a pre-set control strategy.

[0121] The query module 1002 is used to query the page table entry corresponding to the current request using the page table cache; if the page table cache query is successful, the successful page table entry is returned to the instruction TLB or data TLB, and a prefetch request is generated based on the successful access information; if the page table cache query is unsuccessful, a miss result containing the invalid virtual page number is generated through the page table cache, and a first preset granularity page address data block corresponding to the invalid virtual page number and used for filling is obtained based on the miss result.

[0122] In one feasible implementation, the memory management device 1000 is configured to execute the memory management steps provided in the embodiments of this application. In some embodiments, the memory management device has specific functional modules, algorithms, or logic, and is able to query the page table entry corresponding to the current request using the page table cache according to a series of steps, rules, and strategies of the memory management method described in the embodiments of this application. In some embodiments, by writing specific program code, the memory management method is transformed into instructions that the memory management device can understand and execute. This code may include logic such as condition judgment, loop control, and data processing, and uses the page table cache to query the page table entry corresponding to the current request.

[0123] The methods and apparatus provided in the embodiments of this application have been described above. To achieve the functions of the methods provided in the embodiments of this application, the methods and apparatus can be further refined using electronic devices.

[0124] Figure 11 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of this application. Figure 11 The electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0125] like Figure 11 As shown, the electronic device 1100 includes a processor 1101, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1102 or a program loaded from memory 1106 into random access memory (RAM) 1103. The RAM 1103 also stores various programs and data required for the operation of the electronic device 1100. The processor 1101, ROM 1102, and RAM 1103 are interconnected via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0126] The following components are connected to I / O interface 1105: memory 1106 including hard disks, etc.; and communication section 1107 including network interface cards such as LAN (Local Area Network) cards, modems, etc., which performs communication processing via a network such as the Internet; and driver 1108 is also connected to I / O interface 1105 as needed.

[0127] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 1107. When the computer program is executed by processor 1101, it performs the functions defined in the methods of this application.

[0128] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory including instructions, which can be executed by the processor 1101 of the electronic device 1100 to perform the above-described method. Optionally, the storage medium may be a non-transitory computer-readable storage medium, such as a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device.

[0129] In this application, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this application, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can transmit, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wireless, wireline, optical fiber, RF, etc., or any suitable combination thereof.

[0130] This application also provides a chip, which can be referred to in the embodiments. Figure 12 The diagram shows the chip structure. Figure 12 The chip shown includes a central processing unit 1201 and an interface circuit 1202. The number of central processing units 1201 and the number of interface circuits 1202 can be one or more.

[0131] Optionally, the chip also includes a storage device 1203 for storing necessary computer programs and data; an interface circuit 1202 for receiving signals from the storage device 1203 and sending signals to the processor 1201, the signals including computer instructions stored in the storage device 1203, and when the processor 1201 executes the computer instructions, causing the electronic device to perform the memory management method described in the above embodiments of this disclosure.

[0132] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0133] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A memory management unit connected to a primary TLB, the primary TLB comprising an instruction TLB coupled to an instruction fetch unit and a data TLB coupled to a data fetch / store execution unit, characterized in that, include: A multi-selector is used to receive page table query requests from the instruction TLB, the data TLB, the TLB failure queue, and the TLB prefetcher according to a preset strategy, and select one of them as the current request. Page table cache is used to cache multi-level page table entries and respond to the current request to perform a query; if the query is successful, the successful page table entry is returned to the first-level TLB corresponding to the current request, and the successful access information is sent to the TLB prefetcher. If the query fails, a miss result containing the failed virtual page number is sent to the TLB failure queue and page table query component, and the TLB prefetcher is triggered to start a prefetch operation based on the failed virtual page number. The TLB failure queue is used to receive the miss result containing the failed virtual page number output by the page table cache, request the first preset granularity page address data block where the corresponding page table entry is located from the lower layer storage system based on the miss result, and send the obtained data block back to the page table cache for filling. The page table lookup component is used to receive miss results from the page table cache, perform hardware page table traversal on the corresponding virtual address, and fill the page table entries obtained by the traversal into the page table cache. The corresponding virtual address is related to the miss result, and the hardware page table traversal operation is to access the second preset granularity page address page table mapped to the virtual address. The TLB prefetcher is used to generate a prefetch request based on the hit access information or the miss invalid virtual page number provided by the page table cache, and to feed the prefetch request back to the multiselector.

2. The memory management unit according to claim 1, characterized in that, The TLB failure queue is also used for: The system receives a page table query request from the page table query component and points to a page address with a first preset granularity. Based on the physical address of the page table query request, it accesses the page table cache or the underlying storage system to continue the page table traversal process.

3. The memory management unit according to claim 1, characterized in that, The page table query component is also used for: If a big page mapping or an empty page mapping is hit when traversing the page table associated with the second preset granularity page address, the traversed page table entries are returned to the first-level TLB corresponding to the current request; If the traversal reaches a page table entry related to the first preset granularity page address, the page table entry related to the first preset granularity page address is used as a page table lookup request for the first preset granularity page address.

4. The memory management unit according to claim 1, characterized in that, Also includes: The memory access unit of the processor to which the memory management unit belongs includes at least one memory access pipeline. Each memory access pipeline is configured with an independent data TLB, and the TLB in the pipeline used to execute data fetch instructions and the TLB in the pipeline used to execute data store instructions are configured to keep their contents consistent.

5. The memory management unit according to claim 1, characterized in that, Also includes: The page table query component is configured to process page table access requests in a serial manner for accessing the first preset level structure of the page table. The TLB failure queue is configured to process multiple page table access requests in parallel for accessing the second preset level structure of the page table.

6. The memory management unit according to claim 1, characterized in that, The page table cache is also used to store page table entries that meet preset conditions, and the page table cache access width is set according to the processor's cache line width.

7. A memory management method, characterized in that, include: The selector receives translation-related requests from the instruction TLB, data TLB, TLB failure queue, and TLB prefetcher, and selects one as the current request according to the pre-set control policy. Use the page table cache to retrieve the page table entry corresponding to the current request; If a page table cache lookup hits, the hit page table entry is returned to the instruction TLB or data TLB, and a prefetch request is generated based on the hit access information. In the event of a page table cache miss, a miss result containing the invalid virtual page number is generated through the page table cache, and a first preset granularity page address data block corresponding to the invalid virtual page number is obtained based on the miss result for filling. The step of selecting one as the current request according to a pre-set control strategy includes: Translate requests related to the instruction TLB or data TLB are given the first priority, translate requests related to the TLB failure queue are given the second priority, and translate requests related to the TLB prefetcher are given the third priority. The selector selects one translation-related request to output based on a preset control strategy. If there are at least two translation-related requests of the same priority, they are output sequentially according to the receiving time sequence. The step of querying the page table entry corresponding to the current request using the page table cache includes: During the memory address translation process, the page table cache is divided into three independent sub-cache areas, wherein the sub-cache areas are used to store the data of each of the three levels of page tables, and each level of data contains the page table entries of the corresponding level. Upon receiving the translation-related request from the multiselector, the page table cache completes the query operation of the three-level page table information within a single clock cycle based on the parallel query path, wherein the parallel query path is based on three independent sub-cache regions.

8. The method according to claim 7, characterized in that, The scenario where a page table cache lookup fails also includes: Based on the miss result, the corresponding virtual address is obtained. A hardware page table traversal is performed on the corresponding virtual address, and the page table entries obtained by the traversal are filled into the page table cache. The hardware page table traversal operation is to access the second preset granularity page address page table mapped to the virtual address.

9. The method according to claim 7, characterized in that, The method also includes the following when a page table cache lookup fails: The TLB failure queue receives page table query requests from the page table query unit that point to a first preset granularity page address. Based on the physical address of the page table query request, the TLB fails to access the page table cache or the underlying storage system to continue the page table traversal process. If the page table query request for the first preset granularity page address is not ready, the page table query request for the first preset granularity page address is restarted via a selector.

10. The method according to claim 8, characterized in that, The step of performing a hardware page table traversal on the corresponding virtual address further includes: If a big page mapping or an empty page mapping is hit when traversing the page table associated with the second preset granularity page address, the traversed page table entries are returned to the first-level TLB corresponding to the current request; If the traversal reaches a page table entry related to the first preset granularity page address, the page table entry related to the first preset granularity page address is used as a page table query request for the first preset granularity page address; Alternatively, if the page table query component is traversed to the last-level page table address and no page table entry is found, a query failure signal is output to trigger the exception handling process.

11. The method according to claim 7, characterized in that, Also includes: The TLB failure queue receives the failed virtual page number output by the page table cache, requests a first preset granularity page address from the lower-level storage system based on the failed virtual page number, and sends the obtained first preset granularity page address back to the page table cache.

12. The method according to claim 7, characterized in that, The pre-set control strategy also includes a polling control strategy.

13. The method according to claim 7, characterized in that, The step of returning the hit page table entry to the instruction TLB or data TLB when the page table cache query is successful also includes: The page table cache outputs adapted query results to the TLB prefetcher, TLB invalidation queue, or page table lookup unit, respectively.

14. The method according to claim 13, characterized in that, The page table cache outputs adapted query results to the TLB prefetcher, TLB invalidation queue, or page table lookup unit, including: The page table cache outputs a representation of whether a hit page table entry is a prefetch entry to the TLB prefetcher, and outputs decision feedback on the page table level hit status to the TLB invalidation queue or page table lookup unit.

15. The method according to claim 7, characterized in that, The generation of a prefetch request based on the hit access information includes: A prefetch algorithm is used to predict the page table entries that the processor will access, based on the access information obtained from the hit, and the page table entries are loaded into the page table cache in advance.

16. The method according to claim 15, characterized in that, Also includes: In response to a prefetch request initiated by the TLB prefetcher entering the TLB failure queue, it is determined whether the first preset level structure of the page table to be accessed by the prefetch request is missing. If the first preset level structure is missing, the prefetch request is discarded.

17. The method according to claim 15, characterized in that, The execution flow of the pre-set prefetch algorithm includes: Obtain the starting address and fixed length of the page table entry that the processor will access; determine the address to be prefetched based on the starting address and fixed length of the page table entry; if the address to be prefetched has passed the validity check, read the page table entry corresponding to the address to be prefetched from the lower storage system and write it to the page table cache.

18. The method according to claim 17, characterized in that, Also includes: The next-row prefetch algorithm is adopted. When the page table cache access misses or the hit item is a prefetch item, the next prefetch request is generated. The prefetch request is sent to the page table cache for querying. If the prefetch request is not found in the page table cache, the prefetch request is sent to the TLB invalidation queue for processing, wherein the prefetch request is configured not to be processed by the page table lookup unit; and the result obtained by prefetching is stored in the page table cache.

19. The method according to claim 17, characterized in that, Also includes: The prefetch granularity is set according to the width of the data returned by the underlying storage system, wherein the width of the returned data corresponds to the width of a cache line; During the prefetch process, if the acquired data contains page table entries with invalid valid bits, a hardware-based refetch operation is initiated. If the valid bit of the page table entry is still invalid after the fetch operation, a page fault exception is triggered based on software.

20. The method according to claim 7, characterized in that, Also includes: In response to a query miss in the instruction TLB or data TLB, a page table query request is sent to the page table cache; If the page table cache is hit, the corresponding page table entry will be returned to the instruction TLB or data TLB; If the page table cache is missed, the request will be assigned to the page table query unit or the TLB invalidation queue for processing, depending on the busy / idle status of the page table query unit.

21. The method according to claim 20, characterized in that, The step of allocating requests to the page table lookup unit or the TLB failure queue for processing based on the busy / idle status of the page table lookup unit includes: If the page table lookup component is idle, a request will be sent to the page table lookup component to traverse multiple levels of page tables; If the page table lookup unit is busy, the request will be sent to the TLB failure queue for buffering.

22. A memory management device, characterized in that, include: The acquisition module is used to receive translation-related requests from the instruction TLB, data TLB, TLB failure queue and TLB prefetcher through a multi-selector, and select one as the current request according to a pre-set control strategy. The query module is used to query the page table entry corresponding to the current request using the page table cache; if the page table cache query is successful, the successful page table entry is returned to the instruction TLB or data TLB, and a prefetch request is generated based on the successful access information; if the page table cache query is unsuccessful, a miss result containing the invalid virtual page number is generated through the page table cache, and a first preset granularity page address data block corresponding to the invalid virtual page number and used for padding is obtained based on the miss result. The acquisition module is also used for: Translate requests related to the instruction TLB or data TLB are given the first priority, translate requests related to the TLB failure queue are given the second priority, and translate requests related to the TLB prefetcher are given the third priority. The selector selects one translation-related request to output based on a preset control strategy. If there are at least two translation-related requests of the same priority, they are output sequentially according to the receiving time sequence. The query module is also used for: During the memory address translation process, the page table cache is divided into three independent sub-cache areas, wherein the sub-cache areas are used to store the data of each of the three levels of page tables, and each level of data contains the page table entries of the corresponding level. Upon receiving the translation-related request from the multiselector, the page table cache completes the query operation of the three-level page table information within a single clock cycle based on the parallel query path, wherein the parallel query path is based on three independent sub-cache regions.

23. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the steps of the memory management method as described in any one of claims 7 to 21.

24. A non-transitory computer-readable storage medium, characterized in that, When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device is able to perform the steps of the memory management method as described in any one of claims 7 to 21.

25. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the memory management method according to any one of claims 7 to 21.

26. A chip, characterized in that, The chip includes a memory management unit as described in any one of claims 1 to 3; or the chip includes one or more interface circuits and one or more processors; the interface circuits are configured to receive signals from the memory of the electronic device and send the signals to the processors, the signals including computer instructions stored in the memory, which, when executed by the processor, cause the electronic device to perform the steps of the memory management method as described in any one of claims 7 to 21.

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