Display device and driving method thereof

Abstract

The embodiment of the invention provides a display device and a driving method thereof. The display device comprises N rows of pixel units and N levels of gate driving units, wherein the ith level of gate driving unit is electrically connected with a gate line of the ith row of pixel units. The ith-level gate driving unit comprises a pull-up unit and a reset unit, the pull-up unit is electrically connected with a first node, a gate driving signal output end and a level transmission signal output end, the reset unit comprises a first reset subunit and a second reset subunit, the first reset subunit is electrically connected with a first reset control signal line, and the second reset subunit is electrically connected with a second reset control signal line. The second reset subunit is electrically connected with a second reset control signal line. The first reset subunit and the second reset subunit are electrically connected with the first node, the gate drive signal output end and the level transmission signal output end. According to the display device provided by the embodiment of the invention, the charge emptying capability of the gate driving unit on the key node is enhanced, the working time of the thin film transistor is shortened, and the reliability of the gate driving unit is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display device and its driving method. Background Technology

[0002] Gate-driver-on-array (GOA) circuits are widely used in display panels to provide gate drive signals to pixel units. Traditional gate-driver circuits consist of multiple cascaded gate-driver units. Each gate-driver unit typically includes a pull-up control module, a pull-up module, a pull-down module, a pull-down sustaining module, and a reset module. These functional modules are composed of multiple thin-film transistors.

[0003] With the development of the display panel industry, oxide semiconductor thin-film transistors (TFTs) are being used in gate drive circuits due to their excellent electrical characteristics. TFTs have low leakage current characteristics, which makes it difficult for residual charge at critical nodes in the gate drive unit to be released through leakage current. The inability to effectively release residual charge at critical nodes affects the operational stability of the gate drive circuit. Furthermore, TFTs in the gate drive unit are prone to electrical performance degradation under prolonged operation and exposure to large voltage differences, leading to gate drive unit failure and reducing the reliability of the gate drive circuit.

[0004] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this application is to provide a display device and its driving method, which aims to improve the reliability of the gate driving circuit using oxide semiconductor thin film transistors.

[0006] This application provides a display device, which includes a display panel. The display panel includes at least one gate driving circuit and a plurality of pixel units. The plurality of pixel units include N rows of pixel units. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line of the i-th row of pixel units, where i and N are positive integers, and i is less than or equal to N. The i-th level gate driving unit includes: a pull-up unit electrically connected to a first node, a gate driving signal output terminal, and a cascade signal output terminal; and a reset unit including a first reset subunit and a second reset subunit. The first reset subunit is electrically connected to a first reset control signal line, and the second reset unit is electrically connected to a second reset control signal line. Both the first reset subunit and the second reset unit are electrically connected to the first node, the gate driving signal output terminal, and the cascade signal output terminal.

[0007] In the above-described display device, the first reset subunit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor is electrically connected to the first reset control signal line. One of the source and drain of the first transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the first transistor is electrically connected to the first node. The gate of the second transistor is electrically connected to the first reset control signal line. One of the source and drain of the second transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the second transistor is electrically connected to the stage signal output terminal. The gate of the third transistor is electrically connected to the first reset control signal line. One of the source and drain of the third transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the third transistor is electrically connected to the gate drive signal output terminal.

[0008] In the above-described display device, the second reset subunit includes a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the fourth transistor is electrically connected to the second reset control signal line, one of the source and drain of the fourth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the fourth transistor is electrically connected to the first node. The gate of the fifth transistor is electrically connected to the second reset control signal line, one of the source and drain of the fifth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the fifth transistor is electrically connected to the stage signal output terminal. The gate of the sixth transistor is electrically connected to the second reset control signal line, one of the source and drain of the sixth transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the sixth transistor is electrically connected to the gate drive signal output terminal.

[0009] In the above-mentioned display device, the gate driving circuit further includes a first start signal line and a second start signal line. The pull-up control unit of the first stage to the A / 2 stage gate driving unit is electrically connected to the first start signal line, and the pull-up control unit of the A / 2+1 stage to the A stage gate driving unit is electrically connected to the second start signal line, wherein A is the number of clock signal lines of the gate driving circuit.

[0010] In the above-described display device, the gate driving circuit further includes a first start signal line and a second start signal line; the reset unit further includes a seventh transistor and an eighth transistor, the gate of the seventh transistor is electrically connected to the first start signal line, one of the source and drain of the seventh transistor is electrically connected to a second power supply signal line, the other of the source and drain of the seventh transistor is electrically connected to at least one of the first node, the gate driving signal output terminal, and the cascade signal output terminal, the gate of the eighth transistor is electrically connected to the second start signal line, one of the source and drain of the eighth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eighth transistor is electrically connected to at least one of the first node, the gate driving signal output terminal, and the cascade signal output terminal.

[0011] In the above-described display device, the i-th stage gate driving unit further includes a pull-down sustaining unit, comprising a first inverter and a second inverter. The first inverter is electrically connected to a first control signal line, a second control signal line, a first node, the gate driving signal output terminal, and the stage transmission signal output terminal. The second inverter is electrically connected to the first control signal line, the second control signal line, the first node, the gate driving signal output terminal, and the stage transmission signal output terminal. The first control signal transmitted by the first control signal line is out of phase with the second control signal transmitted by the second control signal line.

[0012] In the aforementioned display device, the first inverter includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; the pull-down sustaining unit further includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; the gate of the ninth transistor is electrically connected to the first control signal line, one of the source and drain of the ninth transistor is electrically connected to the first power supply signal line, and the other of the source and drain of the ninth transistor is electrically connected to the second node; the gate of the tenth transistor is electrically connected to the second control signal line, one of the source and drain of the tenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the tenth transistor is electrically connected to the second node; the gate of the eleventh transistor is electrically connected to the stage signal output terminal of the ixth stage gate drive unit, one of the source and drain of the eleventh transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eleventh transistor is electrically connected to the second node; the twelfth transistor... The gate of the 12th transistor is electrically connected to the first node. One of the source and drain of the 12th transistor is electrically connected to the second power signal line, and the other of the source and drain of the 12th transistor is electrically connected to the second node. The gate of the 13th transistor is electrically connected to the second node. One of the source and drain of the 13th transistor is electrically connected to the third power signal line, and the other of the source and drain of the 13th transistor is electrically connected to the gate drive signal output terminal. The gate of the 14th transistor is electrically connected to the second node. One of the source and drain of the 14th transistor is electrically connected to the second power signal line, and the other of the source and drain of the 14th transistor is electrically connected to the first node. The gate of the 15th transistor is electrically connected to the second node. One of the source and drain of the 15th transistor is electrically connected to the second power signal line, and the other of the source and drain of the 15th transistor is electrically connected to the stage drive signal output terminal, where x is a positive integer.

[0013] In the above-described display device, the channel widths of the eleventh transistor and the twelfth transistor are greater than the channel width of the tenth transistor, and the channel width of the tenth transistor is greater than the channel width of the ninth transistor.

[0014] In the aforementioned display device, the second inverter includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; the pull-down sustaining unit further includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; the gate of the sixteenth transistor is electrically connected to the second control signal line, one of the source and drain of the sixteenth transistor is electrically connected to the first power supply signal line, and the other of the source and drain of the sixteenth transistor is electrically connected to the third node; the gate of the seventeenth transistor is electrically connected to the first control signal line, one of the source and drain of the seventeenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the seventeenth transistor is electrically connected to the third node; the gate of the eighteenth transistor is electrically connected to the stage transmission signal output terminal of the ixth stage gate drive unit, one of the source and drain of the eighteenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eighteenth transistor is electrically connected to the third node; the nineteenth transistor... The gate of the body transistor is electrically connected to the first node. One of the source and drain of the nineteenth transistor is electrically connected to the second power signal line, and the other of the source and drain of the nineteenth transistor is electrically connected to the third node. The gate of the twentieth transistor is electrically connected to the third node. One of the source and drain of the twentieth transistor is electrically connected to the third power signal line, and the other of the source and drain of the twentieth transistor is electrically connected to the gate drive signal output terminal. The gate of the twenty-first transistor is electrically connected to the third node. One of the source and drain of the twenty-first transistor is electrically connected to the second power signal line, and the other of the source and drain of the twenty-first transistor is electrically connected to the stage drive signal output terminal. The gate of the twenty-second transistor is electrically connected to the third node. One of the source and drain of the twenty-second transistor is electrically connected to the second power signal line, and the other of the source and drain of the twenty-second transistor is electrically connected to the first node, where x is a positive integer.

[0015] In the above-described display device, the channel widths of the eighteenth and nineteenth transistors are greater than the channel width of the seventeenth transistor, and the channel width of the seventeenth transistor is greater than the channel width of the sixteenth transistor.

[0016] In the above-described display device, the transistor in the i-th gate driving unit is an oxide semiconductor thin-film transistor.

[0017] This application also provides a driving method for a display device, the display device including a display panel, the display panel including at least one gate driving circuit and a plurality of pixel units, the plurality of pixel units including N rows of pixel units, the gate driving circuit including N levels of gate driving units, the i-th level gate driving unit being electrically connected to the gate line of the i-th row of pixel units, the i-th level gate driving unit including a reset unit, the reset unit including a first reset sub-unit and a second reset sub-unit, the first reset sub-unit being electrically connected to a first reset control signal line, the second reset unit being electrically connected to a second reset control signal line, wherein i and N are positive integers, and i is less than or equal to N; the driving method includes: during a reset phase, the first reset sub-unit and the second reset unit respectively pull down the potentials of the first node, the gate driving signal output terminal and the cascade signal output terminal to a low potential state at different time periods.

[0018] In the above driving method, the first reset subunit includes a first transistor, a second transistor, and a third transistor, and the second reset subunit includes a fourth transistor, a fifth transistor, and a sixth transistor. The driving method further includes: during a first reset time period, pulling down the potential of the first node to a low potential state through the first transistor, pulling down the potential of the stage transmission signal output terminal to a low potential state through the second transistor, and pulling down the potential of the gate drive signal output terminal to a low potential state through the third transistor; and during a second reset time period, pulling down the potential of the first node to a low potential state through the fourth transistor, pulling down the potential of the stage transmission signal output terminal to a low potential state through the fifth transistor, and pulling down the potential of the gate drive signal output terminal to a low potential state through the sixth transistor.

[0019] In the display device provided in the embodiments of this application, the reset unit of the i-th stage gate driving unit includes a first reset sub-unit and a second reset sub-unit. The first reset sub-unit is electrically connected to a first reset control signal line, and the second reset sub-unit is electrically connected to a second reset control signal line. Both the first and second reset sub-units are electrically connected to a first node, a gate driving signal output terminal, and a stage transmission signal output terminal. The first and second reset sub-units pull down the potentials of the first node, the gate driving signal output terminal, and the stage transmission signal output terminal at different time periods, thereby enhancing the charge clearing capability of the gate driving unit for critical nodes. Since oxide semiconductor thin-film transistors have low leakage current, residual charge at critical nodes is difficult to release through leakage current. By setting two sets of reset sub-units, each connected to different reset control signal lines, charge clearing of critical nodes at different time periods improves the efficiency of charge clearing. The first and second reset sub-units operate at different time periods, shortening the operating time of the thin-film transistors in each set of reset sub-units, mitigating the electrical performance degradation problem caused by prolonged operation of the thin-film transistors, and improving the reliability of the gate driving unit.

[0020] In the display device provided in the embodiments of this application, the pull-down sustaining unit includes a first inverter and a second inverter. The first inverter is electrically connected to a first control signal line, a second control signal line, a first node, a gate drive signal output terminal, and a cascade signal output terminal. The second inverter is also electrically connected to the first control signal line, the second control signal line, the first node, the gate drive signal output terminal, and the cascade signal output terminal. The first control signal transmitted by the first control signal line is inversely related to the second control signal transmitted by the second control signal line. When the first inverter is in the working state, the second inverter is in the non-working state. The thin-film transistor in the second inverter, electrically connected to the first control signal line, is turned on, releasing the residual charge at the node of the second inverter. When the second inverter is in the working state, the first inverter is in the non-working state. The thin-film transistor in the first inverter, electrically connected to the second control signal line, is turned on, releasing the residual charge at the node of the first inverter. The residual charge at the node of the inverter in the non-working state is continuously released, reducing the risk that the oxide semiconductor thin-film transistor cannot release the residual charge through leakage current when the display device is in an abnormal situation, and improving the stability of the gate drive unit. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a display device provided in an embodiment of this application.

[0022] Figure 2 A circuit diagram of the i-th stage gate driving unit of the gate driving circuit of the display device provided in an embodiment of this application. Detailed Implementation

[0023] The specific embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0024] The terms “first,” “second,” and similar words do not indicate any order, quantity, or importance, but are merely used to distinguish different technical features. The terms “multiple,” and similar words mean two or more, unless otherwise expressly specified.

[0025] The technical solutions of different embodiments of this application can be combined with each other.

[0026] The display device provided in the embodiments of this application may be, for example, an LCD display device, an OLED display device, a Mini-LED display device, or a Micro-LED display device. The embodiments of this application will be described using an LCD display device as an example.

[0027] like Figure 1 As shown, an embodiment of this application provides a display device, which includes a display panel, a source driver chip, and a timing controller. The display panel includes at least one gate driver circuit, multiple pixel units PX, multiple data lines DATA, and multiple gate lines SCAN.

[0028] In the display device of this application, a source driver chip is electrically connected to multiple data lines DATA, and a timing controller is electrically connected to the source driver chip and the gate driver circuit. The timing controller is configured to provide control signals to the source driver chip and the gate driver circuit. The timing controller receives externally input image data and control signals. After processing the image data, the timing controller transmits it to the source driver chip. The source driver chip generates a data voltage signal based on the image data and transmits it to the pixel unit PX through multiple data lines DATA. The timing controller also provides clock signals, control signals, etc., to the gate driver circuit. The gate driver circuit generates a gate drive signal based on the clock signal and control signals and transmits it to the pixel unit PX through multiple gate lines SCAN. The pixel unit PX includes a thin-film transistor and a liquid crystal capacitor. The gate of the thin-film transistor is electrically connected to the gate line SCAN, the source of the thin-film transistor is electrically connected to the data line DATA, and the drain of the thin-film transistor is electrically connected to one electrode of the liquid crystal capacitor. When the gate drive signal transmitted by the gate line SCAN is at an effective level, the thin-film transistor is turned on, and the data voltage signal transmitted by the data line DATA is transmitted to the liquid crystal capacitor through the thin-film transistor. The liquid crystal capacitor stores the data voltage signal, and the voltage difference across the liquid crystal capacitor controls the deflection angle of the liquid crystal molecules, thereby controlling the transmittance of the pixel unit PX and realizing image display.

[0029] Multiple pixel units PX are arranged in an array, comprising N rows of pixel units PX. The gate driving circuit includes N levels of gate driving units, which are cascaded together. The i-th level gate driving unit is electrically connected to the gate line SCAN of the i-th row of pixel units PX. The i-th level gate driving unit outputs a gate driving signal G(i) to the i-th row of pixel units PX, where i and N are positive integers, and i is less than or equal to N. The gate driving signal output terminal G(i) is electrically connected to the gate line SCAN of the i-th row of pixel units PX.

[0030] The thin-film transistor (TFT) in the gate driving unit is an oxide semiconductor TFT, meaning the active layer of the TFT in the gate driving unit is made of an oxide semiconductor material, including at least one of indium gallium zinc oxide, indium zinc oxide, indium tin oxide, indium gallium zinc tin oxide, indium gallium tin oxide, and indium gallium oxide. Oxide semiconductor materials possess high mobility and low leakage current characteristics. The high mobility of oxide semiconductor materials enables the TFT to have strong current driving capability when it is turned on, resulting in a higher voltage amplitude of the gate driving signal output at the gate driving signal output terminal G(i), thus improving the driving capability of the gate driving signal. The low leakage current characteristic of oxide semiconductor materials results in a small leakage current when the TFT is turned off. However, this low leakage current also makes it difficult for residual charge at critical nodes of the gate driving unit to be released through the leakage current of the TFT, thereby affecting the stability of the gate driving circuit.

[0031] like Figure 2 As shown, the i-th gate drive unit includes a pull-up control unit 101, a reset unit 103, a pull-down sustaining unit 104, a pull-up unit 102, and a pull-down unit 105.

[0032] The pull-up control unit 101 is configured to control the potential of the first node Q(i). The pull-up control unit 101 includes a twenty-third transistor T11. The gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. One of the source and drain of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit, and the other of the source and drain of the twenty-third transistor T11 is electrically connected to the first node Q(i), where x is a positive integer. The first node Q(i) is electrically connected to the gate of the twenty-fourth transistor T21.

[0033] In one embodiment, the gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, one of the source and drain of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, and the other of the source and drain of the twenty-third transistor T11 is electrically connected to the first node Q(i). Thus, the gate and one of the source and drain of the twenty-third transistor T11 are both electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit. When the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit outputs a high-level signal, the twenty-third transistor T11 is turned on. The high-level signal output by the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit is transmitted to the first node Q(i) through the twenty-third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0034] In another embodiment, the gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit. One of the source and drain of the twenty-third transistor T11 is electrically connected to the first power supply signal line VGH, and the other of the source and drain of the twenty-third transistor T11 is electrically connected to the first node Q(i). When the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit outputs a high-level signal, the twenty-third transistor T11 is turned on, and the high-level signal transmitted through the first power supply signal line VGH is transmitted to the first node Q(i) through the twenty-third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0035] In another embodiment, the gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit, one of the source and drain of the twenty-third transistor T11 is electrically connected to the gate drive signal output terminal G(ix) of the ixth stage gate driving unit, and the other of the source and drain of the twenty-third transistor T11 is electrically connected to the first node Q(i). When the stage transmission signal output terminal ST(ix) of the ixth stage gate driving unit outputs a high-level signal, the twenty-third transistor T11 is turned on, and the signal of the gate drive signal output terminal G(ix) of the ixth stage gate driving unit is transmitted to the first node Q(i) through the twenty-third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0036] x is greater than or equal to 1 and less than or equal to the number of clock signal lines in the gate drive circuit. Specifically, x is half the number of clock signal lines in the gate drive circuit. The gate drive circuit includes multiple clock signal lines, with the number of clock signal lines ranging from 12 to 16, and x ranging from 6 to 8. For example, the number of clock signal lines is 12, and x is 6. Thus, the gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit. The high-level signal output from the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit is transmitted to the first node Q(i) through the twenty-third transistor T11, causing the potential of the first node Q(i) to rise to a high potential state, thereby controlling the conduction state of the twenty-fourth transistor T21 and the twenty-fifth transistor T22.

[0037] The i-th stage gate driving unit also includes a reset unit 103, which is configured to reset the potential of the critical node of the gate driving unit at the beginning of each frame. The reset unit 103 includes a first reset sub-unit and a second reset sub-unit. The first reset sub-unit is electrically connected to the first reset control signal line RESET1, and the second reset sub-unit is electrically connected to the second reset control signal line RESET2. Both the first reset sub-unit and the second reset sub-unit are electrically connected to the first node Q(i), the gate driving signal output terminal G(i), and the stage transmission signal output terminal ST(i).

[0038] The first reset subunit includes a first transistor T44, a second transistor T74, and a third transistor T34. The gate of the first transistor T44 is electrically connected to the first reset control signal line RESET1. One of the sources and drains of the first transistor T44 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the first transistor T44 is electrically connected to the first node Q(i). The gate of the second transistor T74 is electrically connected to the first reset control signal line RESET1. One of the sources and drains of the second transistor T74 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the second transistor T74 is electrically connected to the stage drive signal output terminal ST(i) of the i-th stage gate drive unit. The gate of the third transistor T34 is electrically connected to the first reset control signal line RESET1. One of the sources and drains of the third transistor T34 is electrically connected to the third power supply signal line VSSG, and the other of the sources and drains of the third transistor T34 is electrically connected to the gate drive signal output terminal G(i).

[0039] The second reset subunit includes a fourth transistor T45, a fifth transistor T75, and a sixth transistor T35. The gate of the fourth transistor T45 is electrically connected to the second reset control signal line RESET2. One of the sources and drains of the fourth transistor T45 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the fourth transistor T45 is electrically connected to the first node Q(i). The gate of the fifth transistor T75 is electrically connected to the second reset control signal line RESET2. One of the sources and drains of the fifth transistor T75 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the fifth transistor T75 is electrically connected to the stage drive signal output terminal ST(i) of the i-th stage gate drive unit. The gate of the sixth transistor T35 is electrically connected to the second reset control signal line RESET2. One of the sources and drains of the sixth transistor T35 is electrically connected to the third power supply signal line VSSG, and the other of the sources and drains of the sixth transistor T35 is electrically connected to the gate drive signal output terminal G(i).

[0040] The first reset control signal line RESET1 transmits the first reset control signal, and the second reset control signal line RESET2 transmits the second reset control signal. The first and second reset control signals output high-level signals at different time periods during the reset phase at the beginning of each frame. During the first reset time period, the first reset control signal line RESET1 outputs a high-level signal, and the first transistor T44, the second transistor T74, and the third transistor T34 are simultaneously turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the first transistor T44, causing the potential of the first node Q(i) to drop to a low potential state. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the second transistor T74, causing the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit to drop to a low potential state. The low-level signal transmitted by the third power signal line VSSG is transmitted to the gate drive signal output terminal G(i) through the third transistor T34, causing the potential of the gate drive signal output terminal G(i) to drop to a low potential state. During the second reset period, the second reset control signal line RESET2 outputs a high-level signal, and the fourth transistor T45, the fifth transistor T75, and the sixth transistor T35 are simultaneously turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the fourth transistor T45, causing the potential of the first node Q(i) to drop to a low potential state. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the fifth transistor T75, causing the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit to drop to a low potential state. The low-level signal transmitted by the third power signal line VSSG is transmitted to the gate drive signal output terminal G(i) through the sixth transistor T35, causing the potential of the gate drive signal output terminal G(i) to drop to a low potential state.

[0041] The reset unit 103 includes two sets of reset sub-units. The first reset sub-unit and the second reset sub-unit reset the potentials of the first node Q(i), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, and the gate drive signal output terminal G(i) at different time periods. Due to the low leakage current characteristics of oxide semiconductor materials, the residual charge of the critical node of the gate drive unit is difficult to release through the leakage current of the thin-film transistor. By setting two sets of reset sub-units, the gate drive unit's ability to clear the potential of the critical node is enhanced, and the stability of the gate drive circuit is improved. The first reset sub-unit and the second reset sub-unit operate at different time periods, which shortens the operating time of each set of reset sub-units, thereby reducing the stress time of the thin-film transistor, reducing the threshold voltage drift of the thin-film transistor, and improving the stability of the gate drive circuit.

[0042] The gate drive circuit also includes a first start signal line STV1 and a second start signal line STV2. The pull-up control unit 101 of the first to A / 2 stage gate drive units is electrically connected to the first start signal line STV1, and the pull-up control unit 101 of the A / 2+1 stage to A stage gate drive units is electrically connected to the second start signal line STV2, where A is the number of clock signal lines in the gate drive circuit. The first start signal line STV1 transmits a first start signal, and the second start signal line STV2 transmits a second start signal. The first start signal and the second start signal control the pull-up control unit 101 of different stages of the gate drive units, respectively.

[0043] For the gate driving units from stage 1 to stage A / 2, the gate of the 23rd transistor T11 is electrically connected to the first start signal line STV1. When the first start signal line STV1 outputs a high-level signal, the 23rd transistor T11 is turned on, and the high-level signal output by the first start signal line STV1 is transmitted to the first node Q(i) through the 23rd transistor T11, causing the potential of the first node Q(i) to rise to a high potential state. For the gate driving units from stage A / 2+1 to stage A, the gate of the 23rd transistor T11 is electrically connected to the second start signal line STV2. When the second start signal line STV2 outputs a high-level signal, the 23rd transistor T11 is turned on, and the high-level signal output by the second start signal line STV2 is transmitted to the first node Q(i) through the 23rd transistor T11, causing the potential of the first node Q(i) to rise to a high potential state.

[0044] By setting the first start signal line STV1 and the second start signal line STV2 to control the pull-up control units 101 of gate driving units of different levels respectively, the operating time of the 23rd transistor T11 of the gate driving unit of the initial stage is shortened, thereby reducing the stress time of the thin-film transistor, reducing the threshold voltage drift of the thin-film transistor, and improving the stability of the gate driving circuit. Specifically, if only one start signal line is used to control the pull-up control units 101 of the first to A-level gate driving units, then the duration of the effective level of the start signal transmitted by the start signal line needs to cover the operating time of the pull-up control units 101 of the first to A-level gate driving units. The longer duration of the effective level of the start signal results in a longer operating time of the 23rd transistor T11 of the first to A-level gate driving units, a longer stress time of the thin-film transistor, and a larger threshold voltage drift. By setting the first start signal line STV1 and the second start signal line STV2 to control the pull-up control units 101 of the gate driving units from level 1 to level A / 2 and from level A / 2+1 to level A respectively, the duration of the effective level of the first start signal only needs to cover the working time of the pull-up control unit 101 of the gate driving units from level 1 to level A / 2, and the duration of the effective level of the second start signal only needs to cover the working time of the pull-up control unit 101 of the gate driving units from level A / 2+1 to level A. The duration of the effective levels of the first start signal and the second start signal are both shortened to half of their original duration, thereby shortening the working time of the 23rd transistor T11 of the gate driving units from level 1 to level A, shortening the stress time of the thin film transistor, reducing the threshold voltage drift, and improving the stability of the gate driving circuit.

[0045] When i is less than or equal to A, the i-th gate drive unit does not include the seventh transistor T46 and the eighth transistor T47, because at this time the gate of the twenty-third transistor T11 is electrically connected to the first start signal line STV1 or the second start signal line STV2. Under the control of the first start signal or the second start signal, the twenty-third transistor T11 pulls the potential of the first node Q(i) to a high potential state. At this time, the seventh transistor T46 and the eighth transistor T47 cannot be allowed to pull the potential of the first node Q(i) to a low potential state.

[0046] When i is greater than A, the i-th stage gate drive unit includes a seventh transistor T46 and an eighth transistor T47. The reset unit 103 also includes a seventh transistor T46 and an eighth transistor T47. The gate of the seventh transistor T46 is electrically connected to the first start signal line STV1, one of the source and drain of the seventh transistor T46 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the seventh transistor T46 is electrically connected to at least one of the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i). The gate of the eighth transistor T47 is electrically connected to the second start signal line STV2, one of the source and drain of the eighth transistor T47 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the eighth transistor T47 is electrically connected to at least one of the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i).

[0047] In one embodiment, the source or drain of the seventh transistor T46 is electrically connected to the first node Q(i), and the source or drain of the eighth transistor T47 is also electrically connected to the first node Q(i). When the first start signal line STV1 outputs a high-level signal, the seventh transistor T46 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the seventh transistor T46, causing the potential of the first node Q(i) to drop to a low potential state. When the second start signal line STV2 outputs a high-level signal, the eighth transistor T47 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the eighth transistor T47, causing the potential of the first node Q(i) to drop to a low potential state.

[0048] In another embodiment, the source or drain of the seventh transistor T46 is electrically connected to the gate drive signal output terminal G(i), and the source or drain of the eighth transistor T47 is also electrically connected to the gate drive signal output terminal G(i). When the first start signal line STV1 outputs a high-level signal, the seventh transistor T46 is turned on, and the low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the gate drive signal output terminal G(i) through the seventh transistor T46, causing the potential of the gate drive signal output terminal G(i) to drop to a low potential state. When the second start signal line STV2 outputs a high-level signal, the eighth transistor T47 is turned on, and the low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the gate drive signal output terminal G(i) through the eighth transistor T47, causing the potential of the gate drive signal output terminal G(i) to drop to a low potential state.

[0049] In another embodiment, the source or drain of the seventh transistor T46 is electrically connected to the stage signal output terminal ST(i), and the source or drain of the eighth transistor T47 is also electrically connected to the stage signal output terminal ST(i). When the first start signal line STV1 outputs a high-level signal, the seventh transistor T46 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage signal output terminal ST(i) through the seventh transistor T46, causing the potential of the stage signal output terminal ST(i) to drop to a low potential state. When the second start signal line STV2 outputs a high-level signal, the eighth transistor T47 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage signal output terminal ST(i) through the eighth transistor T47, causing the potential of the stage signal output terminal ST(i) to drop to a low potential state.

[0050] At this time, the gate of the twenty-third transistor T11 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. Under the control of the stage transmission signal of the ixth stage gate drive unit, the twenty-third transistor T11 pulls the potential of the first node Q(i) to a high potential state. The first start signal and the second start signal are no longer used to control the twenty-third transistor T11. Therefore, the first start signal and the second start signal control the seventh transistor T46 and the eighth transistor T47 to pull down the potential of the critical node during other time periods that are different from the working time periods of the first transistor T44, the fourth transistor T45, the second transistor T74, the fifth transistor T75, the third transistor T34, and the sixth transistor T35.

[0051] By configuring the seventh transistor T46 and the eighth transistor T47, when the first start signal line STV1 and the second start signal line STV2 output high-level signals, the potential of at least one of the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i) is pulled down. This enhances the gate drive unit's ability to clear the potential of critical nodes and improves the stability of the gate drive circuit. The seventh transistor T46 and the eighth transistor T47 are electrically connected to the first start signal line STV1 and the second start signal line STV2, respectively, which shortens the operating time of the seventh transistor T46 and the eighth transistor T47. This reduces the stress time of the thin-film transistor, lowers the threshold voltage drift of the thin-film transistor, and improves the stability of the gate drive circuit.

[0052] Pull-up unit 102 is configured to generate and output gate drive signals, as well as generation and output stage transmission signals. Pull-up unit 102 includes a twenty-fourth transistor T21, a twenty-fifth transistor T22, and a first capacitor Cbt. The gate of the twenty-fourth transistor T21 is electrically connected to the first node Q(i), one of the source and drain of the twenty-fourth transistor T21 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the twenty-fourth transistor T21 is electrically connected to the gate drive signal output terminal G(i). The gate of the twenty-fifth transistor T22 is electrically connected to the first node Q(i), one of the source and drain of the twenty-fifth transistor T22 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the twenty-fifth transistor T22 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit. The first plate of the first capacitor Cbt is electrically connected to the first node Q(i), and the second plate of the first capacitor Cbt is electrically connected to the gate drive signal output terminal G(i).

[0053] The first clock signal line CK(j) transmits the first clock signal, and the duty cycle of the first clock signal is 40% to 44%. The duty cycle of the clock signal refers to the ratio of the duration of the high level of the clock signal in one cycle to the total duration of the entire cycle.

[0054] When the first node Q(i) is at a high potential, the twenty-fourth transistor T21 and the twenty-fifth transistor T22 are simultaneously turned on. The first clock signal transmitted by the first clock signal line CK(j) is transmitted to the gate drive signal output terminal G(i) through the twenty-fourth transistor T21, and the first clock signal transmitted by the first clock signal line CK(j) is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the twenty-fifth transistor T22. In this way, the pull-up unit 102 realizes the generation and output of the gate drive signal, as well as the generation and output of the stage transmission signal.

[0055] When the potential of the gate drive signal output terminal G(i) rises, the potential of the second plate of the first capacitor Cbt rises. Due to the coupling effect of the capacitor, the potential of the first plate of the first capacitor Cbt also rises, thereby causing the potential of the first node Q(i) to rise further, increasing the gate potential of the twenty-fourth transistor T21, enhancing the conduction capability of the twenty-fourth transistor T21, and making the voltage amplitude of the gate drive signal output terminal G(i) higher, thus improving the driving capability of the gate drive signal.

[0056] The i-th stage gate driving unit further includes a pull-down unit 105, which is configured to pull down the potential of the first node Q(i). The pull-down unit 105 includes a twenty-sixth transistor T41, the gate of which is electrically connected to the stage transmission signal output terminal ST(i+y) of the (i+y)-th stage gate driving unit, one of the source and drain of the twenty-sixth transistor T41 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the twenty-sixth transistor T41 is electrically connected to the first node Q(i), where y is a positive integer.

[0057] In one embodiment, y is 8, and the gate of the twenty-sixth transistor T41 is electrically connected to the stage transmission signal output terminal ST(i+8) of the (i+8)th stage gate drive unit. When the stage transmission signal output terminal ST(i+8) of the (i+8)th stage gate drive unit outputs a high-level signal, the twenty-sixth transistor T41 is turned on, and the low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the first node Q(i) through the twenty-sixth transistor T41, causing the potential of the first node Q(i) to drop to a low potential state, thereby turning off the twenty-fourth transistor T21 and the twenty-fifth transistor T22, and stopping the gate drive signal output terminal G(i) and the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit from outputting the gate drive signal.

[0058] The i-th stage gate drive unit further includes a pull-down sustaining unit 104, which includes at least two inverters. Specifically, the pull-down sustaining unit 104 includes a first inverter and a second inverter, both of which are electrically connected to the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i). The pull-down sustaining unit 104 is configured to maintain the gate drive signal output terminal G(i), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, and the first node Q(i) at a low potential.

[0059] The first inverter includes the ninth transistor T51, the tenth transistor T52, the eleventh transistor T53, and the twelfth transistor T54.

[0060] The pull-down sustaining unit 104 also includes a thirteenth transistor T32, a fourteenth transistor T42, and a fifteenth transistor T72.

[0061] The gate of the ninth transistor T51 is electrically connected to the first control signal line LC1. One of the sources and drains of the ninth transistor T51 is electrically connected to the first power supply signal line VGH. The other of the sources and drains of the ninth transistor T51 is electrically connected to the second node P(i). The gate of the tenth transistor T52 is electrically connected to the second control signal line LC2. One of the sources and drains of the tenth transistor T52 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the tenth transistor T52 is electrically connected to the second node P(i). The gate of the eleventh transistor T53 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. One of the sources and drains of the eleventh transistor T53 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the eleventh transistor T53 is electrically connected to the second node P(i). The gate of the twelfth transistor T54 is electrically connected to the first node Q(i). One of the sources and drains of the twelfth transistor T54 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the twelfth transistor T54 is electrically connected to the second node P(i). The gate of the thirteenth transistor T32 is electrically connected to the second node P(i). One of the sources and drains of the thirteenth transistor T32 is electrically connected to the third power supply signal line VSSG, and the other of the sources and drains of the thirteenth transistor T32 is electrically connected to the gate drive signal output terminal G(i). The gate of the fourteenth transistor T42 is electrically connected to the second node P(i). One of the sources and drains of the fourteenth transistor T42 is electrically connected to the second power supply signal line VSSQ, and the other of the sources and drains of the fourteenth transistor T42 is electrically connected to the first node Q(i). The gate of the fifteenth transistor T72 is electrically connected to the second node P(i), one of the source and drain of the fifteenth transistor T72 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the fifteenth transistor T72 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, where x is a positive integer.

[0062] In one embodiment, x is 6, and the gate of the eleventh transistor T53 is electrically connected to the stage transmission signal output terminal ST(i-6) of the i-6th stage gate drive unit.

[0063] The first control signal line LC1 transmits the first control signal, and the second control signal line LC2 transmits the second control signal. The first control signal transmitted by the first control signal line LC1 and the second control signal transmitted by the second control signal line LC2 are out of phase. The first control signal and the second control signal alternate between high and low levels with a time period on the order of seconds. The level states of the first control signal and the second control signal are opposite; when the first control signal is high, the second control signal is low, and when the first control signal is low, the second control signal is high.

[0064] When the first control signal line LC1 outputs a high-level signal, the ninth transistor T51 is turned on, and the high-level signal transmitted by the first power signal line VGH is transmitted to the second node P(i) through the ninth transistor T51, causing the potential of the second node P(i) to rise to a high potential state. When the second node P(i) is at a high potential, the thirteenth transistor T32, the fourteenth transistor T42, and the fifteenth transistor T72 are simultaneously turned on. The low-level signal transmitted by the third power signal line VSSG is transmitted to the gate drive signal output terminal G(i) through the thirteenth transistor T32, so that the potential of the gate drive signal output terminal G(i) is maintained at a low potential. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the fourteenth transistor T42, so that the potential of the first node Q(i) is maintained at a low potential. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the fifteenth transistor T72, so that the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit is maintained at a low potential.

[0065] When the second control signal line LC2 outputs a high-level signal, the tenth transistor T52 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the second node P(i) through the tenth transistor T52, causing the potential of the second node P(i) to drop to a low potential state. When the second node P(i) is in a low potential state, the thirteenth transistor T32, the fourteenth transistor T42, and the fifteenth transistor T72 are simultaneously turned off. The potentials of the gate drive signal output terminal G(i), the first node Q(i), and the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit are not affected by the first inverter.

[0066] When the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit outputs a high-level signal, the eleventh transistor T53 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the second node P(i) through the eleventh transistor T53, causing the potential of the second node P(i) to drop to a low potential state. When the first node Q(i) is in a high potential state, the twelfth transistor T54 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the second node P(i) through the twelfth transistor T54, causing the potential of the second node P(i) to drop to a low potential state.

[0067] The gates of the eleventh transistor T53 and the twelfth transistor T54 are electrically connected to the stage transmission signal output terminal ST(i-6) of the i-6th stage gate drive unit and the first node Q(i), respectively. The stage transmission signal received by the first inverter covers the same waveform width range as the signal of the first node Q(i). The first inverter works normally during the entire effective level of the signal of the first node Q(i), ensuring the output performance of the gate drive circuit.

[0068] As a dedicated signal within the gate drive unit, the stage transmission signal is unaffected by signals within the display area of ​​the display panel, resulting in relatively stable control signals received by the first inverter. The first inverter, controlled by both the stage transmission signal and the first node Q(i), exhibits strong stability. Even if either the stage transmission signal or the first node Q(i) signal fails, the first inverter continues to operate normally, relying on either the stage transmission signal or the first node Q(i) signal for input, thus improving the reliability of the gate drive circuit.

[0069] The channel widths of the eleventh transistor T53 and the twelfth transistor T54 are greater than the channel width of the tenth transistor T52, and the channel width of the tenth transistor T52 is greater than the channel width of the ninth transistor T51. This allows the first inverter to output a more reliable waveform, improving the stability of the gate drive circuit. The larger channel widths of the eleventh transistor T53 and the twelfth transistor T54 give these transistors a strong current drive capability when they are turned on, resulting in a faster potential drop at the second node P(i) and a faster response speed for the first inverter. The moderate channel width of the tenth transistor T52 ensures that it has an appropriate current drive capability when turned on, guaranteeing both the potential drop speed at the second node P(i) and avoiding an increase in area due to an excessively large channel width.

[0070] The second inverter includes the sixteenth transistor T61, the seventeenth transistor T62, the eighteenth transistor T63, and the nineteenth transistor T64.

[0071] The pull-down sustaining unit 104 also includes a twentieth transistor T33, a twenty-first transistor T73, and a twenty-second transistor T43.

[0072] The gate of the sixteenth transistor T61 is electrically connected to the second control signal line LC2. One of the sources and drains of the sixteenth transistor T61 is electrically connected to the first power supply signal line VGH. The other of the sources and drains of the sixteenth transistor T61 is electrically connected to the third node K(i). The gate of the seventeenth transistor T62 is electrically connected to the first control signal line LC1. One of the sources and drains of the seventeenth transistor T62 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the seventeenth transistor T62 is electrically connected to the third node K(i). The gate of the eighteenth transistor T63 is electrically connected to the stage transmission signal output terminal ST(ix) of the ixth stage gate drive unit. One of the sources and drains of the eighteenth transistor T63 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the eighteenth transistor T63 is electrically connected to the third node K(i). The gate of the nineteenth transistor T64 is electrically connected to the first node Q(i). One of the sources and drains of the nineteenth transistor T64 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the nineteenth transistor T64 is electrically connected to the third node K(i). The gate of the twentieth transistor T33 is electrically connected to the third node K(i). One of the sources and drains of the twentieth transistor T33 is electrically connected to the third power supply signal line VSSG. The other of the sources and drains of the twentieth transistor T33 is electrically connected to the gate drive signal output terminal G(i). The gate of the twenty-first transistor T73 is electrically connected to the third node K(i). One of the sources and drains of the twenty-first transistor T73 is electrically connected to the second power supply signal line VSSQ. The other of the sources and drains of the twenty-first transistor T73 is electrically connected to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit. The gate of the 22nd transistor T43 is electrically connected to the third node K(i), one of the source and drain of the 22nd transistor T43 is electrically connected to the second power supply signal line VSSQ, and the other of the source and drain of the 22nd transistor T43 is electrically connected to the first node Q(i), where x is a positive integer.

[0073] In one embodiment, x is 6, and the gate of the eighteenth transistor T63 is electrically connected to the stage transmission signal output terminal ST(i-6) of the i-6th stage gate drive unit.

[0074] When the second control signal line LC2 outputs a high-level signal, the sixteenth transistor T61 is turned on, and the high-level signal transmitted by the first power signal line VGH is transmitted to the third node K(i) through the sixteenth transistor T61, causing the potential of the third node K(i) to rise to a high potential state. When the third node K(i) is at a high potential, the twentieth transistor T33, the twenty-first transistor T73, and the twenty-second transistor T43 are simultaneously turned on. The low-level signal transmitted by the third power signal line VSSG is transmitted to the gate drive signal output terminal G(i) through the twentieth transistor T33, so that the potential of the gate drive signal output terminal G(i) is maintained at a low potential. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit through the twenty-first transistor T73, so that the potential of the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit is maintained at a low potential. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the first node Q(i) through the twenty-second transistor T43, so that the potential of the first node Q(i) is maintained at a low potential.

[0075] When the first control signal line LC1 outputs a high-level signal, the seventeenth transistor T62 is turned on. The low-level signal transmitted by the second power signal line VSSQ is transmitted to the third node K(i) through the seventeenth transistor T62, causing the potential of the third node K(i) to drop to a low potential state. When the third node K(i) is in a low potential state, the twentieth transistor T33, the twenty-first transistor T73, and the twenty-second transistor T43 are simultaneously turned off. The potentials of the gate drive signal output terminal G(i), the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit, and the first node Q(i) are not affected by the second inverter.

[0076] When the stage transmission signal output terminal ST(i-6) of the (i-6)th stage gate drive unit outputs a high-level signal, the eighteenth transistor T63 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the third node K(i) through the eighteenth transistor T63, causing the potential of the third node K(i) to drop to a low potential state. When the first node Q(i) is in a high potential state, the nineteenth transistor T64 is turned on. The low-level signal transmitted by the second power supply signal line VSSQ is transmitted to the third node K(i) through the nineteenth transistor T64, causing the potential of the third node K(i) to drop to a low potential state.

[0077] The gates of the eighteenth transistor T63 and the nineteenth transistor T64 are electrically connected to the stage transmission signal output terminal ST(i-6) of the i-6th stage gate drive unit and the first node Q(i), respectively. The stage transmission signal received by the second inverter covers the same waveform width range as the signal of the first node Q(i). The second inverter works normally during the entire effective level of the signal of the first node Q(i), ensuring the output performance of the gate drive circuit.

[0078] As a dedicated signal within the gate drive unit, the stage transmission signal is unaffected by signals within the display area of ​​the display panel, resulting in a relatively stable control signal received by the second inverter. The second inverter, controlled by both the stage transmission signal and the first node Q(i), exhibits strong stability. Even if either the stage transmission signal or the first node Q(i) signal fails, the second inverter continues to operate normally, relying on either the stage transmission signal or the first node Q(i) signal for input, thus improving the reliability of the gate drive circuit.

[0079] The channel widths of transistors T63 (18th) and T64 (19th) are greater than that of transistor T62 (17th), and the channel width of T62 is greater than that of transistor T61 (16th). This size configuration results in a more reliable waveform output by the second inverter, improving the stability of the gate drive circuit. The larger channel widths of transistors T63 and T64 give them strong current drive capability when turned on, resulting in a faster potential drop at the third node K(i) and a faster response speed for the second inverter. The moderate channel width of transistor T62 provides it with appropriate current drive capability when turned on, ensuring a fast potential drop at the third node K(i) while avoiding an increase in area due to an excessively large channel width.

[0080] The first and second inverters operate alternately. When the first control signal line LC1 outputs a high-level signal, the first inverter operates, and the second inverter does not. Conversely, when the second control signal line LC2 outputs a high-level signal, the second inverter operates, and the first inverter does not. This alternating operation avoids the performance degradation caused by prolonged operation of a single inverter, thus extending the lifespan of the gate drive circuit. Furthermore, the alternating operation halves the operating time of each inverter, thereby reducing the stress time of the thin-film transistor (TFT), lowering its threshold voltage drift, and improving the stability of the gate drive circuit.

[0081] When the first control signal is high and the second control signal is low, the first inverter is in operation and the second inverter is in de-operation. At this time, the ninth transistor T51 is turned on, and the high-level signal transmitted through the first power supply signal line VGH is transmitted to the second node P(i) through the ninth transistor T51, causing the potential of the second node P(i) to rise to a high potential state. Simultaneously, the thirteenth transistor T32, the fourteenth transistor T42, and the fifteenth transistor T72 are turned on, maintaining the low potential state of the gate drive signal output terminal G(i), the first node Q(i), and the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit. At the same time, the seventeenth transistor T62 is turned on, and the low-level signal transmitted through the second power supply signal line VSSQ is continuously transmitted to the third node K(i) through the seventeenth transistor T62, continuously releasing the residual charge of the third node K(i).

[0082] When the first control signal is low and the second control signal is high, the second inverter is in the working state, and the first inverter is in the non-working state. At this time, the sixteenth transistor T61 is turned on, and the high-level signal transmitted by the first power signal line VGH is transmitted to the third node K(i) through the sixteenth transistor T61, causing the potential of the third node K(i) to rise to a high potential state. The twentieth transistor T33, the twenty-first transistor T73, and the twenty-second transistor T43 are turned on simultaneously, maintaining the low potential state of the gate drive signal output terminal G(i), the first node Q(i), and the stage transmission signal output terminal ST(i) of the i-th stage gate drive unit. At the same time, the tenth transistor T52 is turned on, and the low-level signal transmitted by the second power signal line VSSQ is continuously transmitted to the second node P(i) through the tenth transistor T52, continuously releasing the residual charge of the second node P(i).

[0083] In this way, when one inverter is working, the residual charge of the node of the other inverter is continuously released, which further reduces the risk that the oxide semiconductor thin film transistor cannot release the residual charge through the leakage current of the oxide semiconductor thin film transistor itself when the display device is in an abnormal condition, and improves the stability of the gate drive circuit.

[0084] Embodiments of this application also provide a driving method for a display device. The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units PX. The plurality of pixel units PX includes N rows of pixel units PX. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line SCAN of the i-th row of pixel units PX. The i-th level gate driving unit includes a reset unit 103. The reset unit 103 includes a first reset sub-unit and a second reset sub-unit. The first reset sub-unit is electrically connected to a first reset control signal line RESET1, and the second reset sub-unit is electrically connected to a second reset control signal line RESET2. Here, i and N are positive integers, and i is less than or equal to N.

[0085] The driving method includes: during the reset phase, the first reset subunit and the second reset subunit respectively pull down the potentials of the first node Q(i), the gate drive signal output terminal G(i) and the stage transmission signal output terminal ST(i) to a low potential state at different time periods.

[0086] The first reset subunit includes a first transistor T44, a second transistor T74, and a third transistor T34, and the second reset subunit includes a fourth transistor T45, a fifth transistor T75, and a sixth transistor T35.

[0087] The driving method further includes: during a first reset period, pulling down the potential of the first node Q(i) to a low level via a first transistor T44, pulling down the potential of the stage transmission signal output terminal ST(i) to a low level via a second transistor T74, and pulling down the potential of the gate drive signal output terminal G(i) to a low level via a third transistor T34. During a second reset period, pulling down the potential of the first node Q(i) to a low level via a fourth transistor T45, pulling down the potential of the stage transmission signal output terminal ST(i) to a low level via a fifth transistor T75, and pulling down the potential of the gate drive signal output terminal G(i) to a low level via a sixth transistor T35.

[0088] The gate drive circuit also includes a first start signal line STV1 and a second start signal line STV2. The pull-up control unit 101 of the first stage to the A / 2 stage gate drive unit is electrically connected to the first start signal line STV1, and the pull-up control unit 101 of the A / 2+1 stage to the A stage gate drive unit is electrically connected to the second start signal line STV2, where A is the number of clock signal lines of the gate drive circuit.

[0089] The driving method further includes: controlling the pull-up control unit 101 of the gate driving units from level 1 to level A / 2 to pull up the first node Q(i) to a high potential state via the first start signal line STV1; and controlling the pull-up control unit 101 of the gate driving units from level A / 2+1 to level A to pull up the first node Q(i) to a high potential state via the second start signal line STV2.

[0090] When i is greater than A, the reset unit 103 also includes a seventh transistor T46 and an eighth transistor T47.

[0091] The driving method further includes: controlling the seventh transistor T46 via the first start signal line STV1 to pull down the potential of at least one of the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i) to a low potential state. Controlling the eighth transistor T47 via the second start signal line STV2 to pull down the potential of at least one of the first node Q(i), the gate drive signal output terminal G(i), and the stage transmission signal output terminal ST(i) to a low potential state.

[0092] The i-th level gate drive unit also includes a pull-up unit 102, which includes a twenty-fourth transistor T21. The gate of the twenty-fourth transistor T21 is electrically connected to the first node Q(i), one of the source and drain of the twenty-fourth transistor T21 is electrically connected to the first clock signal line CK(j), and the other of the source and drain of the twenty-fourth transistor T21 is electrically connected to the gate drive signal output terminal G(i).

[0093] The driving method also includes: when the first node Q(i) is in a high potential state, the twenty-fourth transistor T21 is turned on, and the first clock signal transmitted by the first clock signal line CK(j) is transmitted to the gate drive signal output terminal G(i) through the twenty-fourth transistor T21.

[0094] The i-th gate drive unit also includes a pull-down sustaining unit 104. The pull-down sustaining unit 104 includes a first inverter and a second inverter. The first inverter is electrically connected to the first control signal line LC1 and the second control signal line LC2. The second inverter is also electrically connected to the first control signal line LC1 and the second control signal line LC2. The level states of the first control signal transmitted by the first control signal line LC1 and the second control signal transmitted by the second control signal line LC2 are complementary.

[0095] The driving method further includes: when the first control signal is high and the second control signal is low, controlling the first inverter to be in an operating state and controlling the second inverter to be in a non-operating state, releasing the residual charge of the nodes of the second inverter. When the first control signal is low and the second control signal is high, controlling the second inverter to be in an operating state and controlling the first inverter to be in a non-operating state, releasing the residual charge of the nodes of the first inverter.

[0096]

[0097] Table 1 As shown in Table 1, the display device provided in the embodiments of this application was verified on an 85-inch 8K resolution display panel. The number of clock signal lines was 12 to 16, the duty cycle of the clock signal was 40% to 44%, the voltage transmitted by the first power signal line VGH was 25 volts, the threshold voltage positive offset margin was 7 volts, greater than the mass production level of 6 volts, the threshold voltage negative offset margin was -7 volts, less than the mass production level of -5 volts, the transistor electrical offset reliability verification was qualified, the 80-degree Celsius electrical parameter table verification was qualified, the -20-degree Celsius electrical parameter table verification was qualified, and the voltage margin of the first power signal line VGH was 5 volts, less than the mass production level of 10 volts. The verification results show that the technical solution of this application has stronger reliability compared to the mass production level gate drive unit, avoiding circuit defects caused by the electrical properties of oxide semiconductor devices, and meeting the requirements of a high-stability oxide semiconductor gate drive circuit. The voltage transmitted by the first power signal line VGH does not exceed 25 volts, avoiding the problem of damage to oxide semiconductor devices due to excessively high driving voltage.

[0098] In the display device provided in the embodiments of this application, the reset unit 103 of the i-th stage gate driving unit includes a first reset sub-unit and a second reset sub-unit. The first reset sub-unit is electrically connected to a first reset control signal line, and the second reset sub-unit is electrically connected to a second reset control signal line. Both the first and second reset sub-units are electrically connected to a first node, a gate driving signal output terminal, and a stage transmission signal output terminal. The first and second reset sub-units pull down the potentials of the first node, the gate driving signal output terminal, and the stage transmission signal output terminal at different time periods, thereby enhancing the charge clearing capability of the gate driving unit for critical nodes. Since oxide semiconductor thin-film transistors have low leakage current, residual charge at critical nodes is difficult to release through leakage current. By setting two sets of reset sub-units, each connected to different reset control signal lines, charge clearing of critical nodes at different time periods improves the efficiency of charge clearing. The first and second reset sub-units operate at different time periods, shortening the operating time of the thin-film transistors in each set of reset sub-units, mitigating the electrical performance degradation problem caused by prolonged operation of the thin-film transistors, and improving the reliability of the gate driving unit.

[0099] In the display device provided in the embodiments of this application, the gate driving circuit includes a first start signal line and a second start signal line. The pull-up control unit 101 of the first to A / 2th stage gate driving units is electrically connected to the first start signal line, and the pull-up control unit 101 of the A / 2+1th to Ath stage gate driving units is electrically connected to the second start signal line, where A is the number of clock signal lines of the gate driving circuit. By setting the first and second start signal lines to control the pull-up control units 101 of different stages of the gate driving units respectively, the operating time of the 23rd transistor of the gate driving unit of the initial stage is shortened, thereby reducing the stress time of the thin-film transistor, reducing the threshold voltage drift of the thin-film transistor, and improving the stability of the gate driving circuit.

[0100] In the display device provided in the embodiments of this application, when i is greater than A, the reset unit 103 of the i-th gate driving unit further includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected to the first start signal line, one of the source and drain of the seventh transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the seventh transistor is electrically connected to at least one of the first node, the gate driving signal output terminal, and the stage transmission signal output terminal. The gate of the eighth transistor is electrically connected to the second start signal line, one of the source and drain of the eighth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eighth transistor is electrically connected to at least one of the first node, the gate driving signal output terminal, and the stage transmission signal output terminal. By setting the seventh transistor and the eighth transistor, when the first start signal line and the second start signal line output high-level signals, the potential of at least one of the first node, the gate driving signal output terminal, and the stage transmission signal output terminal is pulled down, which enhances the gate driving unit's ability to clear the potential of critical nodes and improves the stability of the gate driving circuit. The seventh and eighth transistors are electrically connected to the first and second start signal lines, respectively, which shortens the operating time of the seventh and eighth transistors, thereby reducing the stress time of the thin-film transistor, lowering the threshold voltage drift of the thin-film transistor, and improving the stability of the gate drive circuit.

[0101] In the display device provided in the embodiments of this application, the pull-down sustaining unit 104 includes a first inverter and a second inverter. The first inverter is electrically connected to a first control signal line, a second control signal line, a first node, a gate drive signal output terminal, and a cascade signal output terminal. The second inverter is also electrically connected to the first control signal line, the second control signal line, the first node, the gate drive signal output terminal, and the cascade signal output terminal. The first control signal transmitted by the first control signal line is inverted with the second control signal transmitted by the second control signal line. When the first inverter is in the working state, the second inverter is in the non-working state, and the thin-film transistor in the second inverter that is electrically connected to the first control signal line is turned on, releasing the residual charge of the node of the second inverter. When the second inverter is in the working state, the first inverter is in the non-working state, and the thin-film transistor in the first inverter that is electrically connected to the second control signal line is turned on, releasing the residual charge of the node of the first inverter. The residual charge of the inverter nodes in the non-operating state is continuously released, which reduces the risk that the oxide semiconductor thin film transistor cannot release the residual charge through leakage current when the display device is in an abnormal condition, and improves the stability of the gate drive unit.

[0102] The embodiments of this application have been described in detail above. The content of this specification should not be construed as limiting the scope of protection of this application.

Claims

1. A display device, characterized in that, The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units. The plurality of pixel units include N rows of pixel units. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line of the i-th row of pixel units. Here, i and N are positive integers, and i is less than or equal to N. The i-th stage gate drive unit includes: The pull-up unit is electrically connected to the first node, the gate drive signal output terminal, and the cascade signal output terminal; and The reset unit includes a first reset subunit and a second reset subunit. The first reset subunit is electrically connected to a first reset control signal line, and the second reset subunit is electrically connected to a second reset control signal line. Both the first reset subunit and the second reset subunit are electrically connected to the first node, the gate drive signal output terminal, and the cascade signal output terminal.

2. The display device according to claim 1, characterized in that, The first reset subunit includes a first transistor, a second transistor, and a third transistor. The gate of the first transistor is electrically connected to the first reset control signal line. One of the source and drain of the first transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the first transistor is electrically connected to the first node. The gate of the second transistor is electrically connected to the first reset control signal line. One of the source and drain of the second transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the second transistor is electrically connected to the stage signal output terminal. The gate of the third transistor is electrically connected to the first reset control signal line. One of the source and drain of the third transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the third transistor is electrically connected to the gate drive signal output terminal.

3. The display device according to claim 2, characterized in that, The second reset subunit includes a fourth transistor, a fifth transistor, and a sixth transistor. The gate of the fourth transistor is electrically connected to the second reset control signal line. One of the source and drain of the fourth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the fourth transistor is electrically connected to the first node. The gate of the fifth transistor is electrically connected to the second reset control signal line. One of the source and drain of the fifth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the fifth transistor is electrically connected to the stage signal output terminal. The gate of the sixth transistor is electrically connected to the second reset control signal line. One of the source and drain of the sixth transistor is electrically connected to the third power supply signal line, and the other of the source and drain of the sixth transistor is electrically connected to the gate drive signal output terminal.

4. The display device according to claim 1, characterized in that, The gate driving circuit further includes a first start signal line and a second start signal line. The pull-up control unit of the first stage to the A / 2 stage gate driving unit is electrically connected to the first start signal line, and the pull-up control unit of the A / 2+1 stage to the A stage gate driving unit is electrically connected to the second start signal line, where A is the number of clock signal lines of the gate driving circuit.

5. The display device according to claim 1, characterized in that, The gate drive circuit further includes a first start signal line and a second start signal line; The reset unit further includes a seventh transistor and an eighth transistor. The gate of the seventh transistor is electrically connected to the first start signal line. One of the source and drain of the seventh transistor is electrically connected to the second power supply signal line. The other of the source and drain of the seventh transistor is electrically connected to at least one of the first node, the gate drive signal output terminal, and the cascade signal output terminal. The gate of the eighth transistor is electrically connected to the second start signal line. One of the source and drain of the eighth transistor is electrically connected to the second power supply signal line. The other of the source and drain of the eighth transistor is electrically connected to at least one of the first node, the gate drive signal output terminal, and the cascade signal output terminal.

6. The display device according to claim 1, characterized in that, The i-th stage gate driving unit further includes: The pull-down sustaining unit includes a first inverter and a second inverter. The first inverter is electrically connected to a first control signal line, a second control signal line, a first node, a gate drive signal output terminal, and a cascade signal output terminal. The second inverter is electrically connected to the first control signal line, the second control signal line, the first node, the gate drive signal output terminal, and the cascade signal output terminal. The first control signal transmitted by the first control signal line is out of phase with the second control signal transmitted by the second control signal line.

7. The display device according to claim 6, characterized in that, The first inverter includes a ninth transistor, a tenth transistor, an eleventh transistor, and a twelfth transistor; The pull-down sustaining unit also includes a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor; The gate of the ninth transistor is electrically connected to the first control signal line. One of the source and drain of the ninth transistor is electrically connected to the first power supply signal line, and the other of the source and drain of the ninth transistor is electrically connected to the second node. The gate of the tenth transistor is electrically connected to the second control signal line. One of the source and drain of the tenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the tenth transistor is electrically connected to the second node. The gate of the eleventh transistor is electrically connected to the stage transmission signal output terminal of the ixth stage gate drive unit. One of the source and drain of the eleventh transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eleventh transistor is electrically connected to the second node. The gate of the twelfth transistor is electrically connected to the first node, and one of the source and drain of the twelfth transistor is electrically connected to the second power supply signal line. The source signal line is electrically connected; the other of the source and drain of the twelfth transistor is electrically connected to the second node; the gate of the thirteenth transistor is electrically connected to the second node; one of the source and drain of the thirteenth transistor is electrically connected to the third power supply signal line; the other of the source and drain of the thirteenth transistor is electrically connected to the gate drive signal output terminal; the gate of the fourteenth transistor is electrically connected to the second node; one of the source and drain of the fourteenth transistor is electrically connected to the second power supply signal line; the other of the source and drain of the fourteenth transistor is electrically connected to the first node; the gate of the fifteenth transistor is electrically connected to the second node; one of the source and drain of the fifteenth transistor is electrically connected to the second power supply signal line; the other of the source and drain of the fifteenth transistor is electrically connected to the stage transmission signal output terminal, where x is a positive integer.

8. The display device according to claim 7, characterized in that, The channel widths of the eleventh and twelfth transistors are greater than the channel width of the tenth transistor, and the channel width of the tenth transistor is greater than the channel width of the ninth transistor.

9. The display device according to claim 6, characterized in that, The second inverter includes a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The pull-down sustaining unit also includes a twentieth transistor, a twenty-first transistor, and a twenty-second transistor; The gate of the sixteenth transistor is electrically connected to the second control signal line. One of the source and drain of the sixteenth transistor is electrically connected to the first power supply signal line, and the other of the source and drain of the sixteenth transistor is electrically connected to the third node. The gate of the seventeenth transistor is electrically connected to the first control signal line. One of the source and drain of the seventeenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the seventeenth transistor is electrically connected to the third node. The gate of the eighteenth transistor is electrically connected to the stage transmission signal output terminal of the ixth stage gate drive unit. One of the source and drain of the eighteenth transistor is electrically connected to the second power supply signal line, and the other of the source and drain of the eighteenth transistor is electrically connected to the third node. The gate of the nineteenth transistor is electrically connected to the first node, and one of the source and drain of the nineteenth transistor is electrically connected to the second power supply signal line. The source signal line is electrically connected; the other of the source and drain of the nineteenth transistor is electrically connected to the third node; the gate of the twentieth transistor is electrically connected to the third node; one of the source and drain of the twentieth transistor is electrically connected to the third power supply signal line; the other of the source and drain of the twentieth transistor is electrically connected to the gate drive signal output terminal; the gate of the twenty-first transistor is electrically connected to the third node; one of the source and drain of the twenty-first transistor is electrically connected to the second power supply signal line; the other of the source and drain of the twenty-first transistor is electrically connected to the stage transmission signal output terminal; the gate of the twenty-second transistor is electrically connected to the third node; one of the source and drain of the twenty-second transistor is electrically connected to the second power supply signal line; the other of the source and drain of the twenty-second transistor is electrically connected to the first node, where x is a positive integer.

10. The display device according to claim 9, characterized in that, The channel widths of the eighteenth and nineteenth transistors are greater than the channel width of the seventeenth transistor, and the channel width of the seventeenth transistor is greater than the channel width of the sixteenth transistor.

11. The display device according to any one of claims 1 to 10, characterized in that, The transistor in the i-th gate drive unit is an oxide semiconductor thin-film transistor.

12. A driving method for a display device, characterized in that, The display device includes a display panel, which includes at least one gate driving circuit and a plurality of pixel units. The plurality of pixel units include N rows of pixel units. The gate driving circuit includes N levels of gate driving units. The i-th level gate driving unit is electrically connected to the gate line of the i-th row of pixel units. The i-th level gate driving unit includes a reset unit. The reset unit includes a first reset sub-unit and a second reset sub-unit. The first reset sub-unit is electrically connected to a first reset control signal line, and the second reset unit is electrically connected to a second reset control signal line. Where i and N are positive integers, and i is less than or equal to N. The driving method includes: During the reset phase, the first reset subunit and the second reset subunit respectively pull down the potentials of the first node, the gate drive signal output terminal and the cascade signal output terminal to a low potential state at different time periods.

13. The driving method according to claim 12, characterized in that, The first reset subunit includes a first transistor, a second transistor, and a third transistor; the second reset subunit includes a fourth transistor, a fifth transistor, and a sixth transistor. The driving method further includes: During the first reset time period, the potential of the first node is pulled down to a low level through the first transistor, the potential of the cascade signal output terminal is pulled down to a low level through the second transistor, and the potential of the gate drive signal output terminal is pulled down to a low level through the third transistor; and During the second reset period, the potential of the first node is pulled down to a low potential state through the fourth transistor, the potential of the cascade signal output terminal is pulled down to a low potential state through the fifth transistor, and the potential of the gate drive signal output terminal is pulled down to a low potential state through the sixth transistor.

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