Phase change memory and operation method thereof

Abstract

The embodiment of the invention provides a phase change memory and an operation method thereof. The phase change memory comprises a memory cell array and a peripheral circuit coupled with the memory cell array, the memory cell array comprises a first region and a second region; the second area is located on at least one side of the first area away from the middle of the first area; the peripheral circuit is configured to: in response to the error rate corresponding to the first region exceeding a first threshold of ECC, execute a first refresh operation on the phase change memory cells of the first region; in response to the fact that the bit error rate corresponding to the second area exceeds a second threshold value of the ECC, executing a second refreshing operation on the phase change storage unit of the second area; wherein the first threshold value is smaller than the second threshold value.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a phase-change memory and its operating method. Background Technology

[0002] Phase-change random access memory (PCRAM) bridges the performance gap between dynamic random access memory (DRAM) and flash memory, offering advantages such as high-speed read speeds, high erase / write cycles, non-volatility, small device size, low power consumption, and resistance to strong shocks and radiation, leading to its widespread use. However, slow read disturbance (SRD) in PCRAM can cause an excessively high raw bit error rate (RBER) or error rate. Effective measures are needed to prevent this problem. Summary of the Invention

[0003] This application provides a phase-change memory and its operation method, which can effectively prevent the problem of high original bit error rate or error rate caused by slow read interference.

[0004] In a first aspect, embodiments of this application provide a phase-change memory (PCM), comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of PCM cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; the peripheral circuitry is configured to: perform a first refresh operation on the PCM cells of the first region in response to the bit error rate corresponding to the first region exceeding a first threshold of error checking and correction (ECC); and perform a second refresh operation on the PCM cells of the second region in response to the bit error rate corresponding to the second region exceeding a second threshold of ECC; wherein the first threshold is less than the second threshold.

[0005] In some embodiments, the peripheral circuitry is further configured to disable the phase-change memory cell in the first region in response to the bit error rate of the first region exceeding a third threshold of the ECC, or the number of times the bit error rate of the first region exceeds a fourth threshold of the ECC being greater than or equal to a preset threshold; wherein the third threshold and the fourth threshold are greater than the first threshold; the third threshold is greater than the fourth threshold.

[0006] In some embodiments, the peripheral circuit is specifically configured to: perform a first refresh operation on the phase-change memory cells of the first region based on a first refresh frequency; and perform a second refresh operation on the phase-change memory cells of the second region based on a second refresh frequency; wherein the first refresh frequency is greater than the second refresh frequency.

[0007] In some embodiments, the peripheral circuitry further includes a timer; the timer is configured to set a timestamp; the timestamp records the moment of a read operation request for a phase-change memory cell; the interval between two adjacent read operations of a phase-change memory cell is obtained based on the timestamp; the peripheral circuitry is further configured to perform a third refresh operation on the corresponding phase-change memory cell in response to an interval length greater than or equal to a first duration.

[0008] In some embodiments, the peripheral circuitry is configured to: perform a third refresh operation on the corresponding phase-change memory cell in response to the phase-change memory cell in the first region having an interval duration greater than or equal to a first duration; and perform a third refresh operation on the corresponding phase-change memory cell in the second region having an interval duration greater than or equal to a second duration; wherein the first duration is less than the second duration.

[0009] In some embodiments, the peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are respectively coupled to the phase change memory cell via a first address line and a second address line; wherein the electrical distance between the phase change memory cells in the first region is less than the electrical distance between the phase change memory cells in the second region; the electrical distance is the sum of the first length of the first address line between the phase change memory cell and the first driving circuit and the second length of the second address line between the phase change memory cell and the second driving circuit.

[0010] In some embodiments, the memory cell array further includes a plurality of first contact structures and a plurality of second contact structures; the first contact structures connect a first address line and a first driving circuit; the second contact structures connect a second address line and a second driving circuit; the plurality of first contact structures are arranged along the extension direction of the second address line; the plurality of second contact structures are arranged along the extension direction of the first address line; wherein, the first length is the length of the first address line between the phase-change memory cell and the first contact structure; and the second length is the length of the second address line between the phase-change memory cell and the second contact structure.

[0011] In some embodiments, the first region is located in the middle of the memory cell array; the first contact structure is located in the middle of the first address line; the second contact structure is located in the middle of the second address line; and the first driving circuit and the second driving circuit are located above the first region.

[0012] In some embodiments, the second region includes a third region and a plurality of fourth regions; the third region is located on at least one side of the first region away from the middle of the first region; the plurality of fourth regions are arranged on at least one side of the third region away from the first region; the electrical distance between the phase-change memory cells of the third region is less than the electrical distance between the phase-change memory cells of the fourth region; the peripheral circuit is further configured to: perform a second refresh operation on the phase-change memory cells of the third region in response to the bit error rate of the corresponding third region exceeding a second threshold threshold of the ECC; and perform a second refresh operation on the phase-change memory cells of the fourth region in response to the bit error rate of the corresponding fourth region exceeding a fifth threshold threshold of the ECC; wherein the fifth threshold threshold is greater than the second threshold threshold.

[0013] In some embodiments, when a first refresh operation or a second refresh operation is performed on the phase-change memory cell, the peripheral circuitry is configured to: perform a read operation on the phase-change memory cell; and perform a write operation on the phase-change memory cell based on the data read from the read operation.

[0014] Secondly, embodiments of this application provide an operation method for a phase-change memory (PCM). The PCM includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple first address lines, multiple second address lines, and multiple PCM cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; the operation method of the PCM includes: performing a first refresh operation on the PCM cells of the first region in response to the bit error rate corresponding to the first region exceeding a first threshold of ECC; performing a second refresh operation on the PCM cells of the second region in response to the bit error rate corresponding to the second region exceeding a second threshold of ECC; wherein the first threshold is less than the second threshold.

[0015] In various embodiments of this application, matching ECC thresholds (first threshold and second threshold) can be set for different regions (first region and second region) of the storage cell array. During the bit error rate detection process of the phase-change memory, if the bit error rate exceeds the corresponding threshold, a refresh operation (first refresh operation and second refresh operation) can be performed. In this way, for different situations in different regions of the storage cell array, the slow read interference situation / risk in the corresponding region can be detected in advance, and the storage cells in the corresponding region can be refreshed, effectively preventing the problem of high original bit error rate or error rate caused by slow read interference. Attached Figure Description

[0016] Figure 1 A block diagram of a memory system provided in an embodiment of this application; Figure 2 A block diagram of an exemplary memory including a storage array and peripheral circuitry provided for embodiments of this application; Figure 3 Block diagrams of exemplary storage arrays and exemplary peripheral circuits provided for embodiments of this application; Figure 4 One of the three-dimensional schematic diagrams of a phase-change memory provided in an embodiment of this application; Figure 5 A second three-dimensional schematic diagram of a phase-change memory provided in an embodiment of this application; Figure 6 A schematic diagram of pulses during each operation process of the phase-change memory unit provided in the embodiments of this application; Figure 7 A schematic diagram of the threshold voltage distribution of the phase change memory cell under various slow read interference scenarios provided in the embodiments of this application; Figure 8 A schematic diagram of the planar layout of a storage cell array including a first region and a second region, provided for an embodiment of this application; Figure 9 for Figure 8 A simplified diagram; Figure 10 A schematic diagram of the planar layout of a storage cell array including a first region, a third region, and a fourth region, provided for an embodiment of this application; Figure 11 A schematic diagram illustrating the relationship between the average original bit error rate and the number of cycles under different time intervals, as provided in the embodiments of this application; Figure 12 One of the illustrative flowcharts for performing the first refresh operation provided in the embodiments of this application; Figure 13 A second illustrative flowchart illustrating the execution of the first refresh operation provided in an embodiment of this application; Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application. Detailed Implementation

[0017] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0019] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0020] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0021] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0022] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0023] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solution of this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0024] In the various embodiments of this application, the first direction, the second direction, and the third direction intersect each other (e.g., are orthogonal). The first direction can be understood as the extension direction of the first address line, the second direction can be understood as the extension direction of the second address line, and the third direction can be understood as the stacking direction of each layer / component of the phase-change memory cell. For example, the first direction is represented by the X direction in the figure; the second direction is represented by the Y direction in the figure; and the third direction is represented by the Z direction in the figure. Any two of the X, Y, and Z directions are orthogonal to each other.

[0025] This application provides a system comprising: a host and a memory system coupled to the host (see reference). Figure 1 The system can be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. The host can be the processor of the electronic device, such as a central processing unit (CPU) or a system-on-a-chip (SoC), where the SoC can be, for example, an application processor (AP). The host can be configured to send data to or receive data from the memory system.

[0026] Figure 1 A block diagram of a memory system provided in an embodiment of this application.

[0027] refer to Figure 1This application provides a memory system 100 including: a memory 300; and a memory controller 200 coupled to the memory 300 and configured to control the memory 300.

[0028] In some embodiments, the memory controller 200 may control the overall operation of the memory system 100, such as write operations, read operations, and refresh operations. In some embodiments, the memory controller 200 is configured to store data in the memory 300, or to read data stored in the memory 300.

[0029] In some embodiments, the memory controller 200 is also configured to handle ECC (Electronic Control Classification) of data read from or written to the memory 300. In some embodiments, the memory controller 200 may also be configured to manage various functions relating to data stored or to be stored in the memory, including but not limited to logical-to-physical address translation, bad block management, garbage collection, wear leveling, etc.

[0030] In some embodiments, memory 300 may include one of phase-change random access memory, resistive random access memory (RRAM), magnetic random access memory (MRAM), and nanotube random access memory (NRAM).

[0031] In some embodiments, the memory controller 200 is also configured to store various information required for the operation of the memory system 100 (e.g., metadata information and mapping tables) into volatile memory. Figure 1 (Not shown), and memory 300 can be accessed based on information stored in volatile memory. In some embodiments, the volatile storage device may include dynamic random access memory, static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), or double-data-rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM).

[0032] Figure 2A block diagram of an exemplary memory including a storage array and peripheral circuitry, provided for embodiments of this application.

[0033] refer to Figure 2 The memory 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. In some embodiments, the peripheral circuitry 302 is configured to control the overall operation of the memory 300, such as write operations, read operations, and refresh operations. In some embodiments, the peripheral circuitry 302 is configured to store data in the memory array 301, or to read data stored in the memory array 301.

[0034] Figure 3 Block diagrams of exemplary memory arrays and exemplary peripheral circuits provided for embodiments of this application.

[0035] refer to Figure 3 The memory 300 may include a memory array 301 and peripheral circuitry coupled to the memory array 301. In some embodiments, the memory array 301 may include word lines WL, bit lines BL, and memory cells 301a formed between the word lines WL and BL; the memory cells 301a are located at the intersection between the word lines WL and BL and are coupled to the word lines WL and BL. In some embodiments, the peripheral circuitry may be configured to apply word line voltages to selected word lines WL and bit line voltages to selected bit lines BL, operating the memory cells 301a of the memory array 301. In some embodiments, the peripheral circuitry may include: control logic 312, an address register 314, a voltage generator 310, a row decoder / word line driver 308, a page buffer / sensor amplifier circuit 304, a column decoder / bit line driver 306, and a data register / data I / O 316.

[0036] Page buffer / sensor amplifier circuit 304 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic 312. In one example, page buffer / sensor amplifier 304 can store programming data (write data) to be programmed into a page of memory array 301. In another example, page buffer / sensor amplifier 304 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, page buffer / sensor amplifier 304 can also sense a low-power signal representing a data bit stored in the memory cell from the selected bit line and amplify a small voltage swing to a recognizable logic level during a read operation. In some embodiments, page buffer / sensor amplifier 304 may include a comparator (e.g., a voltage comparator) for comparing a voltage signal (e.g., a read voltage) with a reference voltage signal. Column decoder / bit line driver 306 can be configured to be controlled by control logic 312 and select one or more memory cells and bit lines. Column decoder / bit line driver 306 can be further configured to drive the selected bit line. The column decoder / bit line driver 306 may be further configured to drive the bit lines using a bit line voltage generated from the voltage generator 310. The column decoder / bit line driver 306 may be a binary data storage device for storing bits. In some embodiments, the column decoder / bit line driver 306 may include a read data latch to store read data.

[0037] The data register / data I / O 316 may be coupled to the page buffer / sensor amplifier 304, and / or coupled to the column decoder / bit line driver 306, and is configured to route data input from the data bus 318 to the desired memory cell of the memory array 301, and to route data output from the desired memory cell to the data bus 318.

[0038] The row decoder / word line driver 308 can be configured to be controlled by control logic 312 and to select one or more memory cells and word lines of the memory array 301. The row decoder / word line driver 308 can be further configured to drive the selected word lines. The row decoder / word line driver 308 can be further configured to drive the word lines using word line voltages generated from voltage generator 310.

[0039] The voltage generator 310 can be configured to be controlled according to control signals from the control logic 312 and to generate word line voltages, bit line voltages and reference voltages to be supplied to the memory array 301.

[0040] Control logic 312 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each of the peripheral circuits. Control logic 312 is configured to receive a clock signal ( Figure 3 (Not shown), command signal CMD, address signal ( Figure 3 (Not shown) and data signal DQ, wherein command signal CMD is received via command bus 320; and data signal DQ is received via data bus 318. In some embodiments, control logic 312 may be implemented by a microprocessor, microcontroller (also known as a micro controller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described.

[0041] In some embodiments, memory 300 may be phase-change random access memory, and memory cell 301a of memory array 301 may be phase-change memory cell.

[0042] In some embodiments, the phase-change memory has a transistorless crosspoint architecture that positions the phase-change memory cell 301-0 between intersecting (e.g., perpendicular) word lines WL and bit lines BL. The word lines WL and BL may be made of a conductive material with equal linewidth (Line / Space, L / S) formed after a patterning process.

[0043] Figure 4 This is one of the three-dimensional schematic diagrams of a phase-change memory provided in an embodiment of this application.

[0044] refer to Figure 4 In some embodiments, the phase-change memory includes word line WL, phase-change memory cell 301-0, and bit line BL stacked sequentially from bottom to top; the phase-change memory cell 301-0 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top.

[0045] In some embodiments, the word line WL and bit line BL are made of conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, conductive nitrides, or any combination thereof. The word line WL and bit line BL may have the same conductive material or different conductive materials. Exemplarily, the word line WL and bit line BL are made of tungsten.

[0046] In some embodiments, the first electrode 3011, the second electrode 3013, and the third electrode 3015 are electrode layers in a phase-change memory cell, used for conducting electrical signals. It should be noted that... Figure 4 The electrode layers, designated by different reference numerals in the accompanying drawings, are merely for distinguishing differences in the location of the electrode layers and are not necessarily used to describe a specific order or sequence. In some embodiments, the materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may be the same or different. The materials of the first electrode 3011, the second electrode 3013, and the third electrode 3015 may include amorphous carbon, such as α-phase carbon.

[0047] In some embodiments, the material of the gating element 3012 may include: an octane threshold switching (OTS) material, such as Zn. a Te b 、Ge a Te b 、Nb a O b Or Si a As b Te c etc., where a, b, and c represent stoichiometric coefficients.

[0048] In some embodiments, the phase change memory element 3014 is made of a chalcogenide-based phase change material. Exemplarily, the phase change memory element 3014 is made of a binary phase change material, such as GaSb, InSb, InSe, Sb₂Te₃, Sb₇Te₃, GeTe, etc. Exemplarily, the phase change memory element 3014 is made of a ternary phase change material, such as Ge₂Sb₂Te₅, Ge₁Sb₄Te₇, InSbTe, GaSeTe, etc. Exemplarily, the phase change memory element 3014 is made of a quaternary phase change material, such as AgInSbTe, GeTeSbS, GeTeInGa, etc.

[0049] Figure 5 This is a second three-dimensional schematic diagram of a phase-change memory provided in an embodiment of this application. Figure 5 The phase-change memory shown can be understood as a three-dimensional phase-change memory, which can consist of multiple Figure 4 The phase change memory shown is stacked together.

[0050] In some embodiments, the phase-change memory includes an upper storage structure 301-U and a lower storage structure 301-D stacked sequentially from top to bottom. The lower storage structure 301-D includes a word line WL, a phase-change memory cell 301-1, and a bit line BL stacked sequentially from bottom to top. The phase-change memory cell 301-1 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The upper storage structure 301-U is located above the lower storage structure 301-D and includes a bit line BL, a phase-change memory cell 301-2, and a word line WL stacked sequentially from bottom to top. The phase-change memory cell 301-2 includes a first electrode 3011, a gating element 3012, a second electrode 3013, a phase-change memory element 3014, and a third electrode 3015 stacked sequentially from bottom to top. The materials for the word line WL, bit line BL, first electrode 3011, gating element 3012, second electrode 3013, phase change memory element 3014, and third electrode 3015 can be referenced. Figure 4 The relevant embodiments will be understood from here, and will not be repeated. It is understood that the bit line BL of the upper memory structure 301-U and the bit line BL of the lower memory structure 301-D can be understood as a common bit line.

[0051] It should be noted that, Figure 4 and Figure 5 The word line WL and bit line BL in the phase-change memory shown can also be understood by interchanged positions. In practical applications, by activating the selected word line and the selected bit line, the phase-change memory cell connected to both the selected word line and the selected bit line can be selected.

[0052] Figure 6 This is a pulse diagram illustrating the various operational processes of the phase-change memory unit provided in the embodiments of this application. It should be noted that... Figure 6 The voltage pulses shown are only used to illustrate the principle of the transition between the crystalline and amorphous states of the phase change material in the phase change memory cell. The actual pulses in each operation process of the phase change memory cell can be based on... Figure 6 The principle of the voltage pulse shown is adapted accordingly. For example, Figure 6 The voltage pulse for the SET operation shown is a voltage plateau, but in practice it can also be multiple voltage plateaus in a stepped pattern. For example, Figure 6 The voltage pulses of the RESET operation shown above the melting temperature TM exhibit a curve of rising and then falling, and may actually include a voltage plateau.

[0053] refer to Figure 6In some embodiments, phase change memory (PCM) utilizes the crystalline and amorphous properties of the phase change material in the PCM cell to store data. Different electrical pulses are used to induce a rapid and reversible phase transition between the amorphous and crystalline states of the PCM. During the transition between the crystalline and amorphous states of the PCM in the PCM cell, different pulses (e.g., light pulses, electrical pulses) can be used to control the heating of the PCM. In one optional implementation, a long and medium-intensity programming pulse (also known as a Set Pulse) is applied to raise the temperature of the phase change material in the phase change memory cell above the crystallization temperature TX but below the melting temperature TM, and this temperature is maintained for a period of time to promote nucleus growth. This allows the phase change material in the phase change memory cell to transition from an amorphous state (corresponding to a high-resistivity state) to a crystalline state (corresponding to a low-resistivity state). The process of changing the phase change material in the phase change memory cell from a high configuration (logic state "0") to a low-resistivity state (logic state "1") is called a set operation, or a write operation. After applying a short and high-intensity reset pulse (also known as a Reset Pulse) to raise the temperature of the phase change material in the phase change memory cell above the melting temperature TM, it is then rapidly cooled. The reset (or erase) operation is used to convert the phase change material of a phase change memory cell from a crystalline state to an amorphous state. The process of converting the phase change material from a low-resistance state (logic state "1") to a high-resistance state (logic state "0") is called the reset operation, or the erase operation. The reset and set operations are reversible. A phase change memory cell can use the crystalline state of the phase change material to represent binary data "1" and the amorphous state to represent binary data "0". Applying a short, low-intensity read pulse (also called a read pulse) keeps the temperature of the phase change material far below its crystallization temperature (TX), preventing a phase change. The current in the circuit is measured to determine the resistance of the phase change material. Based on the resistance value, the read data is determined to be either "0" or "1". This process is called the read operation (RD). For example, the set operation of the phase change memory requires time t3 to complete, the reset operation requires time t2 to complete, and the read operation requires time t1 to complete, wherein time t2 is greater than time t1, and time t3 is greater than time t2.

[0054] It should be noted that when a write operation is completed on a phase-change memory (PCM) cell, the PCM cell's storage state is the first target state. After the PCM cell's storage state is maintained for a period of time, or after the PCM cell has been read a certain number of times, the PCM cell's storage state becomes the first state. The first state can be understood as the state after the first target state has degraded. In some cases, although the first target state and the first state can still be distinguished / identified from the second target storage state by read operations, reading a PCM cell in the first state will cause a higher original bit error rate or error rate compared to reading a PCM cell in the first target state. This phenomenon is called slow read interference in PCM. In some embodiments, the longer the storage state of the PCM cell is maintained, or the more times the PCM cell is read, the more severe the slow read interference becomes. Here and below, the first target storage state can be understood as the phase change material of the phase change memory cell being in a crystalline state, i.e., in a low-resistivity state (logic state "1"); the second target storage state can be understood as the phase change material of the phase change memory cell being in a non-crystalline state, i.e., in a high-configuration state (logic state "0").

[0055] Figure 7 This is a schematic diagram showing the threshold voltage distribution of the phase-change memory cell under various slow read interference scenarios provided in the embodiments of this application. Figure 7 Figure (a) shows the threshold voltage distribution of the phase change memory cell before and after read disturbance. Figure 7 Figure (b) shows the threshold voltage distribution of a phase change memory cell before and after the threshold voltage drift (e.g., the threshold voltage drift that occurs after the storage state of the phase change memory cell has been maintained for a period of time). Figure 7 Figure (c) shows the threshold voltage distribution of the phase change memory cell before and after the threshold voltage drift and read operation interference.

[0056] refer to Figure 7 In Figure (a), after data is written to the phase-change memory (PCM) cell, the threshold voltage distribution of the PCM cell is shown by distribution curve L1. After the PCM cell is read a certain number of times, the threshold voltage of the PCM cell drifts due to read operation interference, resulting in the threshold voltage distribution of the PCM cell as shown by distribution curve L2. For example, the maximum threshold voltage Vm2 shown by distribution curve L2 is greater than the maximum threshold voltage Vm1 shown by distribution curve L1. Compared to the maximum threshold voltage Vm1, the maximum threshold voltage Vm2 is closer to the read voltage Vread, indicating more severe slow read interference or a higher risk of slow read interference.

[0057] refer to Figure 7In Figure (b), after data is written to the phase-change memory (PCM) cell, the threshold voltage distribution of the PCM cell is shown by distribution curve L1. After the stored data in the PCM cell is held for a certain period of time, the threshold voltage of the PCM cell drifts due to the duration of data holding, resulting in the threshold voltage distribution of the PCM cell as shown by distribution curve L3. For example, the maximum threshold voltage Vm3 shown by distribution curve L3 is greater than the maximum threshold voltage Vm1 shown by distribution curve L1. Compared to the maximum threshold voltage Vm1, the maximum threshold voltage Vm3 is closer to the read voltage Vread, indicating more severe slow read interference or a higher risk of slow read interference.

[0058] refer to Figure 7 In Figure (c), after data is written to the phase-change memory (PCM) cell, the threshold voltage distribution of the PCM cell is shown by distribution curve L1. After the stored data in the PCM cell is held for a certain period of time and read a certain number of times, the threshold voltage of the PCM cell drifts due to the combined effects of the data holding time and read operation interference, resulting in the threshold voltage distribution of the PCM cell as shown by distribution curve L4. For example, the maximum threshold voltage Vm4 shown by distribution curve L4 is greater than the maximum threshold voltage Vm1 shown by distribution curve L1, and exceeds the read voltage Vread. Compared to the maximum threshold voltage Vm2 (reference... Figure 7 (a) Figure in the middle), maximum threshold voltage Vm3 (reference) Figure 7 As shown in Figure (b), the maximum threshold voltage Vm4 exceeds the read voltage Vread, indicating severe slow read interference. Therefore, it is necessary to detect the situation / risk of slow read interference in advance and perform a refresh operation on the phase-change memory cell in advance, in order to effectively prevent the problem of high original bit error rate or error rate caused by slow read interference.

[0059] Figure 8 This is a schematic diagram of a planar layout of a storage cell array including a first region and a second region, provided for an embodiment of this application. It should be noted that... Figure 8 A partial number of phase-change memory cells Cx are shown. The position of the phase-change memory cell Cx is used to indicate its relative positional relationship with the word line and bit line. The size of the phase-change memory cell Cx is not used to indicate its relative size relationship with the word line and bit line. Figure 9 for Figure 8 A simplified diagram. Compared to Figure 8 , Figure 9 The diagram illustrates one characteristic phase-change memory cell in each of the first and second regions. Figure 10 A schematic diagram of the planar layout of a storage cell array including a first region, a third region, and a fourth region, provided for embodiments of this application.

[0060] refer to Figure 8 , Figure 9 or Figure 10 According to a first aspect of the present application, a phase-change memory (PCM) is provided, comprising: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of PCM cells; the memory cell array includes a first region P101 and a second region P102; the second region P102 is located on at least one side of the first region P101 away from the middle of the first region; the peripheral circuitry is configured to: perform a first refresh operation on the PCM cells of the first region P101 in response to the bit error rate corresponding to the first region P101 exceeding a first threshold threshold of ECC; and perform a second refresh operation on the PCM cells of the second region P102 in response to the bit error rate corresponding to the second region P102 exceeding a second threshold threshold of ECC; wherein the first threshold threshold is less than the second threshold threshold. In this embodiment, matching ECC thresholds (first threshold and second threshold) can be set for different regions (first region and second region) of the storage cell array. During the bit error rate detection process of the phase-change memory, if the bit error rate exceeds the corresponding threshold, a refresh operation (first refresh operation and second refresh operation) can be performed. This allows for targeted early detection of slow read interference / risks in different regions of the storage cell array and enables refresh operations on the corresponding storage cells, effectively preventing high initial bit error rate or error rate due to slow read interference.

[0061] Here and below, the storage array and peripheral circuitry of the phase-change memory can be referenced from the above. Figure 2 and Figure 3 To understand the relevant descriptions, refer to the phase-change memory cells of the memory cell array. Figure 4 and Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0062] Herein and below, the first address line can be understood as one of the word line WL and the bit line BL, and the second address line can be understood as the other of the word line WL and the bit line BL. In the following description, the example of the first address line being the word line WL and the second address line being the bit line BL is used, and this example is not intended to limit the embodiments of this application.

[0063] In some embodiments, the division between different regions (e.g., a first region and a second region) of the memory cell array in the phase-change memory design can be arbitrary. Exemplarily, the proportion of phase-change memory cells in the first or second region to the total number of phase-change memory cells in the memory cell array (e.g., a memory block) can be arbitrary. In some embodiments, the proportion of phase-change memory cells in the first region to the total number of phase-change memory cells in the memory cell array (e.g., a memory block) can range from 0 to 30%. Exemplarily, this proportion can be 1%, 5%, 10%, 15%, 19%, 25%, or 29%, or other values ​​such as 0.3%, 5.5%, 25.6%, or 29.8%.

[0064] In some embodiments, the memory cell array includes a first memory block and a second memory block different from the first memory block. The proportion of phase-change memory cells in a first region of the first memory block and the proportion of phase-change memory cells in the first region of the second memory block can be set independently. For example, the proportion of phase-change memory cells in the first region of the first memory block and the proportion of phase-change memory cells in the first region of the second memory block can be set to be the same or different.

[0065] In some embodiments, the memory cell array can be divided into different regions (e.g., a first region and a second region) based on the relative positions of the phase-change memory cells in the phase-change memory. In some embodiments, the first region is closer to the central region of the memory cell array (e.g., a memory block) than the second region; the second region is closer to the edge region of the memory cell array (e.g., a memory block) than the first region. In some embodiments, the second region is located on opposite sides of the first region along a first direction (the extension direction of the first address line) or along a second direction (the extension direction of the second address line). In some embodiments, the second region may surround the first region. In some embodiments, the phase-change memory cells in the first region are closer to the feature circuitry of the peripheral circuitry (e.g., word line drivers and bit line drivers) than the phase-change memory cells in the second region.

[0066] In some embodiments, the memory cell array can be divided into different regions (e.g., a first region and a second region) based on the performance of the phase-change memory (e.g., ECC-related characteristics). In some embodiments, the first region can be understood as a region where errors occur more frequently than the second region, and a matching ECC threshold needs to be set for the first region and the second region.

[0067] In some embodiments, the memory cell array includes multiple memory blocks; each memory block includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells; each memory block includes a first region and a second region. In some embodiments, the memory block may be a repeating structure having the same number of phase-change memory cells. Exemplarily, a memory block may have M word lines, N bit lines, and M x N phase-change memory cells coupled to the M word lines and N bit lines, where M and N are positive integers. Hereinafter, for ease of description of the embodiments of this application, an example of 32 word lines, 64 bit lines, and 32 x 64 = 2048 phase-change memory cells coupled to the 32 word lines and 64 bit lines will be used for illustration; this example is not intended to limit the embodiments of this application.

[0068] In some embodiments, because the conductive path length of current through the first address line, the phase-change memory cell, and the second address line differs in different regions of the memory block, i.e., the voltage drop caused by the conductive path of the phase-change memory cell differs in different regions, the electrical performance requirements of the phase-change memory cells in different regions differ. Therefore, it is necessary to set matching operations for different regions based on these different electrical performance requirements. For example, when performing a first write operation on phase-change memory cells in different regions, the voltage applied to non-selected bit lines can be set differently. Another example is setting matching ECC thresholds (first threshold and second threshold) to provide different means of detecting slow read interference for phase-change memory cells in different regions, effectively preventing the problem of high original bit error rate or error rate due to regional differences.

[0069] refer to Figure 8 , Figure 9 or Figure 10In some embodiments, the peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are respectively coupled to the phase-change memory cell via a first address line and a second address line; wherein, the electrical distance of the phase-change memory cell in the first region P101 is less than the electrical distance of the phase-change memory cell in the second region P102; the electrical distance is the sum of the first length of the first address line between the phase-change memory cell and the first driving circuit and the second length of the second address line between the phase-change memory cell and the second driving circuit. In the embodiments of this application, the smaller the electrical distance of the phase-change memory cell, the smaller the resistance and the smaller the voltage drop. Compared to driving the phase-change memory cell in the second region, driving the phase-change memory cell in the first region based on the first driving circuit and the second driving circuit results in a smaller voltage drop due to the smaller electrical distance of the phase-change memory cell. In this way, compared to the second region, the threshold can be lowered for the first region (which can be understood as the region where the addresses where errors occur are concentrated). This allows for early detection of slow read interference / risks in the first region, and timely execution of the first refresh operation on the phase change memory units in the first region, effectively preventing the problem of high original bit error rate or error rate in the first region due to slow read interference.

[0070] refer to Figure 9 For example, the phase-change memory cell C14-35 of the first region P101 is located at the intersection between word line WL14 and bit line BL35 and is coupled to word line WL14 and bit line BL35. The electrical distance ED1 of the phase-change memory cell C14-35 can be the sum of size D1 and size D2. The phase-change memory cell C9-45 of the second region P102 is located at the intersection between word line WL9 and bit line BL45 and is coupled to word line WL9 and bit line BL45. The electrical distance ED2 of the phase-change memory cell C9-45 can be the sum of size D3 and size D4. Wherein, the electrical distance ED1 is smaller than the electrical distance ED2.

[0071] Here and below, the first driving circuit can be understood as a word line driver (see reference). Figure 3 The word line driver 308 and bit line driver (see reference) are shown. Figure 3 One of the position line drivers 306 shown, the second driving circuit can be understood as a word line driver (see reference). Figure 3 The word line driver 308 and bit line driver (see reference) are shown. Figure 3 The other of the position line drivers (306) shown. Hereinafter, the first driving circuit is described as a word line driver and the second driving circuit as a bit line driver, but this example is not intended to limit the embodiments of this application.

[0072] In some embodiments, the first and second threshold values ​​can be empirical values; or they can be default values ​​configured at the factory of the phase-change memory (PCM), which are obtained through extensive simulation experiments before the PCM leaves the factory. In some embodiments, the range of the first threshold value is 10 bit / 32B to 15 bit / 32B. For example, the first threshold value is 11 bit / 32B, 12 bit / 32B, 13 bit / 32B, or 14 bit / 32B. In some embodiments, the range of the second threshold value is 16 bit / 32B to 25 bit / 32B. For example, the second threshold value is 17 bit / 32B, 18 bit / 32B, 19 bit / 32B, 20 bit / 32B, 21 bit / 32B, 22 bit / 32B, 23 bit / 32B, or 24 bit / 32B.

[0073] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the memory cell array further includes multiple first contact structures and multiple second contact structures; the first contact structures connect a first address line and a first driving circuit; the second contact structures connect a second address line and a second driving circuit; the multiple first contact structures are arranged along the extension direction of the second address line; the multiple second contact structures are arranged along the extension direction of the first address line; wherein, the first length is the length of the first address line between the phase-change memory cell and the first contact structure; the second length is the length of the second address line between the phase-change memory cell and the second contact structure. In this embodiment, the arrangement of multiple first contact structures along the extension direction of the second address line and multiple second contact structures along the extension direction of the first address line in the plane where the memory cell array is located can ensure that the sum of the electrical distances of all phase-change memory cells in the memory cell array is minimized.

[0074] For example, multiple first contact structures are arranged along the extension direction of the dashed line DL1 (which can be understood as the extension direction of the second address line (bit line BL)). The first contact structures are located at the intersection of the dashed line DL1 and the first address line (word line WL) and are coupled to the first address line (word line WL). For example, multiple second contact structures are arranged along the extension direction of the dashed line DL2 (which can be understood as the extension direction of the first address line (word line WL)). The second contact structures are located at the intersection of the dashed line DL2 and the second address line (bit line BL) and are coupled to the second address line (bit line BL).

[0075] refer to Figure 9 For example, the phase change memory cell C14-35 in the first region P101 has a first length of dimension D1 and a second length of dimension D2; the phase change memory cell C9-45 in the second region P102 has a first length of dimension D3 and a second length of dimension D4.

[0076] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the first region P101 is located in the middle of the memory cell array; the first contact structure is located in the middle of the first address line; the second contact structure is located in the middle of the second address line; and the first driving circuit and the second driving circuit are located above the first region P101. In this embodiment, the driver / driving circuit (the first driving circuit and the second driving circuit) is projected onto the plane where the memory cell array is located, which can ensure the symmetrical layout of the driver / driving circuit (the first driving circuit and the second driving circuit); it can also ensure that the sum of the electrical distances of all phase-change memory cells in the memory cell array is minimized.

[0077] In some embodiments, the second region P102 may be further divided into multiple different regions (e.g., a third region and multiple fourth regions). Specific details regarding the division of the second region P102 into multiple different regions can be understood by referring to the above-described details regarding the division of the memory cell array (e.g., memory blocks) into a first region and a second region, and will not be repeated here.

[0078] refer to Figure 10 In some embodiments, the second region P102 includes a third region P103 and a plurality of fourth regions P104; the third region P103 is located on at least one side of the first region away from the middle of the first region; the plurality of fourth regions P104 are arranged on at least one side of the third region P103 away from the first region; the electrical distance between the phase-change memory cells of the third region P103 is less than the electrical distance between the phase-change memory cells of the fourth region P104; the peripheral circuit is further configured to: perform a second refresh operation on the phase-change memory cells of the third region P103 in response to the bit error rate corresponding to the third region P103 exceeding a second threshold threshold of the ECC; and perform a second refresh operation on the phase-change memory cells of the fourth region P104 in response to the bit error rate corresponding to the fourth region P104 exceeding a fifth threshold threshold of the ECC; wherein the fifth threshold threshold is greater than the second threshold threshold. In this embodiment, matching ECC thresholds (a first threshold, a second threshold, and a fifth threshold) can be set for three different regions of the storage cell array. During the bit error rate detection process of the phase-change memory, if the bit error rate of one region of the storage cell array exceeds the corresponding threshold, a refresh operation (a first refresh operation and a second refresh operation) can be performed on that region. In this way, based on the different conditions of the three different regions of the storage cell array, the slow read interference situation / risk in the corresponding region can be detected in advance, and the storage cells in the corresponding region can be refreshed, effectively preventing the problem of a high original bit error rate or error rate caused by slow read interference.

[0079] In some embodiments, the proportion of phase-change memory cells in the plurality of fourth regions to the total phase-change memory cells in the memory cell array (e.g., memory block) can range from 0 to 30%. For example, this proportion can be 1%, 5%, 10%, 15%, 19%, 25%, or 29%, or other values ​​such as 0.3%, 5.5%, 25.6%, or 29.8%. In some embodiments, the sum of the proportion of phase-change memory cells in the first region to the total phase-change memory cells in the memory cell array (e.g., memory block) and the proportion of phase-change memory cells in the plurality of fourth regions to the total phase-change memory cells in the memory cell array (e.g., memory block) can range from 0 to 30%. For example, this sum can be 1%, 5%, 10%, 15%, 19%, 25%, or 29%, or other values ​​such as 0.3%, 5.5%, 25.6%, or 29.8%. In some embodiments, the fifth threshold can be an empirical value; or it can be a default value configured at the factory of the phase-change memory, which is obtained through extensive simulation experiments before the phase-change memory leaves the factory. In some embodiments, the second threshold ranges from 16 bit / 32B to 20 bit / 32B; the fifth threshold ranges from 21 bit / 32B to 25 bit / 32B. For example, the second threshold is 17 bit / 32B, 18 bit / 32B, or 19 bit / 32B; the fifth threshold is 22 bit / 32B, 23 bit / 32B, or 24 bit / 32B.

[0080] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the peripheral circuitry is further configured to disable the phase-change memory cells of the first region P101 in response to the bit error rate (BER) of the first region P101 exceeding a third threshold of the ECC, or the number of times the BER of the first region P101 exceeds a fourth threshold of the ECC being greater than or equal to a preset threshold; wherein the third threshold and the fourth threshold are greater than the first threshold; the third threshold is greater than the fourth threshold. In this embodiment, based on the fact that the BER of the first region exceeds the third threshold of the ECC, or the number of times the BER of the first region exceeds the fourth threshold of the ECC being greater than or equal to a first preset threshold, the first region can be treated as a bad block, and the addresses within the first region will not be used in subsequent use.

[0081] In some embodiments, the third and fourth threshold values ​​can be empirical values; or they can be default values ​​configured at the factory of the phase-change memory (PCM), which are obtained through extensive simulation experiments before the PCM leaves the factory. In some embodiments, the range of the fourth threshold value is 21 bit / 32B to 30 bit / 32B. For example, the fourth threshold value is 22 bit / 32B, 23 bit / 32B, 24 bit / 32B, 25 bit / 32B, 26 bit / 32B, 27 bit / 32B, 28 bit / 32B, or 29 bit / 32B. In some embodiments, the range of the third threshold value is 31 bit / 32B to 40 bit / 32B. For example, the third threshold value is 32 bit / 32B, 33 bit / 32B, 34 bit / 32B, 35 bit / 32B, 36 bit / 32B, 37 bit / 32B, 38 bit / 32B, or 39 bit / 32B.

[0082] In some embodiments, the preset threshold can be an empirical value; or it can be a default value configured at the factory of the phase-change memory, which is obtained through a large number of simulation experiments before the phase-change memory leaves the factory. In some embodiments, the preset threshold ranges from 5 to 10 times. For example, the third threshold is 6, 7, 8, or 9 times.

[0083] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the peripheral circuitry is further configured to: perform a first refresh operation on the phase-change memory cells of the first region based on a first refresh frequency; and perform a second refresh operation on the phase-change memory cells of the second region based on a second refresh frequency; wherein the first refresh frequency is greater than the second refresh frequency. In this embodiment, different refresh frequencies can be set for different regions of the memory cell array. Compared to the refresh frequency for the phase-change memory cells of the second region, the refresh frequency for the phase-change memory cells of the first region can be increased. This allows for targeted refresh operations on the memory cells of the corresponding regions based on different conditions in different regions of the memory cell array, effectively preventing the problem of high original bit error rate or error rate caused by slow read interference.

[0084] In some embodiments, the first refresh rate can be from 1 / 24 hour to 4 times / 24 hours. For example, the first refresh rate can be 2 / 24 hours or 3 times / 24 hours. In some embodiments, the second refresh rate can be from 5 times / 24 hours to 24 times / 24 hours. For example, the first refresh rate can be 6 times / 24 hours, 7 times / 24 hours, 8 times / 24 hours, 9 times / 24 hours, 10 times / 24 hours, 11 times / 24 hours, 12 times / 24 hours, 13 times / 24 hours, 14 times / 24 hours, 15 times / 24 hours, 16 times / 24 hours, 17 times / 24 hours, 18 times / 24 hours, 19 times / 24 hours, 20 times / 24 hours, 21 times / 24 hours, 22 times / 24 hours, or 23 times / 24 hours.

[0085] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the peripheral circuitry further includes a timer; the timer is configured to set a timestamp; the timestamp records the moment of a read operation request for the phase-change memory cell; the interval between two adjacent read operations of the phase-change memory cell is obtained based on the timestamp; the peripheral circuitry is also configured to perform a third refresh operation on the corresponding phase-change memory cell in response to an interval length greater than or equal to a first duration. In this embodiment, the third refresh operation can be understood as a refresh operation triggered based on an interval length greater than or equal to the first duration. In some embodiments, the specific process by which the peripheral circuitry is configured to perform the third refresh operation on the phase-change memory cell can be understood by referring to the specific process of the first refresh operation or the second refresh operation, and will not be repeated here.

[0086] In some embodiments, the timer is configured to respond to data I / O (reference) Figure 3 The data I / O 316 shown is a read operation, and a timestamp is set. The timestamp is used to record the time of the read operation request of the phase change memory unit. The peripheral circuit is also configured to obtain the interval between two adjacent read operation requests based on the timestamp recorded. This interval is the first duration.

[0087] In some embodiments, the first duration can be an empirical value; or it can be a default value configured at the factory of the phase-change memory, which is obtained through extensive simulation experiments before the phase-change memory leaves the factory. In some embodiments, the range of the first duration is 100s to 1000s. Exemplarily, the first duration is 200s, 300s, 400s, 500s, 600s, 700s, 800s, or 900s.

[0088] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, the peripheral circuitry is configured to: perform a third refresh operation on the corresponding phase-change memory cell in response to the interval duration of the phase-change memory cell in the first region being greater than or equal to a first duration; and perform a third refresh operation on the corresponding phase-change memory cell in response to the interval duration of the phase-change memory cell in the second region being greater than or equal to a second duration; wherein the first duration is less than the second duration. In this embodiment, when matching ECC thresholds (first threshold and second threshold) are set for different regions (first region and second region) of the memory cell array, further, matching durations (first duration and second duration) are set for different regions (first region and second region) of the memory cell array. During the phase-change memory's bit error rate detection process, if the interval duration of a region of the memory cell array is greater than or equal to the corresponding duration threshold, then a corresponding refresh operation (first refresh operation or second refresh operation) can be performed on that region, effectively preventing the problem of a high original bit error rate or error rate due to slow read interference.

[0089] In some embodiments, the first duration ranges from 100s to 500s. Exemplarily, the first duration is 150s, 200s, 250s, 300s, 350s, 400s, or 450s. In some embodiments, the second duration ranges from 600s to 1000s. Exemplarily, the first duration is 650s, 700s, 750s, 800s, 850s, 900s, or 950s.

[0090] Figure 11 This diagram illustrates the relationship between the average original bit error rate and the number of cycles under different time intervals, as provided in embodiments of this application. (Reference) Figure 11 Curves L5, L6, and L7 illustrate the relationship between the average original bit error rate and the number of cycles for time intervals Tint1, Tint2, and Tint3, respectively. Time interval Tint1 is less than time interval Tint2, and time interval Tint2 is less than time interval Tint3. From curves L5, L6, and L7, it can be seen that, with a fixed number of cycles, the longer the time interval between two adjacent read operations, the higher the average original bit error rate, which can be understood as the more severe the slow read interference.

[0091] refer to Figure 8 , Figure 9 or Figure 10 In some embodiments, when performing a first refresh operation or a second refresh operation on the phase-change memory cell, the peripheral circuit is configured to: perform a read operation on the phase-change memory cell; and perform a write operation on the phase-change memory cell based on the data read from the read operation.

[0092] For example, a first refresh operation is performed on the phase-change memory cell, and the peripheral circuitry is configured to: based on a read operation, read the stored data of the phase-change memory cell in the first region to a sense amplifier (reference). Figure 3 In the sense amplifier 304 shown; and, based on a read operation, the stored data of the sense amplifier is written to the phase-change memory cell in the first region. In some embodiments, the first refresh operation or the second refresh operation may not involve passing the stored data of the sense amplifier through a column decoder (see reference 304). Figure 3 The column decoder 306 shown transfers data I / O (see reference). Figure 3 The operation of data I / O 316 shown.

[0093] Figure 12 This is one of the schematic flowcharts for performing the first refresh operation provided in the embodiments of this application.

[0094] refer to Figure 12 In some embodiments, the peripheral circuitry is configured to perform the following steps: steps S101 and S102, based on data I / O (reference... Figure 3 The data I / O 316 shown is requested to confirm whether it is a read operation; step S103: based on the fact that it is a read operation, confirm whether the interval duration exceeds the first duration; step S104: based on the fact that the interval duration exceeds the first duration, confirm whether the address involved in the read operation belongs to the address of the storage unit in the first region; step S105: based on the fact that the address involved in the read operation belongs to the address of the storage unit in the first region, perform a first refresh operation on the storage unit corresponding to the address involved in the read operation.

[0095] refer to Figure 12 In some embodiments, the peripheral circuit is also configured to perform the following steps: step S106, based on the interval duration not exceeding the first duration, return to execute step S101, data I / O request; or, step S107, based on the address involved in the read operation not belonging to the first region, return to execute step S101, data I / O request.

[0096] Figure 13 This is the second illustrative flowchart of performing the first refresh operation provided in an embodiment of this application.

[0097] refer to Figure 13 In some embodiments, the peripheral circuitry is configured to perform the following steps: steps S201 and S202, based on data I / O (refer to...) Figure 3The data I / O 316 shown is requested to confirm whether it is a read operation; step S203: based on the fact that it is a read operation, confirm whether the address involved in the read operation belongs to the address of the storage unit in the first region; step S204: based on the fact that the address involved in the read operation belongs to the address of the storage unit in the first region, confirm whether the interval duration exceeds the first duration; step S205: based on the fact that the interval duration exceeds the first duration, perform a first refresh operation on the storage unit corresponding to the address involved in the read operation.

[0098] refer to Figure 13 In some embodiments, the peripheral circuit is also configured to perform the following steps: step S206, based on the address involved in the read operation not belonging to the first region, return to execute step S201, data I / O request; or, step S207, based on the interval duration not exceeding the first duration, return to execute step S201, data I / O request.

[0099] According to a second aspect of the present application, a method for operating a phase-change memory (PCM) is provided. The PCM includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of PCM cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; the method for operating the PCM includes: performing a first refresh operation on the PCM cells of the first region in response to a bit error rate (BER) of the corresponding region exceeding a first ECC threshold; and performing a second refresh operation on the PCM cells of the second region in response to a BER of the corresponding region exceeding a second ECC threshold; wherein the first threshold is less than the second threshold.

[0100] In some embodiments, the operation method of the phase-change memory further includes: disabling the phase-change memory cells in the first region in response to the bit error rate of the first region exceeding a third threshold of the ECC, or the number of times the bit error rate of the first region exceeds a fourth threshold of the ECC being greater than or equal to a preset threshold; wherein the third threshold and the fourth threshold are greater than the first threshold; the third threshold is greater than the fourth threshold.

[0101] In some embodiments, the operation method of the phase-change memory includes: performing a first refresh operation on the phase-change memory cells in a first region based on a first refresh frequency; and performing a second refresh operation on the phase-change memory cells in a second region based on a second refresh frequency; wherein the first refresh frequency is greater than the second refresh frequency.

[0102] In some embodiments, the peripheral circuitry further includes a timer; the timer sets a timestamp; the timestamp records the moment of the read operation request of the phase-change memory cell; the interval between two adjacent read operations of the phase-change memory cell is obtained based on the timestamp; the operation method of the phase-change memory further includes: in response to the interval being greater than or equal to a first duration, performing a third refresh operation on the corresponding phase-change memory cell.

[0103] In some embodiments, the operation method of the phase-change memory includes: performing a third refresh operation on the corresponding phase-change memory cell in response to the phase-change memory cell in the first region having an interval duration greater than or equal to a first duration; and performing a third refresh operation on the corresponding phase-change memory cell in the second region having an interval duration greater than or equal to a second duration; wherein the first duration is less than the second duration.

[0104] In some embodiments, the peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are respectively coupled to the phase change memory cell via a first address line and a second address line; wherein the electrical distance between the phase change memory cells in the first region is less than the electrical distance between the phase change memory cells in the second region; the electrical distance is the sum of the first length of the first address line between the phase change memory cell and the first driving circuit and the second length of the second address line between the phase change memory cell and the second driving circuit.

[0105] In some embodiments, the memory cell array further includes a plurality of first contact structures and a plurality of second contact structures; the first contact structures connect a first address line and a first driving circuit; the second contact structures connect a second address line and a second driving circuit; the plurality of first contact structures are arranged along the extension direction of the second address line; the plurality of second contact structures are arranged along the extension direction of the first address line; wherein, the first length is the length of the first address line between the phase-change memory cell and the first contact structure; and the second length is the length of the second address line between the phase-change memory cell and the second contact structure.

[0106] In some embodiments, the first region is located in the middle of the memory cell array; the first contact structure is located in the middle of the first address line; the second contact structure is located in the middle of the second address line; and the first driving circuit and the second driving circuit are located above the first region.

[0107] In some embodiments, the second region includes a third region and a plurality of fourth regions; the third region is located on at least one side of the first region away from the middle of the first region; the plurality of fourth regions are arranged on at least one side of the third region away from the first region; the electrical distance between the phase-change memory cells in the third region is less than the electrical distance between the phase-change memory cells in the fourth region; the operation method of the phase-change memory further includes: performing a second refresh operation on the phase-change memory cells in the third region in response to the bit error rate corresponding to the third region exceeding a second threshold threshold of the ECC; performing a second refresh operation on the phase-change memory cells in the fourth region in response to the bit error rate corresponding to the fourth region exceeding a fifth threshold threshold of the ECC; wherein the fifth threshold threshold is greater than the second threshold threshold.

[0108] In some embodiments, a first refresh operation or a second refresh operation is performed on the phase-change memory cell. The operation method of the phase-change memory includes: performing a read operation on the phase-change memory cell; and performing a write operation on the phase-change memory cell based on the data read in the read operation.

[0109] The phase-change memory used in the operation method of the phase-change memory provided in the second aspect of this application is the same as or similar to the phase-change memory in the first aspect of the above-described embodiments. For technical features not disclosed in detail in the second aspect of this application, please refer to the phase-change memory in the first aspect of the above-described embodiments for understanding, and will not be repeated here.

[0110] According to a third aspect of the present application, a memory system is provided, the memory system comprising: a memory, including any phase-change memory as provided in the first aspect, or a phase-change memory applied according to any operating method provided in the second aspect; and a memory controller, coupled to the memory and configured to control the memory.

[0111] In this embodiment, the memory and memory controller of the memory system can be referred to the above. Figure 1 The relevant descriptions can be used for understanding, and will not be repeated here. The storage array and peripheral circuitry of the phase-change memory can be referred to the above. Figure 2 and Figure 3 To understand the relevant descriptions, refer to the phase-change memory cells of the memory cell array. Figure 4 and Figure 5 The relevant descriptions will be understood and will not be repeated here.

[0112] Figure 14 A block diagram of a readable storage medium provided in an embodiment of this application.

[0113] like Figure 14As shown, according to a fourth aspect of the present application, a readable storage medium 400 is provided, which stores a computer program 410. When the computer program 410 is executed, it can implement any of the phase-change memory operation methods provided in the second aspect.

[0114] For example, a phase-change memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes a plurality of first address lines, a plurality of second address lines, and a plurality of phase-change memory cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; an operation method of the phase-change memory includes: performing a first refresh operation on the phase-change memory cells of the first region in response to the bit error rate corresponding to the first region exceeding a first threshold threshold of ECC; performing a second refresh operation on the phase-change memory cells of the second region in response to the bit error rate corresponding to the second region exceeding a second threshold threshold of ECC; wherein the first threshold threshold is less than the second threshold threshold.

[0115] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0116] The above description is only a preferred embodiment of this application and does not limit the scope of protection of this application. All equivalent structural transformations made under the inventive concept of this application using the content of this application specification and drawings, or direct / indirect applications in other related technical fields, are included within the scope of protection of this application.

Claims

1. A phase-change memory, characterized in that, include: A memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; The peripheral circuit is configured as follows: In response to the bit error rate of the first region exceeding the first threshold of error checking and correction (ECC), a first refresh operation is performed on the phase change memory cell of the first region. In response to the bit error rate of the second region exceeding the second threshold of ECC, a second refresh operation is performed on the phase change memory cell of the second region; Wherein, the first threshold is less than the second threshold.

2. The phase-change memory according to claim 1, characterized in that, The peripheral circuit is also configured to: In response to the bit error rate of the first region exceeding the third threshold of ECC, or the number of times the bit error rate of the first region exceeds the fourth threshold of ECC is greater than or equal to a preset threshold, the phase change memory unit of the first region is disabled. Wherein, the third threshold and the fourth threshold are greater than the first threshold; the third threshold is greater than the fourth threshold.

3. The phase-change memory according to claim 1, characterized in that, The peripheral circuit is specifically configured as follows: Based on the first refresh frequency, the first refresh operation is performed on the phase-change memory unit in the first region; Based on the second refresh frequency, the second refresh operation is performed on the phase-change memory unit in the second region; The first refresh frequency is greater than the second refresh frequency.

4. The phase-change memory according to claim 1, characterized in that, The peripheral circuit also includes a timer; the timer is configured to set a timestamp; the timestamp records the moment of the read operation request of the phase-change memory unit; and the interval between two adjacent read operations of the phase-change memory unit is obtained based on the timestamp. The peripheral circuit is also configured to: In response to the interval being greater than or equal to the first duration, a third refresh operation is performed on the corresponding phase-change memory cell.

5. The phase-change memory according to claim 4, characterized in that, The peripheral circuit is configured as follows: In response to the phase change memory cell in the first region having an interval duration greater than or equal to the first duration, the third refresh operation is performed on the corresponding phase change memory cell. In response to the phase change memory cell in the second region having an interval duration greater than or equal to the second duration, the third refresh operation is performed on the corresponding phase change memory cell; Wherein, the first duration is shorter than the second duration.

6. The phase-change memory according to claim 1, characterized in that, The peripheral circuit includes a first driving circuit and a second driving circuit; the first driving circuit and the second driving circuit are respectively coupled to the phase-change memory unit through the first address line and the second address line. Wherein, the electrical distance between the phase-change memory cells in the first region is less than the electrical distance between the phase-change memory cells in the second region; the electrical distance is the sum of the first length of the first address line between the phase-change memory cell and the first driving circuit and the second length of the second address line between the phase-change memory cell and the second driving circuit.

7. The phase-change memory according to claim 6, characterized in that, The memory cell array further includes a plurality of first contact structures and a plurality of second contact structures; the first contact structures are connected to the first address lines and the first driving circuit. The second contact structure connects the second address line and the second driving circuit; Multiple first contact structures are arranged along the extension direction of the second address lines; multiple second contact structures are arranged along the extension direction of the first address lines; Wherein, the first length is the length of the first address line between the phase-change memory cell and the first contact structure; the second length is the length of the second address line between the phase-change memory cell and the second contact structure.

8. The phase-change memory according to claim 7, characterized in that, The first region is located in the middle of the memory cell array; the first contact structure is located in the middle of the first address line; the second contact structure is located in the middle of the second address line; the first driving circuit and the second driving circuit are located above the first region.

9. The phase-change memory according to claim 6, characterized in that, The second region includes a third region and a plurality of fourth regions; the third region is located on at least one side of the first region away from the middle of the first region; the plurality of fourth regions are arranged on at least one side of the third region away from the first region; the electrical distance between the phase change memory cells in the third region and the phase change memory cells in the fourth regions is smaller than the electrical distance between the phase change memory cells in the fourth regions. The peripheral circuit is also configured to: In response to the bit error rate of the third region exceeding the second threshold of ECC, the second refresh operation is performed on the phase change memory cell of the third region; In response to the bit error rate of the fourth region exceeding the fifth threshold of ECC, the second refresh operation is performed on the phase change memory cell of the fourth region; The fifth threshold is greater than the second threshold.

10. The phase-change memory according to claim 1, characterized in that, When performing the first refresh operation or the second refresh operation on the phase-change memory unit, the peripheral circuit is configured as follows: Perform a read operation on the phase-change memory unit; Based on the data read by the read operation, a write operation is performed on the phase-change memory unit.

11. A method for operating a phase-change memory, characterized in that, The phase-change memory includes: a memory cell array and peripheral circuitry coupled to the memory cell array; the memory cell array includes multiple first address lines, multiple second address lines, and multiple phase-change memory cells; the memory cell array includes a first region and a second region; the second region is located on at least one side of the first region away from the middle of the first region; The operation method includes: In response to the bit error rate of the first region exceeding the first threshold of ECC, a first refresh operation is performed on the phase change memory cell of the first region. In response to the bit error rate of the second region exceeding the second threshold of ECC, a second refresh operation is performed on the phase change memory cell of the second region; Wherein, the first threshold is less than the second threshold.

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