Inverter type linear equalizer based on feedforward capacitance

Abstract

A kind of inverter type linear equalizer based on feedforward capacitor, including: inverter type input stage unit, feedforward capacitor passage, inductive peaking load and common mode feedback (CMFB) module, the application is realized by using inverter architecture as differential input stage, current multiplexing of NMOS and PMOS device, obtain the equivalent transconductance higher than traditional common source stage structure;The feedforward capacitor passage introduced in design, actively modulates the source voltage of input MOS tube at high frequency, further improves the effective transconductance of circuit, in transfer function, it is shown as generating a pair of zero-pole pairs for bandwidth expansion;Inductive peaking technology is used at load end, a zero point and a pair of conjugate poles are introduced in transfer function, effectively expand the system bandwidth.

Description

Technical Field

[0001] This invention relates to a technology in the field of signal processing, specifically an inverter-type linear equalizer based on a feedforward capacitor. Background Technology

[0002] Existing continuous-time linear equalization (CTLE) techniques typically employ source degradation networks combined with inductor peaking techniques. This involves introducing a zero in the transfer function using an RC parallel connection to enhance high-frequency gain. An inductor is connected in series with the load resistor to push the dominant pole to a higher frequency, thereby increasing the overall bandwidth. However, this technique only introduces a zero in the transfer function and does not effectively improve the amplifier's equivalent transconductance. This results in low capacitor utilization efficiency, and the overall transconductance of the circuit remains fundamentally limited by the transconductance of a single input transistor. Existing inverter-based CTLE techniques suffer from a long feedforward signal path, making it impossible to actively enhance the equivalent transconductance of the input stage itself. Summary of the Invention

[0003] To address the aforementioned shortcomings of existing technologies, this invention proposes an inverter-type linear equalizer based on a feedforward capacitor. This equalizer uses a feedforward capacitor path to send the inverted input signal to the source terminal of the input MOS transistor. By modulating the small-signal voltage at the source terminal, the equivalent transconductance of the circuit can be improved. Simultaneously, a zero is introduced into the transfer function, achieving efficient utilization of the capacitor. Furthermore, the inverter architecture and feedforward path are integrated into a unipolar linear equalizer, enabling efficient current multiplexing and significantly improving the circuit's equivalent transconductance. In addition, by combining inductor peaking and common-mode feedback techniques, the bandwidth is further enhanced, and common-mode stable control is achieved.

[0004] This invention is achieved through the following technical solution:

[0005] This invention relates to an inverter-type linear equalizer based on a feedforward capacitor, comprising: an inverter-type input stage unit, a feedforward capacitor path, an inductive peaking load, and a common-mode feedback (CMFB) module, wherein: the inverter-type input stage unit receives a differential input signal and generates a high transconductance small-signal current using the current multiplexing effect of NMOS and PMOS devices; the feedforward capacitor path couples the inverted input signal to the source terminal of the input stage NMOS transistor, modulating the small-signal voltage at the source terminal to introduce a zero in the transfer function and further improve the effective transconductance; the inductive peaking load is connected to the output terminal of the inverter-type input stage unit, receives the small-signal current output by the inverter-type input stage unit, and outputs the equalized differential signal; the CMFB module generates a control voltage based on the differential signal to adjust the small-signal current of the inverter-type input stage unit.

[0006] The inverter-type input stage unit is used to improve the equivalent transconductance of the circuit. The inverter-type input stage unit adopts a sleeve structure, a folded structure, or a common source cascode structure. Among them, the folded structure can expand the input common mode voltage range and input swing, but it will increase the circuit power consumption. It is suitable for application scenarios with special requirements for input swing.

[0007] The sleeve-type inverter-type input stage unit includes: first to eighth transistors, and first and second degradation resistors, wherein: the first to fourth transistors form a pair of inverters as a differential input stage, the seventh and eighth transistors serve as tail current sources; the fifth and sixth transistors are controlled by a common-mode feedback circuit to stabilize the output common-mode level.

[0008] The feedforward capacitor path employs a capacitive-resistive parallel network or a capacitive-inductive series network. The inductive peaking load is connected in series with the load inductor at the load resistor to delay the transfer function poles and increase circuit bandwidth.

[0009] Technical effect

[0010] This invention combines a feedforward capacitor path with an inverter input stage to achieve synergistic transconductance multiplication. By combining a feedforward capacitor path with inductor peaking technology, the bandwidth of the CTLE is broadened, pushing the peak frequency to higher frequencies. The use of a common-mode feedback circuit enables the circuit to transmit the complete signal spectrum from DC to high frequencies, while ensuring precise input and output common-mode level matching. All modules are integrated into a single-stage CTLE. Compared with existing technologies, this invention effectively improves high-frequency gain compensation capabilities while maintaining low power consumption, resulting in significantly improved energy efficiency compared to existing CTLE architectures. It achieves effective gain compensation at higher frequencies. The compact structure reduces design and layout complexity. It significantly enhances system compatibility and versatility. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of the present invention;

[0012] Figure 2 This is a schematic diagram of the ideal amplitude-frequency response model of the present invention;

[0013] Figure 3 and Figure 4 This is a schematic diagram illustrating the effect of the example;

[0014] Figure 3 (a) CTLE amplitude-frequency response; (b) Schematic diagram comparing amplitude-frequency response before and after signal equalization following channel attenuation.

[0015] Figure 4 (a) Balanced anterior eye image (b) Balanced posterior eye image Detailed Implementation

[0016] like Figure 1 As shown in the figure, this embodiment relates to an inverter-type linear equalizer based on a feedforward capacitor, including: an inverter-type input stage unit, a feedforward capacitor path, an inductor peaking load, and a common-mode feedback (CMFB) module. Specifically: the inverter-type input stage unit receives differential input signals Vin+ and Vin-, and utilizes the current multiplexing effect of NMOS and PMOS devices to generate a small-signal current with high transconductance; the feedforward capacitor path receives the input signals Vin+ and Vin-, performs source-terminal voltage modulation processing, modulates the source-terminal voltage of the input stage NMOS transistor, and introduces a zero in the transfer function to increase the effective transconductance of the circuit; the inductor peaking load receives the small-signal current output by the inverter-type input stage unit, performs load impedance boosting and bandwidth expansion processing, and outputs a bandwidth-expanded differential voltage signal, while simultaneously outputting a common-mode level; the CMFB module receives the common-mode level output by the inductor peaking load and outputs a control voltage to adjust the bias current of the inverter-type input stage unit.

[0017] The feedforward capacitor path includes: first to fourth path capacitors C f1 C f2 C f3 C f4 Where: the first path capacitor C f1 The second-path capacitor C is located at the source terminals of Vin+ and M2. f2 The third-path capacitor C is located at the source terminals of Vin- and M1. f3 The fourth capacitor C is located at the source terminals of Vin+ and M4. f4 Set at the source end of Vin- and M3.

[0018] In this embodiment, the capacitance values ​​of the four channels are the same.

[0019] The inductive peaked load includes: first and second load inductors L1 and L2, and first and second load resistors R. L1 R L2 Where: the first load resistance R L1 Set at L1 and CMFB input voltage V cmfb Second load resistor R L2 Set at L2 and CMFB input voltage V cmfb The first load inductor L1 is set at R. L1 With the inverting output terminal Vout-, the second load inductor L2 is set at R. L2 The positive output terminal Vout+.

[0020] The inverter-type input stage unit includes: first to eighth transistors M1-M8, and first and second degradation resistors R. s1 R s2Wherein: the gates of the first and third transistors M1 and M3 are connected to the non-inverting input terminal Vin+ and their drains are connected together, serving as the inverting output terminal Vout-; the gates of the second and fourth transistors M2 and M4 are connected to the inverting input terminal Vin- and their drains are connected together, serving as the non-inverting output terminal Vout+; the gates of the seventh and eighth transistors M7 and M8 are connected to the external bias voltage Vbias and their sources are grounded, with their drains connected to the sources of the third and fourth transistors M3 and M4, respectively; the gates of the fifth and sixth transistors M5 and M6 are connected to the CMFB output voltage and their sources are connected to the power supply voltage VDD, with their drains connected to the sources of the first and second transistors M1 and M2, respectively; the first degradation resistor R s1 The sources of the first and second transistors M1 and M2 are connected; the second degradation resistor R s2 Connect the sources of the third and fourth transistors M3 and M4.

[0021] In this embodiment, the two degraded resistors have the same resistance value.

[0022] The first, second, fifth, and sixth transistors are PMOS transistors, and the third, fourth, seventh, and eighth transistors are NMOS transistors.

[0023] The CMFB module includes: transistors nine through thirteen, wherein: transistors eleven and twelfth are M 11 M 12 The gates are respectively connected to the external common-mode input V. ref With CMFB input voltage V cmfb And the source is connected to the thirteenth transistor M. 13 The drain of the thirteenth transistor M; 13 The gate is connected to an external bias voltage V. bias And the source is grounded; the ninth and tenth transistors M9 and M 10 The source is connected to the power supply voltage VDD, and the drain and gate are respectively connected to the eleventh and twelfth transistors M. 11 M 12 The drain of the ninth transistor M9 is the gate of the CMFB, and it is connected to the gates of the fifth and sixth transistors M5 and M6.

[0024] The ninth and tenth transistors are PMOS transistors, and the eleventh to thirteenth transistors are NMOS transistors.

[0025] The voltage transfer function of the inverter-type linear equalizer in the s-domain in this embodiment is: ,in: , , , , gm1 is the transconductance of the first and second transistors M1 and M2, gm2 is the transconductance of the third and fourth transistors M3 and M4, and r o1 r is the internal resistance of the first and second transistors M1 and M2. o2 R is the internal resistance of the third and fourth transistors M3 and M4. s Representative source degradation resistance R s1 R s2 (where R) s =R s1 =R s2 ), C f Represents the feedforward capacitor C f1 ~C f4 (where C) f =C f1 = C f2 = C f3 =C f4 ), R L Represents the output impedance Z L In the figure, the load resistor L represents the output impedance Z. L Peaking inductance in C L Represents the output impedance Z L External load capacitor in.

[0026] The voltage transfer function has two zeros and three poles. To achieve the amplitude-frequency response of CTLE, the second zero Z2 needs to be equal to the first pole p1 to cancel each other out, meaning the circuit parameters satisfy the constraint: Under these conditions, the system is equivalent to a structure with a single zero and a pair of conjugate poles, and its amplitude-frequency response exhibits the following characteristics: Figure 2 The ideal gain peak characteristics shown help to achieve effective equalization at the target frequency.

[0027] Through practical application experiments, the inverter-type linear equalizer based on feedforward capacitor of this invention was designed and simulated using Cadence Spectre under 40nm CMOS process, 27°C temperature, and 1.2V power supply voltage. The simulation results of the frequency response are as follows: Figure 4 As shown in (a), this CTLE achieves a peak gain of 13.01 dB at 16.60 GHz, while consuming only 5.94 mW of core circuitry. Subsequently, the equalization performance was evaluated using a channel with a 15.43 dB attenuation at 16.6 GHz. The signal transmitted through this channel was equalized using this CTLE. The frequency response before and after equalization is shown below. Figure 4 As shown in (b), the equalized response exhibits appropriate suppression at low frequencies, while showing a significant enhancement near 16.6 GHz, achieving a peak gain compensation of 13.01 dB.

[0028] To evaluate time-domain performance, a 33.2 Gb / s pseudo-random bit sequence was passed through the aforementioned channel and then equalized using the CTLE circuit. The eye diagrams of the channel output and the CTLE output were compared as follows: Figure 3 As shown, the equalized output shows a significant improvement in eye opening, with a measured eye width of 0.87 UI and an eye height of 391.86 mV.

[0029] Compared with existing technologies, this invention achieves synergistic multiplication of transconductance by combining a feedforward capacitor path with an inverter input stage, resulting in a core circuit power consumption of only 5.94 mW when achieving a peak gain of 13.01 dB. By combining the zeros introduced by the feedforward capacitor with the zeros and poles introduced by the inductor peaking technology, the overall bandwidth is effectively extended, achieving a peak frequency of 16.60 GHz. Furthermore, the inverter input stage, feedforward path, inductor peaking load, and CMFB module are highly integrated into a single-stage amplifier.

[0030] In summary, this invention achieves a compact design, reducing design complexity, while enabling the circuit to transmit a complete signal spectrum from DC to high frequencies through common-mode feedback, and ensuring accurate input and output common-mode level matching, thus significantly improving energy efficiency.

[0031] The above-described specific implementations can be partially adjusted by those skilled in the art in different ways without departing from the principles and purpose of the present invention. The scope of protection of the present invention is defined by the claims and is not limited to the above-described specific implementations. All implementation schemes within the scope of the claims are bound by the present invention.

Claims

1. An inverter-type linear equalizer based on a feedforward capacitor, characterized in that, include: The system comprises an inverter-type input stage, a feedforward capacitor path, an inductive peaked load, and a common-mode feedback (CMFB) module. The inverter-type input stage receives the differential input signal and utilizes the current multiplexing effect of NMOS and PMOS devices to generate a high transconductance small-signal current. The feedforward capacitor path couples the inverted input signal to the source terminal of the input stage NMOS transistor, modulating the small-signal voltage at the source terminal to introduce a zero in the transfer function and further enhance the effective transconductance. The inductive peaked load is connected to the output terminal of the inverter-type input stage, receiving the small-signal current output by the inverter-type input stage and outputting an equalized differential signal. The CMFB module generates a control voltage based on the differential signal to regulate the small-signal current of the inverter-type input stage. The inverter-type input stage unit adopts a sleeve-type structure, a folded structure, or a common source cascode structure; The feedforward capacitor path adopts a capacitive-resistive parallel network or a capacitive-inductive series network; The inductive peaking load is connected in series with the load inductor at the load resistor to delay the poles of the transfer function and increase the circuit bandwidth.

2. The inverter-type linear equalizer based on a feedforward capacitor according to claim 1, characterized in that, The sleeve-type inverter-type input stage unit includes: first to eighth transistors, and first and second degradation resistors, wherein: the first to fourth transistors form a pair of inverters as a differential input stage, the seventh and eighth transistors serve as tail current sources; the fifth and sixth transistors are controlled by a common-mode feedback circuit to stabilize the output common-mode level.

3. The inverter-type linear equalizer based on a feedforward capacitor according to claim 2, characterized in that, The feedforward capacitor path includes: first to fourth path capacitors, wherein: the first path capacitor is disposed between the non-inverting input terminal and the source terminal of the second transistor; the second path capacitor is disposed between the inverting input terminal and the source terminal of the first transistor; the third path capacitor is disposed between the non-inverting input terminal and the source terminal of the fourth transistor; and the fourth path capacitor is disposed between the inverting input terminal and the source terminal of the third transistor.

4. The inverter-type linear equalizer based on a feedforward capacitor according to claim 3, characterized in that, The capacitance values ​​of the first to fourth path capacitors are equal.

5. The inverter-type linear equalizer based on a feedforward capacitor according to claim 1, characterized in that, The inductive peaked load includes: first and second load inductors and first and second load resistors, wherein: the first load resistor is disposed between the first load inductor and the CMFB voltage input terminal; the second load resistor is disposed between the second load inductor and the CMFB voltage input terminal; the first load inductor is disposed between the first load resistor and the inverting output terminal, and the second load inductor is disposed between the second load resistor and the non-inverting output terminal.

6. The inverter-type linear equalizer based on a feedforward capacitor according to claim 1 or 2, characterized in that, The inverter-type input stage unit includes: first to eighth transistors, and first and second degradation resistors, wherein: the gates of the first and third transistors are connected to the non-inverting input terminals and their drains are connected together, serving as inverting output terminals; the gates of the second and fourth transistors are connected to the inverting input terminals and their drains are connected together, serving as non-inverting output terminals; the gates of the seventh and eighth transistors are connected to an external bias voltage Vbias and their sources are grounded, and their drains are respectively connected to the sources of the third and fourth transistors; the gates of the fifth and sixth transistors are connected to the CMFB output voltage and their sources are connected to the power supply voltage VDD, and their drains are respectively connected to the sources of the first and second transistors; the first degradation resistor is connected to the sources of the first and second transistors; and the second degradation resistor is connected to the sources of the third and fourth transistors.

7. The inverter-type linear equalizer based on a feedforward capacitor according to claim 6, characterized in that, The resistance values ​​of the first and second degradation resistors are equal.

8. The inverter-type linear equalizer based on a feedforward capacitor according to claim 6, characterized in that, The first, second, fifth, and sixth transistors are PMOS transistors, and the third, fourth, seventh, and eighth transistors are NMOS transistors.

9. The inverter-type linear equalizer based on a feedforward capacitor according to claim 1, characterized in that, The CMFB module includes: ninth to thirteenth transistors, wherein: the gates of the eleventh and twelfth transistors are respectively connected to the external common-mode input Vref and the CMFB input voltage Vcmfb, and their sources are connected to the drain of the thirteenth transistor; the gate of the thirteenth transistor is connected to the external bias voltage Vbias, and its source is grounded; the sources of the ninth and tenth transistors are connected to the power supply voltage VDD, and their drains and gates are respectively connected to the drains of the eleventh and twelfth transistors; the gate of the ninth transistor is the output of the CMFB and is connected to the gates of the fifth and sixth transistors.

10. The inverter-type linear equalizer based on a feedforward capacitor according to claim 9, characterized in that, The ninth and tenth transistors are PMOS transistors, and the eleventh to thirteenth transistors are NMOS transistors.

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