Random analog pulse signal generation circuit

Abstract

The invention discloses a random analog pulse signal generation circuit, which is characterized in that the output of an excitation pulse generation module obeying discrete random time distribution is connected to an excitation pulse generation module obeying continuous random time distribution, and the excitation pulse generation module is used for generating square wave pulses of which the time interval of the front edges of two adjacent excitation square waves obeying discrete distribution; the output of the excitation pulse generation module obeying continuous random time distribution is connected to the analog narrow pulse generation module, and the analog narrow pulse generation module is used for converting the generated square-wave pulse into a square-wave excitation pulse of which the leading edge obeys specific distribution; and the analog narrow pulse generation module is used for converting the leading edge of the square wave excitation pulse into a narrow pulse signal so as to generate a signal waveform suitable for a fast detector electronics system test. According to the circuit, the inherent discreteness of digital logic is eliminated while better programmability of the digital logic is kept, so that the finally output pulse waveform signal is closer to the time characteristic of the signal processed by the detector under the real working condition.

Description

Technical Field

[0001] This invention relates to the field of analog signal generation technology, and more particularly to a random analog pulse signal generation circuit. Background Technology

[0002] When testing detector processing electronics systems, a signal source needs to generate a corresponding excitation signal to input the processing electronics system in order to test its performance. However, since most commercial signal sources generate periodic signals, this is somewhat different from the actual operating conditions of the corresponding detector electronics system. This may prevent the detection of some potential problems of the corresponding electronics system under real signal conditions.

[0003] Currently, some commercial signal generating instruments can achieve the function of quasi-random signals through pre-programming or digital logic sampling, thereby simulating the time characteristics of real signals to a certain extent. However, since such functions are implemented through digital logic, due to the inherent characteristics of digital logic, the time interval between two adjacent signals must be an integer multiple of a certain minimum clock cycle. If the time interval between adjacent signals output by such instruments is statistically analyzed and a histogram is plotted, the statistical distribution can better follow the sampling distribution when the granularity of the time axis of the histogram is large compared to the minimum clock cycle. However, when the time granularity is reduced to less than the clock cycle, there will inevitably be gaps in the histogram. The existence of these gaps due to the minimum counting cycle will cause the time characteristics of the random signals generated digitally to differ from those of the signals received by the real detector, thus failing to accurately simulate the time characteristics of real signals.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] The purpose of this invention is to provide a random analog pulse signal generation circuit to solve the aforementioned technical problems existing in the prior art. The circuit of this invention, while retaining the good programmability of digital logic, eliminates the inherent discreteness of digital logic, making the final output pulse waveform signal closer to the time characteristics of the signal processed by the detector under real operating conditions.

[0006] The objective of this invention is achieved through the following technical solution: A random analog pulse signal generation circuit includes an excitation pulse generation module that follows a discrete random time distribution, an excitation pulse generation module that follows a continuous random time distribution, and an analog narrow pulse generation module, wherein: The output of the excitation pulse generation module that follows a discrete random time distribution is connected to the excitation pulse generation module that follows a continuous random time distribution. The excitation pulse generation module that follows a discrete random time distribution is used to generate square wave pulses whose time interval between the leading edges of two adjacent excitation square waves follows a discrete distribution. The output of the excitation pulse generation module that follows a continuous random time distribution is connected to the analog narrow pulse generation module. This excitation pulse generation module that follows a continuous random time distribution is used to convert the generated square wave pulse into a square wave excitation pulse whose leading edge follows a specific distribution. The analog narrow pulse generation module is used to convert the leading edge of the square wave excitation pulse output by the excitation pulse generation module that follows a continuous random time distribution into a narrow pulse signal, thereby generating a signal waveform suitable for testing fast detector electronics systems.

[0007] Compared with the prior art, the circuit described in this invention retains the good programmability of digital logic while eliminating the inherent discreteness of digital logic, making the final output pulse waveform signal closer to the time characteristics of the detector processing signals under real working conditions. It has certain practical value in long-term stability testing of devices such as TDC or electronic detector modules. Attached Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 A schematic diagram of the random analog pulse signal generation circuit is provided for embodiments of the present invention; Figure 2 This is a schematic diagram of the internal structure of the excitation pulse generation module that follows a continuous random time distribution, as described in an embodiment of the present invention. Figure 3 This is a schematic diagram of a specific implementation of the random analog pulse signal generation circuit described in an embodiment of the present invention; Figure 4 This is a histogram showing the distribution of approximately 100,000 adjacent pulse intervals in an embodiment of the present invention. Detailed Implementation

[0010] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them, and do not constitute a limitation on the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the protection scope of the present invention.

[0011] The technical solution provided by this invention will be described in detail below. Contents not described in detail in the embodiments of this invention are prior art known to those skilled in the art. Where specific conditions are not specified in the embodiments of this invention, they shall be performed according to conventional conditions in the art or conditions recommended by the manufacturer. Reagents or instruments used in the embodiments of this invention whose manufacturers are not specified are all conventional products that can be purchased commercially.

[0012] like Figure 1 The diagram shown is a schematic representation of a random analog pulse signal generation circuit provided in an embodiment of the present invention. The circuit includes an excitation pulse generation module that follows a discrete random time distribution, an excitation pulse generation module that follows a continuous random time distribution, and an analog narrow pulse generation module, wherein: The output of the excitation pulse generation module that follows a discrete random time distribution is connected to the excitation pulse generation module that follows a continuous random time distribution. The excitation pulse generation module that follows a discrete random time distribution is used to generate square wave pulses whose time interval between the leading edges of two adjacent excitation square waves follows a discrete distribution. The output of the excitation pulse generation module that follows a continuous random time distribution is connected to the analog narrow pulse generation module. This excitation pulse generation module that follows a continuous random time distribution is used to convert the generated square wave pulse into a square wave excitation pulse whose leading edge follows a specific distribution. The analog narrow pulse generation module is used to convert the leading edge of the square wave excitation pulse output by the excitation pulse generation module that follows a continuous random time distribution into a narrow pulse signal, thereby generating a signal waveform suitable for testing fast detector electronics systems.

[0013] In specific implementation, the excitation pulse generation module that follows a discrete random time distribution generates square wave excitation pulses that follow a expected discrete distribution through digital logic sampling. This is achieved using a Monte Carlo sampling algorithm implemented with a programmable gate array (FPGA). The specific process is as follows: S1, the continuous cumulative distribution function Discretizing into n parts yields the discrete cumulative function: Let k represent the k-th segment after discretization. Specifically, assuming the domain of F(x) is [a, b], the independent variable is discretized into n parts, that is, [a, b] is divided into n equal segments, each segment having a length of (ba) / n. Then, Fdes(k) = F(k(ba) / n). Furthermore, assume a continuous cumulative distribution function... The corresponding probability density function is The corresponding discretized density distribution function is ; In this embodiment, it is designed according to an exponential distribution, i.e., a continuous distribution. Discrete distribution Continuous density Discrete density ,in For count rate , The counter clock cycle; S2, will The function value at each point is multiplied by a scaling factor used to expand the sample space. Round down and store in a lookup table. In the context of the lookup table, the addresses are set from 1 to n, corresponding to the continuous cumulative distribution function. Each value of the distribution function after discretization; In this embodiment, , ; S3. Use a Fibonacci shift feedback register to generate m bits in the range of 1 to 2. A random number R that is uniformly distributed between them; S4. Determine the address of the random number R in the lookup table. If: ; Then k will be passed to the counter module; S5. The counter module counts from 0 to k, then generates a single-cycle square wave pulse output. The clock period of the counter module is... For example, setting the counter clock cycle. ; Steps S3, S4, and S5 can run in parallel, and the corresponding data is buffered using a First-in-First-out (FIFO) stack. Ultimately, the leading edge of the output single-cycle square wave pulse satisfies a discretized distribution. .

[0014] like Figure 2The diagram shown is an internal structure diagram of the excitation pulse generation module that follows a continuous random time distribution according to an embodiment of the present invention. This excitation pulse generation module includes a broadening sub-circuit, an exponential waveform shaping sub-circuit, a threshold level generation circuit, and a compare-latch circuit, wherein: The input of the widening sub-circuit is connected to the output of the excitation pulse generation module that follows a discrete random time distribution, while its output is connected to the exponential wave shaping sub-circuit. This widening sub-circuit is used to widen a square wave pulse signal with a pulse width of a single clock cycle into a square wave pulse signal of a specific length. The output of the exponential wave shaping sub-circuit is connected to one of the inputs of the comparator-latch circuit. The exponential wave shaping sub-circuit is used to shape the input square wave pulse signal into an exponential wave signal with the same pulse width as the widened square wave pulse signal. The output of the threshold level generation circuit is connected to another input of the comparator-latch circuit. This threshold level generation circuit is used to generate the threshold voltage at the inverting input of the comparator in the comparator-latch circuit. The compare-latch circuit is used to lock the first threshold crossing moment and reset to achieve the output of a square wave pulse signal, the pulse width of which is... It follows a specific continuous distribution.

[0015] The goal of the stretching subcircuit is to stretch a single-cycle square wave pulse signal to a length of [length missing]. The square wave pulse signal; first It cannot be too narrow. Need to At least broadened to width, The width parameter is used to ensure that the excitation pulse, which follows a discrete distribution, is applied near its leading edge time. Within a given time frame, there is a probability equal to (or very close to) 1 that at least one excitation pulse will be generated; simultaneously However, the pulse width cannot be too wide, as this will prolong the dead time of the circuit, thereby reducing the maximum repetition frequency. A comprehensive consideration is needed in practical design. In specific implementations, this pulse width extension circuit can be implemented using digital logic to simplify circuit design, and the pulse width can be set to... , This is the clock cycle of the counter module.

[0016] In the stretched sub-circuit, the stretched width parameter The distribution parameters introduced for the excitation pulse generation module that conforms to a continuous random time distribution are, specifically: The widening sub-circuit widens the narrow-width square wave pulse signal output by the excitation pulse generation module, which follows a discrete random time distribution, to at least [a certain value]. A square wave pulse signal with a pulse width of [missing information], and That is, the standard deviation of the normal distribution, and The following conditions must be met: ; This is the clock cycle of the counter module. In this example, it is set to... .

[0017] The goal of the exponential wave shaping sub-circuit is to shape the broadened square wave pulse signal into an exponential wave of equal width, which is achieved through an RC charging circuit. The output waveform of this RC charging circuit satisfies that the rising edge is an exponential wave, and this is achieved by selecting an appropriate exponential wave amplitude. With charging time This ensures that the pulse width of the excitation square wave output by the subsequent compare-latch circuit conforms to (or is close to) its specified value. The normal distribution This is the clock cycle of the counter module. In this embodiment, it is set... , .

[0018] The threshold level generation circuit consists of a noise source and a digital-to-analog converter (DAC), with the noise source used to generate noise voltage. The noise voltage is amplified by a noise diode; DAC output constant level The noise voltage output by the noise source is superimposed on the constant level output by the DAC through transformer coupling. The resulting threshold level Represented as: ; The noise source produces low-pass white noise, which can be controlled by selecting an appropriate bandwidth. Super noise ratio And the spectral shape causes the excitation square wave pulse width of the output of the subsequent compare-latch circuit to conform to (or approximately conform to) the specified frequency. The normal distribution This is the clock cycle of the counter module.

[0019] In this embodiment, , The spectral shape is close to that of ideal low-pass white noise.

[0020] In addition, the comparator-latch circuit consists of a comparator, a D flip-flop, and a delay chip, wherein: The inverting input of the comparator is connected to the threshold level output of the threshold level generation circuit. ; The exponential wave is input to the non-inverting input of the comparator and output as an exponential wave by the sub-circuit. The comparator's output is fed into the clock port of the subsequent D flip-flop. The input of the D flip-flop is fixed at logic "1", which locks the first transition from logic "0" to logic "1" in the comparator output. The delay chip is used to adjust the reset signal of the D flip-flop. The reset signal is provided by the external FPGA module. The delay chip adjusts the reset signal to be pulled low in time before the exponential wave arrives to enable the D flip-flop; and pulled high in time after the exponential wave ends to reset the D flip-flop.

[0021] In a specific implementation, the analog narrow pulse generation module converts the single-ended square wave pulse signal output from the previous stage into a differential signal, and uses the differential signal as two inverted single-ended signals. Two inverted single-ended signals are input to the two input ports of a high-speed NOR gate, and the two single-ended signals are not precisely inverted by controlling the trace length. When a square wave excitation signal is input, the logic gate will generate a high-speed narrow pulse with a pulse width in the sub-ns range due to race conditions and hazards. This will convert the leading edge of the square wave excitation pulse into a narrow pulse signal for subsequent testing of the fast detector electronics system.

[0022] like Figure 3 The diagram shown is a specific implementation schematic of the random analog pulse signal generation circuit according to an embodiment of the present invention. Figure 3 The circuit shown outputs a narrow pulse signal, and the time interval between adjacent pulse signals is counted, such as... Figure 4 The figure shown is a histogram of the distribution of approximately 100,000 adjacent pulse intervals in an embodiment of the present invention. It can be observed that this statistic basically follows a continuous distribution. It more closely approximates the time characteristics of real detector signals.

[0023] In summary, compared with existing time-random pulse signal generation techniques, the embodiments of the present invention, by introducing simulated randomness, generate random signals whose temporal characteristics are closer to those of signals processed by detector electronics systems in real environments. This makes the signals more suitable as test signal sources for fast detector processing electronics systems and has practical value in the stability testing of electronics systems.

[0024] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims. The information disclosed in the background section is intended only to enhance the understanding of the overall background technology of the present invention and should not be construed as an admission or implication in any way that such information constitutes prior art known to those skilled in the art.

Claims

1. A random analog pulse signal generation circuit, characterized in that, The circuit includes an excitation pulse generation module that follows a discrete random time distribution, an excitation pulse generation module that follows a continuous random time distribution, and an analog narrow pulse generation module, wherein: The output of the excitation pulse generation module that follows a discrete random time distribution is connected to the excitation pulse generation module that follows a continuous random time distribution. The excitation pulse generation module that follows a discrete random time distribution is used to generate square wave pulses whose time interval between the leading edges of two adjacent excitation square waves follows a discrete distribution. The output of the excitation pulse generation module that follows a continuous random time distribution is connected to the analog narrow pulse generation module. This excitation pulse generation module that follows a continuous random time distribution is used to convert the generated square wave pulse into a square wave excitation pulse whose leading edge follows a specific distribution. The analog narrow pulse generation module is used to convert the leading edge of the square wave excitation pulse output by the excitation pulse generation module that follows a continuous random time distribution into a narrow pulse signal, thereby generating a signal waveform suitable for testing fast detector electronics systems.

2. The random analog pulse signal generation circuit according to claim 1, characterized in that, The excitation pulse generation module that follows a discrete random time distribution specifically generates square wave excitation pulses that follow a expected discrete distribution through digital logic sampling. This is achieved using a Monte Carlo sampling algorithm implemented with a programmable gate array (FPGA). The specific process is as follows: S1, the continuous cumulative distribution function Discretizing into n parts yields the discrete cumulative function: Let k represent the k-th segment after discretization; further, assume a continuous cumulative distribution function. The corresponding probability density function is The corresponding discretized density distribution function is ; S2, will The function value at each point is multiplied by a scaling factor used to expand the sample space. Round down and store in a lookup table. In the context of the lookup table, the addresses are set from 1 to n, corresponding to the continuous cumulative distribution function. Each value of the distribution function after discretization; S3. Use a Fibonacci shift feedback register to generate m bits in the range of 1 to 2. A random number R that is uniformly distributed between them; S4. Determine the address of the random number R in the lookup table. If: ； Then k will be passed to the counter module; S5. The counter module counts from 0 to k, then generates a single-cycle square wave pulse output. The clock period of the counter module is... ; Steps S3, S4, and S5 can run in parallel, and the corresponding data is buffered using a first-in-first-out (FIFO) stack. Ultimately, the leading edge of the output single-cycle square wave pulse satisfies a discretized distribution. .

3. The random analog pulse signal generation circuit according to claim 1, characterized in that, The excitation pulse generation module, which follows a continuous random time distribution, includes a broadening sub-circuit, an exponential waveform shaping sub-circuit, a threshold level generation circuit, and a compare-latch circuit, wherein: The input of the widening sub-circuit is connected to the output of the excitation pulse generation module that follows a discrete random time distribution, while its output is connected to the exponential wave shaping sub-circuit. This widening sub-circuit is used to widen a square wave pulse signal with a pulse width of a single clock cycle into a square wave pulse signal of a specific length. The output of the exponential wave shaping sub-circuit is connected to one of the inputs of the comparator-latch circuit. The exponential wave shaping sub-circuit is used to shape the input square wave pulse signal into an exponential wave signal with the same pulse width as the widened square wave pulse signal. The output of the threshold level generation circuit is connected to another input of the comparator-latch circuit. This threshold level generation circuit is used to generate the threshold voltage at the inverting input of the comparator in the comparator-latch circuit. The compare-latch circuit is used to lock the first threshold crossing moment and reset to achieve the output of a square wave pulse signal, the pulse width of which is... It follows a specific continuous distribution.

4. The random analog pulse signal generation circuit according to claim 3, characterized in that, The goal of the stretching subcircuit is to stretch a single-cycle square wave pulse signal to a length of [length missing]. Square wave pulse signal; Need to At least broadened to width, The width parameter is used to ensure that the excitation pulse, which follows a discrete distribution, is applied near its leading edge time. Within a given time frame, there is a probability equal to 1 that at least one excitation pulse will be generated.

5. The random analog pulse signal generation circuit according to claim 4, characterized in that, In the stretched sub-circuit, the stretched width parameter The distribution parameters introduced for the excitation pulse generation module that conforms to a continuous random time distribution are, specifically: The widening sub-circuit widens the narrow-width square wave pulse signal output by the excitation pulse generation module, which follows a discrete random time distribution, to at least [a certain value]. A square wave pulse signal with a pulse width of [missing information], and That is, the standard deviation of the normal distribution, and The following conditions must be met: ； This is the clock cycle of the counter module.

6. The random analog pulse signal generation circuit according to claim 3, characterized in that, The goal of the exponential wave shaping sub-circuit is to shape the broadened square wave pulse signal into an exponential wave of equal width, which is achieved through an RC charging circuit. The output waveform of this RC charging circuit satisfies that the rising edge is an exponential wave, and this is achieved by selecting an appropriate exponential wave amplitude. With charging time This ensures that the pulse width of the excitation square wave output by the subsequent compare-latch circuit conforms to... The normal distribution This is the clock cycle of the counter module.

7. The random analog pulse signal generation circuit according to claim 3, characterized in that, The threshold level generation circuit consists of a noise source and a digital-to-analog converter (DAC), with the noise source used to generate noise voltage. The noise voltage is amplified by a noise diode; DAC output constant level The noise voltage output by the noise source is superimposed on the constant level output by the DAC through transformer coupling. The resulting threshold level Represented as: ； The noise source produces low-pass white noise, which can be controlled by selecting an appropriate bandwidth. Super noise ratio And the spectral shape causes the excitation square wave pulse width of the output of the subsequent compare-latch circuit to conform to... The normal distribution This is the clock cycle of the counter module.

8. The random analog pulse signal generation circuit according to claim 3, characterized in that, The compare-latch circuit consists of a comparator, a D flip-flop, and a delay chip, wherein: The inverting input of the comparator is connected to the threshold level output of the threshold level generation circuit. ; The exponential wave is input to the non-inverting input of the comparator and output as an exponential wave by the sub-circuit. The comparator's output is fed into the clock port of the subsequent D flip-flop. The input of the D flip-flop is fixed at logic "1", which locks the first transition from logic "0" to logic "1" in the comparator output. The delay chip is used to adjust the reset signal of the D flip-flop. The reset signal is provided by the external FPGA module. The delay chip adjusts the reset signal to be pulled low in time before the exponential wave arrives to enable the D flip-flop; and pulled high in time after the exponential wave ends to reset the D flip-flop.

9. The random analog pulse signal generation circuit according to claim 1, characterized in that, Specifically, the analog narrow pulse generation module converts the single-ended square wave pulse signal output from the previous stage into a differential signal, and uses the differential signal as two inverted single-ended signals. Two inverted single-ended signals are input to the two input ports of a high-speed NOR gate, and the two single-ended signals are not precisely inverted by controlling the trace length. When a square wave excitation signal is input, the logic gate will generate a high-speed narrow pulse with a pulse width in the sub-ns range due to race conditions and hazards. This will convert the leading edge of the square wave excitation pulse into a narrow pulse signal for subsequent testing of the fast detector electronics system.

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