A silicon wafer, cell and photovoltaic module

Abstract

The application discloses a silicon wafer, a battery wafer and a photovoltaic module, relates to the technical field of silicon wafer manufacturing, and aims to solve the problem that the silicon wafer is easy to break. The silicon wafer has two opposite surfaces and four side surfaces between the two surfaces; two adjacent side surfaces are connected through a chamfer; the silicon wafer contains antimony; the content of the antimony in the chamfer is 3E+13 atoms / cm 3 1E+16 atoms / cm 3 2, and the roughness Ra of the chamfer is 0.03 microns-0.5 microns.

Description

Technical Field

[0001] This invention relates to the field of silicon wafer technology, and more particularly to a silicon wafer, a solar cell, and a photovoltaic module. Background Technology

[0002] In the photovoltaic manufacturing industry chain, silicon wafers are a core basic material, and their production quality and processing efficiency directly affect the performance and cost of cells and modules. With the development of silicon wafer thinning, their mechanical stress sensitivity in cutting, transporting, cleaning and subsequent processes has increased significantly, leading to an increasingly prominent problem of silicon wafer breakage rate during production.

[0003] Therefore, how to solve the problem of high silicon wafer breakage rate has become an urgent issue for those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a silicon wafer, a solar cell, and a photovoltaic module that reduces the breakage rate.

[0005] In a first aspect, the present invention provides a silicon wafer having two opposing surfaces and four side surfaces located between the two surfaces; adjacent side surfaces are connected by chamfers; the silicon wafer contains antimony, and the antimony content of the chamfers is 3E+13 atoms / cm³. 3 ~1E+16 atoms / cm 3 The roughness Ra of the chamfer is 0.03μm~0.5μm.

[0006] Using the above technical solution, this application controls the antimony content in the chamfer of the silicon wafer to be 3E+13 atoms / cm during the silicon wafer fabrication process. 3 ~1E+16 atoms / cm 3 Simultaneously, setting the roughness Ra of the silicon wafer chamfer to 0.03μm~0.5μm can effectively reduce the silicon wafer breakage rate. On one hand, the chamfer contains antimony, which uses antimony atoms to anchor dislocations and defects in silicon, preventing their movement and thus increasing the mechanical strength of the silicon wafer chamfer. Improving the mechanical strength of the chamfer reduces the breakage rate. If the antimony content at the chamfer is less than 3E+13 atoms / cm², the breakage rate can be reduced. 3 When the antimony content is too low, the mechanical strength at the chamfer is insufficient, and the fragmentation rate is relatively high; however, when the antimony content is greater than 1E+16 atoms / cm 3When antimony atoms have large radii, while increasing mechanical strength, they can easily create stress concentration zones at the chamfer, leading to an increased breakage rate. On the other hand, when the chamfer roughness is between 0.03 μm and 0.5 μm, the stress concentration caused by antimony can be effectively alleviated, thus effectively reducing the breakage rate. When the chamfer roughness Ra is greater than 0.5 μm, the stress concentration of antimony at the chamfer is not effectively alleviated, resulting in excessive contact stress and increasing the breakage rate of the silicon wafer during subsequent transport. When the chamfer roughness Ra is less than 0.03 μm, although the stress concentration of antimony is effectively alleviated, the processing time for chamfering increases significantly. The excessively long processing time introduces greater processing stress into the chamfer, increasing the probability of microcracks at the silicon wafer chamfer and also increasing the breakage rate.

[0007] In some possible implementations, the antimony content of the chamfer is 7E+13 atoms / cm². 3 ~5E+15 atoms / cm 3 .

[0008] In some possible implementations, the roughness Ra of the chamfer is 0.1 μm to 0.4 μm.

[0009] In some possible implementations, the silicon wafer has two opposing first edges and two opposing second edges, the length of the first edges being greater than the length of the second edges, one of the first edges having a chamfer between itself and the two adjacent second edges being a first chamfer, and the other first edge having a chamfer between itself and the two adjacent second edges being a second chamfer; the roughness Ra of the first chamfer is less than the roughness Ra of the second chamfer, and the difference between the roughness Ra of the first chamfer and the roughness Ra of the second chamfer is greater than 0.03 μm.

[0010] With the above technical solution, since the length of the first side of the silicon wafer is greater than the length of the second side, the roughness of the two first chamfers adjacent to one of the first sides is the same. When the silicon wafer is cleaned, the first side is perpendicular to the direction of silicon wafer travel, and setting the roughness of the two chamfers adjacent to the same first side is the same, which can ensure that the cleaning effect along the first side is consistent. Since the second side is parallel to the direction of silicon wafer travel during cleaning, the difference between the roughness Ra of the first chamfer and the roughness Ra of the second chamfer along the direction of the second side is greater than 0.03μm. During the cleaning process along the silicon wafer, the first chamfer with relatively smaller roughness is in front, which reduces the initial resistance of the cleaning liquid adhering to the silicon wafer, so that the cleaning liquid can uniformly form a stable and continuous liquid film on the first chamfer, reducing the probability of contaminant residue. The roughness of the second chamfer is relatively large, which can increase the scouring of the second chamfer behind by the cleaning liquid, reduce the accumulation of contaminants in the second chamfer, and ensure the cleaning effect of the silicon wafer.

[0011] In some possible implementations, the roughness Ra of the first chamfer is 0.03 μm to 0.2 μm; and / or, the roughness Ra of the second chamfer is 0.09 μm to 0.5 μm.

[0012] In some possible implementations, the difference between the roughness Ra of the chamfer and the roughness Ra of the side surface is less than 0.5 μm. When the difference in roughness between the side surface and the chamfer of the silicon wafer is greater than 0.5 μm, in the initial stage of slicing, the cutting line simultaneously contacts the side surface and the chamfer. Due to the excessive difference in roughness between the side surface and the chamfer, the force on the cutting line is uneven during slicing, which increases the probability of fragmentation during slicing.

[0013] In some possible implementations, the surface roughness Ra is 0.01 μm to 0.4 μm.

[0014] When the surface roughness Ra of the silicon wafer is greater than 0.4 μm, the excessive surface roughness will affect the passivation effect of the side of the solar cell and thus affect the cell efficiency. When the surface roughness Ra is less than 0.01 μm, the silicon wafer is prone to sliding in the quartz boat during cell fabrication due to smooth contact, which will affect the stability of the process.

[0015] In some possible implementations, the silicon wafer has two opposing first sides and two opposing second sides, the length of the first side being greater than the length of the second side; wherein the difference between the roughness Ra of one side containing the first side and the roughness Ra of the other side containing the first side is greater than 0.01 μm.

[0016] In some possible implementations, the roughness Ra at the middle position of the side containing the first side is less than the roughness Ra at both ends of the side containing the first side along its length. Thus, during silicon wafer dicing, since the shorter second side contacts the wafer holder, setting different roughness levels on the side containing the first side ensures that the cutting fluid flows from the side with higher roughness to the side with lower roughness along the direction of the second side (i.e., the direction where the arc length on the silicon wafer first increases and then decreases). The side with higher roughness ensures that more cutting fluid is carried onto the cutting line, thereby cooling the cutting line; while the side with lower roughness ensures that the cutting fluid travels a longer path on the cutting line, thus ensuring that cutting fluid also cools the cutting line in the middle region of the cut, reducing the probability of silicon wafers sticking together during the thinning process.

[0017] In some possible implementations, the surface roughness Ra at the middle position of the side containing the first edge is 0.01 μm to 0.2 μm; the surface roughness Ra at both ends of the side containing the first edge is 0.02 μm to 0.15 μm. Within the above range, the surface roughness at the middle and both ends of the side containing the first edge is different, which can reduce the silicon wafer breakage rate while improving the silicon wafer processing efficiency.

[0018] In some possible implementations, the silicon wafer has two opposing first sides and two opposing second sides, with the length of the first side being greater than the length of the second side; the ratio of the length of the first side to the length of the second side is 1.2 to 6. Because the length ratio of the first side to the second side of the silicon wafer is between 1.2 and 6, the utilization rate of silicon rods can be effectively improved during the silicon wafer manufacturing process; and given a fixed module layout, the space of the container can be fully utilized.

[0019] In some possible implementations, the length of the first side is 182mm~300mm, and the length of the second side is 83mm~150mm. Silicon wafers of this size do not require laser scribing during cell fabrication, improving edge passivation and increasing photoelectric conversion efficiency. This design is suitable for various cell sizes and photovoltaic module designs.

[0020] In some possible implementations, the projected length of the chamfer is 1mm to 5mm. When the projected length of the chamfer is within this range, a smaller chamfer can be obtained to improve the utilization rate of the silicon rod, without being too small and reducing the breakage rate of the chamfer.

[0021] Secondly, the present invention also provides a solar cell prepared from the silicon wafer described in any of the preceding claims. Since the solar cell is prepared from the silicon wafer of the first aspect, it has the same beneficial effects as the first aspect, and will not be described again.

[0022] Thirdly, the present invention also provides a photovoltaic module, comprising at least two solar cells and at least one conductive interconnect, wherein the conductive interconnect is connected between two adjacent solar cells, and the solar cells are as described above. Since the photovoltaic module includes the solar cells of the second aspect, it has the same beneficial effects as the first and second aspects, and will not be described again. Attached Figure Description

[0023] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of a silicon wafer provided in an embodiment of the present invention.

[0024] The attached diagram uses the following labels: 1 for the first side, 2 for the second side, 3 for the first chamfer, 4 for the second chamfer, 5 for the surface, 6 for the side surface, and 7 for the chamfer. Detailed Implementation

[0025] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0026] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0027] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0028] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0030] It should be noted that the roughness of the silicon wafer chamfer and side surface in this application is detected by atomic force microscopy (AFM); when detecting the roughness of the silicon wafer chamfer, the scanning area is 50μm×50μm; when detecting the roughness of the silicon wafer side surface, the scanning area is 50μm×50μm; the arithmetic mean roughness in the detection results corresponds to Ra in this application.

[0031] The antimony content in this application can be obtained using secondary ion mass spectrometry (SIMS), or by ICP-MS, GDMS, etc. If ICP-MS is used, due to the small area of ​​the chamfer, to avoid detection errors caused by insufficient sample weight, three or all chamfers within a 30mm × 30mm area of ​​the silicon wafer can be sampled for ICP-MS dissolution to obtain the antimony content of the chamfers. Alternatively, the aerosol generated after laser ablation of the chamfers can be analyzed by ICP-MS to obtain the antimony content of each chamfer.

[0032] like Figure 1 As shown, this embodiment of the invention provides a silicon wafer having two opposing surfaces 5 and four side surfaces 6 located between the two surfaces 5; adjacent side surfaces 6 are connected by chamfers 7; the silicon wafer contains antimony, and the antimony content of each chamfer 7 is 3E+13 atoms / cm³. 3 ~1E+16 atoms / cm 3 The roughness Ra of each chamfer 7 is 0.03μm~0.5μm.

[0033] In this application, the antimony content of the chamfer 7 of the silicon wafer is controlled at 3E+13atoms / cm3~1E+16atoms / cm3 during the silicon wafer preparation process, and the roughness Ra of the chamfer 7 of the silicon wafer is set at 0.03μm~0.5μm, which can effectively reduce the fragmentation rate of the silicon wafer.

[0034] For example, the antimony content of each chamfer 7 can specifically be 3E+13 atoms / cm³. 3 4E+13atoms / cm 3 5E+13 atoms / cm 3 6E+13atoms / cm 3 7E+13 atoms / cm 3 8E+13atoms / cm 3 9E+13atoms / cm 3 1E+14 atoms / cm 3 2E+14 atoms / cm 3 3E+14 atoms / cm 3 4E+14atoms / cm3 5E+14 atoms / cm 3 6E+14 atoms / cm 3 7E+14 atoms / cm 3 8E+14 atoms / cm 3 9E+14 atoms / cm 3 1E+15 atoms / cm 3 2E+15 atoms / cm 3 3E+15 atoms / cm 3 4E+15 atoms / cm 3 5E+15 atoms / cm 3 1E+16 atoms / cm 3 wait.

[0035] For example, the roughness Ra of each chamfer 7 can be 0.03μm, 0.05μm, 0.08μm, 0.1μm, 0.11μm, 0.14μm, 0.17μm, 0.2μm, 0.22μm, 0.24μm, 0.26μm, 0.28μm, 0.3μm, 0.32μm, 0.34μm, 0.36μm, 0.38μm, 0.4μm, 0.42μm, 0.44μm, 0.46μm, 0.48μm, or 0.5μm.

[0036] This application reduces the breakage rate by controlling the antimony content and roughness of the chamfer 7 of the silicon wafer. On one hand, the presence of antimony at chamfer 7 utilizes antimony atoms to anchor dislocations and defects in silicon, preventing their movement and thus increasing the mechanical strength of the chamfer 7. Improving the mechanical strength of the chamfer 7 reduces the breakage rate. If the antimony content at chamfer 7 is less than 3E+13 atoms / cm², the breakage rate can be reduced. 3 When the antimony content is too low, the mechanical strength at chamfer 7 is insufficient, and the fragmentation rate is relatively high; however, when the antimony content is greater than 1E+16 atoms / cm 3When antimony atoms have large radii, while increasing mechanical strength, they easily form stress concentration zones at the chamfer, leading to an increased breakage rate. On the other hand, when the roughness of chamfer 7 is between 0.03μm and 0.5μm, the stress concentration caused by antimony can be effectively alleviated, thus effectively reducing the breakage rate. When the roughness Ra of chamfer 7 is greater than 0.5μm, the stress concentration of antimony at chamfer 7 is not effectively alleviated, resulting in excessive contact stress at chamfer 7 and increasing the breakage rate of the silicon wafer during subsequent transport. When the roughness Ra of chamfer 7 is less than 0.03μm, although the stress concentration of antimony is effectively alleviated, the processing time required for chamfer 7 increases significantly. The excessively long processing time introduces large processing stress into chamfer 7, increasing the probability of microcracks at the chamfer 7 of the silicon wafer, which also increases the breakage rate.

[0037] Furthermore, in this embodiment, the antimony content of each chamfer 7 is 7E+13 atoms / cm³. 3 ~5E+15 atoms / cm 3 Specifically, it can be 7E+13 atoms / cm. 3 8E+13atoms / cm 3 9E+13atoms / cm 3 1E+14 atoms / cm 3 2E+14 atoms / cm 3 3E+14 atoms / cm 3 4E+14atoms / cm 3 5E+14 atoms / cm 3 6E+14 atoms / cm 3 7E+14 atoms / cm 3 8E+14 atoms / cm 3 9E+14 atoms / cm 3 1E+15 atoms / cm 3 2E+15 atoms / cm 3 3E+15 atoms / cm 3 4E+15 atoms / cm 3 5E+15 atoms / cm 3 .

[0038] Furthermore, in this embodiment, the roughness Ra of each chamfer 7 is 0.1μm to 0.4μm. Specifically, it can be 0.1μm, 0.11μm, 0.14μm, 0.17μm, 0.2μm, 0.22μm, 0.24μm, 0.26μm, 0.28μm, 0.3μm, 0.32μm, 0.34μm, 0.36μm, 0.38μm, or 0.4μm.

[0039] like Figure 1 As shown, in some embodiments, the silicon wafer has two opposing first edges 1 and two opposing second edges 2, the length of the first edge 1 is greater than the length of the second edge 2, one of the first edges 1 and the two adjacent second edges 2 have a chamfer 7 between them, which is a first chamfer 3, and the other first edge 1 and the two adjacent second edges 2 have a chamfer 7 between them, which is a second chamfer 4; the roughness Ra of the first chamfer 3 is less than the roughness Ra of the second chamfer 4, and the difference between the roughness Ra of the first chamfer 3 and the roughness Ra of the second chamfer 4 is greater than 0.03 μm.

[0040] Since the length of the first side 1 of the silicon wafer in this application is greater than the length of the second side 2, the roughness of the two first chamfers 3 adjacent to one of the first sides 1 is the same. When the silicon wafer is cleaned, the first side 1 is perpendicular to the direction of silicon wafer travel. Setting the roughness of the two chamfers 7 adjacent to the same first side 1 is the same, which can ensure that the cleaning effect along the first side 1 is consistent. Since the second side 2 is parallel to the direction of silicon wafer travel during cleaning, the difference between the roughness Ra of the first chamfer 3 and the roughness Ra of the second chamfer 4 along the direction of the second side 2 is greater than 0.03μm. During the silicon wafer cleaning process, the first chamfer 3 with relatively smaller roughness is in front, which reduces the initial resistance of the cleaning liquid adhering to the silicon wafer. This allows the cleaning liquid to form a stable and continuous liquid film uniformly on the first chamfer 3, reducing the probability of contaminant residue. The roughness of the second chamfer 4 is relatively large, which can increase the scouring of the second chamfer 4 behind by the cleaning liquid, reduce the accumulation of contaminants in the second chamfer, and ensure the cleaning effect of the silicon wafer.

[0041] For example, the difference between the roughness Ra of the first chamfer 3 and the roughness Ra of the second chamfer 4 can be 0.03μm, 0.05μm, 0.07μm, 0.09μm, 0.11μm, 0.13μm, 0.15μm, 0.2μm, etc.

[0042] Specifically, the roughness Ra of the first chamfer 3 is 0.03μm~0.2μm, specifically 0.03μm, 0.05μm, 0.07μm, 0.09μm, 0.11μm, 0.13μm, 0.15μm, 0.2μm, etc. and / or, the roughness Ra of the second chamfer 4 is 0.09μm~0.5μm, specifically 0.09μm, 0.13μm, 0.18μm, 0.22μm, 0.26μm, 0.31μm, 0.36μm, 0.4μm, 0.45μm, 0.5μm, etc.

[0043] In some embodiments, the difference between the roughness Ra of the chamfer 7 and the roughness Ra of the side surface 6 is less than 0.5 μm. When the difference between the roughness Ra of the side surface 6 and the chamfer 7 is greater than 0.5 μm, in the initial stage of slicing, the cutting line contacts both the side surface 6 and the chamfer 7 simultaneously. When the roughness difference between the side surface 6 and the chamfer 7 is too large, the force on the cutting line is uneven during slicing, which increases the probability of fragmentation during slicing.

[0044] In some embodiments, the roughness Ra of the silicon wafer side surface 6 is 0.01 μm to 0.4 μm. Specifically, it can be 0.01 μm, 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.06 μm, 0.07 μm, 0.08 μm, 0.09 μm, 0.1 μm, 0.11 μm, 0.12 μm, 0.13 μm, 0.14 μm, 0.15 μm, 0.2 μm, 0.25 μm, 0.3 μm, 0.36 μm, 0.4 μm, etc.

[0045] In this application, when the roughness Ra of the side surface 6 is greater than 0.4 μm, the excessive roughness Ra of the side surface 6 affects the passivation effect of the side surface 6 of the solar cell prepared by the silicon wafer, thus affecting the cell efficiency; when the roughness Ra of the side surface 6 is less than 0.01 μm, the silicon wafer is prone to sliding in the quartz boat due to smooth contact during cell preparation, thus affecting the stability of the process.

[0046] It should be noted that the surface roughness Ra of chamfer 7 and side surface 6 can be achieved by controlling the grit size of the grinding wheel, the grinding speed, and the number of grinding passes, resulting in chamfer 7 and side surface 6 with different surface roughness Ra. The smaller the grit size of the grinding wheel, the smaller the surface roughness Ra. For example, if the larger first chamfer 3 is achieved using a grinding wheel with a grit size of 800 mesh, while the smaller second chamfer 4 is achieved using a grinding wheel with a grit size of 600 mesh, the surface roughness Ra of the second chamfer 4 will be greater than that of the first chamfer 3.

[0047] In some embodiments, the silicon wafer has two opposing first sides 1 and two opposing second sides 2, the length of the first side 1 being greater than the length of the second side 2; wherein the difference between the roughness Ra of one side 6 containing the first side 1 and the roughness Ra of the other side 6 containing the first side 1 is greater than 0.01 μm.

[0048] By setting the difference in roughness Ra between the two sides 6 containing the opposite first side 1 to be greater than 0.01 μm, during the silicon wafer cutting process, since the shorter second side 2 contacts the crystal holder, setting the roughness on the two sides 6 containing the first side 1 to be different during the cutting process ensures that the cutting line flows from the side 6 with higher roughness to the side 6 with lower roughness along the direction of the second side 2, i.e., the direction in which the arc of the silicon wafer first increases and then decreases. The side with higher roughness ensures that more cutting fluid is carried into the cutting line, thereby cooling the cutting line; while the side with lower roughness ensures that the path of the cutting fluid on the cutting line is longer, thereby ensuring that there is also cutting fluid in the middle area of ​​the cutting to cool the cutting line, reducing the probability of silicon wafers sticking together during the thinning process.

[0049] Furthermore, in this embodiment, the roughness Ra of the middle position of the side 6 containing the longer first side 1 is less than the roughness Ra of the two ends of the side 6 containing the first side 1. By making the roughness Ra of the middle position of the silicon wafer side 6 less than the roughness Ra of the two ends of the side 6, since the middle position of the side 6 accounts for a larger proportion of the side 6, the roughness of the middle position of the side 6 is reduced, which improves the consistency of the film layer in the middle part of the side 6 during the battery fabrication process, thereby improving the photoelectric conversion efficiency of the battery.

[0050] It should be noted that, in this application, the middle position of the side 6 where the first side 1 is located refers to the area on the side 6 where the first side 1 is located, along the direction parallel to the first side 1, where the distance from the first chamfer 3 of the silicon wafer is greater than 10mm; correspondingly, the two ends of the side 6 where the first side 1 is located are the areas on the direction parallel to the first side 1, where the distance from the first chamfer 3 of the silicon wafer is less than 10mm.

[0051] For example, the roughness Ra of the middle position of the side surface 6 where the first side 1 is located is 0.01μm~0.2μm, specifically it can be 0.01μm, 0.02μm, 0.03μm, 0.04μm, 0.05μm, 0.06μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, 0.12μm, 0.15μm, 0.17μm, 0.19μm, 0.2μm, etc. The surface roughness Ra at both ends of the side surface 6 where the first side 1 is located is 0.02μm~0.15μm, specifically 0.02μm, 0.03μm, 0.04μm, 0.05μm, 0.06μm, 0.07μm, 0.08μm, 0.09μm, 0.1μm, 0.11μm, 0.12μm, 0.13μm, 0.14μm, 0.15μm, etc.

[0052] In some embodiments, for a silicon wafer having a longer first side 1 and a shorter second side 2, the ratio of the length of the first side 1 to the length of the second side 2 is 1.2 to 6. This ratio can specifically be 1.2, 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, etc. Because the length ratio of the first side 1 to the second side 2 of the silicon wafer is between 1.2 and 6, the utilization rate of silicon rods can be effectively improved during the silicon wafer manufacturing process; and given a fixed module layout, the space in the container can be fully utilized.

[0053] In some embodiments, the length of the first side 1 is 182mm~300mm, and the length of the second side 2 is 83mm~150mm. Due to the presence of chamfers 7, the length of the first side 1 can be represented by the distance between two opposing second sides 2, i.e., the sum of the length of the first side 1 and the projected lengths of the two first chamfers 3 on the first side 1 is 182mm~300mm, defined as the long side distance. Specific long side distances can be 182mm, 185mm, 190mm, 195mm, 200mm, 205mm, 210mm, 220mm, 230mm, 240mm, 250mm, 270mm, 290mm, 300mm, etc.; the length of the second side 2 is 83mm~150mm. Because of the presence of chamfer 7, the length of the second side 2 can be defined as 83mm~150mm by the distance between the two opposite first sides 1. That is, the sum of the length of the second side 2, the projection length of the first chamfer 3 on the second side 2 and the projection length of the second chamfer 4 on the second side 2 is 83mm~150mm, which is defined as the short side distance. The specific short side distance can be 83mm, 85mm, 90mm, 91mm, 96mm, 100mm, 105mm, 110mm, 115mm, 120mm, 125mm, 135mm, 145mm, 150mm, etc.

[0054] Those skilled in the art choose the first side 1 and the second side 2 within the aforementioned length range. Compared to other side lengths, the silicon rod has a higher utilization rate. At the same time, when using such silicon wafers to prepare modules, the blank area between the cells is small, which can maximize the use of the container size and improve the utilization rate of the container at the module end.

[0055] Silicon wafers of this size eliminate the need for laser scribing during cell fabrication, improving edge passivation and increasing photoelectric conversion efficiency. Suitable for various cell sizes and photovoltaic module designs.

[0056] In some embodiments, the projected length of the first chamfer 3 is greater than the projected length of the second chamfer 4. It should be noted that the projected length of the silicon wafer chamfer 7 refers to the projected length on the first side 1 or the second side 2 of the silicon wafer after the edge or corner of the wafer has been chamfered. The shape of the silicon wafer chamfer 7 can be an arc-shaped chamfer or a linear chamfer. The projected length of the chamfer 7 can be measured by optical measurement, scanning microscopy, or other measurement methods.

[0057] In this application, the projected lengths of the first chamfer 3 and the second chamfer 4 refer to the projections of the first chamfer 3 and the second chamfer 4 onto the first side 1 and / or the second side 2. The projection length of the first chamfer 3 being greater than the projection length of the second chamfer 4 means that the projection length of the first chamfer 3 onto the first side 1 is greater than the projection length of the second chamfer 4 onto the first side 1, and the projection length of the first chamfer 3 onto the second side 2 is greater than the projection length of the second chamfer 4 onto the second side 2.

[0058] With the above technical solution, the size of chamfer 7 is distinguished by the projected length of chamfer 7. Chamfer 7 includes a relatively large first chamfer 3 and a relatively small second chamfer 4. The different sizes of the first chamfer 3 and the second chamfer 4 serve to identify the silicon wafer, making it easy to identify the placement direction of the solar cells made from the silicon wafer, thus assisting in the alignment of the PN regions and the differentiation of positive and negative electrodes among multiple solar cells. For example, when arranging multiple solar cells to form a battery string for a module, if each solar cell is placed in the same direction and aligned sequentially in the order of first chamfer 3, second chamfer 4, first chamfer 3, and second chamfer 4 in a row, the P region of the previous solar cell automatically aligns with the P region or N region of the next solar cell. This facilitates the selection of appropriate conductive interconnects and string bonding processes to produce the battery module. Therefore, there is no need to set additional markings on the silicon wafer or solar cells, eliminating the marking process, saving time, and improving processing efficiency.

[0059] In one specific embodiment, the projected length of the first chamfer 3 is greater than the projected length of the second chamfer 4; the roughness Ra of the first chamfer is 0.03μm~0.2μm.

[0060] With the above technical solution, the larger first chamfer 3 can increase the ratio of the square silicon rod obtained after removing the edge skin to the original round silicon rod, thereby improving the utilization rate of the silicon rod. At the same time, the larger projected length can effectively disperse the stress at the chamfer and reduce the probability of silicon wafer fragmentation. By setting a smaller roughness Ra at the first chamfer 3, it can be ensured that the adhesion of the film layer at the chamfer 7 is increased without affecting the fragmentation rate, thereby improving the photoelectric conversion efficiency of the solar cell prepared from the silicon wafer.

[0061] In some embodiments, the projected length of the chamfer 7 is 1mm to 5mm. For example, the projected length of the chamfer 7 on the first side 1 is 1mm to 5mm, or the projected length of the chamfer 7 on the second side 2 is 1mm to 5mm. Specifically, the projected length of the chamfer 7 can be 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. When the projected length of the chamfer 7 adopts the above range, the utilization rate of the silicon rod can be improved; and the chamfer will not be too small, reducing the breakage rate of the chamfer.

[0062] For example, the projection length of the first chamfer 3 on the first side 1 is 2mm to 5mm, specifically 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. The projection length of the second chamfer 4 on the first side 1 is 1mm to 4mm, specifically 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, etc. It is acceptable as long as the projection length of the first chamfer 3 on the first side 1 is greater than the projection length of the second chamfer 4 on the first side 1.

[0063] Alternatively, the projection length of the first chamfer 3 on the second side 2 can be 2mm to 5mm, specifically 2mm, 2.5mm, 3mm, 3.5mm, 4mm, 4.5mm, 5mm, etc. The projection length of the second chamfer 4 on the second side 2 can be 1mm to 4mm, specifically 1mm, 1.5mm, 2mm, 2.5mm, 3mm, 3.5mm, 4mm, etc. The requirement is that the projection length of the first chamfer 3 on the second side 2 is greater than the projection length of the second chamfer 4 on the second side 2.

[0064] It should be noted that the projected length of the first chamfer 3 on the first side 1 and the projected length of the first chamfer 3 on the second side 2 may be equal or unequal. Similarly, the projected length of the second chamfer 4 on the first side 1 and the projected length of the second chamfer 4 on the second side 2 may be equal or unequal. The only requirement is that the projected length of the first chamfer 3 is greater than the projected length of the second chamfer 4.

[0065] For those skilled in the art, the antimony content at the chamfer 7 of the silicon wafer can be adjusted by controlling the amount of feed during silicon crystal growth to regulate the overall antimony content of the silicon rod, by controlling the furnace pressure and argon flow rate to regulate the volatilization of antimony at the edge of the silicon rod, and by controlling the crystal pulling speed to adjust the shape of the melt at the solid-liquid interface of the molten silicon, thereby achieving the regulation of the antimony content at the edge of the silicon rod. For example, the feed amount during the crystal pulling process is 980 kg, with 15 g of elemental antimony, a furnace pressure of 11 torr, an argon flow rate of 70~120 L / min, and a crystal pulling speed of 80~110 mm / h. After the silicon rod has undergone squaring and slicing, the chamfer 7 area is the original edge region of the silicon rod. Therefore, controlling the Sb content at the edge of the silicon rod is equivalent to controlling the Sb content at the chamfer 7 of the silicon wafer.

[0066] The roughness Ra of the chamfer 7 in this application can be obtained by controlling the grit size of the grinding wheel, the grinding speed, and the number of grinding cycles during the chamfering process to obtain a silicon wafer with the chamfer roughness Ra of this application.

[0067] Based on the silicon wafer described in any of the above embodiments, this invention also provides a battery cell, which is fabricated from the silicon wafer described in any of the above embodiments. For example, the first surface of the battery cell has a first electrode, and the second surface has a second electrode, with the first and second electrodes having opposite polarities, forming a bifacial battery. Alternatively, the first surface of the battery cell simultaneously has a first electrode and a second electrode with opposite polarities, forming a back-contact battery.

[0068] Since the solar cells are made from the silicon wafers described in any of the above embodiments, they have the same beneficial effects as the silicon wafers in the above embodiments, and will not be repeated here.

[0069] To make the objectives, technical solutions, and beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments 1-6 and comparative examples 1-4. However, the specific embodiments described are only used to explain the present invention and are not intended to limit the present invention.

[0070] Example 1 Selected antimony content of 5E+15 atoms / cm 3 10,000 silicon wafers with a chamfer roughness Ra of 0.05 μm were used to record the breakage rate of the silicon wafers during the battery fabrication process, as detailed in Table 1 below.

[0071] Example 2 Unlike Example 1, the chamfered antimony content was 4.5E+14 atoms / cm². 3 The chamfer roughness Ra is 0.08μm.

[0072] Example 3 Unlike Example 1, the chamfered antimony content was 2.6E+14 atoms / cm². 3 The chamfer roughness Ra is 0.1 μm.

[0073] Example 4 Unlike Example 1, the chamfered antimony content was 3.5E+13 atoms / cm. 3 The chamfer roughness Ra is 0.2μm.

[0074] Example 5 Unlike Example 1, the chamfered antimony content is 3.5E+14 atoms / cm². 3 The chamfer roughness Ra is 0.4 μm.

[0075] Example 6 Unlike Example 5, the chamfered antimony content was 5E+15 atoms / cm. 3 .

[0076] Comparative Example 1 Unlike Example 2, the chamfer roughness Ra is 0.01 μm.

[0077] Comparative Example 2 Unlike Comparative Example 1, the chamfer roughness is 0.8 μm.

[0078] Comparative Example 3 Unlike Example 4, the chamfered antimony content was 2.5E+13 atoms / cm². 3 .

[0079] Comparative Example 4 Unlike Comparative Example 3, the chamfered antimony content was 1.2E+16 atoms / cm². 3 .

[0080] The silicon wafers from Examples 1-6 and Comparative Examples 1-4 of this application were transported to a solar cell workshop and fabricated into solar cells using the same manufacturing process. The fragmentation rate of the silicon wafers in different examples and comparative examples was statistically analyzed. To further illustrate the reduction, the fragmentation rate of the silicon wafer in Comparative Example 1 was set to 100%. The relative proportions of the fragmentation rates of Examples 1-6 and Comparative Examples 2-4 compared to the fragmentation rate of Comparative Example 1 were calculated, where: The relative proportion of fragmentation rate of the embodiment = fragmentation rate of the embodiment / fragmentation rate of Comparative Example 1 × 100%; The relative proportion of the fragmentation rate of the comparative example = fragmentation rate of the comparative example / fragmentation rate of comparative example 1 × 100%.

[0081] The statistical results are shown in Table 1.

[0082] Table 1 <![CDATA[Antimony content at chamfer (unit: atoms / cm 3 )]]> Chamfer roughness (unit: μm) The relative proportion of fragmentation rate Example 1 5E+15 0.05 62% Example 2 4.5E+14 0.08 54% Example 3 2.6E+14 0.1 56% Example 4 3.5E+13 0.2 60% Example 5 3.5E+14 0.4 68% Example 6 5E+15 0.4 70% Comparative Example 1 4.5E+14 0.01 100% Comparative Example 2 4.5E+14 0.8 110% Comparative Example 3 2E+13 0.2 93% Comparative Example 4 1.2E+16 0.2 102% The results recorded in Table 1 clearly show that, compared with Comparative Examples 1 and 2, when the antimony content in the chamfer of the silicon wafer is the same, the roughness is different. The relative proportion of the fragmentation rate in Comparative Examples 1 and 2 is significantly higher than that in Example 2. When the chamfer roughness is the same as that in Comparative Examples 3 and 4, but the antimony content in the chamfer is different, the fragmentation rate of Comparative Examples 3 and 4 is higher than that of Example 4.

[0083] This indicates that the antimony content in the silicon wafer of this application is 3E+13 atoms / cm³. 3 ~1E+16 atoms / cm 3 The roughness Ra of each chamfer is 0.03μm~0.5μm, which can significantly improve the breakage rate of solar cells made from silicon wafers.

[0084] This invention also provides a photovoltaic module, including at least two solar cells and at least one conductive interconnect. The conductive interconnect connects two adjacent solar cells, and the solar cells are as described in any of the above embodiments. For example, for a back-contact solar cell, the conductive interconnect can be a solder strip. One end of the conductive interconnect is connected to the positive electrode on the back of the previous solar cell, and the other end is connected to the negative electrode on the back of the next solar cell, thus achieving positive and negative electrode connection between adjacent solar cells. The positive and negative electrodes of the solar cells are identified and arranged based on a first chamfer and a second chamfer on the cell to prevent incorrect connection.

[0085] Since the photovoltaic module includes solar cells, it has the same beneficial effects as the silicon wafers and solar cells described in any of the above embodiments, and will not be repeated here.

[0086] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0087] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A silicon wafer, characterized in that, The silicon wafer has two opposing surfaces and four side surfaces located between the two surfaces; adjacent side surfaces are connected by chamfers; the silicon wafer contains antimony, and the antimony content of the chamfers is 3E+13 atoms / cm³. 3 ~1E+16 atoms / cm 3 The roughness Ra of the chamfer is 0.03μm~0.5μm; The silicon wafer has two opposing first edges and two opposing second edges, the length of the first edges being greater than the length of the second edges, one of the first edges having a chamfer between itself and the two adjacent second edges being a first chamfer, and the other of the first edges having a chamfer between itself and the two adjacent second edges being a second chamfer; the roughness Ra of the first chamfer is less than the roughness Ra of the second chamfer, and the difference between the roughness Ra of the first chamfer and the roughness Ra of the second chamfer is greater than 0.03 μm.

2. The silicon wafer according to claim 1, characterized in that, The antimony content of the chamfer is 7E+13 atoms / cm³. 3 ~5E+15 atoms / cm 3 .

3. The silicon wafer according to claim 1 or 2, characterized in that, The roughness Ra of the chamfer is 0.1μm~0.4μm.

4. The silicon wafer according to claim 1, characterized in that, The roughness Ra of the first chamfer is 0.03 μm to 0.2 μm; and / or, the roughness Ra of the second chamfer is 0.09 μm to 0.5 μm.

5. The silicon wafer according to claim 1, characterized in that, The difference between the roughness Ra of the chamfer and the roughness Ra of the side surface is less than 0.5 μm.

6. The silicon wafer according to claim 1, characterized in that, The surface roughness Ra is 0.01μm~0.4μm.

7. The silicon wafer according to claim 1, characterized in that, The silicon wafer has two opposing first sides and two opposing second sides, wherein the length of the first side is greater than the length of the second side; The difference between the surface roughness Ra of one of the first edges and the surface roughness Ra of the other first edge is greater than 0.01 μm.

8. The silicon wafer according to claim 7, characterized in that, Along the length of the first side, the roughness Ra at the middle position of the side surface containing the first side is less than the roughness Ra at both ends of the side surface containing the first side.

9. The silicon wafer according to claim 8, characterized in that, The surface roughness Ra at the middle position of the side surface where the first side is located is 0.01μm~0.2μm; The surface roughness Ra at both ends of the side surface where the first side is located is 0.02μm~0.15μm.

10. The silicon wafer according to claim 1, characterized in that, The silicon wafer has two opposing first sides and two opposing second sides, wherein the length of the first side is greater than the length of the second side; the ratio of the length of the first side to the length of the second side is 1.2 to 6. Alternatively, the length of the first side is 182mm~300mm, and the length of the second side is 83mm~150mm; Alternatively, the projected length of the chamfer is 1mm to 5mm.

11. A battery cell, characterized in that, It is prepared from the silicon wafer described in any one of claims 1-10.

12. A photovoltaic module comprising at least two solar cells and at least one conductive interconnect, the conductive interconnect connecting two adjacent solar cells, characterized in that, The battery cell is the battery cell as described in claim 11.

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