Fan-out packaging process and structure with optimized aEASI function

Abstract

The invention discloses an aEASI function optimized fan-out type packaging technology and structure, and relates to the technical field of semiconductor packaging, and the technology comprises the steps: preparing an ASIC control module comprising a vertical interconnection channel; glass is used as a temporary substrate, and the 3P2M configuration fan-out type conductive structure A is fixed through pyrolysis glue; after the ASIC module is inversely installed, the ASIC module is coated with an epoxy molding compound and ground to be thinned; a 3P2M-configuration fan-out conductive structure B (provided with an LED), a low-refractive-index light-transmitting material layer and a 3P2M-configuration fan-out conductive structure C with a notch right above the LED are sequentially arranged, a temporary substrate is removed after ball mounting, and a heat dissipation assembly containing fin type heat dissipation pieces is arranged on the back face of the fan-out conductive structure A. According to the scheme, the signal loss is reduced by more than 20%, the thermal resistance is reduced from 1.5 DEG C / W to 1.0 DEG C / W, the LED luminous efficiency is improved, the high integration level is realized, and the method is suitable for electronic equipment with high requirements on the performance and the integration level.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor packaging technology, specifically relating to a functionally optimized fan-out advanced packaging process and structure based on aEASI (ASE Embedded Active System Integration) technology. Background Technology

[0002] Existing fan-out packaging technologies suffer from drawbacks such as low heat dissipation efficiency, high signal transmission loss, and limited package size, making it difficult to meet the stringent requirements of high-performance chips (such as AI chips and 5G base station chips). Although aEASI technology has made breakthroughs in system-level integration, its performance limits are constrained by issues such as redundant process steps and material performance bottlenecks in traditional packaging processes.

[0003] Current embedded first-substrate technologies mainly include AT&S' ECP (Embedded Component Package), TDK's SESUB (Semiconductor Embedded Substrate), and aEASI's embedded assembly solutions. However, these technologies still face the challenge of balancing complexity, I / O count, pin pitch, and layer count. For example, ECP technology has lower complexity but limited applicability, SESUB technology has high complexity but high cost, and while aEASI technology has improved electrical performance, there is still room for improvement in heat dissipation and signal integrity. In addition, traditional chip bonding processes (such as silver paste bonding) have poor thermal / electrical conductivity, while diffusion bonding (TLPB) technology has high reliability but is complex and costly.

[0004] Therefore, there is an urgent need for an innovative process flow and structural design to systematically improve packaging performance. Summary of the Invention

[0005] The purpose of this invention is to provide a fan-out packaging process and structure with optimized aEASI functionality. Through process innovation and structural design optimization, the fan-out packaging achieves comprehensive improvements in heat dissipation, signal transmission, and size.

[0006] The objective of this invention is achieved through the following technical solution: A fan-out packaging process with aEASI functionality optimization is characterized by comprising the following steps: S1. Prepare an ASIC control module. The ASIC control module realizes vertical interconnect channels through laser drilling and copper electroplating. The diameter of the vertical interconnect channels is not greater than 10 μm and the density is not less than 1000 per cm². S2. A glass wafer is selected as a temporary substrate, and a fan-out conductive structure A is fixed on the temporary substrate by thermal adhesive. The fan-out conductive structure A adopts a 3P2M stacked configuration. S3. A first copper pillar is set on the surface of the fan-shaped conductive structure A by copper plating process; S4. Rotate the ASIC control module 180° and invert it onto the fan-out conductive structure A. Use epoxy molding compound to inject into a preset mold to cover the ASIC control module and the first copper pillar and heat to cure to form the first EMC layer. Grind the upper surface of the first EMC layer to expose the upper end of the first copper pillar and the upper end of the ASIC control module. S5. A fan-out conductive structure B is formed on the surface of the first EMC layer. The fan-out conductive structure B adopts a 3P2M stacked configuration. A second copper pillar is formed on the surface of the fan-out conductive structure B using a copper plating process. Then, the LED is set at a designated position on the fan-out conductive structure B. S6. A light-transmitting material is selected to encapsulate a second copper pillar and an LED on the surface of the fan-shaped conductive structure B to form a light-transmitting material layer; a fan-shaped conductive structure C is set on the surface of the light-transmitting material layer, and the fan-shaped conductive structure C adopts a 3P2M stacked configuration; a notch is designed on the fan-shaped conductive structure C through a patterned process, and the notch is precisely located above the LED; S7. BGA balls are placed on the surface of the fan-shaped conductive structure C by a ball-planting process. S8. The temporary substrate is heated to decompose and volatilize the pyrolytic adhesive, thereby removing the temporary substrate; BGA balls are placed on the back of the fan-out conductive structure A using a ball-planting process; a heat dissipation assembly is installed on the back of the fan-out conductive structure A using solder paste, the heat dissipation assembly including a heat dissipation base and finned heat sinks, the finned heat sinks being installed on the heat dissipation base using nano-silver solder; simultaneously, an LED light-emitting lens is provided at the notch to improve light emission efficiency and prevent light from scattering in unwanted directions.

[0007] As a further improvement of the present invention, the copper plating process in step S3 includes: coating a photoresist on a fan-out conductive structure A and forming a photoresist layer by exposure and development, wherein the photoresist layer has an opening at the location where a copper pillar needs to be formed, and copper is electroplated in the opening area to the required height, and then the remaining photoresist layer is removed.

[0008] As a further improvement of the present invention, step S1, "preparing the ASIC control module", specifically includes the following steps: S11. A lead frame is used as the first substrate; S12. Transient liquid phase diffusion bonding technology is used to achieve low-stress bonding between the ASIC chip and the first substrate: the bonding temperature is precisely controlled at 363℃, the pressure is strictly controlled at 10-50MPa, and the cooling rate is maintained at 10-20℃ / s; the bonding layer material is a polymer with a low coefficient of thermal expansion. S13. An ASIC chip on a first substrate is packaged using a dielectric material to form a first dielectric layer, and copper is plated on the surface of the first dielectric layer to form a first copper plating layer. S14. A CO2 laser is used to perform vertical drilling on the product obtained in step S13 to form a through hole with a copper layer at the bottom. The diameter of the through hole is no greater than 10 μm. S15. Copper is plated again on the surface of the first copper plating layer to form a second copper plating layer. During the copper plating process, copper liquid fills the through hole so that the second copper plating layer is electrically connected to the first substrate. S16. Photoresist is coated on the surface of the second copper plating layer to form a photoresist layer. Chemical etching or plasma etching is used to form solder joints on the exposed part of the second copper plating layer. Then, the photoresist layer is removed by chemical reagents. S17. Solder resist is applied at predetermined positions around the welding point and at the bottom of the first substrate, and a solder resist block is formed after curing. S18. A solder pad is formed in the area enclosed by the solder mask using a reflow soldering process; S19. Cut the product obtained in step S18 along the preset cutting line to divide it into independent ASIC control modules with a single ASIC chip as the core.

[0009] As a further improvement of the present invention, the pyrolytic adhesive in step S2 satisfies the following requirements: it has good adhesion and mechanical support at room temperature, and can be completely decomposed and volatilized without leaving any residue when heated to 250–400°C.

[0010] As a further improvement of the present invention, the light-transmitting material in step S6 is a low-refractive-index optical adhesive.

[0011] A fan-out package structure with optimized aEASI functionality, fabricated using the above-described process, includes: Fan-out conductive structure A serves as the base layer of the entire packaging structure; The ASIC control module is inverted and mounted on the fan-out conductive structure A. It has vertical interconnect channels with a diameter of no more than 10μm and a density of no less than 1000 per cm², and serves as the core control unit of the system. The first EMC layer is made of epoxy molding compound and uniformly covers the ASIC control module and the first copper pillar. The first copper pillar is set on the surface of the fan-out conductive structure A and its upper end is exposed on the first EMC layer. It is used to realize the electrical connection between the ASIC control module and the fan-out conductive structure B. Fan-out conductive structure B is set on the surface of the first EMC layer, and a second copper pillar and LED are provided on its surface to realize optical function integration; The light-transmitting material layer, made with low-refractive-index optical adhesive, is set on the surface of the fan-shaped conductive structure B, encapsulating the second copper pillar and the LED to ensure smooth light transmission. A fan-shaped conductive structure C is set on the surface of the light-transmitting material layer, and a notch is precisely positioned above the LED to avoid blocking the light. The BGA ball assembly includes BGA balls disposed on the surface of the fan-out conductive structure C and BGA balls disposed on the back side of the fan-out conductive structure A, providing a reliable connection interface between the package structure and external circuitry. A heat dissipation component, mounted on the back of a fan-out conductive structure A with solder paste, includes a heat dissipation base and finned heat sinks, wherein the finned heat sinks are mounted on the heat dissipation base with nano-silver solder.

[0012] As a further improvement of the present invention, the ASIC control module includes a first substrate, an ASIC chip, a first dielectric layer, a first copper plating layer, a second copper plating layer, solder joints, solder resist blocks, and pads; the ASIC chip is bonded to the first substrate using transient liquid phase diffusion soldering technology; the first dielectric layer covers the ASIC chip, the first copper plating layer covers the first dielectric layer, the second copper plating layer covers the first copper plating layer, and the two are connected by a via formed by drilling with a CO2 laser; the solder joints are formed by etching the second copper plating layer, the solder resist blocks surround the solder joints and the bottom of the first substrate, and the pads are located in the area enclosed by the solder resist blocks.

[0013] The above technical solution has the following beneficial effects: 1. Significantly reduces signal loss and adapts to large-scale circuits: The vertical interconnect channel (diameter ≤10μm, density ≥1000 pieces / cm²) and copper metal layer interconnect design of the ASIC control module reduce signal transmission loss by more than 20%. At the same time, the 3P2M configuration of the fan-out conductive structure further optimizes the signal path and meets the low-loss transmission requirements of large-scale circuits.

[0014] 2. Improved thermal stability and heat dissipation efficiency: The glass wafer temporary substrate ensures thermal stability; the ASIC chip adopts a low thermal expansion coefficient polymer adhesive layer + TLPB precision process (363℃, 10-50MPa, 10-20℃ / s cooling) to reduce temperature stress; the heat dissipation component (fin heat sink + nano silver solder) reduces the thermal resistance from 1.5℃ / W to 1.0℃ / W, efficiently dissipating heat and ensuring stable device operation.

[0015] 3. Maximize LED light output efficiency: The notch of the fan-shaped conductive structure C is precisely aligned with the top of the LED. Combined with a low-refractive-index optical adhesive layer with the same light transmittance as glass, light blockage is completely avoided, significantly improving the LED light output efficiency.

[0016] 4. Achieve residue-free temporary substrate treatment: The pyrolytic adhesive has reliable adhesion and support at room temperature, and can be completely decomposed without residue when heated to 250-400℃, which not only ensures the stability of the temporary substrate but also avoids impurities from affecting the packaging quality.

[0017] 5. High integration and high space utilization: The first EMC layer is thinned by grinding to reduce the device thickness; the multi-layer 3P2M fan-out conductive structure achieves high-density interconnection; at the same time, it integrates ASIC control, LED optical functions and efficient heat dissipation to meet the multiple requirements of high-demand electronic devices for performance, integration and miniaturization.

[0018] 6. Improved structural reliability: Each fan-out conductive structure adopts a release layer bonding process, and the ASIC chip bonding and cutting process is precise and controllable, ensuring reliable connection of each layer, low stress, and extending the service life of the package structure. Attached Figure Description

[0019] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0020] The structures, proportions, sizes, etc. shown in this specification are only used to complement the content disclosed in the specification for those skilled in the art to understand and read, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed in the present invention.

[0021] Figure 1 This is a schematic diagram of the overall process of the present invention.

[0022] Figure 2 This is a schematic diagram of the fabrication process of the ASIC control module in step S1 of the present invention.

[0023] Figure 3 A schematic diagram of the fan-out package structure optimized for the aEASI function provided by the present invention.

[0024] In the picture: 1. ASIC control module; 11. First substrate; 12. ASIC chip; 13. First dielectric layer; 14. First copper plating layer; 15. Via; 16. Second copper plating layer; 17. Solder joint; 18. Solder mask; 19. Pad; 2. Temporary substrate; 31. Fan-out conductive structure A; 32. Fan-out conductive structure B; 33. Fan-out conductive structure C; 331. Notch; 41. First bronze pillar; 42. Second bronze pillar; 5. First EMC layer; 6. Translucent material layer; 7. LED; 81, 82, BGA balls; 9. Heat dissipation components; 10. Light output lens. Detailed Implementation

[0025] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction of the component itself; similarly, for ease of understanding and description, "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this invention.

[0026] First embodiment, such as Figure 1 As shown, an aEASI-optimized fan-out packaging process includes the following steps: S1. Fabricate ASIC control module 1. This ASIC control module 1 achieves vertical interconnect channels through laser drilling and copper electroplating. The channel diameter is no greater than 10 μm, and the density is no less than 1000 channels / cm². This structure can effectively reduce signal transmission loss. Actual testing shows that the loss can be reduced by more than 20%, meeting the requirements of low-loss signal transmission for large-scale circuit connections.

[0027] S2. A glass wafer is selected as the temporary substrate 2. Glass wafers have advantages such as high flatness and good thermal stability. A fan-out conductive structure A31 (RDL redistribution layer) is fixed on the temporary substrate 2 using thermal adhesive. This fan-out conductive structure A31 adopts a 3P2M stacked configuration, with three dielectric layers (P) and two metal layers (M) stacked alternately. Copper layers are used as the metal layers, utilizing copper's high conductivity to achieve efficient interconnection. Release layer bonding is used between the layers. By precisely controlling the material and bonding parameters of the release layers, reliable connections between the layers are ensured, providing a stable foundation for subsequent packaging processes.

[0028] The above-mentioned pyrolytic adhesive has good adhesion and mechanical support at room temperature. When heated to a specific temperature (usually 250–400℃), it can be completely decomposed and volatilized without leaving any residue.

[0029] S3. A first copper pillar 41 is formed on the surface of the pair of fan-out conductive structures A31 by a copper plating process. Specifically, a layer of photoresist is first coated on the fan-out conductive structure A31, and after exposure and development, a photoresist layer with a predetermined pattern is formed. The photoresist layer has openings at the locations where the copper pillars are to be formed. Subsequently, copper is electroplated in the opening areas to fill the copper to the required height, forming the first copper pillar 41. After the copper plating is completed, a suitable stripping process, such as chemical stripping or mechanical stripping, is used to remove the remaining photoresist layer, exposing a complete and clean surface of the fan-out conductive structure A31.

[0030] S4. Rotate the ASIC control module 1 prepared in step S1 180° and invert it onto the fan-out conductive structure A31, ensuring accurate installation. Then, select epoxy molding compound (EMC) as the molding material and inject it into a pre-set mold to uniformly cover the ASIC control module 1 and the first copper pillar 41. Curing is then achieved through heating, ultimately forming a dense first EMC layer 5 on the fan-out conductive structure A31. Next, the upper surface of the first EMC layer 5 is ground, exposing the upper ends of the first copper pillar 41 and the ASIC control module 1. This grinding process reduces the overall package thickness, helping to decrease device thickness and improve space utilization.

[0031] S5. A fan-out conductive structure B32 (RDL redistribution layer) is formed on the surface of the first EMC layer 5. This fan-out conductive structure B32 also adopts a 3P2M stacked configuration, that is, it includes three dielectric layers (P) and two metal layers (M), wherein the metal layers are preferably copper layers, which are used to achieve high conductivity interconnection; the layers are reliably connected through a release layer bonding process. After the fan-out conductive structure B32 is formed, a second copper pillar 42 is formed on its surface according to the copper plating process in step S3. First, photoresist is coated, exposed and developed to form a photoresist layer, then copper is electroplated in the opening area to the required height, and finally the photoresist layer is removed. Afterwards, the light-emitting diode (LED7) is precisely mounted on the fan-out conductive structure B32, and the mounting position must strictly correspond to the design requirements.

[0032] S6. A light-transmitting material (with the same light transmittance as glass, such as low-refractive-index optical adhesive) is selected as the encapsulation material. The second copper pillar 42 and LED7 are encapsulated on the surface of the fan-out conductive structure B32 to form a light-transmitting material layer 6, ensuring that light can pass through smoothly. Subsequently, a fan-out conductive structure C33 (RDL redistribution layer) is set on the surface of the light-transmitting material layer 6. This structure also adopts a 3P2M stacked configuration. A notch 331 is designed on the fan-out conductive structure C33. Through precise patterning processes, such as photolithography and etching, the notch 331 is precisely positioned above the LED7, ensuring that the light emitted by the LED7 is not obstructed and improving the light emission efficiency.

[0033] S7. BGA balls 81 are placed on the surface of the fan-out conductive structure C33 by means of a ball-planting process.

[0034] S8. The temporary substrate 2 is heated to decompose and volatilize the pyrolytic adhesive, thereby easily removing the temporary substrate 2. Next, using the same ball-mounting process, BGA balls 82 are placed on the back of the fan-out conductive structure A31. A heat dissipation component 9 is also mounted on the back of the fan-out conductive structure A31 using solder paste. This heat dissipation component 9 consists of a heat dissipation base and finned heat sinks. The finned heat sinks are mounted on the heat dissipation base using nano-silver solder. Nano-silver solder has excellent electrical and thermal conductivity, ensuring that the heat dissipation component 9 efficiently conducts heat away, improving the overall heat dissipation performance of the package structure. Simultaneously, an LED light-emitting lens 10 is provided at the notch 331 to reduce unnecessary light loss, allowing more light to be emitted effectively, while also preventing light scattering in unwanted directions.

[0035] The fabrication process of the ASIC control module 1 in step S1 is as follows: Figure 2 As shown, it includes the following steps: S11, copper has good electrical and thermal conductivity, which can meet the electrical performance and heat dissipation requirements of ASIC control modules. A lead frame is used as the first substrate 11, which has a downset area for placing chips.

[0036] S12. Transient liquid phase diffusion bonding (TLPB) technology is used to achieve low-stress bonding between the ASIC chip 12 and the first substrate 11. During the bonding process, the temperature is precisely controlled at the eutectic temperature of 363°C, while the pressure is strictly controlled within the range of 10-50 MPa, and the cooling rate is maintained at 10-20°C / s. By optimizing the adhesive layer material, a polymer with a low coefficient of thermal expansion is selected. This material can effectively reduce the stress caused by temperature changes, thereby improving heat dissipation efficiency and reliability.

[0037] S13. The ASIC chip 12 on the first substrate 11 is encapsulated using a dielectric material (resin) to form a first dielectric layer 13, and copper is plated on the surface of the first dielectric layer 13 to form a first copper plating layer 14.

[0038] S14. For the product prepared in step S13, a CO2 laser is used for vertical drilling. The laser emitted by the CO2 laser has unique properties; its wavelength has extremely high absorption for the dielectric material (resin) used in the first dielectric layer 13, but extremely low absorption for the copper layer. Based on this characteristic, when the laser acts on the product, it can precisely ablate and remove the upper dielectric material without damaging the lower first substrate 11, thus forming a via 15 with a copper layer at the bottom. In actual operation, there are strict requirements for the via 15. Its aperture must be controlled within the range of no more than 10 μm to ensure the accuracy and stability of signal transmission; the density must be no less than 1000 vias / cm² to meet the needs of large-scale circuit connections. This precise drilling method lays a solid foundation for subsequent circuit connections.

[0039] S15. A second copper plating operation is performed on the surface of the first copper plating layer 14 to form a second copper plating layer 16 that is perfectly integrated with the first copper plating layer 14. During the copper plating process, the copper liquid naturally fills the vias 15, enabling the second copper plating layer 16 to achieve electrical connection with the first substrate 11. This connection method constructs a complete circuit path for the entire ASIC control module 1, ensuring smooth transmission of signals and current within the module, thereby ensuring stable and reliable operation of the module.

[0040] S16. Apply photoresist to the surface of the second copper plating layer 16 to form a photoresist layer. This photoresist layer must precisely cover the areas of the second copper plating layer 16 that will be retained later, while exposing the areas to be etched. In practice, the thickness and uniformity of the photoresist coating can be precisely controlled to ensure that the photoresist layer provides good masking. Next, use a suitable etching process to etch the exposed parts of the second copper plating layer 16 to form several solder joints 17. The etching method can be chemical etching or plasma etching, as long as it achieves precise etching. After etching, a chemical reagent compatible with the photoresist must be used to completely remove the photoresist layer, ensuring that the surface of the second copper plating layer 16 is clean and ready for subsequent processes.

[0041] S17. Solder resist is applied at predetermined positions around the solder joint 17 and at the bottom of the first substrate 11. The solder resist coating should be uniform and of appropriate thickness, and after curing, it forms a solder resist block 18. The solder resist block 18 can effectively prevent short circuits and other defects during subsequent soldering operations, ensuring the stability and reliability of the circuit.

[0042] Step S18 employs a reflow soldering process to form pads 19 within the area enclosed by the solder mask 18. The reflow soldering process ensures that the solder melts accurately and fills the designated area, forming high-quality pads 19 that provide a stable connection point for subsequent component soldering.

[0043] Step S19 involves cutting the product prepared in step S18. Along the pre-designed cutting line, the product is divided into ASIC control modules 1 with a single ASIC chip 12 as the core. Each module has independent and complete functions.

[0044] An aEASI-optimized fan-out package structure, fabricated using the above-described process, is as follows: Figure 3 As shown, it integrates an ASIC control module, a multi-layer fan-out conductive structure, copper pillars, LEDs, BGA balls, and heat dissipation components, achieving a balance between efficient signal transmission, integrated optical functions, and excellent heat dissipation performance. It is suitable for electronic devices with high performance and integration requirements. The specific structure is as follows: The fan-out conductive structure A31 serves as the foundation layer of the entire package structure, possessing stable and reliable electrical connection characteristics. The ASIC control module 1, mounted on it, is the core control unit of the entire system, capable of implementing various complex functional controls. The first EMC layer 5 uses high-performance epoxy molding compound, uniformly encapsulating the ASIC control module 1 and the first copper pillar 41 through a molding process. This not only provides mechanical protection but also effectively prevents external environmental interference to the internal components.

[0045] The first EMC layer 5 has a fan-out conductive structure B32, on which a second copper pillar 42 is formed by copper plating, and an LED 7 is installed to achieve optical function integration. The first copper pillar 41 is used to realize the electrical connection between the ASIC control module 1 and the fan-out conductive structure B32. The above structure realizes a low-loss and high-stability electrical connection between the ASIC control module 1 and the fan-out conductive structure B32.

[0046] The light-transmitting material layer 6 uses low-refractive-index optical adhesive and other light-transmitting materials, which have good light transmittance and chemical stability. During the encapsulation process, the second copper pillar 42 and LED7 are encapsulated on the surface of the fan-out conductive structure B32 to ensure smooth light transmission.

[0047] A fan-out conductive structure C33 is disposed on the surface of the light-transmitting material layer 6. A notch 331 is precisely formed in the C333 through processes such as laser cutting. The notch 331 is located directly above the LED 7, and a light-emitting lens 10 is disposed at the notch 331 to ensure that the light emitted by the LED 7 is not obstructed, thereby improving the light emission efficiency. BGA balls 82 and 81 are respectively disposed on the back of the fan-out conductive structure A31 and the surface of the fan-out conductive structure C33. Through the ball-mounting process, a reliable interface is provided for the connection between the entire package structure and the external circuit, meeting the electrical connection requirements of different application scenarios.

[0048] In this solution, the ASIC control module 1 forms vertical interconnect channels through laser drilling and copper plating. The channel diameter is no greater than 10 μm, and the density is no less than 1000 channels / cm². This fine interconnect structure helps to achieve low-loss signal transmission, reducing losses by more than 20%, and meeting the requirements of large-scale circuit connections.

[0049] A heat dissipation component 9, comprising a heat dissipation base and finned heat sinks, is disposed on the back of the fan-out conductive structure A31. The finned heat sinks are mounted on the heat dissipation base using nano-silver solder. Nano-silver solder has excellent electrical and thermal conductivity, which can efficiently conduct heat generated inside the package structure away, improving heat dissipation performance and ensuring stable operation of the package structure. Through the application of the aforementioned heat dissipation component 9, the thermal resistance is reduced from 1.5°C / W to 1.0°C / W, and signal loss is reduced by 25%.

[0050] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0051] It should be noted that the terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in sequences other than those illustrated or described herein.

[0052] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A fan-out packaging process with optimized aEASI functionality, characterized in that, Includes the following steps: S1. Prepare an ASIC control module (1). The ASIC control module (1) realizes vertical interconnection channels through laser drilling and copper electroplating. The diameter of the vertical interconnection channels is not greater than 10 μm and the density is not less than 1000 / cm². S2. A glass wafer is selected as a temporary substrate (2), and a fan-out conductive structure A (31) is fixed on the temporary substrate (2) by thermal adhesive. The fan-out conductive structure A (31) adopts a 3P2M stacked configuration. S3. A first copper pillar (41) is set on the surface of the fan-shaped conductive structure A (31) by copper plating process. S4. Rotate the ASIC control module (1) 180° and invert it onto the fan-out conductive structure A (31). Use epoxy molding compound to inject into a preset mold to cover the ASIC control module (1) and the first copper pillar (41) and heat to cure to form the first EMC layer (5). Grind the upper surface of the first EMC layer (5) to expose the upper end of the first copper pillar (41) and the upper end of the ASIC control module (1). S5. A fan-out conductive structure B (32) is provided on the surface of the first EMC layer (5). The fan-out conductive structure B (32) adopts a 3P2M stacked configuration. A second copper pillar (42) is provided on the surface of the fan-out conductive structure B (32) using a copper plating process. Then, the LED (7) is placed at a designated position on the fan-out conductive structure B (32). S6. A light-transmitting material is selected to encapsulate a second copper pillar (42) and an LED (7) on the surface of the fan-out conductive structure B (32) to form a light-transmitting material layer (6); a fan-out conductive structure C (33) is set on the surface of the light-transmitting material layer (6), and the fan-out conductive structure C (33) adopts a 3P2M stacked configuration; a notch (331) is designed on the fan-out conductive structure C (33) through a patterned process, and the notch (331) is precisely located above the LED (7); S7. BGA balls (81) are placed on the surface of the fan-shaped conductive structure C (33) by a ball-planting process. S8. The temporary substrate (2) is heated to decompose and volatilize the pyrolytic adhesive to remove the temporary substrate (2); BGA balls (82) are placed on the back of the fan-out conductive structure A (31) by a ball-planting process; a heat dissipation component (9) is installed on the back of the fan-out conductive structure A (31) by solder paste. The heat dissipation component (9) includes a heat dissipation base and a finned heat sink. The finned heat sink is installed on the heat dissipation base by nano-silver solder; an LED light-emitting lens (10) is provided at the notch (331).

2. The fan-out packaging process according to claim 1, characterized in that, The copper plating process in step S3 includes: coating a photoresist onto a fan-out conductive structure A (31) and forming a photoresist layer by exposure and development; opening an opening in the photoresist layer at the location where a copper pillar needs to be formed; electroplating copper in the opening area to the required height; and then removing the remaining photoresist layer.

3. The fan-out packaging process according to claim 1, characterized in that, Step S1, "Preparing the ASIC control module (1)", specifically includes the following steps: S11, A lead frame is used as the first substrate (11). S12. The ASIC chip (12) and the first substrate (11) are bonded with low stress using transient liquid phase diffusion bonding technology: the bonding temperature is precisely controlled at 363℃, the pressure is strictly controlled at 10-50MPa, and the cooling rate is maintained at 10-20℃ / s; the bonding layer material is a polymer with a low coefficient of thermal expansion. S13. The ASIC chip (12) on the first substrate (11) is packaged with dielectric material to form a first dielectric layer (13), and copper is plated on the surface of the first dielectric layer (13) to form a first copper plating layer (14). S14. A CO2 laser is used to perform vertical drilling on the product obtained in step S13 to form a through hole (15) with a copper layer at the bottom. The diameter of the through hole (15) is not greater than 10 μm. S15. Copper is plated again on the surface of the first copper plating layer (14) to form a second copper plating layer (16). During the copper plating process, copper liquid fills the through hole (15) so that the second copper plating layer (16) and the first substrate (11) are electrically connected. S16. Photoresist is coated on the surface of the second copper plating layer (16) to form a photoresist layer. Chemical etching or plasma etching is used to form solder joints (17) on the exposed part of the second copper plating layer (16). Then, the photoresist layer is removed by chemical reagents. S17. Solder resist is applied at predetermined positions around the welding point (17) and at the bottom of the first substrate (11), and a solder resist block (18) is formed after curing. S18. A solder pad (19) is formed in the area enclosed by the solder mask block (18) using a reflow soldering process. S19. Cut the product obtained in step S18 along the preset cutting line to divide it into an independent ASIC control module (1) with a single ASIC chip (12) as the core.

4. The fan-out packaging process according to claim 1, characterized in that, The pyrolytic adhesive in step S2 meets the following requirements: it has good adhesion and mechanical support at room temperature, and it can be completely decomposed and volatilized without leaving any residue when heated to 250–400℃.

5. The fan-out packaging process according to claim 1, characterized in that, The light-transmitting material in step S6 is a low-refractive-index optical adhesive.

6. A fan-out package structure with optimized aEASI functionality, characterized in that, Prepared using the process described in any one of claims 1-5, comprising: Fan-out conductive structure A (31) serves as the base layer of the entire encapsulation structure; The ASIC control module (1) is inverted and mounted on the fan-out conductive structure A (31), and has vertical interconnect channels with a diameter of no more than 10 μm and a density of no less than 1000 units / cm², serving as the core control unit of the system. The first EMC layer (5) is made of epoxy molding compound and uniformly covers the ASIC control module (1) and the first copper pillar (41). The first copper pillar (41) is set on the surface of the fan-out conductive structure A (31) and its upper end is exposed on the first EMC layer (5) to realize the electrical connection between the ASIC control module (1) and the fan-out conductive structure B (32). A fan-out conductive structure B (32) is disposed on the surface of the first EMC layer (5), and a second copper pillar (42) and an LED (7) are provided on its surface to achieve optical function integration; The light-transmitting material layer (6) is prepared with low-refractive-index optical adhesive and set on the surface of the fan-shaped conductive structure B (32). The second copper pillar (42) and the LED (7) are encapsulated to ensure that light passes through smoothly. A fan-shaped conductive structure C (33) is disposed on the surface of the light-transmitting material layer (6), and a notch (331) is precisely located above the LED (7) thereon. A light-emitting lens (10) is disposed at the notch (331). The BGA ball assembly includes a BGA ball (81) disposed on the surface of the fan-out conductive structure C (33) and a BGA ball (82) disposed on the back side of the fan-out conductive structure A (31), providing a reliable connection interface between the package structure and external circuits; The heat dissipation component (9) is installed on the back of the fan-out conductive structure A (31) by solder paste, and includes a heat dissipation base and a finned heat sink, which is installed on the heat dissipation base by nano-silver solder.

7. The fan-out packaging structure according to claim 6, characterized in that, The ASIC control module (1) includes a first substrate (11), an ASIC chip (12), a first dielectric layer (13), a first copper plating layer (14), a second copper plating layer (16), a solder joint (17), a solder mask block (18), and a pad (19). The ASIC chip (12) is bonded to the first substrate (11) by transient liquid phase diffusion soldering technology. The first dielectric layer (13) covers the ASIC chip (12), the first copper plating layer (14) covers the first dielectric layer (13), and the second copper plating layer (16) covers the first copper plating layer (14). The two are connected by a through hole (15) formed by drilling with a CO2 laser. The solder joint (17) is formed by etching the second copper plating layer (16). The solder mask block (18) surrounds the solder joint (17) and the bottom of the first substrate (11). The pad (19) is located in the area surrounded by the solder mask block (18).

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