Overlay error compensation method

Abstract

An overlay error compensation method comprises the steps that a wafer with an overlay mark pattern is provided, the overlay mark pattern comprises three sets of cross-shaped overlay marks which correspond to a first structural layer, a second structural layer and a third structural layer respectively, and the three sets of cross-shaped overlay marks are all formed on the first structural layer. And measuring offsets of the centers of the three groups of cross-shaped overlay marks in the first direction and the second direction to obtain overlay error compensation data, determining an overlay error compensation value of the wafer in the next batch, and compensating the exposure machine according to the overlay error compensation value. The overlay mark pattern is arranged in the exposure area of the wafer, so that the overlay precision can be further improved, the occupancy rate of the cutting channel area of the wafer is reduced, and the processing efficiency of the wafer is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and in particular relates to a method for compensating for overlay errors. Background Technology

[0002] Overlay error refers to the deviation of the current layer pattern on a wafer relative to the previous layer pattern in IC manufacturing along the x and y directions. Specialized equipment measures the relative position between the current and previous layer patterns to determine overlay error. The patterns on the wafer used to measure overlay error are called overlay markers, and each layer has multiple overlay markers. After processing a layer (current layer), the positional deviation between a specific overlay marker on the current layer and its corresponding marker on the previous layer—that is, the overlay error of that marker—can be calculated to correct the processing positioning. This ensures that the overlay marker in the next layer is more aligned with the overlay marker in the previous layer, thus aligning all layers of the wafer. To improve correction accuracy, the manufacturing positioning of the next layer is typically determined by the overlay error of all overlay markers on the wafer; this process is called overlay error compensation.

[0003] In semiconductor photolithography processes, the VIA1 layer (first via layer) plays a crucial role in the electrical structure, connecting the MET1 (first metal layer) and MET2 (second metal layer). The VIA1 layer (first via layer) requires prior measurement... Figure 1 The MET1:VIA1 (first metal layer: first via layer) overlay pattern is shown. Then, the MET2:VIA1 (second metal layer: first via layer) overlay pattern is measured. Engineers need to find two sets of coordinates to create the overlay program, extending the measurement time. Furthermore, the two overlay patterns will occupy more of the dicing area on the wafer, such as... Figure 3 As shown.

[0004] Therefore, how to reduce the occupancy rate of the wafer dicing area and improve the overlay accuracy has become an urgent problem to be solved. Summary of the Invention

[0005] This application provides an overlay error compensation method. Three sets of cross-shaped overlay marks are formed in the wafer exposure area, corresponding to the first, second, and third structural layers respectively. All three sets of cross-shaped overlay marks are formed in the first structural layer. By measuring the offset of the centers of the three sets of cross-shaped overlay marks in the first and second directions, overlay error compensation data is obtained, determining the overlay error compensation value for the wafer in the next batch. The exposure equipment is then compensated based on the overlay error compensation value. The overlay mark pattern of this application is set in the wafer exposure area, which can further improve overlay accuracy, reduce the occupancy rate of the wafer dicing area, and improve wafer processing efficiency.

[0006] Other objects and advantages of the present invention can be further understood from the technical features disclosed herein.

[0007] To achieve one, some, or all of the above objectives or other objectives, the present invention provides a method for compensating for overlay errors.

[0008] A method for compensating overlay error includes: A wafer with an overlay marking pattern is provided, the overlay marking pattern including three sets of cross overlay markings, respectively corresponding to a first structural layer, a second structural layer and a third structural layer, and all three sets of cross overlay markings are formed on the first structural layer; By measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions, overlay error compensation data is obtained, the overlay error compensation value of the next batch of wafers is determined, and the exposure machine is compensated according to the overlay error compensation value.

[0009] The three sets of cross-shaped markings are the same size, with the width of the cross being greater than or equal to 0.3 μm and the width of each cross-shaped marking being greater than or equal to 1 μm.

[0010] In each group of cross-shaped markings, the number of cross-shaped markings must be at least four.

[0011] The specific process of obtaining the overlay error compensation data by measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions is as follows: Obtain the geometric center point coordinates of the first set of cross-shaped markings corresponding to the first structural layer, as the first coordinate; obtain the geometric center point coordinates of the second set of cross-shaped markings corresponding to the second structural layer, as the second coordinate; obtain the geometric center point coordinates of the third set of cross-shaped markings corresponding to the third structural layer, as the third coordinate; The overlay error compensation data is obtained based on the offsets of the first coordinate and the second coordinate in the first and second directions, and the offsets of the second coordinate and the third coordinate in the first and second directions.

[0012] The first direction is the X direction, and the second direction is the Y direction.

[0013] The four interlocking cross marks are symmetrically distributed, and the geometric center point of a set of interlocking cross marks is determined by the intersection of the diagonals of the four interlocking cross marks.

[0014] The overprinted marking pattern is set in the exposure area, and the overprinted marking pattern is set at each of the four corners of the exposure area.

[0015] The cross-shaped markings are distributed around the devices within the exposure area of ​​the wafer, and the spacing between the devices is smaller than the width of the dicing area of ​​the wafer.

[0016] The width of the cutting channel area is 60±5um, and the spacing between the devices is 40±5um.

[0017] The specific process of compensating for overlay errors using an exposure machine is as follows: The production execution system collects the current batch overlay error compensation data of the current batch of wafers and transmits it to the advanced process control system. The advanced process control system calculates the current batch overlay error compensation value based on the current batch overlay error compensation data of the current batch of wafers. The overlay accuracy compensation is then performed on the photolithography process of the next batch of wafers based on the current batch overlay error compensation value.

[0018] Compared with the prior art, the beneficial effects of the present invention mainly include: This application forms three sets of cross-shaped overlay marks corresponding to the first, second, and third structural layers respectively in the wafer exposure area, and all three sets of cross-shaped overlay marks are formed in the first structural layer. By measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions, overlay error compensation data is obtained, the overlay error compensation value of the wafer in the next batch is determined, and the exposure machine is compensated according to the overlay error compensation value, which can further improve the overlay accuracy, reduce the occupancy rate of the wafer dicing area, and improve the wafer processing efficiency.

[0019] To make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 Illustration of overlaying marking graphics for existing technology Figure 1 .

[0022] Figure 2 Illustration of overlaying marking graphics for existing technology Figure 2 .

[0023] Figure 3 A schematic diagram of overlaying markings on the cutting area of ​​existing technology.

[0024] Figure 4 A schematic diagram of the overlay marking pattern for the exposure area provided in the embodiments of this application. Figure 1 .

[0025] Figure 5 A schematic diagram of the overlay marking pattern for the exposure area provided in the embodiments of this application. Figure 2 .

[0026] Figure 6 A schematic diagram of the overprinted marking pattern of the cutting area provided in the embodiments of this application.

[0027] Figure 7 A schematic diagram of the overlay marking pattern for the exposure area provided in the embodiments of this application. Figure 3 . Detailed Implementation

[0028] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0029] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0030] Example like Figure 4 As shown, a wafer with an overlay marking pattern is provided. The overlay marking pattern includes three sets of cross overlay markings, which correspond to the first structural layer, the second structural layer and the third structural layer, respectively, and all three sets of cross overlay markings are formed in the first structural layer.

[0031] Specifically, such as Figure 4 As shown, the three sets of cross-shaped markings are the same size and can be adjusted according to the process. The width of the cross is greater than or equal to 0.3um to ensure that it can be identified. 0.3um is close to or higher than the theoretical resolution limit of the measuring machine's optical system to ensure that the line width is sufficient to form a clear edge signal with sufficient contrast during imaging, ensuring that the marking can be stably photolithographically and etched without deformation.

[0032] like Figure 4As shown, the overlay marking pattern is set in the exposure area. The overlay markings are distributed around the devices in the exposure area of ​​the wafer. The width of the overlay markings is greater than or equal to 1µm, which is much smaller than the spacing between the devices in the exposure area of ​​the wafer. The smaller size allows them to be placed near the devices in the exposure area to monitor the overlay error inside the exposure area, reduce the occupancy rate of the wafer dicing area, improve overlay accuracy, and further improve the wafer processing efficiency.

[0033] like Figure 4 As shown, overlay markings are placed at the four corners of the wafer exposure area, and the spacing between the overlay markings is fixed. In wafer lithography, a wafer is divided into many rectangular areas called "exposure fields" or "shots." Each exposure field is the area covered by a single exposure of the lithography machine lens, used to print one or more chips. At each of the four corners of each exposure field (usually near the boundary but within the exposure area), an overlay marking is placed. The design distance between the four overlay markings is precisely known and fixed, providing a reference for subsequent exposure machine compensation.

[0034] In a preferred embodiment of this application, the width of the wafer dicing area is 60±5µm, and the spacing between devices within the exposure area of ​​the wafer is 40±5µm. The device spacing is smaller than the width of the wafer dicing area, which increases the number of devices that can be placed within the exposure area. Figure 5 As shown.

[0035] This application obtains overlay error compensation data by measuring the offset of the center of three sets of cross overlay marks in the first and second directions, determines the overlay error compensation value of the wafer in the next batch, and compensates the exposure machine according to the overlay error compensation value.

[0036] Specifically, each set of cross-shaped markings in this application has at least four markings. The center position is determined by the diagonals of the four cross-shaped markings. The four cross-shaped markings are symmetrically distributed to form a rectangle or square. The geometric center of a set of cross-shaped markings is determined by the intersection of the two diagonals. Obtain the coordinates of the geometric center point of the first set of overlay marks, and use them as the first coordinates (x1, y1); Obtain the coordinates of the geometric center point of the second set of overlay marks, and use them as the second coordinates (x2, y2); Obtain the coordinates of the geometric center point of the third set of overlay marks, and use them as the third coordinates (x3, y3); Based on the offsets of the first coordinate and the second coordinate in the first and second directions, the overlay error compensation data (ΔX12, ΔY12) is obtained, and based on the offsets of the second coordinate and the third coordinate in the first and second directions, the overlay error compensation data (ΔX23, ΔY23) is obtained. This application collects the current batch overlay error compensation data of the current batch of wafers through the production execution system and transmits it to the advanced process control system; the advanced process control system calculates the current batch overlay error compensation value based on the current batch overlay error compensation data of the current batch of wafers; and performs overlay accuracy compensation for the photolithography process of the next batch of wafers based on the current batch overlay error compensation value.

[0037] In a preferred embodiment of this application, the first direction is the X direction and the second direction is the Y direction.

[0038] like Figure 6 As shown, the overlay mark pattern is located in the dicing area of ​​the wafer, occupying the dicing area area on the wafer; this application sets the overlay mark pattern in the wafer exposure area, which does not occupy the dicing area of ​​the wafer, reducing the occupancy rate of the dicing area by 100%, as shown. Figure 7 As shown.

[0039] In summary, this application forms three sets of cross-shaped overlay marks in the wafer exposure area, corresponding to the first, second, and third structural layers, respectively. All three sets of cross-shaped overlay marks are formed in the first structural layer. By measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions, overlay error compensation data is obtained, the overlay error compensation value of the wafer in the next batch is determined, and the exposure machine is compensated according to the overlay error compensation value. This can further improve the overlay accuracy, reduce the occupancy rate of the wafer dicing area, and improve the wafer processing efficiency.

[0040] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0041] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for compensating overlay error, characterized in that, include: A wafer with an overlay marking pattern is provided, the overlay marking pattern including three sets of cross overlay markings, respectively corresponding to a first structural layer, a second structural layer and a third structural layer, and all three sets of cross overlay markings are formed on the first structural layer; By measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions, overlay error compensation data is obtained, the overlay error compensation value of the next batch of wafers is determined, and the exposure machine is compensated according to the overlay error compensation value.

2. The overlay error compensation method according to claim 1, characterized in that, The three sets of cross-shaped markings are the same size, with the width of the cross being greater than or equal to 0.3 μm and the width of each cross-shaped marking being greater than or equal to 1 μm.

3. The overprinting error compensation method according to claim 1, characterized in that, In each group of cross-shaped markings, the number of cross-shaped markings must be at least four.

4. The overprinting error compensation method according to claim 1, characterized in that, The specific process of obtaining the overlay error compensation data by measuring the offset of the center of the three sets of cross-shaped overlay marks in the first and second directions is as follows: Obtain the geometric center point coordinates of the first set of cross-shaped markings corresponding to the first structural layer, as the first coordinate; obtain the geometric center point coordinates of the second set of cross-shaped markings corresponding to the second structural layer, as the second coordinate; obtain the geometric center point coordinates of the third set of cross-shaped markings corresponding to the third structural layer, as the third coordinate; The overlay error compensation data is obtained based on the offsets of the first coordinate and the second coordinate in the first and second directions, and the offsets of the second coordinate and the third coordinate in the first and second directions.

5. The overlay error compensation method according to claim 4, characterized in that, The first direction is the X direction, and the second direction is the Y direction.

6. The overlay error compensation method according to claim 3, characterized in that, The four interlocking cross marks are symmetrically distributed, and the geometric center point of a set of interlocking cross marks is determined by the intersection of the diagonals of the four interlocking cross marks.

7. The overlay error compensation method according to claim 1, characterized in that, The overprinted marking pattern is set in the exposure area, and the overprinted marking pattern is set at each of the four corners of the exposure area.

8. The overlay error compensation method according to claim 1, characterized in that, The cross-shaped markings are distributed around the devices within the exposure area of ​​the wafer, and the spacing between the devices is smaller than the width of the dicing area of ​​the wafer.

9. The overlay error compensation method according to claim 8, characterized in that, The width of the cutting channel area is 60±5um, and the spacing between the devices is 40±5um.

10. The overprinting error compensation method according to claim 1, characterized in that, The specific process of compensating for overlay errors using an exposure machine is as follows: The production execution system collects the current batch overlay error compensation data of the current batch of wafers and transmits it to the advanced process control system; the advanced process control system calculates the current batch overlay error compensation value based on the current batch overlay error compensation data of the current batch of wafers. The overlay accuracy is compensated for in the photolithography process of the next batch of wafers based on the overlay error compensation value of the current batch.

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