An acceleration card optimization method and system for application performance improvement

Abstract

The application provides an acceleration card optimization method and system for application performance improvement, and relates to the technical field of computer hardware performance optimization. First, the application obtains the computation graph structure generated by the application running, power consumption distribution data and heat distribution data. Second, the parallel computation intensive subgraph and the sequential logic intensive subgraph are extracted. Third, in the logic resource array, the hardware computing unit is configured as a first working frequency state, and the hardware control unit is configured as a second working frequency state. Fourth, the power consumption distribution data and the heat distribution data are coupled with the physical layout position of the hardware computing unit to generate a frequency adjustment vector. Finally, the hardware computing unit and the hardware control unit are cooperatively optimized according to the frequency adjustment vector and the computation graph structure to complete the optimization of the acceleration card. The technical scheme provided by the application not only guarantees the correctness of the computation timing, but also realizes the overall improvement of the application performance and energy efficiency.

Description

Technical Field

[0001] This application relates to the field of computer hardware performance optimization technology, and in particular to an accelerator card optimization method and system for improving application performance. Background Technology

[0002] With the widespread deployment of intelligent computing applications on accelerator cards, processing tasks are showing a dual trend of increasingly complex computation graph structures and localized hardware power consumption and heat distribution, which puts forward more refined requirements for the dynamic optimization of accelerator cards. Application scenarios not only require accelerator cards to efficiently execute mixed tasks that are intensive in parallel computing and intensive in sequential logic, but also to deal with the problem of local high temperature and power consumption surges caused by the aggregation of high-load computing units in real time during operation, so as to ensure the continuous high performance and hardware stability of computing applications.

[0003] To address the aforementioned needs, existing technical solutions employ a method that dynamically senses hardware status and computational load by monitoring real-time data from multiple power consumption and temperature sensors within the accelerator card chip, combined with analysis of the computational graph structure of the running computational tasks. Based on preset power consumption and temperature thresholds, this technical solution uniformly adjusts the frequency of hardware units processing different computational tasks on the accelerator card. For example, when the overall power consumption or temperature approaches the safe upper limit, the frequency of the computational units is appropriately reduced to control heat accumulation, attempting to maintain performance while ensuring hardware safety.

[0004] However, this technical solution has the drawback that its frequency adjustment strategy fails to fully consider the inherent dependency between parallel computing units and sequential logic units within the computation graph, as well as the specific physical layout of high-power computing units on the chip. At the same time, its global or coarse-grained frequency adjustment can easily disrupt the frequency coordination required between different computing units to maintain correct computation timing, which may limit the overall performance improvement or even cause computation errors due to timing issues. Summary of the Invention

[0005] This application provides an accelerator card optimization method and system for improving application performance, in order to solve the problems of insufficient precision in dynamic frequency adjustment in the prior art, making it difficult to coordinate the optimization of the timing correctness of computing tasks and hardware thermal power consumption constraints.

[0006] In a first aspect, this application provides an accelerator card optimization method for improving application performance, comprising:

[0007] Acquire the computation graph structure generated by the target computing application during runtime, as well as the power consumption and heat distribution data at the hardware level;

[0008] Extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph from the computation graph structure;

[0009] In the logical resource array of the accelerator card, the hardware computing unit corresponding to the parallel computing intensive subgraph is configured to the first operating frequency state, and the hardware control unit corresponding to the sequential logic intensive subgraph is configured to the second operating frequency state.

[0010] The power consumption distribution data and heat distribution data at the hardware level are coupled with the physical layout location of the hardware computing unit in the first operating frequency state to generate a frequency adjustment vector related to the physical location of the hardware computing unit in the first operating frequency state.

[0011] Based on the frequency adjustment vector and the computation graph structure, the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card are collaboratively optimized to complete the optimization of the accelerator card.

[0012] Optionally, the computation graph structure generated during the runtime of the target computing application, as well as the power consumption and heat distribution data at the hardware level, are obtained, including:

[0013] While the target computing application is running on the accelerator card, the computing instruction flow of the target computing application executed on the accelerator card is parsed, and the dependencies and data flow between computing instructions in the computing instruction flow are recorded to form a directed acyclic graph description.

[0014] At the same time, the multiple power consumption sensors and temperature sensors pre-arranged inside the accelerator card chip are polled, and the real-time measurement values ​​of each power consumption sensor and temperature sensor are read.

[0015] The real-time measurement values ​​of each power consumption sensor and temperature sensor are mapped to the physical coordinates of the chip plane of the accelerator card, so that each real-time measurement value corresponds to a known chip plane coordinate position.

[0016] Based on the chip's planar coordinate position, the real-time measurement values ​​from the power consumption sensor are processed into power consumption distribution data, and the measurement values ​​from the temperature sensor are processed into heat distribution data.

[0017] Optionally, the parallel computation-intensive subgraph and the sequential logic-intensive subgraph in the computation graph structure are extracted, including:

[0018] The computation mode of the computation nodes in the directed acyclic graph is determined. From the computation instructions of the computation nodes in the directed acyclic graph, multiple identical computation instructions that can be executed in parallel are identified, and the computation nodes corresponding to the multiple identical computation instructions are integrated to obtain a set of parallel computation nodes.

[0019] From the computation instructions of the computation nodes described by the directed acyclic graph, multiple different operation instructions are identified, and the computation nodes corresponding to the multiple different operation instructions are integrated to obtain a set of sequential logical nodes, wherein the multiple different operation instructions have a sequential execution order;

[0020] In the description of the directed acyclic graph, the connection edges associated with each computing node in the set of parallel computing nodes are determined, and based on the connection edges, a parallel computing dense subgraph with internal edge connections is partitioned in the set of parallel computing nodes.

[0021] In the description of the directed acyclic graph, the connection edges associated with each computation node in the set of sequential logic nodes are determined, and based on the connection edges, a dense sequential logic subgraph with internal edge connections is partitioned in the set of sequential logic nodes.

[0022] Optionally, in the logic resource array of the accelerator card, the hardware computing units corresponding to the parallel computing-intensive subgraphs are configured to a first operating frequency state, while the hardware control units corresponding to the sequential logic-intensive subgraphs are configured to a second operating frequency state, including:

[0023] Within the logic resource array of the accelerator card, a hardware computing unit prepared for executing the parallel computing intensive subgraph is located, the hardware computing unit comprising a circuit module of an arithmetic logic unit.

[0024] Within the logic resource array of the accelerator card, a hardware control unit prepared for executing the sequential logic-dense subgraph is located, the hardware control unit comprising a circuit module of a status register;

[0025] Obtain a first reference frequency value that matches the working mode of the parallel computing dense subgraph from a preset frequency configuration table;

[0026] Obtain a second reference frequency value that matches the operating mode of the sequential logic dense subgraph from a preset frequency configuration table;

[0027] Write the first reference frequency value into the operating frequency register of the hardware computing unit to configure the hardware computing unit to the first operating frequency state.

[0028] The second reference frequency value is written into the operating frequency register of the hardware control unit to configure the hardware control unit to the second operating frequency state.

[0029] Optionally, the power consumption distribution data and heat distribution data at the hardware level are coupled with the physical layout location of the hardware computing unit in the first operating frequency state to generate a frequency adjustment vector related to the physical location of the hardware computing unit in the first operating frequency state, including:

[0030] On the chip plane of the accelerator card, determine the central physical coordinate position of each hardware computing unit in the first operating frequency state;

[0031] A physical influence range is defined for each of the central physical coordinate locations;

[0032] On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each power measurement point in the power distribution data;

[0033] On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each temperature measurement point in the thermal distribution data;

[0034] The number of all power consumption measurement points within the physical influence range of the hardware computing unit operating at the first operating frequency is counted to obtain the first influence value;

[0035] The number of all temperature measurement points within the physical influence range of the hardware computing unit operating at the first frequency is counted to obtain the second influence value;

[0036] The first influence value and the second influence value are weighted and combined to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state.

[0037] For all hardware computing units on the accelerator card that are in the first operating frequency state, the statistical operation and weighted combination operation are repeatedly performed to obtain multiple coupling values ​​corresponding to all hardware computing units in the first operating frequency state.

[0038] Multiple coupling values ​​are arranged in a preset order on the chip plane according to the hardware computing units to obtain a frequency adjustment vector.

[0039] Optionally, the first influence value and the second influence value are weighted and combined to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state, including:

[0040] Calculate the distance factor of each power consumption measurement point and each temperature measurement point relative to the center position of the hardware computing unit within the physical influence range of each hardware computing unit in the first operating frequency state.

[0041] Based on the distance factor, determine the first distance weight for each power consumption measurement point and the second distance weight for each temperature measurement point;

[0042] Based on the first distance weight, the power consumption measurement point data of all power consumption measurement points within the physical influence range are weighted and summed to obtain the weighted power consumption influence value;

[0043] Based on the second distance weight, the data of all temperature measurement points within the physical influence range are weighted and summed to obtain the weighted temperature influence value;

[0044] The weighted power consumption influence value is multiplied by a preset third weighting factor, and the weighted temperature influence value is multiplied by a preset fourth weighting factor. The two product results are added together to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state.

[0045] Optionally, based on the frequency adjustment vector and the computation graph structure, the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card are collaboratively optimized to complete the optimization of the accelerator card, including:

[0046] Based on the frequency adjustment vector, calculate the frequency offset corresponding to the hardware computing unit for each first operating frequency state;

[0047] Based on the computation graph structure, determine the hardware control unit with a second operating frequency state that has a data exchange relationship with each hardware computing unit;

[0048] Based on the frequency offset and the data exchange relationship, calculate the accompanying frequency offset corresponding to the hardware control unit for each second operating frequency state;

[0049] The target operating frequency of each hardware computing unit is obtained by combining the current operating frequency of each hardware computing unit with the corresponding frequency offset.

[0050] The target operating frequency of each hardware control unit is obtained by combining the current operating frequency of each hardware control unit with the corresponding accompanying frequency offset.

[0051] The target operating frequency of each hardware computing unit and the target operating frequency of each hardware control unit are written into the corresponding operating frequency registers of the hardware computing unit and hardware control unit to complete the optimization of the accelerator card.

[0052] Secondly, this application provides an accelerator card optimization system for improving application performance, comprising:

[0053] The acquisition module is used to acquire the computation graph structure generated by the target computing application during runtime, as well as the power consumption distribution data and heat distribution data at the hardware level.

[0054] The extraction module is used to extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph in the computation graph structure;

[0055] The configuration module is used to configure the hardware computing unit corresponding to the parallel computing intensive subgraph in the logical resource array of the accelerator card to the first operating frequency state, and at the same time configure the hardware control unit corresponding to the sequential logic intensive subgraph to the second operating frequency state.

[0056] The coupling module is used to couple the power consumption distribution data and heat distribution data at the hardware level with the physical layout position of the hardware computing unit in the first operating frequency state, so as to generate a frequency adjustment vector related to the physical position of the hardware computing unit in the first operating frequency state.

[0057] The optimization module is used to perform collaborative optimization of the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card according to the frequency adjustment vector and the computation graph structure, so as to complete the optimization of the accelerator card.

[0058] Thirdly, this application provides a computing device, including a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are invoked and executed by the processing component to implement an accelerator card optimization method for improving application performance as described in the first aspect above.

[0059] Fourthly, this application provides a computer storage medium storing a computer program, which, when executed by a computer, implements an accelerator card optimization method for improving application performance as described in the first aspect.

[0060] This application achieves fine-grained frequency control of the accelerator card's computing and control units by combining computation graph analysis with hardware physical state awareness. The method configures the two types of units with differentiated base frequencies based on the characteristics of the computing task, and generates a frequency adjustment vector that reflects local thermal risks by combining real-time power consumption and heat distribution data of the hardware. This enables precise and dynamic frequency management of high-load computing units and effectively avoids global performance loss caused by local overheating.

[0061] Furthermore, based on the data dependencies revealed by the computation graph structure, the frequency adjustment of the computation unit is intelligently transmitted to the associated control unit to achieve collaborative frequency optimization between the two. This mechanism ensures that the hardware units with close cooperation can maintain the frequency matching required for correct computation timing, thereby ensuring high computational efficiency and computational reliability when dealing with complex computational loads and hardware thermal constraints.

[0062] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0063] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0064] Figure 1 A flowchart of an accelerator card optimization method for improving application performance, provided in this application, is shown.

[0065] Figure 2 A schematic diagram of the structure of an accelerator card optimization system for improving application performance is shown in this application;

[0066] Figure 3 A schematic diagram of the structure of a computing device provided in this application is shown. Detailed Implementation

[0067] To enable those skilled in the art to better understand the present application, the technical solution of the present application will be clearly and completely described below with reference to the accompanying drawings.

[0068] In some of the processes described in the specification, claims, and accompanying drawings of this application, multiple operations appearing in a specific order are included. However, it should be clearly understood that these operations may not be executed in the order they appear herein, or may be executed in parallel. The operation numbers, such as 101, 102, etc., are merely used to distinguish different operations and do not themselves represent any execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that the descriptions such as "first," "second," etc., in this document are used to distinguish different messages, devices, modules, etc., and do not represent a chronological order, nor do they limit "first" and "second" to different types.

[0069] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] Figure 1 This application provides a flowchart of an accelerator card optimization method for improving application performance, such as... Figure 1 As shown, the method includes:

[0071] Step 101: Obtain the computation graph structure and hardware-level power consumption and heat distribution data generated during the runtime of the target computing application.

[0072] Optionally, step 101 may specifically include:

[0073] Step 1011: While the target computing application is running on the accelerator card, the computing instruction flow of the target computing application executed on the accelerator card is parsed, and the dependencies and data flow between computing instructions in the computing instruction flow are recorded to form a directed acyclic graph description.

[0074] Step 1012: Simultaneously poll the multiple power consumption sensors and temperature sensors pre-arranged inside the accelerator card chip, and read the real-time measurement values ​​of each power consumption sensor and temperature sensor respectively.

[0075] Step 1013: Establish a mapping relationship between the real-time measurement values ​​of each power consumption sensor and temperature sensor and the physical coordinates of the chip plane of the accelerator card, so that each real-time measurement value corresponds to a known chip plane coordinate position.

[0076] Step 1014: Based on the chip's planar coordinate position, process the real-time measurement values ​​from the power consumption sensor into power consumption distribution data, and process the measurement values ​​from the temperature sensor into heat distribution data.

[0077] In this solution, the target computing application refers to a specific computing task program that executes on the accelerator card to achieve high-performance computing functions, and is obtained through application code written and deployed by the user.

[0078] A computation graph structure is a model that uses graphics to represent the various operational steps and their data dependencies in a computation task. It is used to describe the logical flow of the computation process and is obtained by parsing the instruction flow during runtime.

[0079] Hardware-level power consumption distribution data refers to the set of energy consumption values ​​in different physical areas of the accelerator card chip, which reflects the power consumption of each part of the chip during operation. It is obtained by reading and processing the measurement values ​​of the power consumption sensor integrated on the chip.

[0080] Thermal distribution data refers to the set of temperature values ​​of different physical regions on the accelerator card chip, which is used to reflect the heat generation of various parts of the chip during operation. It is obtained by reading and processing the measurement values ​​of the temperature sensor integrated on the chip.

[0081] An accelerator card is a hardware device specifically designed to improve computing performance. It is inserted into a computer motherboard to run target applications.

[0082] The computation instruction stream refers to a sequence of operation instructions generated when the target computing application is executed on the accelerator card. It describes the execution order of computation steps and is obtained by monitoring the instructions generated during application runtime.

[0083] A directed acyclic graph (DAG) is a graphical structure without circular dependencies, where nodes represent computational operations and edges represent data flow. It is used to clearly represent the dependencies between computational instructions and is obtained by analyzing the sequential relationships in the instruction flow.

[0084] Pre-placed power and temperature sensors refer to miniature measurement elements embedded during the manufacturing process of accelerator card chips. These elements are used to monitor the chip's power consumption and temperature changes in real time and are integrated into the chip circuitry through hardware design. For example, in the design of this accelerator card chip, engineers pre-placed dozens of tiny sensors inside it. Several power sensors are integrated around the GPU core array responsible for massively parallel computing, while several temperature sensors are distributed on the chip surface and in key areas such as heat sink contact points.

[0085] Real-time measurements refer to the actual physical quantities collected by the sensor at a specific point in time. These instantaneous data represent the current state and are obtained by periodically reading the sensor registers.

[0086] Chip planar physical coordinates refer to a two-dimensional positioning system with the surface of the accelerator card chip as a reference. It is used to accurately locate each physical point on the chip and is defined by the coordinate grid provided by the chip design drawings.

[0087] Chip planar coordinate position refers to the specific two-dimensional coordinate value of a point on the chip, used to identify the position of sensors or functional units, and is obtained through coordinate system mapping.

[0088] Power distribution data refers to the set of power consumption values ​​of each region of the chip after processing, forming a spatial distribution pattern, which is used to analyze power hotspots.

[0089] Thermal distribution data refers to the set of temperature values ​​of various regions of a chip after processing, forming a spatial distribution pattern, which is used to analyze areas of heat accumulation.

[0090] In this step, the physical center position of each hardware computing unit on the accelerator card chip plane at the first operating frequency is first identified by coordinate mapping technology, and a circular physical influence range is set for each center position. At the same time, the chip plane coordinate position corresponding to each power measurement point in the power distribution data and each temperature measurement point in the heat distribution data is obtained by sensor data polling technology, and the spatial correspondence between the hardware computing unit position and the sensor monitoring point is established.

[0091] Secondly, the physical influence range of each hardware computing unit is processed by the proximity analysis algorithm. The proximity analysis algorithm calculates the number of power consumption measurement points and temperature measurement points contained within the physical influence range, and obtains the first influence value and the second influence value respectively. Specifically, the operation is to take the center coordinates of each hardware computing unit as the center and the preset radius as the boundary, scan and count the number of all effective sensor measurement points falling into this circular area.

[0092] Then, the first and second influence values ​​are combined using a weighted fusion algorithm. Each measurement point is assigned a distance weight based on its distance from the center of the hardware computing unit; the closer the distance, the higher the weight. All measurement points are then weighted and summed to generate weighted power consumption influence values ​​and weighted temperature influence values. Finally, these two weighted values ​​are combined using a linear combination technique according to a preset global weight factor to generate a coupling value for that hardware computing unit. This process is repeated for all target hardware computing units on the accelerator card, and the coupling values ​​are arranged according to a preset order of the chip planar layout to ultimately form a frequency adjustment vector.

[0093] For example, when running a natural language processing model on a certain AI inference accelerator card of Company A, the core coordinates of the eight hardware computing units responsible for matrix multiplication on the chip are first located using coordinate mapping technology, and an influence area with a radius of 2 mm is set for each hardware computing unit. Next, real-time data and coordinates of 64 temperature sensors and 64 power sensors distributed on the chip are read, and a proximity analysis algorithm is used to identify that five power sensors within the influence area of ​​computing unit 3 have abnormally high readings, while four temperature sensors show a significant temperature increase in that area. Then, a weighted fusion algorithm is used to calculate weights based on the distance between these temperature sensors and the core of unit 3, and combined with preset global weights, to derive an adjustment suggestion that unit 3 needs to appropriately reduce its operating frequency. Finally, after this process is completed on all computing units, a frequency adjustment vector containing eight adjustment values ​​is generated for subsequent collaborative optimization.

[0094] This step can synchronously and accurately capture the internal logic structure of computing applications and the real-time physical state of chips, ensuring that subsequent optimization processes take into account both the characteristics of computing tasks and the actual hardware conditions. This provides a comprehensive and consistent data foundation for dynamic resource adjustments, thereby improving the accuracy and reliability of optimization decisions.

[0095] Step 102: Extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph from the computation graph structure.

[0096] Optionally, step 102 may specifically include:

[0097] Step 1021: Determine the operation mode of the computing nodes in the directed acyclic graph description, identify multiple identical operation instructions that can be executed in parallel from the computing instructions of the computing nodes in the directed acyclic graph description, and integrate the computing nodes corresponding to the multiple identical operation instructions to obtain a set of parallel computing nodes.

[0098] Step 1022: Identify multiple different operation instructions from the computation instructions of the computation nodes described by the directed acyclic graph, and integrate the computation nodes corresponding to the multiple different operation instructions to obtain a set of sequential logical nodes, wherein the multiple different operation instructions have a sequential execution order.

[0099] Step 1023: In the description of the directed acyclic graph, determine the connection edges associated with each computing node in the set of parallel computing nodes, and based on the connection edges, divide the set of parallel computing nodes into a parallel computing dense subgraph with internal edge connections.

[0100] Step 1024: In the description of the directed acyclic graph, determine the connection edges associated with each computing node in the set of sequential logic nodes, and based on the connection edges, divide the set of sequential logic nodes into a dense sequential logic subgraph with internal edge connections.

[0101] In this step, the parallel computation-dense subgraph refers to the subgraph structure extracted from the computation graph, consisting of multiple computation nodes that can be executed simultaneously. It is used to improve the parallel processing efficiency of computation tasks and is obtained by identifying nodes with the same operation instructions and analyzing their connection relationships.

[0102] A sequential logic dense subgraph refers to a subgraph structure extracted from a computation graph, consisting of multiple computation nodes that must be executed in a specific order. It is used to ensure the correctness and dependency of computation logic and is obtained by identifying different operation instruction nodes with sequential execution order and analyzing their connection relationships.

[0103] A set of parallel computing nodes refers to a temporary aggregation of a group of computing nodes that are identified as being capable of parallel execution, serving as the basis for subsequent subgraph partitioning.

[0104] Computation instructions refer to the basic operation command units executed by the accelerator card, which are used to describe the specific behavior of the computing task and are obtained by parsing the instruction stream generated by the target computing application during runtime.

[0105] A sequential logical node set refers to a temporary aggregation of computational nodes that are identified as needing to be executed sequentially, serving as the basis for subsequent subgraph partitioning.

[0106] Multiple different operation instructions refer to different types of operation commands that need to be executed in a strict order in the computation graph. They are used to construct complex logical processes and are obtained by analyzing the dependencies between instructions and the data flow.

[0107] In this step, each computation node in the directed acyclic graph is first processed using instruction flow feature analysis technology. The computation instructions contained in each computation node are parsed, and batch matrix multiplication is used to identify multiple identical operation instructions that can be executed in parallel. All computation nodes corresponding to these identical operation instructions are then aggregated to form a set of parallel computation nodes. At the same time, the instruction flow feature technology identifies multiple different operation instructions in the computation graph that must be executed in a strict order, such as performing data preprocessing before performing model inference. The nodes corresponding to these different operation instructions are then aggregated into a set of sequential logical nodes.

[0108] Secondly, the two node sets are refined using a subgraph connectivity partitioning algorithm. First, the connection edges between nodes in the parallel computing node set are scanned in the directed acyclic graph description. Based on the connection relationship of the edges, the node groups with direct data dependencies are partitioned to form a dense parallel computing subgraph with tight internal connections. Similarly, the same operation is performed on the sequential logic node set. Based on the connection edge relationship between the nodes, a dense sequential logic subgraph with continuous internal dependencies is partitioned.

[0109] For example, following the specific implementation of the previous step, firstly, after successfully running the image recognition application C on the accelerator card B developed by Company A and generating a directed acyclic graph and chip physical state data, the computation mode of the computation nodes in the description of the directed acyclic graph is determined by instruction feature analysis technology; secondly, the instruction feature analysis technology identifies that all nodes performing convolution operations in the computation graph have the same computation instruction structure and no mutual dependency relationship, and integrates these nodes into a set of parallel computing nodes; at the same time, it is identified that the pooling layer and fully connected layer nodes need to be executed in the order of data flow and have different instruction types, and these nodes are integrated into a set of sequential logic nodes;

[0110] Next, the data flow path inside the set of parallel computing nodes is scanned in the description of the directed acyclic graph using a graph connectivity analysis algorithm, and the convolution node group with direct edge connection is divided into an independent parallel computing dense subgraph; then, the dependency relationship of pooling and fully connected nodes in the set of sequential logic nodes is tracked simultaneously, and the sequential logic dense subgraph is divided according to the continuous connection edges between nodes.

[0111] This step accurately distinguishes between parallel computing units and sequential logic units in a computing task, providing a clear task partitioning basis for subsequent resource allocation, while ensuring the correct maintenance of computing dependencies, thereby improving the overall computing efficiency and reliability of the accelerator card.

[0112] Step 103: In the logic resource array of the accelerator card, configure the hardware computing unit corresponding to the parallel computing intensive subgraph to the first operating frequency state, and at the same time configure the hardware control unit corresponding to the sequential logic intensive subgraph to the second operating frequency state.

[0113] Optionally, step 103 may specifically include:

[0114] Step 1031: Locate the hardware computing unit prepared for executing the parallel computing intensive subgraph in the logic resource array of the accelerator card. The hardware computing unit includes a circuit module of an arithmetic logic unit.

[0115] Step 1032: Locate the hardware control unit prepared for executing the sequential logic dense subgraph in the logic resource array of the accelerator card. The hardware control unit includes a circuit module of a status register.

[0116] Step 1033: Obtain the first reference frequency value that matches the working mode of the parallel computing dense subgraph from the preset frequency configuration table.

[0117] Step 1034: Obtain a second reference frequency value that matches the working mode of the sequential logic dense subgraph from a preset frequency configuration table.

[0118] Step 1035: Write the first reference frequency value into the operating frequency register of the hardware computing unit to configure the hardware computing unit to the first operating frequency state.

[0119] Step 1036: Write the second reference frequency value into the operating frequency register of the hardware control unit to configure the hardware control unit to the second operating frequency state.

[0120] In this step, the logic resource array refers to the physical layout set of programmable logic resources on the accelerator card, which is used to allocate and map hardware computing units and control units, and is obtained through wiring planning during chip manufacturing.

[0121] Hardware computing units refer to dedicated circuit modules that perform arithmetic and logical operations, used to process parallel computing tasks, and are obtained by configuring arithmetic logic unit circuits in a logic resource array.

[0122] The first operating frequency state refers to the high-performance frequency mode in which the hardware computing unit operates, which is used to improve computing throughput. It is set by writing a specific frequency value into the operating frequency register.

[0123] The hardware control unit refers to the circuit module that manages the data flow and state sequence, and is used to coordinate sequential logic operations.

[0124] The second operating frequency state refers to the energy-saving frequency mode in which the hardware control unit operates, which is used to reduce power consumption. It is set by writing a lower frequency value to the operating frequency register.

[0125] The circuit module of an arithmetic logic unit refers to the hardware component that performs mathematical operations and logical judgments, used to achieve high-speed computing, and is implemented through integrated circuit design.

[0126] The circuit module of the status register refers to the hardware component that stores operating status information to maintain the continuity of control logic. It is implemented through register circuit design.

[0127] The preset frequency configuration table refers to a database that stores operating frequency parameters in advance. It is used to quickly query frequency values ​​that are adapted to different computing modes. It is obtained through system calibration tests. For example, when the accelerator card starts processing a neural network model task, it first analyzes the computation graph structure of the task to identify which parts belong to parallel computation-intensive subgraphs that can be processed in parallel and which parts belong to sequential logic-intensive subgraphs that must be executed step by step.

[0128] The first reference frequency value refers to the frequency parameter that matches the operating characteristics of the parallel computing intensive subgraph. It is used to initialize the hardware computing unit and is obtained by querying the frequency configuration table.

[0129] The second reference frequency value refers to the frequency parameter that matches the operating characteristics of the sequential logic dense subgraph. It is used to initialize the hardware control unit and is obtained by querying the frequency configuration table.

[0130] In this step, the logic resource array of the accelerator card is first processed using hardware resource mapping technology. This hardware resource mapping technology scans the physical layout of the logic resource array, identifies the circuit modules dedicated to performing arithmetic logic operations, and positions these circuit modules as hardware computing units. At the same time, the control circuit modules containing status registers are identified and positioned as hardware control units. The hardware units are accurately located by parsing the wiring information and functional unit identifiers of the logic resource array.

[0131] Secondly, the preset frequency configuration table is accessed through table lookup retrieval technology. The working mode characteristics of the parallel computing intensive subgraph, such as instruction parallelism and data throughput requirements, are matched with the mode labels in the frequency configuration table to extract the corresponding first reference frequency value. At the same time, the working mode characteristics of the sequential logic intensive subgraph, such as instruction dependency and timing requirements, are matched with the frequency configuration table to extract the second reference frequency value. The frequency configuration table is stored in key-value pair format, with the working mode characteristics as the key and the reference frequency value as the corresponding value.

[0132] Then, the first reference frequency value is transferred to the working frequency register of the hardware computing unit through a direct register write operation, so that it enters the first working frequency state; simultaneously, the second reference frequency value is written to the working frequency register of the hardware control unit, so that it enters the second working frequency state; finally, the physical address of the working frequency register is mapped to the system virtual address space through memory mapping technology, and the value is written directly through memory write instructions.

[0133] For example, following the specific implementation of the previous step, firstly, on the accelerator card B developed by Company A, the computation graph of image recognition application C is successfully decomposed into a parallel computation-intensive subgraph and a sequential logic-intensive subgraph. Then, the hardware recognition program locates the convolutional computation unit containing arithmetic logic units as the hardware computation unit in the logic resource array of the accelerator card B, and simultaneously locates the pooling control unit containing a status register as the hardware control unit. Next, the preset frequency configuration table is accessed, and high-frequency operating parameters are retrieved as the first reference frequency value based on the parallel characteristics of the convolutional subgraph, and low-frequency operating parameters are retrieved as the second reference frequency value based on the sequential characteristics of the pooling subgraph. Finally, the high-frequency values ​​are written to the frequency register of the convolutional computation unit and the low-frequency values ​​are written to the frequency register of the pooling control unit through the register configuration interface, thus completing the differentiated frequency configuration of the hardware units.

[0134] This step can accurately allocate the operating frequency of hardware resources according to the characteristics of the computing task, realize the differentiated configuration of computing units and control units, thereby optimizing energy efficiency while ensuring computing performance, and providing basic hardware configuration conditions for subsequent collaborative optimization.

[0135] Step 104: Couple the power consumption distribution data and heat distribution data at the hardware level with the physical layout location of the hardware computing unit in the first operating frequency state to generate a frequency adjustment vector related to the physical location of the hardware computing unit in the first operating frequency state.

[0136] Optionally, step 104 may specifically include:

[0137] Step 1041: On the chip plane of the accelerator card, determine the central physical coordinates of each hardware computing unit in the first operating frequency state.

[0138] Step 1042: Set a physical influence range for each of the central physical coordinate locations.

[0139] Step 1043: On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each power measurement point in the power distribution data.

[0140] Step 1044: On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each temperature measurement point in the thermal distribution data.

[0141] Step 1045: Count the number of all power consumption measurement points within the physical influence range of the hardware computing unit in the first operating frequency state to obtain the first influence value.

[0142] Step 1046: Count the number of all temperature measurement points within the physical influence range of the hardware computing unit operating at the first operating frequency state to obtain the second influence value.

[0143] Step 1047: The first influence value and the second influence value are weighted and combined to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state.

[0144] Optionally, step 1047 may specifically include the following steps: calculating the distance factors of each power consumption measurement point and each temperature measurement point within the physical influence range of each hardware computing unit in the first operating frequency state relative to the center position of the hardware computing unit; determining a first distance weight and a second distance weight for each power consumption measurement point based on the distance factors; performing a weighted summation of all power consumption measurement point data within the physical influence range based on the first distance weight to obtain a weighted power consumption influence value; performing a weighted summation of all temperature measurement point data within the physical influence range based on the second distance weight to obtain a weighted temperature influence value; multiplying the weighted power consumption influence value by a preset third weight factor, multiplying the weighted temperature influence value by a preset fourth weight factor, and adding the two product results to generate a coupling value related to the physical position of the hardware computing unit in the first operating frequency state.

[0145] Step 1048: Repeatedly perform statistical and weighted combination operations on all hardware computing units on the accelerator card that are in the first operating frequency state to obtain multiple coupling values ​​corresponding to all hardware computing units in the first operating frequency state.

[0146] Step 1049: Arrange multiple coupling values ​​according to a preset order of the hardware computing units on the chip plane to obtain a frequency adjustment vector.

[0147] In this step, the physical layout location refers to the actual two-dimensional coordinates of the hardware computing unit on the surface of the accelerator card chip, which is used to identify the physical location of the computing unit and is obtained through the coordinate system of the chip design drawings.

[0148] A frequency adjustment vector is a sequence of values ​​arranged in a specific order, used to represent the amount of frequency adjustment required for each hardware computing unit.

[0149] The central physical coordinate position refers to a two-dimensional coordinate point with reference to the geometric center of the hardware computing unit. It is used to accurately locate the core position of the computing unit and is obtained by averaging the boundary coordinates of the computing unit.

[0150] The physical influence range refers to the circular area surrounding the central coordinates, used to define the range of sensor data that affects the computing unit, and is set by a preset radius parameter.

[0151] The first impact value refers to the statistical value of the number of power consumption measurement points within the physical influence range, which is used to reflect the energy consumption intensity of the area and is obtained through counting operations.

[0152] The second impact value refers to the statistical value of the number of temperature measurement points within the physical influence range, which is used to reflect the degree of heat load in the area and is obtained through counting operations.

[0153] The coupling value is a composite index value that takes into account the combined effects of power consumption and temperature, and is used to evaluate the degree of frequency adjustment required by the computing unit.

[0154] The distance factor refers to the relative distance between the measurement point and the center of the calculation unit. It is used to measure spatial correlation and is obtained through the coordinate distance calculation formula.

[0155] The first distance weight refers to the importance coefficient of the power consumption measurement point based on the distance factor, which is used to reflect the priority of near-field influence and is calculated through the distance attenuation function.

[0156] The second distance weight refers to the importance coefficient of the temperature measurement point based on the distance factor, which is used to reflect the locality of heat propagation and is calculated through the distance attenuation function.

[0157] The weighted power consumption impact value is a comprehensive measure that takes into account the power consumption impact of distance weighting, and is used to correct for simple counting bias.

[0158] The weighted temperature influence value is a comprehensive measure of the thermal influence that takes into account distance weights, and is used to improve the accuracy of thermal assessments.

[0159] The preset third weighting factor refers to the importance parameter of power consumption in the coupled calculation. It is used to balance the contribution of power consumption and temperature. It is obtained through system calibration. For example, if the preset third weighting factor is 0.7 and the fourth weighting factor is 0.3, it indicates that the decision tends to consider power consumption. Then the coupling value of the unit is calculated to be 13.41. This result reflects the impact of high power consumption more. It is more likely that the frequency of the computing unit will be reduced significantly to reduce energy consumption.

[0160] The preset fourth weighting factor refers to the importance parameter of temperature influence in the coupling calculation. It is used to adjust the weight of thermal factors in the decision-making process and is obtained through system calibration. For example, if the system presets the third weighting factor to be 0.3 and the fourth weighting factor to be 0.7, it indicates that the decision is more inclined to prevent overheating. The coupling value is calculated to be 14.49. This result more strongly reflects the influence of high temperature and is more likely to instruct the heat dissipation system to strengthen the cooling of this area, while making a small adjustment to the frequency.

[0161] In this step, the physical layout of the accelerator card chip is first processed by spatial positioning technology. This spatial positioning technology reads the hardware design file of the accelerator card and identifies the center coordinates of each hardware computing unit in the first operating frequency state on the two-dimensional plane of the chip. Then, a circular physical influence range is set for each center coordinate, and the physical influence range is bounded by a preset radius to define the sensor data acquisition area that may have a thermal or power consumption impact on the computing unit.

[0162] Secondly, by using coordinate mapping technology, the discrete measurement points in the power distribution data and heat distribution data are associated with the chip plane coordinates. The preset physical coordinates of each power sensor and temperature sensor are queried, and their real-time measurement values, such as power consumption and temperature values, are marked on the chip coordinate map, thereby forming a sensor data map with spatial location covering the entire chip.

[0163] Then, the physical influence range of each hardware computing unit is scanned by the proximity analysis algorithm. The number of power consumption measurement points and temperature measurement points contained in each circular influence range is calculated. The first influence value reflects the local energy consumption intensity and the second influence value reflects the local heat load. The Euclidean distance between the measurement point and the center of the unit is calculated and it is determined whether it is less than the preset radius.

[0164] Finally, a weighted fusion algorithm is used to convert all values ​​into adjustment parameters. First, a distance factor is calculated based on the distance between each measurement point and the center of the computing unit. The closer the distance, the higher the weight. Then, the weight is used to sum all power consumption and temperature measurements within the range to obtain the weighted power consumption impact value and the weighted temperature impact value. Subsequently, these two weighted values ​​are multiplied and summed with the preset global weight factors, the third weight factor and the fourth weight factor, respectively, to generate the final coupling value for the computing unit. Finally, this process is repeated for all target hardware computing units, and the coupling values ​​are arranged according to their layout order on the chip to generate the final frequency adjustment vector.

[0165] For example, following the specific implementation of the previous step, after completing the frequency configuration of the hardware computing units on the accelerator card B developed by Company A, the coupling analysis of power consumption heat distribution and physical location is started; secondly, the center coordinates of the 8 high-frequency computing units are located, and a circular influence area with a radius of 2 mm is set for each unit; then, the measurement values ​​of 64 power consumption sensors and 64 temperature sensors are mapped onto the chip coordinate diagram, and then the number of sensors within the influence range of computing unit 3 is counted, finding that it includes 5 power consumption sensors and 4 temperature sensors; then, the distance between each sensor and the center of unit 3 is calculated, and higher weights are assigned to the closer sensors. After weighted summation, a weighted power consumption value of 12.6 and a weighted temperature value of 15.3 are obtained; finally, these two values ​​are multiplied and added with preset weight factors of 0.7 and 0.3 to obtain a coupling value of 13.41. Finally, the calculation results of all units are arranged in the chip layout order to form a frequency adjustment vector.

[0166] This step effectively integrates real-time physical state data of the hardware with spatial location information of the computing unit to generate frequency adjustment suggestions that reflect the local operating state, providing data support for subsequent precise frequency control, thereby improving the stability and energy efficiency of the accelerator card under complex loads.

[0167] Step 105: Based on the frequency adjustment vector and the computation graph structure, perform collaborative optimization on the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card to complete the optimization of the accelerator card.

[0168] Optionally, step 105 may specifically include:

[0169] Step 1051: Based on the frequency adjustment vector, calculate the frequency offset corresponding to the hardware computing unit of each first operating frequency state.

[0170] Step 1052: Based on the computation graph structure, determine the hardware control unit with the second operating frequency state that has a data exchange relationship with each hardware computing unit.

[0171] Step 1053: Calculate the accompanying frequency offset corresponding to the hardware control unit for each second operating frequency state based on the frequency offset and the data exchange relationship.

[0172] Step 1054: Combine the current operating frequency of each hardware computing unit with the corresponding frequency offset to obtain the target operating frequency of each hardware computing unit.

[0173] Step 1055: Combine the current operating frequency of each hardware control unit with the corresponding accompanying frequency offset to obtain the target operating frequency of each hardware control unit.

[0174] Step 1056: Write the target operating frequency of each hardware computing unit and the target operating frequency of each hardware control unit into the corresponding operating frequency registers of the hardware computing unit and hardware control unit to complete the optimization of the accelerator card.

[0175] In this step, the frequency offset refers to the frequency adjustment value calculated for each hardware computing unit based on physical state data, which reflects the independent frequency adjustment required by that unit.

[0176] Data exchange relationships refer to the data transfer dependencies between hardware computing units and hardware control units in a computation graph structure. They are used to determine the unit pairs that require coordinated frequency adjustment and are obtained by analyzing the connection edges of a directed acyclic graph.

[0177] The accompanying frequency offset refers to the corresponding frequency adjustment value calculated for the control unit based on the data exchange relationship. It is used to maintain the timing synchronization between the computing unit and the control unit and is obtained through the frequency offset propagation algorithm.

[0178] The current operating frequency refers to the operating frequency value of the hardware unit before optimization, which serves as the reference value for frequency adjustment and is obtained by reading the operating frequency register.

[0179] The target operating frequency refers to the target operating frequency of the hardware unit after co-optimization, which is used to achieve the best balance between performance and power consumption.

[0180] In this step, the coupling value corresponding to each hardware computing unit in the frequency adjustment vector is first analyzed by frequency offset calculation technology. The coupling value is then multiplied by a preset adjustment coefficient to generate the frequency offset of each hardware computing unit. The numerical multiplication operation is also implemented by an arithmetic logic unit to convert the coupling value representing the influence of physical state into a specific frequency adjustment value.

[0181] Secondly, by traversing the connection edges described by the directed acyclic graph using graph analysis technology, we can identify the hardware control units directly connected to each hardware computing unit, establish a data exchange relationship mapping table, and use the adjacency list query algorithm to determine the data flow and dependencies between units by scanning the outgoing and incoming edges of each computing node.

[0182] Next, the frequency offset and data exchange relationship are processed through a collaborative optimization algorithm. The frequency offset of all hardware computing units connected to each hardware control unit is statistically analyzed. The average value is calculated using a weighted average algorithm and then multiplied by a preset collaborative adjustment coefficient to generate the accompanying frequency offset. The statistical calculation is performed through an accumulator and a divider to ensure that the frequency adjustment of the control unit is synchronized with the associated computing unit.

[0183] Then, the current operating frequency and offset are processed by frequency synthesis technology. First, an arithmetic adder is used to add the current operating frequency of each hardware computing unit to its frequency offset to obtain the target operating frequency; at the same time, the current operating frequency of each hardware control unit is added to its associated frequency offset to obtain its target operating frequency.

[0184] Finally, the target operating frequency is configured to the hardware through direct register write technology. Through memory-mapped input / output operations, the calculated target operating frequency value is written to the operating frequency register of the corresponding hardware unit according to the address. This process uses direct memory access technology to ensure that the frequency configuration value is accurately written to the specified hardware register.

[0185] For example, following the specific implementation of the previous step, after obtaining the frequency adjustment vector on the accelerator card B developed by Company A, the coupling values ​​corresponding to the eight high-frequency computing units in the frequency adjustment vector are analyzed and multiplied by the adjustment coefficient 0.8 to obtain the frequency offset. Then, the computing graph structure is analyzed, and it is found that there is a direct data connection between computing unit 3 and control unit 5, and a correspondence is established. Then, the average value of the frequency offset of all connected computing units of control unit 5 is calculated and multiplied by the coordination coefficient 0.6 to obtain the accompanying frequency offset. Finally, the current frequency of computing unit 3 (1.2GHz) is added to the offset of 0.15GHz to obtain the target frequency of 1.35GHz, and the current frequency of control unit 5 (800MHz) is added to the accompanying offset of 90MHz to obtain the target frequency of 890MHz. These values ​​are then written into the corresponding registers to complete the optimization.

[0186] This step establishes a frequency coordination mechanism between the computing unit and the control unit, which ensures the correctness of the computing timing while realizing the dynamic optimization of hardware resources, effectively improving the overall energy efficiency and task execution efficiency of the accelerator card.

[0187] Figure 2 This application provides a schematic diagram of the structure of an accelerator card optimization system for improving application performance, as shown below. Figure 2 As shown, the system includes:

[0188] The acquisition module 21 is used to acquire the computation graph structure generated by the target computing application during runtime, as well as the power consumption distribution data and heat distribution data at the hardware level.

[0189] Extraction module 22 is used to extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph in the computation graph structure;

[0190] The configuration module 23 is used to configure the hardware computing unit corresponding to the parallel computing intensive subgraph in the logic resource array of the accelerator card to the first operating frequency state, and at the same time configure the hardware control unit corresponding to the sequential logic intensive subgraph to the second operating frequency state.

[0191] The coupling module 24 is used to couple the power consumption distribution data and heat distribution data at the hardware level with the physical layout position of the hardware computing unit in the first operating frequency state, so as to generate a frequency adjustment vector related to the physical position of the hardware computing unit in the first operating frequency state.

[0192] The optimization module 25 is used to perform collaborative optimization of the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card according to the frequency adjustment vector and the computation graph structure, so as to complete the optimization of the accelerator card.

[0193] Figure 2 The aforementioned accelerator card optimization system for improving application performance can execute... Figure 1 The implementation principle and technical effects of the accelerator card optimization method for application performance improvement described in the illustrated embodiment will not be repeated here. The specific methods by which each module and unit performs operations in the accelerator card optimization system for application performance improvement described in the above embodiments have been described in detail in the embodiments related to this method, and will not be elaborated upon here.

[0194] In one possible design, Figure 2 An accelerator card optimization system for application performance improvement, as shown in the embodiment, can be implemented as a computing device, such as... Figure 3 As shown, the computing device may include a storage component 31 and a processing component 32;

[0195] The storage component 31 stores one or more computer instructions, wherein the one or more computer instructions are invoked and executed by the processing component 32.

[0196] The processing component 32 is used for the above Figure 1 The embodiment describes an accelerator card optimization method for improving application performance.

[0197] The processing component 32 may include one or more processors to execute computer instructions to complete all or part of the steps in the above-described method. Alternatively, the processing component may be implemented as one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to perform the above-described method.

[0198] Storage component 31 is configured to store various types of data to support operations at the terminal. The storage component can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0199] Of course, computing devices may also include other components, such as input / output interfaces, display components, communication components, etc.

[0200] Input / output interfaces provide interfaces between processing components and peripheral interface modules, which can be output devices, input devices, etc.

[0201] The communication components are configured to facilitate wired or wireless communication between computing devices and other devices.

[0202] The computing device can be a physical device or an elastic computing host provided by a cloud computing platform. In this case, the computing device can refer to a cloud server, and the aforementioned processing components, storage components, etc., can be basic server resources rented or purchased from the cloud computing platform.

[0203] This application also provides a computer storage medium storing a computer program, which, when executed by a computer, can perform the above-described functions. Figure 1 The embodiment shown illustrates an accelerator card optimization method for improving application performance.

[0204] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0205] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0206] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0207] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. An accelerator card optimization method for improving application performance, characterized in that, include: Acquire the computation graph structure generated by the target computing application during runtime, as well as the power consumption and heat distribution data at the hardware level; Extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph from the computation graph structure; In the logical resource array of the accelerator card, the hardware computing unit corresponding to the parallel computing intensive subgraph is configured to the first operating frequency state, and the hardware control unit corresponding to the sequential logic intensive subgraph is configured to the second operating frequency state. The power consumption distribution data and heat distribution data at the hardware level are coupled with the physical layout location of the hardware computing unit in the first operating frequency state to generate a frequency adjustment vector related to the physical location of the hardware computing unit in the first operating frequency state. Based on the frequency adjustment vector and the computation graph structure, the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card are collaboratively optimized to complete the optimization of the accelerator card.

2. The method according to claim 1, characterized in that, Obtain the computation graph structure generated during the runtime of the target computing application, as well as the power consumption and heat distribution data at the hardware level, including: While the target computing application is running on the accelerator card, the computing instruction flow of the target computing application executed on the accelerator card is parsed, and the dependencies and data flow between computing instructions in the computing instruction flow are recorded to form a directed acyclic graph description. At the same time, the multiple power consumption sensors and temperature sensors pre-arranged inside the accelerator card chip are polled, and the real-time measurement values ​​of each power consumption sensor and temperature sensor are read. The real-time measurement values ​​of each power consumption sensor and temperature sensor are mapped to the physical coordinates of the chip plane of the accelerator card, so that each real-time measurement value corresponds to a known chip plane coordinate position. Based on the chip's planar coordinate position, the real-time measurement values ​​from the power consumption sensor are processed into power consumption distribution data, and the measurement values ​​from the temperature sensor are processed into heat distribution data.

3. The method according to claim 2, characterized in that, Extracting the parallel computation-intensive subgraph and the sequential logic-intensive subgraph from the computation graph structure, including: The computation mode of the computation nodes in the directed acyclic graph is determined. From the computation instructions of the computation nodes in the directed acyclic graph, multiple identical computation instructions that can be executed in parallel are identified, and the computation nodes corresponding to the multiple identical computation instructions are integrated to obtain a set of parallel computation nodes. From the computation instructions of the computation nodes described by the directed acyclic graph, multiple different operation instructions are identified, and the computation nodes corresponding to the multiple different operation instructions are integrated to obtain a set of sequential logical nodes, wherein the multiple different operation instructions have a sequential execution order; In the description of the directed acyclic graph, the connection edges associated with each computing node in the set of parallel computing nodes are determined, and based on the connection edges, a parallel computing dense subgraph with internal edge connections is partitioned in the set of parallel computing nodes. In the description of the directed acyclic graph, the connection edges associated with each computation node in the set of sequential logic nodes are determined, and based on the connection edges, a dense sequential logic subgraph with internal edge connections is partitioned in the set of sequential logic nodes.

4. The method according to claim 1, characterized in that, In the logic resource array of the accelerator card, the hardware computing units corresponding to the parallel computing-intensive subgraphs are configured to a first operating frequency state, and the hardware control units corresponding to the sequential logic-intensive subgraphs are configured to a second operating frequency state, including: Within the logic resource array of the accelerator card, a hardware computing unit prepared for executing the parallel computing intensive subgraph is located, the hardware computing unit comprising a circuit module of an arithmetic logic unit. Within the logic resource array of the accelerator card, a hardware control unit prepared for executing the sequential logic-dense subgraph is located, the hardware control unit comprising a circuit module of a status register; Obtain a first reference frequency value that matches the working mode of the parallel computing dense subgraph from a preset frequency configuration table; Obtain a second reference frequency value that matches the operating mode of the sequential logic dense subgraph from a preset frequency configuration table; Write the first reference frequency value into the operating frequency register of the hardware computing unit to configure the hardware computing unit to the first operating frequency state. The second reference frequency value is written into the operating frequency register of the hardware control unit to configure the hardware control unit to the second operating frequency state.

5. The method according to claim 1, characterized in that, The power consumption distribution data and heat distribution data at the hardware level are coupled with the physical layout location of the hardware computing unit in the first operating frequency state to generate a frequency adjustment vector related to the physical location of the hardware computing unit in the first operating frequency state, including: On the chip plane of the accelerator card, determine the central physical coordinate position of each hardware computing unit in the first operating frequency state; A physical influence range is defined for each of the central physical coordinate locations; On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each power measurement point in the power distribution data; On the chip plane of the accelerator card, determine the chip plane coordinates corresponding to each temperature measurement point in the thermal distribution data; The number of all power consumption measurement points within the physical influence range of the hardware computing unit operating at the first operating frequency is counted to obtain the first influence value; The number of all temperature measurement points within the physical influence range of the hardware computing unit operating at the first frequency is counted to obtain the second influence value; The first influence value and the second influence value are weighted and combined to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state. For all hardware computing units on the accelerator card that are in the first operating frequency state, the statistical operation and weighted combination operation are repeatedly performed to obtain multiple coupling values ​​corresponding to all hardware computing units in the first operating frequency state. Multiple coupling values ​​are arranged in a preset order on the chip plane according to the hardware computing units to obtain a frequency adjustment vector.

6. The method according to claim 5, characterized in that, The first influence value and the second influence value are weighted and combined to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state, including: Calculate the distance factor of each power consumption measurement point and each temperature measurement point relative to the center position of the hardware computing unit within the physical influence range of each hardware computing unit in the first operating frequency state. Based on the distance factor, determine the first distance weight for each power consumption measurement point and the second distance weight for each temperature measurement point; Based on the first distance weight, the power consumption measurement point data of all power consumption measurement points within the physical influence range are weighted and summed to obtain the weighted power consumption influence value; Based on the second distance weight, the data of all temperature measurement points within the physical influence range are weighted and summed to obtain the weighted temperature influence value; The weighted power consumption influence value is multiplied by a preset third weighting factor, and the weighted temperature influence value is multiplied by a preset fourth weighting factor. The two product results are added together to generate a coupling value related to the physical location of the hardware computing unit in the first operating frequency state.

7. The method according to claim 1, characterized in that, Based on the frequency adjustment vector and the computation graph structure, the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card are collaboratively optimized to complete the optimization of the accelerator card, including: Based on the frequency adjustment vector, calculate the frequency offset corresponding to the hardware computing unit for each first operating frequency state; Based on the computation graph structure, determine the hardware control unit with a second operating frequency state that has a data exchange relationship with each hardware computing unit; Based on the frequency offset and the data exchange relationship, calculate the accompanying frequency offset corresponding to the hardware control unit for each second operating frequency state; The target operating frequency of each hardware computing unit is obtained by combining the current operating frequency of each hardware computing unit with the corresponding frequency offset. The target operating frequency of each hardware control unit is obtained by combining the current operating frequency of each hardware control unit with the corresponding accompanying frequency offset. The target operating frequency of each hardware computing unit and the target operating frequency of each hardware control unit are written into the corresponding operating frequency registers of the hardware computing unit and hardware control unit to complete the optimization of the accelerator card.

8. An accelerator card optimization system for improving application performance, characterized in that, include: The acquisition module is used to acquire the computation graph structure generated by the target computing application during runtime, as well as the power consumption distribution data and heat distribution data at the hardware level. The extraction module is used to extract the parallel computation-intensive subgraph and the sequential logic-intensive subgraph in the computation graph structure; The configuration module is used to configure the hardware computing unit corresponding to the parallel computing intensive subgraph in the logical resource array of the accelerator card to the first operating frequency state, and at the same time configure the hardware control unit corresponding to the sequential logic intensive subgraph to the second operating frequency state. The coupling module is used to couple the power consumption distribution data and heat distribution data at the hardware level with the physical layout position of the hardware computing unit in the first operating frequency state, so as to generate a frequency adjustment vector related to the physical position of the hardware computing unit in the first operating frequency state. The optimization module is used to perform collaborative optimization of the hardware computing unit in the first operating frequency state and the hardware control unit in the second operating frequency state on the accelerator card according to the frequency adjustment vector and the computation graph structure, so as to complete the optimization of the accelerator card.

9. A computing device, characterized in that, It includes a processing component and a storage component; the storage component stores one or more computer instructions; the one or more computer instructions are invoked and executed by the processing component to implement the accelerator card optimization method for improving application performance as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that, The device contains a computer program that, when executed by a computer, implements an accelerator card optimization method for improving application performance as described in any one of claims 1 to 7.

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