Scanning driver and electronic device including the same

Abstract

The invention discloses a scan driver and an electronic device including the same. The scan driver includes: a stage including: an input circuit controlling a voltage of a first node in response to a signal at a first input terminal and a second input terminal; a first signal processing circuit controlling a voltage of a second node in response to a signal at the first input terminal, and supplying a voltage of a first power source to the second node in response to a signal at the second input terminal; a second signal processing circuit supplying a voltage of a second power supply to the first node in response to a signal at a third input terminal and a voltage of a second node; a first output circuit outputting a signal at the third input terminal as a first scan signal; and a second output circuit that outputs a signal at the fourth input terminal as a second scan signal at a timing different from the first scan signal.

Description

[0001] This application is a divisional application of the invention patent application filed on July 5, 2021, with application number 202110757323.5 and entitled "Scan Driver".

[0002] Cross-references to related applications

[0003] This application claims priority to Korean Patent Application No. 10-2020-0083646, filed on July 7, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] This invention relates to a display device. More specifically, this invention relates to a display device including a scan driver. Background Technology

[0005] For example, a display device is an output device used to represent information in a visual form. A display device, such as an organic light-emitting display device, includes a data driver for supplying data signals to data lines, a scan driver for supplying scan signals to scan lines, an emission driver for supplying emission control signals to emission control lines, and pixels connected to the data lines, scan lines, and emission control lines.

[0006] Reducing the size of non-display areas, such as the bezel of a display device, can result in a larger screen without increasing the device's overall size. Therefore, various studies have been conducted to minimize non-display areas, such as the bezel of a display device. Summary of the Invention

[0007] According to an exemplary embodiment of the present invention, a scan driver is provided, comprising: a stage configured to output a scan signal, wherein the stage includes: an input circuit that controls a voltage of a first node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; a first signal processing circuit that controls a voltage of a second node in response to a signal supplied to the first input terminal and supplies a voltage of a first power supply to the second node in response to a signal supplied to the second input terminal; a second signal processing circuit that supplies a voltage of a second power supply to the first node in response to a signal supplied to a third input terminal and a voltage of the second node; a first output circuit that outputs a signal supplied to the third input terminal as a first scan signal based on the voltage of the first node and the voltage of the second node; and a second output circuit that outputs a signal supplied to a fourth input terminal as a second scan signal based on the voltage of the first node and the voltage of the second node, wherein the second scan signal and the first scan signal are output at different times.

[0008] The signal supplied to the second input terminal can be a first clock signal, the signal supplied to the third input terminal can be a second clock signal, and the signal supplied to the fourth input terminal can be a third clock signal. The gate conduction level of the first clock signal, the gate conduction level of the second clock signal, and the gate conduction level of the third clock signal can be non-overlapping.

[0009] The first output circuit may include: a sixth transistor connected between the first node and the third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and the first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node; and a second capacitor connected between the third node and the first output terminal.

[0010] The second output circuit may include: a ninth transistor connected between the first node and the fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between the fourth input terminal and the second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node; and a third capacitor connected between the fourth node and the second output terminal.

[0011] The input circuit may include a first transistor connected between a first input terminal and a first node, wherein the first transistor has a gate electrode connected to a second input terminal.

[0012] The first signal processing circuit may include: a second transistor connected between a second input terminal and a second node, wherein the second transistor has a gate electrode connected to a first node; and a third transistor connected between a first power supply and the second node, wherein the third transistor has a gate electrode connected to the second input terminal.

[0013] The second signal processing circuit may include a fourth transistor and a fifth transistor connected in series between the first node and the second power supply, the gate electrode of the fourth transistor being connected to the second node, and the gate electrode of the fifth transistor being connected to the third input terminal.

[0014] The second signal processing circuit may further include a first capacitor connected between the second node and the second power supply.

[0015] The first input terminal can be supplied with a start pulse or a second scan signal output from the previous stage.

[0016] The second scan signal can be offset relative to the first scan signal.

[0017] According to an exemplary embodiment of the present invention, a display device is provided, comprising: a pixel; a scan driver including a stage for supplying a scan signal to the pixel via a scan line; a data driver for supplying a data signal to the pixel via a data line; and a timing controller for controlling the scan driver and the data driver, wherein at least one stage includes: an input circuit that controls a voltage of a first node in response to a signal supplied to a first input terminal and a signal supplied to a second input terminal; and a first signal processing circuit that controls a voltage of a second node in response to a signal supplied to the first input terminal and a signal supplied to a second input terminal. The system comprises: a first power supply voltage supplied to a second node in response to a signal at a third input terminal; a second signal processing circuit that supplies a second power supply voltage to a first node in response to a signal at a third input terminal and a voltage at a second node; a first output circuit that outputs a signal supplied to a third input terminal as a first scan signal based on the voltage at the first node and the voltage at the second node; and a second output circuit that outputs a signal supplied to a fourth input terminal as a second scan signal based on the voltage at the first node and the voltage at the second node, wherein the second scan signal is output at a different time than the first scan signal.

[0018] The second input terminal may be provided with a first clock signal, the third input terminal may be provided with a second clock signal, and the fourth input terminal may be provided with a third clock signal, and the gate conduction level of the first clock signal, the gate conduction level of the second clock signal, and the gate conduction level of the third clock signal may not overlap with each other.

[0019] The first output circuit may include: a sixth transistor connected between the first node and the third node, wherein the sixth transistor has a gate electrode connected to the first power supply; a seventh transistor connected between the third input terminal and the first output terminal, wherein the seventh transistor has a gate electrode connected to the third node; an eighth transistor connected between the first output terminal and the second power supply, wherein the eighth transistor has a gate electrode connected to the second node; and a second capacitor connected between the third node and the first output terminal.

[0020] The second output circuit may include: a ninth transistor connected between the first node and the fourth node, wherein the ninth transistor has a gate electrode connected to the first power supply; a tenth transistor connected between the fourth input terminal and the second output terminal, wherein the tenth transistor has a gate electrode connected to the fourth node; an eleventh transistor connected between the second output terminal and the second power supply, wherein the eleventh transistor has a gate electrode connected to the second node; and a third capacitor connected between the fourth node and the second output terminal.

[0021] The input circuit may include: a first transistor connected between a first input terminal and a first node, wherein the first transistor has a gate electrode connected to a second input terminal; and wherein the first signal processing circuit includes: a second transistor connected between a second input terminal and a second node, wherein the second transistor has a gate electrode connected to the first node; and a third transistor connected between a first power supply and the second node, wherein the third transistor has a gate electrode connected to the second input terminal.

[0022] The second signal processing circuit may include: a fourth transistor and a fifth transistor connected in series between the first node and the second power supply; and a first capacitor connected between the second node and the second power supply, wherein the gate electrode of the fourth transistor is connected to the second node and the gate electrode of the fifth transistor is connected to the third input terminal.

[0023] The first input terminal can be provided with a start pulse or a second scan signal output from the previous stage.

[0024] The second scan signal can be offset relative to the first scan signal.

[0025] According to an exemplary embodiment of the present invention, a scan driver is provided, comprising: a stage including a first output circuit and a second output circuit, wherein the first output circuit includes: a first transistor connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply; a second transistor connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to a third node; and a third transistor connected between the first output terminal and a second power supply, wherein the third transistor has a gate electrode connected to a second node, wherein the second output circuit includes: a fourth transistor connected between the first node and a fourth node, wherein the fourth transistor has a gate electrode connected to the first power supply; a fifth transistor connected between a second clock terminal and a second output terminal, wherein the fifth transistor has a gate electrode connected to the fourth node; and a sixth transistor connected between the second output terminal and the second power supply, wherein the sixth transistor has a gate electrode connected to the second node.

[0026] A first clock terminal may be supplied with a first clock signal and a second clock terminal may be supplied with a second clock signal, wherein the low level of the first clock signal and the low level of the second clock signal may not overlap.

[0027] The first output circuit can be configured to output a first scan signal to a first output terminal at a first moment, and the second output circuit can be configured to output a second scan signal to a second output terminal at a second moment different from the first moment.

[0028] The first and second scan signals can be based on the voltage of the second node, which can be generated in response to a third clock signal. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0030] Figure 2 This is a block diagram illustrating a scan driver according to an exemplary embodiment of the present invention.

[0031] Figure 3 This illustrates an exemplary embodiment of the invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0032] Figure 4 This illustrates an exemplary embodiment of the invention. Figure 3 The timing diagram of the operations at the level.

[0033] Figure 5 It is used to illustrate exemplary embodiments of the present invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0034] Figure 6 This illustrates an exemplary embodiment of the invention. Figure 2 The circuit diagram of the stages included in the scan driver. Detailed Implementation

[0035] In the following, exemplary embodiments of the present invention will be described in further detail with reference to the accompanying drawings. The same reference numerals may refer to the same elements in the drawings, and therefore, redundant descriptions of the same elements may be omitted.

[0036] Figure 1 This is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0037] Reference Figure 1 The display device 1000 may include a pixel unit 100, a scan driver 200, a transmit driver 300, a data driver 400, and a timing controller 500.

[0038] The display device 1000 can display images at various drive frequencies (or image refresh rates and screen refresh rates) depending on certain driving conditions. The drive frequency is the frequency at which data signals are written to the driving transistors of pixels PX. For example, the drive frequency can be referred to as the screen refresh rate or screen playback frequency, and represents the frequency at which the display screen plays content for one second. In other words, the drive frequency can be the frequency at which an image is displayed on the display screen for one second. The display device 1000 can display images in response to various drive frequencies from 1Hz to 120Hz.

[0039] Pixel unit 100 may include scan lines SL1 to SLn, emission control lines EL1 to ELn, and data lines DL1 to DLm. Pixel unit 100 may include pixels PX connected to scan lines SL1 to SLn, emission control lines EL1 to ELn, and data lines DL1 to DLm (where m and n are integers greater than 1). Each pixel PX may include a driving transistor, a plurality of switching transistors, and at least one light-emitting element. Pixel PX may receive voltages from a first driving power supply VDD and a second driving power supply VSS from the outside.

[0040] In an exemplary embodiment of the present invention, the light-emitting element may be an organic light-emitting diode (OLED) including an organic light-emitting layer. In another exemplary embodiment of the present invention, the light-emitting element may be an inorganic light-emitting element formed of inorganic materials. In another exemplary embodiment of the present invention, the light-emitting element may be a light-emitting element composed of inorganic and organic materials.

[0041] Furthermore, pixel PX can be connected to one or more scan lines SLi (where i is a natural number n or smaller) and emission control lines ELi corresponding to the pixel's circuit structure. For example, Figure 1 The example pixel PX shown is connected to the i-th scan line SLi, the j-th data line DLj (j is a natural number m or less), and the i-th emission control line ELi.

[0042] The timing controller 500 can receive input control signals and input image signals from an image source such as an external graphics device. Based on the input image signals, the timing controller 500 generates image data RGB suitable for the operating conditions of the pixel unit 100 and provides the image data RGB to the data driver 400. The timing controller 500 can generate a first control signal SCS for controlling the drive timing of the scan driver 200, a second control signal ECS for controlling the drive timing of the transmit driver 300, and a third control signal DCS for controlling the drive timing of the data driver 400, based on the input control signals. The timing controller 500 can provide the first control signal SCS, the second control signal ECS, and the third control signal DCS to the scan driver 200, the transmit driver 300, and the data driver 400, respectively.

[0043] The scan driver 200 can receive a first control signal SCS from the timing controller 500. The scan driver 200 can supply scan signals to scan lines SL1 to SLn in response to the first control signal SCS. The first control signal SCS may include multiple clock signals and a start pulse for the scan signals.

[0044] The scan signal can be set to a gate on-state voltage (e.g., logic low) corresponding to the type of transistor to which the scan signal is supplied. The transistor receiving the scan signal can be turned on when the scan signal is supplied. For example, the gate on-state voltage of the scan signal supplied to a P-channel metal-oxide-semiconductor (PMOS) transistor can be logic low, and the gate on-state voltage of the scan signal supplied to an N-channel metal-oxide-semiconductor (NMOS) transistor can be logic high. Hereinafter, the phrase "scan signal supplied" can mean that the scan signal is supplied at a logic level capable of turning on the transistor controlled by the scan signal.

[0045] In an exemplary embodiment of the present invention, the stages included in the scan driver 200 can be connected to multiple scan lines. The stages can supply scan signals to the scan lines to which they are connected at different times. For example, a stage of the scan driver 200 can supply a first scan signal to a first scan line at a different time than when it supplies a second scan signal to a second scan line.

[0046] The transmit driver 300 can receive a second control signal ECS from the timing controller 500. The transmit driver 300 can supply transmit control signals to transmit control lines EL1 to ELn in response to the second control signal ECS. The second control signal ECS may include multiple clock signals and a start pulse for the transmit control signal.

[0047] The transmit control signal can be set to a gate on-state voltage (e.g., a low voltage). The transistor receiving the transmit control signal can be turned on when the transmit control signal is supplied and can be turned off under other conditions. In the following text, the phrase "the transmit control signal is supplied" can mean that the transmit control signal is supplied at a logic level that enables the transistor controlled by the transmit control signal to turn on.

[0048] In an exemplary embodiment of the present invention, the stages included in the transmit driver 300 can be connected to multiple transmit control lines. Each stage can supply transmit control signals to the transmit control lines to which it is connected at different times. For example, a stage of the transmit driver 300 can supply a first transmit control signal to a first transmit control line at a different time than when it supplies a second transmit control signal to a second transmit control line.

[0049] exist Figure 1In this illustration, for ease of description, each of the scan driver 200 and the transmit driver 300 is shown as a single unit, but the invention is not limited thereto. According to an exemplary embodiment of the invention, the scan driver 200 may include a plurality of scan drivers that respectively supply at least one scan signal of scan signals of different waveforms. Furthermore, at least a portion of the scan driver 200 and the transmit driver 300 may be integrated into a single drive circuit or module, etc.

[0050] The data driver 400 can receive a third control signal DCS from the timing controller 500. The data driver 400 can convert the image data RGB into an analog data signal (e.g., data voltage) in response to the third control signal DCS, and can supply the data signal to the data lines DL1 to DLm.

[0051] In an exemplary embodiment of the present invention, the display device 1000 may further include a power supply. The power supply may supply the voltage of a first driving power supply VDD and a second driving power supply VSS for driving the pixel PX to the pixel unit 100.

[0052] Figure 2 This is a block diagram illustrating a scan driver according to an exemplary embodiment of the present invention.

[0053] exist Figure 2 For ease of description, four stages and the scan signals output from them will be shown.

[0054] Reference Figure 1 and Figure 2 The scan driver 200 may include multiple stages comprising a first stage ST1, a second stage ST2, a third stage ST3, and a fourth stage ST4. For example, the first stage ST1 to the fourth stage ST4 may be connected to the first scan line SL1, the second scan line SL2, the third scan line SL3, the fourth scan line SL4, the fifth scan line SL5, the sixth scan line SL6, the seventh scan line SL7, and the eighth scan line SL8, respectively, and may output scan signals in response to the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3. The first stage ST1 to the fourth stage ST4 may be implemented using substantially the same circuitry.

[0055] Although the first stage ST1 to the fourth stage ST4 of the scan drive 200 are in Figure 2 The example shown is merely illustrative. For instance, the transmitter driver 300 could also have... Figure 2 The first stage ST1 through the fourth stage ST4 have essentially the same or similar configuration. In this case, the first stage ST1 through the fourth stage ST4 can output transmit control signals.

[0056] In an exemplary embodiment of the present invention, each of the first stage ST1 to the fourth stage ST4 may be connected to two scan lines. For example, the first stage ST1 may be connected to the first scan line SL1 and the second scan line SL2. The first stage ST1 may supply a first scan signal S(1) to the first scan line SL1 and a second scan signal S(2) to the second scan line SL2. The first scan line SL1 may be connected to the first pixel row (e.g., the first horizontal line) of the pixel unit 100, and the second scan line SL2 may be connected to the second pixel row (e.g., the second horizontal line) of the pixel unit 100. The first scan signal S(1) and the second scan signal S(2) may have substantially the same pulse and may be output at different times. For example, the second scan signal S(2) may be a signal that offsets the first scan signal S(1) by a predetermined time period. In other words, the second scan signal S(2) may be offset relative to the first scan signal S(1).

[0057] Similarly, the second stage ST2 can be connected to the third scan line SL3 and the fourth scan line SL4. The second stage ST2 can supply the third scan signal S(3) to the third scan line SL3 and the fourth scan signal S(4) to the fourth scan line SL4. The third stage ST3 can supply the fifth scan signal S(5) to the fifth scan line SL5 and the sixth scan signal S(6) to the sixth scan line SL6. The fourth stage ST4 can supply the seventh scan signal S(7) to the seventh scan line SL7 and the eighth scan signal S(8) to the eighth scan line SL8.

[0058] For ease of description, the first scan signal S(1) to the eighth scan signal S(8) are arbitrarily defined, and the first scan signal S(1) to the eighth scan signal S(8) can have substantially the same pulse and can be output at different times.

[0059] Furthermore, the connection relationships between the first scan lines SL1 to the eighth scan lines SL8 and the horizontal lines (e.g., pixel rows) can be set differently depending on the pixel structure and driving method of the display device 1000. For example, the first scan line SL1 connected to the first level ST1 can be connected to multiple horizontal lines (or pixel rows).

[0060] Each of the first level ST1 to the fourth level ST4 may include a first input terminal 101, a second input terminal 102, a third input terminal 103, a fourth input terminal 104, a first output terminal 105, and a second output terminal 106.

[0061] The first input terminal 101 can receive a start pulse SSP or an output signal (e.g., a second scan signal S(2)) output from the second output terminal 106 of the previous stage. For example, the first input terminal 101 of the first stage ST1 can receive the start pulse SSP, and the first input terminal 101 of the second stage ST2 can receive the second scan signal S(2) output from the first stage ST1.

[0062] In an exemplary embodiment of the present invention, the second input terminal 102 of the k-th stage (here, k is a natural number) can receive the first clock signal CLK1, the third input terminal 103 of the k-th stage can receive the second clock signal CLK2, and the fourth input terminal 104 of the k-th stage can receive the third clock signal CLK3. Conversely, the second input terminal 102 of the (k+1)-th stage can receive the third clock signal CLK3, the third input terminal 103 of the (k+1)-th stage can receive the first clock signal CLK1, and the fourth input terminal 104 of the (k+1)-th stage can receive the second clock signal CLK2. The second input terminal 102 of the (k+2)-th stage can receive the second clock signal CLK2, the third input terminal 103 of the (k+2)-th stage can receive the third clock signal CLK3, and the fourth input terminal 104 of the (k+2)-th stage can receive the first clock signal CLK1.

[0063] The first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 have the same period, and the phases of the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 do not overlap. In other words, the gate on level (e.g., logic low) of the first clock signal CLK1, the gate on level (e.g., logic low) of the second clock signal CLK2, and the gate on level (e.g., logic low) of the third clock signal CLK3 do not overlap. For example, each of the second clock signal CLK2 and the third clock signal CLK3 can be configured as a signal with a different time offset from the first clock signal CLK1.

[0064] Furthermore, stages ST1 through ST4 receive the voltages of the first power supply VGL and the second power supply VGH. The voltages of both power supplies VGL and VGH can have DC voltage levels. The voltage of the second power supply VGH can be set to be greater than the voltage of the first power supply VGL.

[0065] The voltage of the first power supply VGL can be set to a gate-on level, and the voltage of the second power supply VGH can be set to a gate-off level. For example, when the pixel PX is composed of a PMOS transistor, the voltage of the first power supply VGL (e.g., a gate-on level) can correspond to a low level, and the voltage of the second power supply VGH (e.g., a gate-off level) can correspond to a high level. However, this is only an example, and the first power supply VGL and the second power supply VGH are not limited thereto. For example, the voltage of the first power supply VGL and the voltage of the second power supply VGH can be set depending on the type of transistor and the operating environment of the display device 1000, etc.

[0066] Figure 3 This illustrates an exemplary embodiment of the invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0067] Reference Figure 2 and Figure 3 The k-th level STk (where k is a natural number) may include an input circuit 210, a first signal processing circuit 220, a second signal processing circuit 230, a first output circuit 240, and a second output circuit 250.

[0068] like Figure 3 The diagram illustrates a k-th stage STk in which a first clock signal CLK1 is supplied to the second input terminal 102, a second clock signal CLK2 is supplied to the third input terminal 103, and a third clock signal CLK3 is supplied to the fourth input terminal 104. However, this is merely exemplary, and in the (k+1)-th stage, the third clock signal CLK3 can be supplied to the second input terminal 102, the first clock signal CLK1 can be supplied to the third input terminal 103, and the second clock signal CLK2 can be supplied to the fourth input terminal 104. In the (k+2)-th stage, the second clock signal CLK2 can be supplied to the second input terminal 102, the third clock signal CLK3 can be supplied to the third input terminal 103, and the first clock signal CLK1 can be supplied to the fourth input terminal 104.

[0069] In an exemplary embodiment of the present invention, the start pulse SSP can be supplied to the first input terminal 101 of the first stage ST1, and the scan signal output from the second output terminal 106 of the previous stage can be supplied to the first input terminal 101 of other stages.

[0070] In the following text, the k-th level STk will be referred to as level STk.

[0071] The input circuit 210 can control the voltage of the first node N1 in response to signals supplied to the first input terminal 101 and the second input terminal 102. In an exemplary embodiment of the present invention, the input circuit 210 may include a first transistor T1.

[0072] The first transistor T1 may be connected between the first input terminal 101 and the first node N1. The first transistor T1 may include a gate electrode connected to the second input terminal 102. The first transistor T1 may be turned on when the first clock signal CLK1 has a gate on level (e.g., low level) to electrically connect the first input terminal 101 and the first node N1.

[0073] The first signal processing circuit 220 can control the voltage of the second node N2 in response to a signal supplied to the first input terminal 101, and can supply the voltage of the first power supply VGL to the second node N2 in response to a signal supplied to the second input terminal 102. In an exemplary embodiment of the present invention, the first signal processing circuit 220 may include a second transistor T2 and a third transistor T3.

[0074] The second transistor T2 can be connected between the second input terminal 102 and the second node N2. The gate electrode of the second transistor T2 can be connected to the first node N1. The second transistor T2 can be turned on or off in response to the voltage of the first node N1.

[0075] In an exemplary embodiment of the invention, the second transistor T2 may include a plurality of sub-transistors connected in series with each other. Each of the sub-transistors may include a gate electrode (e.g., a dual-gate structure) commonly connected to the first node N1. Therefore, current leakage caused by the second transistor T2 can be minimized. However, this is merely exemplary, and at least one of the other transistors, as well as the second transistor T2, may have a dual-gate structure.

[0076] The third transistor T3 can be connected between the first power supply terminal 107, which receives the voltage of the first power supply VGL, and the second node N2. The gate electrode of the third transistor T3 can be connected to the second input terminal 102. The third transistor T3 can be turned on when the first clock signal CLK1 is supplied to the second input terminal 102 to supply the voltage of the first power supply VGL to the second node N2.

[0077] The second signal processing circuit 230 can supply the voltage of the second power supply VGH to the first node N1 in response to the signal supplied to the third input terminal 103 and the voltage of the second node N2. In an exemplary embodiment of the present invention, the second signal processing circuit 230 may include a fourth transistor T4, a fifth transistor T5, and a first capacitor C1.

[0078] The fourth transistor T4 and the fifth transistor T5 can be connected in series between the first node N1 and the second power supply terminal 108, which is supplied with the second power supply VGH. The gate electrode of the fourth transistor T4 can be connected to the second node N2. The gate electrode of the fifth transistor T5 can be connected to the third input terminal 103.

[0079] The fourth transistor T4 can be turned on or off in response to the voltage at the second node N2.

[0080] The fifth transistor T5 can be turned on in response to the gate conduction level of the second clock signal CLK2 supplied to the third input terminal 103.

[0081] A first capacitor C1 can be connected between the second node N2 and the second power supply terminal 108. The voltage difference between the voltage of the second node N2 and the voltage of the second power supply VGH can be charged into the first capacitor C1. The first capacitor C1 can be used to stably maintain (or hold) the low level of the second node N2 by the voltage of the second power supply VGH, which is a DC voltage.

[0082] The first output circuit 240 can output the signal supplied to the third input terminal 103 as the i-th scan signal S(i) (i is an integer k or greater) to the first output terminal 105 based on the voltage of the first node N1 and the voltage of the second node N2. In an exemplary embodiment of the present invention, the first output circuit 240 may include a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a second capacitor C2.

[0083] A sixth transistor T6 can be connected between the first node N1 and the third node N3. The gate electrode of the sixth transistor T6 can be connected to the first power supply terminal 107, which is supplied with the voltage of the first power supply VGL. Therefore, the sixth transistor T6 can be in a conducting state. When the voltage of the third node N3 drops below the voltage of the first power supply VGL due to coupling (or boosting) through the second capacitor C2, the voltage of the first node N1 can be maintained relatively stable by the sixth transistor T6. For example, the voltage of the first node N1 is not lower than the voltage of the first power supply VGL. Therefore, even if the voltage change of the third node N3 is large, the amplitude of the drain-source voltage of the first transistor T1 can be prevented from increasing suddenly, and the bias stress that can be applied to the first transistor T1 can be reduced. Therefore, the first transistor T1 can be protected from the voltage fluctuations of the third node N3.

[0084] The seventh transistor T7 can be connected between the third input terminal 103 and the first output terminal 105. The gate electrode of the seventh transistor T7 can be connected to the third node N3. For example, the gate electrode of the seventh transistor T7 can be connected between the sixth transistor T6 and the second capacitor C2. The seventh transistor T7 can be turned on or off in response to the voltage of the third node N3. Here, the i-th scan signal S(i) supplied to the first output terminal 105 can be at a low level (e.g., the gate on-state voltage of the P-type transistor) when the seventh transistor T7 is turned on.

[0085] The eighth transistor T8 can be connected between the first output terminal 105 and the second power supply VGH (e.g., the second power supply terminal 108). The gate electrode of the eighth transistor T8 can be connected to the second node N2. The eighth transistor T8 can be turned on or off based on the voltage of the second node N2. When the eighth transistor T8 is turned on, the i-th scan signal S(i) supplied to the first output terminal 105 can have a high level (e.g., the gate turn-off voltage of a P-type transistor).

[0086] The second capacitor C2 can be connected between the third node N3 and the first output terminal 105. The second capacitor C2 can couple the voltage of the first output terminal 105 and the voltage of the third node N3. For example, the second capacitor C2 can boost the voltage of the third node N3 based on the voltage of the first output terminal 105.

[0087] The second output circuit 250 can output the signal supplied to the fourth input terminal 104 as the (i+1)th scan signal S(i+1) to the second output terminal 106 based on the voltage of the first node N1 and the voltage of the second node N2. In an exemplary embodiment of the present invention, the second output circuit 250 may include a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, and a third capacitor C3.

[0088] The configuration and operation of the second output circuit 250 can be similar to that of the first output circuit 240.

[0089] The ninth transistor T9 can be connected between the first node N1 and the fourth node N4. For example, the ninth transistor T9 can be connected to the sixth transistor T6 (first node N1) and the third capacitor C3. The gate electrode of the ninth transistor T9 can be connected to the first power supply VGL (e.g., the first power supply terminal 107). Therefore, the ninth transistor T9 can be in a conducting state. When the voltage of the fourth node N4 drops below the voltage of the first power supply VGL due to coupling (e.g., boost) through the third capacitor C3, the voltage of the first node N1 can be maintained relatively stable by the ninth transistor T9. Therefore, the first transistor T1 can be protected from voltage fluctuations at the fourth node N4.

[0090] The tenth transistor T10 can be connected between the fourth input terminal 104 and the second output terminal 106. The gate electrode of the tenth transistor T10 can be connected to the fourth node N4. The tenth transistor T10 can be turned on or off in response to the voltage of the fourth node N4. Here, the i+1th scan signal S(i+1) supplied to the second output terminal 106 can be at a low level (e.g., the gate on-state voltage of a P-type transistor) when the tenth transistor T10 is turned on.

[0091] The eleventh transistor T11 can be connected between the second output terminal 106 and the second power supply VGH (e.g., the second power supply terminal 108). The gate electrode of the eleventh transistor T11 can be connected to the second node N2. The gate electrode of the eleventh transistor T11 can also be connected to the first capacitor C1. The eleventh transistor T11 can be turned on or off based on the voltage at the second node N2.

[0092] The third capacitor C3 can be connected between the fourth node N4 and the second output terminal 106. The third capacitor C3 can couple the voltage of the second output terminal 106 and the voltage of the fourth node N4.

[0093] As described above, the first output circuit 240 and the second output circuit 250 can share the first node N1 and the second node N2, and can output the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1) respectively by using the time difference of clock signals CLK2 and CLK3 with gate conduction level supplied to the third input terminal 103 and the fourth input terminal 104. Therefore, stage STk can stably output the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1) with the same waveform at different times using only three clock signals CLK1, CLK2 and CLK3. Although the first output circuit 240 and the second output circuit 250 share a similar configuration, the first output circuit 240 receives the second clock signal CLK2 via the third input terminal 103 and the second output circuit 250 receives the third clock signal CLK3 via the fourth input terminal 104.

[0094] Therefore, the area occupied by the scan driver 200 in the display device 1000 can be reduced. In addition, multiple different scan signals can be output from a single stage STk using a minimum number of first clock signals CLK1, second clock signals CLK2 and third clock signals CLK3 and a line structure, so as to reduce the manufacturing cost and power consumption of the display device 1000.

[0095] Figure 4 This illustrates an exemplary embodiment of the invention. Figure 3 The timing diagram of the operations at the level.

[0096] Reference Figure 1 , Figure 3 and Figure 4 The first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be supplied at different times. The gate on level (e.g., logic low) of the first clock signal CLK1, the gate on level (e.g., logic low) of the second clock signal CLK2, and the gate on level (e.g., logic low) of the third clock signal CLK3 do not overlap with each other.

[0097] For example, the second clock signal CLK2 can be set to a signal offset by a horizontal time period from the first clock signal CLK1, and the third clock signal CLK3 can be set to a signal offset by a horizontal time period from the second clock signal CLK2. The first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can be activated sequentially.

[0098] A high level (or high voltage) of the start pulse SSP can correspond to the voltage of the second power supply VGH, and a low level (or low voltage) of the start pulse SSP can correspond to the voltage of the first power supply VGL. For example, the voltage of the first power supply VGL can be approximately -8V, and the voltage of the second power supply VGH can be approximately 10V. However, this is only an example, and the voltage level of the start pulse is not limited thereto.

[0099] Furthermore, the low level of the third node N3 can be similar to the value obtained by adding the absolute value of the threshold voltage of the sixth transistor T6 to the voltage of the first power supply VGL. However, because the threshold voltage of the sixth transistor T6 is very small compared to the voltage of the first power supply VGL, the low levels of the third node N3, the fourth node N4, the first power supply VGL, the low level of the start pulse SSP, and the low level of the scan signal can be substantially the same as or similar to each other and will be described below.

[0100] Furthermore, a 2-low level (e.g., the voltage at the third node N3 from the third time point t3 to the fourth time point t4) can be similar to... The voltage level.

[0101] The following description will depict how, when the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are supplied, the voltage of the first power supply VGL (or a low-level voltage, gate-on voltage) is supplied to each of the second input terminals 102, the third input terminal 103, and the fourth input terminal 104. Furthermore, when the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 are not supplied, the voltage of the second power supply VGH (or a high-level voltage, gate-off voltage) is supplied to each of the second input terminals 102, the third input terminal 103, and the fourth input terminal 104.

[0102] The (i-1)th scan signal S(i-1) is high after the second time point t2.

[0103] The (i-1)th scan signal S(i-1) can be supplied to the first input terminal 101 at the first time point t1, and the first clock signal CLK1 can be supplied to the second input terminal 102. In other words, between the first time point t1 and the second time point t2, the (i-1)th scan signal S(i-1) and the first clock signal CLK1 can be at a low level.

[0104] The first transistor T1 can be turned on by the first clock signal CLK1, and the voltage of the first node N1 can be at a low level. The voltages of the third node N3 and the fourth node N4 can be changed to a low level by the sixth transistor T6 and the ninth transistor T9, which are in the on state.

[0105] Furthermore, the second transistor T2 can be turned on in response to a low-level voltage at the first node N1, and the third transistor T3 can be turned on in response to a low-level first clock signal CLK1. Therefore, the second node N2 can have a low-level voltage.

[0106] The supply of the (i-1)th scan signal S(i-1) and the first clock signal CLK1 can be stopped at the second time point t2. In other words, both the (i-1)th scan signal S(i-1) and the first clock signal CLK1 can transition to a high level at the second time point t2. Because the voltage of the first node N1 is maintained at a low level, the second transistor T2 can be turned on at the second time point t2. Therefore, the high level of the first clock signal CLK1 can be supplied to the second node N2, and the voltage of the second node N2 can transition to a high level at the second time point t2.

[0107] The second clock signal CLK2 can be supplied to the third input terminal 103 at the third time point t3. Because the voltage of the first output terminal 105 is switched to a low level by the second clock signal CLK2, the voltage of the third node N3 can be switched to a 2-low level through the coupling of the second capacitor C2. In other words, the voltage of the third node N3 can drop or even go lower between the third time point t3 and the fourth time point t4. Therefore, the seventh transistor T7 can be fully turned on so that the low-level i-th scan signal S(i) can be output to the first output terminal 105.

[0108] The supply of the second clock signal CLK2 can be stopped at the fourth time point t4, and the voltage of the first output terminal 105 can be changed to a high level. Therefore, the voltage of the third node N3 can be changed to a low level. The output of the i-th scan signal S(i) can be stopped at the fourth time point t4. In other words, the high level of the i-th scan signal S(i) is output at the fourth time point t4.

[0109] The third clock signal CLK3 can be supplied to the fourth input terminal 104 at the fifth time point t5. Because the voltage of the second output terminal 106 is switched to a low level by the third clock signal CLK3, the voltage of the fourth node N4 can be switched to a 2-low level through the coupling of the third capacitor C3. In other words, the voltage of the fourth node N4 can drop or even go lower between the fifth time point t5 and the sixth time point t6. Therefore, the tenth transistor T10 can be fully turned on so that the low-level i+1 scan signal S(i+1) can be output to the second output terminal 106.

[0110] The supply of the third clock signal CLK3 can be stopped at the sixth time point t6, and the voltage of the second output terminal 106 can be changed to a high level. Therefore, the voltage of the fourth node N4 can be changed to a low level. The output of the (i+1)th scan signal S(i+1) can be stopped at the sixth time point t6. In other words, the high level of the (i+1)th scan signal S(i+1) is output at the sixth time point t6.

[0111] As described above, the i-th scan signal S(i) can be output synchronously with the second clock signal CLK2, and the (i+1)-th scan signal S(i+1) can be output synchronously with the third clock signal CLK3. For example, the low levels of the i-th scan signal S(i) and the second clock signal CLK2 can overlap, and the low levels of the (i+1)-th scan signal S(i+1) and the third clock signal CLK3 can overlap.

[0112] The first clock signal CLK1 can be supplied to the second input terminal 102 again at the seventh time point t7. The first transistor T1 can be turned on in response to the first clock signal CLK1, and the voltage of the first node N1 can be switched to a high level. Therefore, the voltages of the third node N3 and the fourth node N4 can also be switched to a high level by the turned-on sixth transistor T6 and ninth transistor T9.

[0113] Furthermore, the third transistor T3 can be turned on at the seventh time point t7 in response to the first clock signal CLK1, and the voltage of the first power supply VGL can be supplied to the second node N2. Therefore, the voltage of the second node N2 can switch to a low level.

[0114] The fourth transistor T4 can be turned on in response to the low voltage at the second node N2. Because the voltage of the second power supply VGH, which is a DC voltage, is supplied to one terminal of the first capacitor C1, the voltage at the second node N2 can be stably maintained at a low level after the seventh time point t7.

[0115] Subsequently, the second clock signal CLK2 can be supplied to the third input terminal 103 at the eighth time point t8. The fifth transistor T5 can be turned on in response to the second clock signal CLK2, and the voltage of the second power supply VGH can be supplied to the first node N1 through the fifth transistor T5 and the fourth transistor T4. In other words, after the seventh time point t7, the voltage of the second power supply VGH is periodically supplied to the first node N1 through the second clock signal CLK2 so that the voltages of the third node N3 and the fourth node N4 can be stably maintained at a high level.

[0116] As described above, stage STk can use a simple structure that shares all configurations except for the first output circuit 240 and the second output circuit 250, and only three clock signals CLK1, CLK2 and CLK3 to stably output the i-th scan signal S(i) and the i+1-th scan signal S(i+1) with the same waveform at different times.

[0117] Therefore, the area occupied by the scan driver 200 in the display device 1000, the manufacturing cost of the display device 1000, and the power consumption can be reduced.

[0118] according to Figures 1 to 4In the exemplary embodiment of the invention shown, the scan driver 200 includes a stage STk configured to output a scan signal, wherein the stage STk includes: an input circuit 210 that controls the voltage of a first node N1 in response to a signal supplied to a first input terminal 101 and a signal supplied to a second input terminal 102; a first signal processing circuit 220 that controls the voltage of a second node N2 in response to a signal supplied to the first input terminal 101 and supplies the voltage of a first power supply VGL to the second node N2 in response to a signal supplied to the second input terminal 102; and a second signal processing circuit... Path 230, the second signal processing circuit 230 supplies the voltage of the second power supply VGH to the first node N1 in response to the signal supplied to the third input terminal 103 and the voltage of the second node N2; the first output circuit 240 outputs the signal supplied to the third input terminal 103 as the i-th scan signal S(i) based on the voltage of the first node N1 and the voltage of the second node N2; and the second output circuit 250 outputs the signal supplied to the fourth input terminal 104 as the (i+1)-th scan signal S(i+1) based on the voltage of the first node N1 and the voltage of the second node N2. The (i+1)-th scan signal S(i+1) and the i-th scan signal S(i) are output at different times.

[0119] Figure 5 It is used to illustrate exemplary embodiments of the present invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0120] exist Figure 5 In this context, the same reference numerals may be used for reference. Figure 3 The aforementioned constituent elements, and therefore, can be omitted from repeated descriptions of these constituent elements. Furthermore, Figure 5 The level STk_A can have the same Figure 3 The configuration of the STk stage is basically the same or similar, except for the configuration of the input terminal connected to the gate electrode of the fifth transistor T5.

[0121] Reference Figure 4 and Figure 5 The STk_A stage may include an input circuit 210, a first signal processing circuit 220, a second signal processing circuit 230, a first output circuit 240, and a second output circuit 250.

[0122] In an exemplary embodiment of the present invention, the gate electrode of the fifth transistor T5 may be connected to the fourth input terminal 104. The fifth transistor T5 may be turned on in response to the third clock signal CLK3.

[0123] Because the second signal processing circuit 230 periodically supplies the voltage of the second power supply VGH to the first node N1 for a period of time after the seventh time point t7, the gate electrode of the fifth transistor T5 can be connected to the third input terminal 103 or the fourth input terminal 104. Therefore, after the seventh time point t7, the voltage of the second power supply VGH is periodically supplied to the first node N1 through the third clock signal CLK3 so that the voltages of the third node N3 and the fourth node N4 can be stably maintained at a high level.

[0124] Figure 6 This illustrates an exemplary embodiment of the invention. Figure 2 The circuit diagram of the stages included in the scan driver.

[0125] exist Figure 6 In this context, the same reference numerals may be used for reference. Figure 3 The aforementioned constituent elements, and therefore, can be omitted from repeated descriptions of these constituent elements. Furthermore, Figure 6 The level STk_B can have the same Figure 3 The STk stage has essentially the same or similar configuration, except for the type of transistor and the voltage levels of the input and output signals.

[0126] Reference Figure 6 The STk_B stage may include an input circuit 210, a first signal processing circuit 220, a second signal processing circuit 230, a first output circuit 240, and a second output circuit 250.

[0127] The first transistor T1 through the eleventh transistor T11 can be n-type transistors. Therefore, the first clock signal CLK1, the second clock signal CLK2, and the third clock signal CLK3 can have the same characteristics as... Figure 4 The waveform is the opposite of the waveform. In addition, the voltage of the second power supply VGH can be supplied to the first power supply terminal 107, and the voltage of the first power supply VGL can be supplied to the second power supply terminal 108.

[0128] Therefore, the i-th scan signal S(i) and the (i+1)-th scan signal S(i+1) can be expressed as... Figure 4 The output waveform is the opposite of the waveform. Figure 6 The STk_B level can be applied to pixels, scan drivers, and display devices driven by n-type transistors.

[0129] As described above, the scan driver and display device according to exemplary embodiments of the present invention may include stages sharing a configuration other than the first output circuit and the second output circuit, and have a simple structure for implementing multiple outputs of scan signals. Furthermore, a single stage can stably output scan signals of the same waveform at different times using three clock signals.

[0130] Therefore, the area occupied by the scan driver in the display device, the manufacturing cost of the display device, and the power consumption can be reduced.

[0131] Although the invention has been shown and described with reference to exemplary embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made thereto without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A scan driver, comprising: The stage includes a first output circuit and a second output circuit. The first output circuit includes: A first transistor is connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply terminal; A second transistor is connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to the third node; and A third transistor is connected between the first output terminal and the second power supply terminal, wherein the third transistor has a gate electrode connected to the second node. The second output circuit includes: A fourth transistor, connected between the second clock terminal and the second output terminal, wherein the fourth transistor has a gate electrode connected to a fourth node; and A fifth transistor is connected between the second output terminal and the second power supply terminal, wherein the fifth transistor has a gate electrode connected to the second node. Wherein, the first output circuit is configured to output a first scan signal to the first output terminal at a first moment, and the second output circuit is configured to output a second scan signal to the second output terminal at a second moment different from the first moment. The first node is electrically connected to the fourth node.

2. The scan driver according to claim 1, in, When the first transistor is turned on, the first node and the fourth node are electrically connected.

3. The scan driver according to claim 1, in, The stage further includes a capacitor connected between the second node and the second power supply terminal.

4. The scan driver according to claim 1, in, The sixth transistor comprises multiple sub-transistors connected in series with each other, and Each of the plurality of sub-transistors includes a gate electrode that is commonly connected to a third clock terminal.

5. The scan driver according to claim 1, in, The first clock signal supplied to the first clock terminal is different from the second clock signal supplied to the second clock terminal.

6. The scan driver according to claim 5, wherein, The level further includes: An input circuit that controls the voltage of the first node in response to a signal supplied to a first input terminal and a signal supplied to a third clock terminal.

7. The scan driver according to claim 6, wherein, The input circuit includes: The sixth transistor is connected between the first input terminal and the first node.

8. The scan driver according to claim 6, wherein, The signal supplied to the first input terminal is a third clock signal, and The gate conduction levels of the first clock signal, the second clock signal, and the third clock signal do not overlap.

9. The scan driver according to claim 6, wherein, The level further includes: A first signal processing circuit controls the voltage of the second node in response to the signal supplied to the first input terminal, and supplies the voltage of the first power supply terminal to the second node in response to the signal supplied to the third clock terminal; and The second signal processing circuit supplies the voltage of the second power supply terminal to the first node in response to the signal supplied to the first clock terminal and the voltage of the second node.

10. The scan driver according to claim 9, wherein, The first signal processing circuit includes: A seventh transistor is connected between the second input terminal and the second node; and The eighth transistor is connected between the first power terminal and the second node.

11. The scan driver according to claim 9, wherein, The second signal processing circuit includes: The seventh transistor and the eighth transistor are connected in series between the first node and the second power supply terminal.

12. The scan driver according to claim 9, wherein, The voltage level at the second power terminal is higher than the voltage level at the first power terminal.

13. A scan driver, comprising: The stage includes a first output circuit and a second output circuit. The first output circuit includes: A first transistor is connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply terminal; A second transistor is connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to the third node; and The third transistor is connected between the first output terminal and the second power supply terminal. The second output circuit includes: A fourth transistor, connected between the second clock terminal and the second output terminal, wherein the fourth transistor has a gate electrode connected to a fourth node; and The fifth transistor is connected between the second output terminal and the second power supply terminal. Wherein, the first output circuit is configured to output a first scan signal to the first output terminal at a first moment, and the second output circuit is configured to output a second scan signal to the second output terminal at a second moment different from the first moment. The third node and the fourth node are electrically connected via the first node.

14. The scan driver according to claim 13, in, The gate electrode of the third transistor and the gate electrode of the fifth transistor are both connected to the second node.

15. The scan driver according to claim 13, wherein, The level further includes: A sixth transistor is connected between the first node and the fourth node, wherein the sixth transistor has a gate electrode connected to the first power supply terminal.

16. A scan driver, comprising: The stage includes a first output circuit and a second output circuit. The first output circuit includes: A first transistor is connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply terminal; A second transistor is connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to the third node; and The third transistor is connected between the first output terminal and the second power supply terminal. The second output circuit includes: A fourth transistor is connected between the first node and the fourth node, wherein the fourth transistor has a gate electrode connected to the first power supply terminal; A fifth transistor, connected between the second clock terminal and the second output terminal, wherein the fifth transistor has a gate electrode connected to the fourth node; and The sixth transistor is connected between the second output terminal and the second power supply terminal. The third node and the fourth node are electrically connected via the first node.

17. The scan driver according to claim 16, in, The gate electrode of the third transistor and the gate electrode of the sixth transistor are both connected to the second node.

18. A scan driver, comprising: The stage includes a first output circuit and a second output circuit. The first output circuit includes: A first transistor is connected between a first clock terminal and a first output terminal, wherein the first transistor has a gate electrode connected to a third node; and A second transistor is connected between the first output terminal and the second power supply terminal, wherein the second transistor has a gate electrode connected to the second node. The second output circuit includes: A third transistor is connected between the first node and the fourth node, wherein the third transistor has a gate electrode connected to the first power supply terminal; A fourth transistor, connected between the second clock terminal and the second output terminal, wherein the fourth transistor has a gate electrode connected to the fourth node; and A fifth transistor is connected between the second output terminal and the second power supply terminal, wherein the fifth transistor has a gate electrode connected to the second node. Wherein, the first output circuit is configured to output a first scan signal to the first output terminal at a first moment, and the second output circuit is configured to output a second scan signal to the second output terminal at a second moment different from the first moment. The first node is electrically connected to the third node.

19. The scan driver according to claim 18, in, When the third transistor is turned on, the first node and the third node are electrically connected.

20. An electronic device comprising: A pixel unit includes a pixel and a scan line connected to the pixel; as well as A scan driver includes multiple stages for supplying scan signals to the pixels via the scan lines. The multiple stages include a first output circuit and a second output circuit. The first output circuit includes: A first transistor is connected between a first node and a third node, wherein the first transistor has a gate electrode connected to a first power supply terminal; A second transistor is connected between a first clock terminal and a first output terminal, wherein the second transistor has a gate electrode connected to the third node; and A third transistor is connected between the first output terminal and the second power supply terminal, wherein the third transistor has a gate electrode connected to the second node. The second output circuit includes: A fourth transistor, connected between the second clock terminal and the second output terminal, wherein the fourth transistor has a gate electrode connected to a fourth node; and A fifth transistor is connected between the second output terminal and the second power supply terminal, wherein the fifth transistor has a gate electrode connected to the second node. Specifically, the first output circuit is configured to output a first scan signal from the scan signal to the first output terminal at a first moment, and the second output circuit is configured to output a second scan signal from the scan signal to the second output terminal at a second moment different from the first moment. The first node is electrically connected to the fourth node.

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