Semiconductor integrated circuit

Abstract

Embodiments of the present invention provide a semiconductor integrated circuit capable of suppressing a deviation in a read current in a semiconductor integrated circuit in which a potential level is controlled using charge sharing. A semiconductor integrated circuit according to an embodiment controls a potential level using charge sharing, in which a calculation is performed in a semiconductor correction circuit using a potential level controlled by the charge sharing between a plurality of circuit blocks including a plurality of memory cells and a global circuit block, the global circuit block including a plurality of memory cells. The potential level is set as a potential level of a read line for reading out data provided in accordance with a state of the memory cell.

Description

[0001] Related applications

[0002] This application enjoys priority to Japanese Patent Application No. 2024-164833 (filed on September 24, 2024) and Japanese Patent Application No. 2025-045747 (filed on March 19, 2025). This application incorporates the entire contents of the basic applications by reference to them. Technical Field

[0003] Embodiments of the present invention relate to semiconductor integrated circuits. Background Technology

[0004] In conventional semiconductor integrated circuits with a standard architecture, computations were performed by processors such as MPUs, and data was stored in memory.

[0005] In contrast, in recent years, in the memory of semiconductor integrated circuits, CiM (Computing in Memory or In-memory computing) has been proposed, which performs operations in memory and saves the results of the operations.

[0006] The background for proposing CiM is the following understanding: In the operations of neural networks and machine learning, product summation is basically performed. In semiconductor integrated circuits that perform product summation, most of the power consumed is not due to the product summation operation itself, but rather due to the communication between the processor and the memory.

[0007] Therefore, by performing product summation operations in CiM, power consumption can be reduced and a significant increase in processing speed can be achieved.

[0008] Furthermore, if we take the case of using SRAM bit cells as memory as an example, since SRAM bit cells are composed of transistors of small (e.g., the smallest) size, the impact of manufacturing deviations is large, and the deviation of read current is also large. Therefore, in order to construct CiM, it is difficult to perform the product operation based on the bit line current read simultaneously.

[0009] As a method to suppress manufacturing deviations in transistors, the transistor size is generally increased. However, SRAM bit cells are manufactured according to special design rules, so they are basically impossible to change. Summary of the Invention

[0010] Embodiments of the present invention provide a semiconductor integrated circuit capable of suppressing readout current deviations in a semiconductor integrated circuit that uses charge sharing to control potential levels.

[0011] The semiconductor integrated circuit of the embodiment is a semiconductor integrated circuit that uses charge sharing to control the potential level, wherein the potential level controlled by the charge sharing between multiple circuit blocks and a global circuit block is operated in a semiconductor correction circuit, the circuit block containing multiple memory cells, and the potential level is set to the potential level of the readout line for reading data provided according to the state of the memory cell. Attached Figure Description

[0012] Figure 1 This is an explanatory diagram of the main parts of the storage device that serves as the application object in the implementation method.

[0013] Figure 2 This is the signal timing diagram for normal mode.

[0014] Figure 3 This is the signal timing diagram for CiM mode when performing product summation operations on memory.

[0015] Figure 4 This is an illustration of the bit line level calculation results when performing a product-sum operation on all data states in a local 4-cell memory cell in a 2-bit CiM configuration with 4 values.

[0016] Figure 5 This is an illustration of the bit line level calculation results when performing a product-sum operation on all data states in a local 8-cell memory cell in the case of performing a 3-bit CiM operation in an 8-value manner.

[0017] Figure 6 This is an explanatory diagram illustrating the construction principle of the readout circuit in any local unit array.

[0018] Figure 7 This is an explanatory diagram of a first configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0019] Figure 8 This is an explanatory diagram of a second configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0020] Figure 9 This is an explanatory diagram of a third configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0021] Figure 10 This is an explanatory diagram of a fourth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0022] Figure 11This is an explanatory diagram of a fifth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0023] Figure 12 This is an explanatory diagram of a sixth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0024] Figure 13 This is a diagram illustrating a more specific circuit structure of the memory cell array portion of a storage device.

[0025] Figure 14A yes Figure 13 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit (Part 1).

[0026] Figure 14B yes Figure 13 The timing diagram of the operation of the column on the reference potential generation side in the CiM mode of the circuit (one of them).

[0027] Figure 15A yes Figure 13 Timing diagram of the operation of the column on the operation side in CiM mode of the circuit (Part 2).

[0028] Figure 15B yes Figure 13 Timing diagram of the operation of the column on the reference potential generation side in CiM mode of the circuit (Part 2).

[0029] Figure 16 This is an explanatory diagram of the first connection example of the read circuit in a storage device.

[0030] Figure 17 yes Figure 16 The diagram illustrates the relationship between the potential levels of the first global bit lines GBLT[0] to GBLT[7], the second global bit lines GBLB[0] to GBLB[7], and the reference voltage in the circuit.

[0031] Figure 18 This is an explanatory diagram of a second connection example of the readout circuit in a storage device.

[0032] Figure 19 This is a schematic diagram illustrating the digital multiplication and summation circuit.

[0033] Figure 20 This is an explanatory diagram illustrating the specific circuit structure of the data readout section of the storage cell array in the storage device of the second embodiment.

[0034] Figure 21 This is an explanatory diagram of a first variation of the second embodiment.

[0035] Figure 22This is an explanatory diagram of a second variation of the second embodiment.

[0036] Figure 23A yes Figure 21 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit.

[0037] Figure 23B yes Figure 21 The timing diagram of the operation of the column on the reference potential generation side in the CiM mode of the circuit.

[0038] Figure 24A This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB for each local block in an 8-bit CiM without the use of charge collection circuitry.

[0039] Figure 24B This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block in an 8-bit CiM circuit where a charge collection circuit is used to share bit lines between two columns.

[0040] Figure 24C This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block in an 8-bit CiM circuit where bit lines are shared across four columns using a charge collection circuit.

[0041] Figure 25 This is an explanatory diagram of a first configuration example of a memory cell array in the case of 8-bit CiM.

[0042] Figure 26 This is an explanatory diagram of a second configuration example of a memory cell array in the case of 8-bit CiM.

[0043] Figure 27 This is an explanatory diagram of a third configuration example of a memory cell array in the case of 8-bit CiM.

[0044] Figure 28 This is an explanatory diagram of the main parts of the storage device that is the application object of the third embodiment.

[0045] Figure 29 yes Figure 28 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit.

[0046] Figure 30 This is an illustration diagram of a conventional latch-type decision circuit.

[0047] Figure 31 This is an explanatory diagram of the signal states of each part of a conventional latch-type decision circuit.

[0048] Figure 32 This is an explanatory diagram of a circuit example of the latch-type determination circuit according to the fourth embodiment.

[0049] Figure 33 This is a graph illustrating the potential simulation results of the global bit line and the reference bit line.

[0050] Figure 34 This is an explanatory diagram of the first aspect of the fifth embodiment.

[0051] Figure 35 This is an explanatory diagram of the second aspect of the fifth embodiment.

[0052] Explanation of reference numerals in the attached figures

[0053] 10. 10A storage device

[0054] 11-1~11-4 First Readout Amplifier~Fourth Readout Amplifier

[0055] 21-cell array block

[0056] 22-cell array

[0057] 23 Pre-charge auxiliary circuit

[0058] 24-Action Mode Switching Circuit

[0059] 25-column selector

[0060] 26 Readout Amplifier

[0061] 27. Reference potential generation data setting circuit

[0062] 28 Data Reset Circuit

[0063] 31-character selector

[0064] 41 Global Bit Line Precharge Circuit

[0065] 42-column selector

[0066] 43 Reference Voltage Generation Circuit Section

[0067] 43-1~43-4 First Reference Voltage Generation Circuit~Fourth Reference Voltage Generation Circuit

[0068] 44 Readout Amplifier Section

[0069] 44-1 to 44-18 First Readout Amplifier to Eighteenth Readout Amplifier

[0070] 44A First Readout Amplifier Section

[0071] 44B Second Readout Amplifier Section

[0072] 45-2 Second Load Capacity Adjustment Circuit

[0073] 45-3 Third Load Capacity Adjustment Circuit

[0074] 45 Load Capacity Adjustment Section

[0075] 45-1 First Load Capacity Adjustment Circuit

[0076] 45-4 Fourth Load Capacity Adjustment Circuit

[0077] 50 Multiplication and Sum Operation Circuit

[0078] 51 Four-bit adder

[0079] 53 First Addition Section

[0080] 54 Five-bit adder

[0081] 55 Second Addition Section

[0082] 61-cell array block

[0083] 62 Pre-charge auxiliary circuit

[0084] 63. Operation Mode Switching Circuit

[0085] 64. Latch circuit

[0086] 64A latch circuit

[0087] 64B latch circuit

[0088] 65. Local Column Selector

[0089] 66 Global Bitline Selector

[0090] 67. Reference potential generation data setting circuit

[0091] 68 Data Reset Circuit

[0092] 69 boost circuit

[0093] A Data Reset Line

[0094] BLx input bit line potential

[0095] Cell storage unit

[0096] CSL column selection line

[0097] GBLB Second Global Bitline

[0098] GBLT First Global Bitline

[0099] LO11 First Output Line

[0100] LO12 Second Output Line

[0101] LA_0~LA_n local arrays

[0102] LAT latch circuit

[0103] LBLB Second Local Bitline

[0104] LBLBx Second Local Bitline

[0105] LBLT First Local Bitline

[0106] LBLTx First Local Bitline

[0107] MCA storage cell array

[0108] RC readout circuit

[0109] Reference voltages Ref1 to Ref8 (first reference voltage to eighth reference voltage)

[0110] SW00~SW11 switches

[0111] SWB Second Switch

[0112] SWT First Switch

[0113] VBL bit line potential

[0114] VSS low-potential side power supply

[0115] WLx lettering

[0116] Reference voltages Ref1 to Ref8 (first reference voltage to eighth reference voltage)

[0117] SWC0 switch control line

[0118] SWC1 switch control line

[0119] TR1 and TR2 transistors Detailed Implementation

[0120] Hereinafter, the semiconductor integrated circuit according to embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0121] First, before describing the implementation method, the subject matter of this application will be explained.

[0122] A reference potential (Ref potential) can also be generated based on the power supply voltage and bandgap voltage. It is assumed that the bit line potential, which is the result of the calculation, will change due to the parasitic capacitance ratio of the metal layer (due to manufacturing deviations).

[0123] Therefore, when generating potentials based on power supply voltage and bandgap voltage, it is necessary to make fine adjustments to the reference potential (Ref potential) based on variations caused by manufacturing deviations. Since evaluation and fine-tuning are required during manufacturing testing, the circuit area is large and the testing time (cost) increases, which is undesirable.

[0124] Therefore, in this application, the first global bit line GBLT and the second global bit line GBLB of adjacent columns are used to generate the reference potential (Ref potential).

[0125] That is, the reference potential (Ref potential) is also generated through charge sharing, which can also offset the effects of manufacturing deviations in bit line capacitance, and no fine-tuning is required, so cost reduction can be expected.

[0126] [1] First implementation method

[0127] Figure 1 This is an explanatory diagram of the main parts of the storage device that serves as the application object in the implementation method.

[0128] The storage device 10 includes n+1 (n is an integer greater than or equal to 2) local arrays LA_0 to LA_n, a first global bit line GBLT, a second global bit line GBLB, and a readout circuit RC.

[0129] In the above structure, the local arrays LA_0 to LA_n function as local circuit blocks, and the column formed by the local arrays LA_0 to LA_n as a whole functions as a global circuit block (the same applies below).

[0130] In addition, the first global bit line GBLT and the second global bit line GBLB form a complementary pair of bit lines (the same applies below).

[0131] Each local array LA_x (x: an integer from 0 to n) is connected to a column selection line CSL[x] and m word lines WLx[0] to WLx[m].

[0132] Each local array LA_x has a first local bit line LBLTx, a second local bit line LBLBx, memory cells Cell0 to Celln, a first switch swTx, and a second switch swBx.

[0133] In the above structure, the first local bit line LBLTx and the second local bit line LBLBx constitute a complementary pair of bit lines (the same applies below).

[0134] In the above structure, each memory cell is connected between the first local bit line LBLTx and the second local bit line LBLBx.

[0135] In addition, the first local bit line LBLTx is connected to the readout circuit RC via the first switch swTx.

[0136] Furthermore, the second local bit line LBLBx is connected to the readout circuit RC via the second switch swBx.

[0137] Furthermore, when the first switch swTx and the second switch swBx are selected through the column selection line CSL[x], the corresponding local array LA_x is turned on, connecting the first local bit line LBLTx to the first global bit line GBLT, and connecting the second local bit line LBLBx to the second global bit line GBLB.

[0138] Figure 2 This is the signal timing diagram for normal mode.

[0139] Figure 2 An example is the signal timing diagram when reading the data from the storage cell Cell0 that constitutes the local array LA_0.

[0140] When word line WL0[0] becomes “H” level, the first local bit line LBLT0 maintains “H” level, and the second local bit line LBLB0 changes to “L” level.

[0141] Next, when the word line WL0[0] is converted to the "L" level and the column select line CSL[0] is converted to the "H" level, the first switch swT0 and the second switch swB0 are turned on, the storage cell Cell0 is connected to the first global bit line GBLT and the second global bit line GBLB, and the stored data is read out by the readout circuit RC.

[0142] More specifically, any one word line corresponding to the memory cell of the read object becomes the "H" level, either the first local bit line LBLT0 or the second local bit line LBLB0 of the local array LA_0 becomes the "H" level, and the other becomes the "L" level (full transition).

[0143] Next, when the word line that will become "H" level is set to "L" level, and the first switch swT0 and the second switch swB0 are closed through the column selection line CSL[0] corresponding to the word line, the first local bit line LBLT0 is connected to the first global bit line GBLT in the "H" level state, and the second local bit line LBLB0 is connected to the second global bit line GBLB in the "H" level state.

[0144] As a result, the charge of the local bit line with "L" level in the first local bit line LBLT0 or the global bit line with "H" level is shared with the charge of the local bit line with "L" level. The potential of the local bit line with "L" level rises and the potential of the corresponding global bit line falls.

[0145] The change in potential at this time is determined by the capacitance value of the local bit line at the "L" level and the capacitance value of the corresponding global bit line.

[0146] That is, based on the charge sharing method, the potential of the bit line is determined by the capacitance value, so the readout potential can be generated without being affected by the manufacturing deviation of the transistor.

[0147] Figure 3 This is the signal timing diagram for CiM mode when performing product summation operations on memory.

[0148] Any one word line connected to all local arrays LA_0 to LA_n becomes the "H" level. Either the first local bit line LBLTx or the second local bit line LBLBx of all local arrays LA_0 to LA_n becomes the "H" level, and the other becomes the "L" level (full conversion).

[0149] Next, the word lines that will be at the "H" level are set to the "L" level, all column select lines CSL[0] to CSL[n] are set to the "H" level, and all first switches swTx and second switches swBx are closed.

[0150] Then, the first local bit line LBLTx of each local array LA_0~LA_n is connected to the first global bit line GBLT in the "H" level state, and the second local bit line LBLBx is connected to the second global bit line GBLB in the "H" level state.

[0151] As a result, the charge of the local bit lines with "L" level in the first local bit line LBLTx or the second local bit line LBLBx in each local array LA_0~LA_n is shared with the charge of the global bit lines with "H" level. The potential of all local bit lines with "L" level increases, and the potential of all corresponding global bit lines decreases.

[0152] As a result, the potentials of the first global bit line GBLT and the second global bit line GBLB are converted to potentials corresponding to the data of the accessed cell. At this time, the potentials of the first global bit line GBLT and the second global bit line GBLB become the product of the accessed memory cell.

[0153] Therefore, by reading it out using an RC readout circuit and performing analog-to-digital conversion, it is possible to perform product summation operations that are unaffected by deviations in the unit current.

[0154] Next, regarding Figure 1 The estimated voltage levels of the read bit lines in the shown memory cell array are explained.

[0155] Figure 4This is an illustration of the bit line level calculation results when performing a product-sum operation on all data states in a local 4-cell memory cell in a 2-bit CiM configuration with 4 values.

[0156] In this case, assume that the capacitance ratio of the local bit line to the global bit line is 1:5.

[0157] like Figure 4 As shown in the first column from the left, when the value of the first local bit line LBLT is 4, the value of the second local bit line LBLB becomes 0.

[0158] Similarly, when the values ​​of the first local bit line LBLT are 3, 2, 1, and 0, the values ​​of the second local bit line LBLB are 1, 2, 3, and 4, respectively.

[0159] Additionally, as shown in columns 7 and 8 from the left, when the value of the first local bit line LBLT is 4, the potential of the first global bit line GBLT and the potential of the second global bit line GBLB become 56%:100%.

[0160] Therefore, when the power supply voltage of the first global bit line GBLT and the second global bit line GBLB is set to 1.5V, and the value of the first local bit line LBLT is 4, the voltage of the first global bit line GBLT is as follows: Figure 4 The second column from the right shows 0.833V, and the voltage of the second global bit line GBLB is as follows. Figure 4 The first column from the right shows 1.500V.

[0161] Similarly, when the value of the first local bit line LBLT is 3, 2, 1, or 0, the voltage of the first global bit line GBLT is as follows: Figure 4 As shown in the second column from the right, the values ​​are 1.000V, 1.167V, 1.333V, and 1.500V.

[0162] Furthermore, when the value of the first local bit line LBLT is 3, 2, 1, or 0, the voltage of the second global bit line GBLB is as follows: Figure 4 As shown in the first column from the right, the values ​​are 1.333V, 1.167V, 1.000V, and 0.833V.

[0163] Therefore, as reference voltages for identifying them, for example, the following four reference voltages are needed: a first reference voltage Ref1 with a voltage range of 1.500V to 1.333V for identifying the voltage of the first global bit line GBLT between 1.500V and 1.333V; a second reference voltage Ref2 with a voltage range of 1.333V to 1.167V for identifying the voltage of the first global bit line GBLT between 1.333V and 1.167V; a third reference voltage Ref3 with a voltage range of 1.167V to 1.000V for identifying the voltage of the first global bit line GBLT between 1.167V and 1.000V; and a fourth reference voltage Ref4 with a voltage range of 1.000V to 0.833V for identifying the voltage of the first global bit line GBLT between 1.000V and 0.833V.

[0164] Figure 5 This is an illustration of the bit line level calculation results when performing a product-sum operation on all data states in a local 8-cell memory cell in the case of performing a 3-bit CiM operation in an 8-value manner.

[0165] In this case, assume that the capacitance ratio of the local bit line to the global bit line is 1:10.

[0166] like Figure 5 As shown in the first column from the left, when the value of the first local bit line LBLT is 8, the value of the second local bit line LBLB becomes 0.

[0167] Similarly, when the value of the first local bit line LBLT is 7, 6, 5, 4, 3, 2, 1, 0, the value of the second local bit line LBLB becomes 1, 2, 3, 4, 5, 6, 7, 8 respectively.

[0168] Additionally, as shown in columns 7 and 8 from the left, when the value of the first local bit line LBLT is 4, the potential of the first global bit line GBLT and the potential of the second global bit line GBLB become 56%:100%.

[0169] Therefore, when the power supply voltage of the first global bit line GBLT and the second global bit line GBLB is set to 1.5V, and the value of the first local bit line LBLT is 8, the voltage of the first global bit line GBLT is as follows: Figure 5 The second column from the right shows 0.833V, and the voltage of the second global bit line GBLB is as follows. Figure 5 The first column from the right shows 1.500V.

[0170] Similarly, when the value of the first local bit line LBLT is 7, 6, 5, 4, 3, 2, 1, 0, the voltage of the first global bit line GBLT is as follows: Figure 5 As shown in the second column from the right, the values ​​are 0.917V, 1.000V, 1.083V, 1.167V, 1.250V, 1.333V, 1.417V, and 1.500V.

[0171] Furthermore, when the values ​​of the first local bit line LBLT are 7, 6, 5, 4, 3, 2, 1, and 0, the voltage of the second global bit line GBLB is as follows: Figure 5 As shown in the first column from the right, the values ​​are 1.417V, 1.333V, 1.250V, 1.167V, 1.083V, 1.000V, 0.917V, and 0.833V.

[0172] Therefore, as reference voltages for identifying them, the following eight reference voltages are required, for example: a first reference voltage Ref1 with a voltage range of 1.500V to 1.417V (e.g., an intermediate potential. The same applies below) for identifying the voltage of the first global bit line GBLT between 1.500V and 1.417V; a second reference voltage Ref2 with a voltage range of 1.417V to 1.333V for identifying the voltage of the first global bit line GBLT between 1.417V and 1.333V; a third reference voltage Ref3 with a voltage range of 1.333V to 1.250V for identifying the voltage of the first global bit line GBLT between 1.333V and 1.250V; and a third reference voltage Ref3 with a voltage range of 1.250V to 1.167V for identifying the voltage of the first global bit line GBLT between 1.250V and 1.167V. The following are reference voltages: a fourth reference voltage Ref4 with a voltage range of 7V; a fifth reference voltage Ref5 with a voltage range of 1.167V to 1.083V for identifying the voltage of the first global bit line GBLT between 1.167V and 1.083V; a sixth reference voltage Ref6 with a voltage range of 1.083V to 1.000V for identifying the voltage of the first global bit line GBLT between 1.083V and 1.000V; a seventh reference voltage Ref7 with a voltage range of 1.000V to 0.917V for identifying the voltage of the first global bit line GBLT between 1.000V and 0.917V; and an eighth reference voltage Ref8 with a voltage range of 0.917V to 0.833V for identifying the voltage of the first global bit line GBLT between 0.917V and 0.833V.

[0173] In addition, Figure 4 Examples and situations Figure 5In any of the examples, in the actual generation of the reference voltage, the memory cell is set to the desired data state, and the intermediate potential of the desired global bit line potential is generated as the reference voltage. However, when the number of reference voltages is large, the area of ​​the memory cell used to generate the reference voltage increases.

[0174] In addition, the potential change of the first global bit line GBLT is symmetrical to the potential change of the second global bit line GBLB.

[0175] Therefore, in Figure 4 In an example, for instance, using a first reference voltage Ref1 with a voltage in the range of 1.500V to 1.333V for identifying the voltage of the first global bit line GBLT between 1.500V and 1.333V, and a second reference voltage Ref2 with a voltage in the range of 1.333V to 1.167V for identifying the voltage of the first global bit line GBLT between 1.333V and 1.167V, when the value of the first local bit line LBLT is 4 to 2, the first reference voltage Ref1 or the second reference voltage Ref2 is compared with the voltage of the second global bit line; when the value of the first local bit line LBLT is 2 to 0, the first reference voltage Ref1 or the second reference voltage Ref2 is compared with the voltage of the first global bit line GBLT. Thus, only two reference voltages need to be set, and therefore the area of ​​the memory cell used to generate the reference voltage can be halved.

[0176] The above explanation describes the case where the first reference voltage Ref1 or the second reference voltage Ref2 is used. When the value of the first local bit line LBLT is 4 to 2, the third reference voltage Ref3 or the fourth reference voltage Ref4 is compared with the voltage of the first global bit line GBLT. When the value of the first local bit line LBLT is 2 to 0, the third reference voltage Ref3 or the fourth reference voltage Ref4 is compared with the voltage of the second global bit line GBLB. Thus, in this case, only two reference voltages need to be set, so the area of ​​the memory cell used to generate the reference voltage can be halved.

[0177] Similarly, in Figure 5In example, for instance, a first reference voltage Ref1 with a voltage in the range of 1.500V to 1.417V is used to identify the voltage of the first global bit line GBLT between 1.417V and 1.500V; a second reference voltage Ref2 with a voltage in the range of 1.417V to 1.333V is used to identify the voltage of the first global bit line GBLT between 1.417V and 1.333V; a third reference voltage Ref3 with a voltage in the range of 1.333V to 1.250V is used to identify the voltage of the first global bit line GBLT between 1.333V and 1.250V; and a third reference voltage Ref3 with a voltage in the range of 1.250V is used to identify the voltage of the first global bit line GBLT between 1.500V and 1.417V. A fourth reference voltage Ref4, which identifies the voltage of the first global bit line GBLT between V and 1.167V, has a voltage range of 1.250V to 1.167V. When the value of the first local bit line LBLT is 8 to 4, the first reference voltage Ref1 to the fourth reference voltage Ref4 are compared with the voltage of the second global bit line GBLB. When the value of the first local bit line LBLT is 4 to 0, the first reference voltage Ref1 to the fourth reference voltage Ref4 are compared with the voltage of the first global bit line GBLT. Thus, only four reference voltages need to be set, so the area of ​​the memory cell used to generate the reference voltage can be halved.

[0178] The above explanation describes the case where the first reference voltage Ref1 to the fourth reference voltage Ref4 are used. When the fifth reference voltage Ref5 to the eighth reference voltage Ref8 are used, if the value of the first local bit line LBLT is 8 to 4, the fifth reference voltage Ref5 to the eighth reference voltage Ref8 are compared with the voltage of the first global bit line. If the value of the first local bit line LBLT is 4 to 0, the fifth reference voltage Ref5 to the eighth reference voltage Ref8 are compared with the voltage of the second global bit line. Thus, in this case, only four reference voltages need to be set, so the area of ​​the memory cell used to generate the reference voltage can be halved.

[0179] Figure 6 This is an explanatory diagram illustrating the construction principle of the readout circuit in any local unit array.

[0180] exist Figure 6 The description provides an example of the configuration of the readout circuit RC when the first reference voltage Ref1 and the second reference voltage Ref2 are used as the reference voltages for performing a 2-bit CiM in a 4-value manner in the memory cell of a local 4-memory bank.

[0181] The readout circuit RC includes: a first readout amplifier (SA) 11-1, one input terminal of which is connected to a first global bit line GBLT corresponding to the local cell array of the readout object, and another input terminal of which is connected to a first reference voltage Ref1 generated by charge sharing using the first global bit line GBLT and the second global bit line GBLB of the local cell array that generates the first reference voltage Ref1; a second readout amplifier 11-2, one input terminal of which is connected to the first global bit line GBLT corresponding to the local cell array of the readout object, and another input terminal of which is connected to a second reference voltage Ref2 generated by charge sharing using the first global bit line GBLT and the second global bit line GBLB of the local cell array that generates the second reference voltage Ref2; a third readout amplifier 11-3, one input terminal of which is connected to the second global bit line GBLB corresponding to the local cell array of the readout object, and another input terminal of which is connected to the first reference voltage Ref1; and a fourth readout amplifier 11-4, one input terminal of which is connected to the second global bit line GBLB corresponding to the local cell array of the readout object, and another input terminal of which is connected to the second reference voltage Ref2.

[0182] In this case, the first read amplifier 11-1 to the fourth read amplifier 11-4 are conventionally proven read amplifiers used in SRAM readout.

[0183] Furthermore, the RC output of the readout circuit is the product sum of the readout results from the first readout amplifier 11-1 to the fourth readout amplifier 11-4.

[0184] According to this embodiment, as described above, the reference voltage that serves as the reference potential is also generated on the same semiconductor integrated circuit through charge sharing. Therefore, it can also offset the effects of manufacturing deviations in bit line capacitance and does not require fine-tuning, thus achieving cost reduction.

[0185] Next, we will provide a more specific explanation.

[0186] Figure 7 This is an explanatory diagram of a first configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0187] exist Figure 7 In the example, there are two columns CL0 and CL1. When performing a product sum operation on one column, a reference potential is generated using a local array for generating the reference potential of the other column, and then the product sum operation is performed.

[0188] Column CL0 has a first global bit line GBLT (not shown) and a second global bit line GBLB (not shown), four local arrays LA_001 to LA_301 connected to them, and a local array LA_R01 for generating reference potential connected to the first global bit line GBLT (not shown) and the second global bit line GBLB (not shown).

[0189] Column CL1 has a first global bit line GBLT (not shown) and a second global bit line GBLB (not shown), four local arrays LA_002 to LA_302 connected to them, and a local array LA_R02 for generating reference potential connected to the first global bit line GBLT (not shown) and the second global bit line GBLB (not shown).

[0190] In the above structure, the local array LA_R01 generates a reference voltage that serves as the reference potential when accessing column CL1. This local array LA_R01 consists of half the number of rows (rows: word lines) of the other local arrays LA_001 to LA_301.

[0191] Similarly, local array LA_R02 generates a reference voltage that serves as the reference potential when accessing column CL0. This local array LA_R02 consists of half the number of rows (rows: word lines) of the other local arrays LA_002 to LA_302.

[0192] This is to generate intermediate potentials such as the intermediate potential between 0 and 1, and the intermediate potential between 1 and 2.

[0193] With the local bit line capacitance set to CLBL, the global bit line capacitance set to CGBL, and the power supply voltage set to VPW, the bit line potential Vbl is expressed by the following formula.

[0194] Vbl=(1-(CLBL / (CGBL+CLBL))×VPW

[0195] Figure 8 This is an explanatory diagram of a second configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0196] exist Figure 8 In the example, the memory cell array MCA has four columns CL0, CL1, CL2, and CL3. When performing a product sum operation on columns CL0 and CL1, at least a portion of the local arrays LA_20 to LA_23 and LA_30 to LA_33 constituting columns CL2 and CL3 are used to generate a reference potential for the product sum operation.

[0197] In addition, when performing the product sum operation of columns CL2 and CL3, at least a portion of the local arrays LA_00~LA_03 and LA_10~LA_13 constituting columns CL0 and CL1 are used to generate a reference potential for performing the product sum operation.

[0198] Column CL0 has a first global bit line GBLT and a second global bit line GBLB. It also has a switch SW00 for short-circuiting the first global bit line GBLT and the second global bit line GBLB, and the switch SW00 is controlled via a switch control line SWC0.

[0199] CL1 has a first global bit line GBLT and a second global bit line GBLB. It also has a switch SW01 for short-circuiting the first global bit line GBLT and the second global bit line GBLB, and the switch SW01 is controlled via a switch control line SWC0.

[0200] Column CL2 has a first global bit line GBLT and a second global bit line GBLB. It also has a switch SW10 for short-circuiting the first global bit line GBLT and the second global bit line GBLB, and the switch SW10 is controlled via a switch control line SWC1.

[0201] Column CL3 has a first global bit line GBLT and a second global bit line GBLB. It also has a switch SW11 for short-circuiting the first global bit line GBLT and the second global bit line GBLB, and the switch SW11 is controlled via a switch control line SWC1.

[0202] exist Figure 8 In this context, the object of the product sum operation is column CL0. Therefore, the reason for performing the product sum operation on the local arrays LA_00~LA_03 constituting column CL0 is... Figure 8 The thin, sloping shading line on the top right of the middle line is to indicate that the first local bit line LBLT of these local arrays is connected to the first global bit line GBLT, and the second local bit line LBLB is connected to the second global bit line GBLB (the same applies below).

[0203] On the other hand, the reason for drawing a sandy shading line on column CL1, which is not an object of the product sum operation, is to indicate that the first local bit line LBLT of these local arrays LA10 to LA13 is not connected to the first global bit line GBLT, and the second local bit line LBLB is not connected to the second global bit line GBLB (the same applies below).

[0204] Furthermore, in the column used to generate the reference potential (in Figure 8In the example of columns CL2 and CL3, there are local arrays LA21 to LA23 and LA33 that are marked with sand-like shaded lines. In these local arrays, the first local bit line LBLT is not connected to the first global bit line GBLT, and the second local bit line LBLB is not connected to the second global bit line GBLB. Therefore, the load capacity is different from that of the column performing the product operation, and thus the reference potential contains an error.

[0205] Therefore, to reduce this error, a structure can also be adopted in which only the bit lines of the "H" level are connected in a local array that is filled with light color.

[0206] Furthermore, in the column used to generate the reference potential, when the first global bit line GBLT0 / GBLT1 / GBLT2 / GBLT3 and the corresponding complementary pair of second global bit lines GBLB0 / GBLB1 / GBLB2 / GBLB3 are not short-circuited, intermediate values ​​such as 0.5 and 1.5 cannot be output. Therefore, in Figure 8 In the example case, by turning on switch SW10, the first global bit line GBLT2 and the second global bit line GBLB2 are short-circuited, thereby doubling the capacitance of the global bit lines and enabling the output of intermediate values.

[0207] Figure 9 This is an explanatory diagram of a third configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0208] exist Figure 9 In the example, with Figure 8 Similarly, the memory cell array MCA has four columns CL0, CL1, CL2, and CL3. When performing a product sum operation on columns CL0 and CL1, at least a portion of the local arrays LA_20 to LA_23 and LA_30 to LA_33 constituting columns CL2 and CL3 is used to generate a reference potential for the product sum operation.

[0209] In addition, when performing the product sum operation of columns CL2 and CL3, at least a portion of the local arrays LA_00~LA_03 and LA_10~LA_13 constituting columns CL0 and CL1 are used to generate a reference potential for performing the product sum operation.

[0210] Figure 9 The third constituent example and Figure 8The difference in the configuration examples is that the local arrays LA_00~LA_03 constituting column CL0, LA_10~LA_13 constituting column CL1, LA_20~LA_23 constituting column CL2, and LA_30~LA_33 constituting column CL3 are respectively divided into two regions, array region PU and array region PL, thus making the functions different.

[0211] More specifically, in Figure 9 In the example, there are array regions marked with thin, upward-sloping shaded lines (this region is where the first local bit line LBLT of the local array is connected to the first global bit line GBLT and the second local bit line LBLB is connected to the second global bit line GBLB), array regions marked with sandy-like shaded lines (this region is where the first local bit line LBLT of the local array is not connected to the first global bit line GBLT and the second local bit line LBLB is not connected to the second global bit line GBLB), and array regions marked with upward-sloping shaded lines (this region is where the first local bit line LBLT at the "H" level is connected to the first global bit line GBLT and the second local bit line LBLB at the "H" level is connected to the first global bit line GBLT, thus sharing charge).

[0212] By employing this structure, it is also possible to connect local bit line pairs and global bit line pairs of the "H" level, and... Figure 8 Compared to the previous configuration, the error of the reference potential is reduced.

[0213] Figure 10 This is an explanatory diagram of a fourth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0214] exist Figure 10 In the example, with Figure 9 Similarly, the memory cell array MCA has four columns CL0, CL1, CL2, and CL3. When performing a product sum operation on columns CL0 and CL1, at least a portion of the local arrays LA_20 to LA_23 and LA_30 to LA_33 constituting columns CL2 and CL3 is used to generate a reference potential for the product sum operation.

[0215] In addition, when performing the product sum operation of columns CL2 and CL3, at least a portion of the local arrays LA_00~LA_03 and LA_10~LA_13 constituting columns CL0 and CL1 are used to generate a reference potential for performing the product sum operation.

[0216] Figure 10 The fourth constituent example and Figure 9The difference in the third configuration example is that, for each of the local arrays LA_00~LA_03 constituting column CL0, the local arrays LA_10~LA_13 constituting column CL1, the local arrays LA_20~LA_23 constituting column CL2, and the local arrays LA_30~LA_33 constituting column CL3, when the functions are different due to the division into two regions, array region PU and array region PL, the array region marked with a sandy shaded line (this region is the region where the first local bit line LBLT of the local array is not connected to the first global bit line GBLT and the second local bit line LBLB is not connected to the second global bit line GBLB) is configured on the array region PU side on the column CL0 and column CL1 side, and on the array region PL side on the column CL2 and column CL3 side.

[0217] By employing this structure, it is also possible to connect local bit line pairs and global bit line pairs of the "H" level, and... Figure 8 Compared to the previous configuration, the error of the reference potential is reduced.

[0218] Figure 11 This is an explanatory diagram of a fifth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0219] In addition, Figure 11 The diagrams of switch SW10 or switch SW11 and their associated structures are omitted.

[0220] exist Figure 11 In the fifth constituent example, for the case of... Figure 9 and Figure 10 Similarly, in the configuration examples, each of the local arrays LA_00~LA_03 constituting column CL0, the local arrays LA_10~LA_13 constituting column CL1, the local arrays LA_20~LA_23 constituting column CL2, and the local arrays LA_30~LA_33 constituting column CL3, when divided into two regions, array region PU and array region PL, and thus having different functions, in the array region PU and array region PL of the same local array, one performs the CiM operation, and the other performs the operation for generating the reference potential.

[0221] In addition, Figure 11 In this context, for ease of understanding, a single global bitline is used to represent a pair of global bitlines, and the description is omitted.

[0222] According to this structure, all local arrays serve various functions, eliminating useless arrays or columns. As a result, it can be constructed with a small area.

[0223] Figure 12 This is an explanatory diagram of a sixth configuration example of a memory cell array used to generate a reference potential (reference voltage) through charge sharing.

[0224] Figure 12 Will Figure 11 The 4-valued CiM is constructed as an 8-valued CiM.

[0225] In Figure 12 In the sixth example, for ease of understanding, a single global bitline is used to represent a pair of global bitlines, and the description is omitted.

[0226] Figure 13 This is a diagram illustrating a more specific circuit structure of the memory cell array portion of a storage device.

[0227] exist Figure 13 The diagram shows cell array blocks 21-0 and 21-1 corresponding to the two columns.

[0228] In this case, since cell array block 21-0 and cell array block 21-1 have the same structure, cell array block 21-0 will be used as an example for explanation.

[0229] The unit array block 21-0 includes unit arrays 22-0 and 22-1, pre-charge auxiliary circuits 23-0 and 23-1, operating mode switching circuits 24-0 and 24-1, column selector 25, readout amplifier 26, reference potential generation data setting circuit 27, and data reset circuit 28.

[0230] In cell arrays 22-0 and 22-1, the memory cell selected by the word line selected by the word selection signal from the corresponding word selector (not shown) is connected to the first local bit line LBLT and the second local bit line LBLB.

[0231] During pre-charging, the pre-charging auxiliary circuit releases a charge corresponding to the change in bit line potential while the first local bit line LBLT and the second local bit line LBLB are short-circuited.

[0232] The operation mode switching circuits 24-0 and 24-1 set the operation mode to either the normal mode, which performs read / write operations on the selected column as usual, or the CiM mode, which performs a product operation on the data of multiple memory cells.

[0233] As a result, in normal mode, the object's storage unit is connected to the first global bit line GBLT and the second global bit line GBLB via the first local bit line LBLT and the second local bit line LBLB for read or write processing.

[0234] In addition, in CiM mode, the data of multiple storage units of the object are multiplied and summed, and the result of the multiplication and summation is output to the readout circuit RC via the first global bit line GBLT and the second global bit line GBLB.

[0235] Column selector 25 selects the column of the readout object or the column of the product sum operation object in column C0 or column C1 and connects it to the readout amplifier.

[0236] The sense amplifier 26 amplifies the signal level of the data read from the memory cells of the cell array connected via the column selector 25 and outputs it to the sense circuit RC. Furthermore, the sense amplifier 26 is not required when there are no issues with low-speed operation.

[0237] The reference potential generation data setting circuit 27 sets the data for generating the reference potential for the memory cell array.

[0238] The data reset circuit 28 sets the potential level of the local bit line to the same setting as when reading "0" data without opening the word line, and shares charge with the global bit line.

[0239] Next, the specific actions will be explained.

[0240] Figure 14A yes Figure 13 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit (Part 1).

[0241] Figure 14B yes Figure 13 The timing diagram of the operation of the column on the reference potential generation side in the CiM mode of the circuit (one of them).

[0242] In the columns on the computation side of CiM mode, such as Figure 14A As shown, at time t1, the word line corresponding to the memory cell that is actually being operated on changes to the "H" level, which is the potential corresponding to the data held by the memory cell corresponding to the word line.

[0243] In addition, the precharge enable lines PRE0 to PREn switch to the "L" level, and the precharge ends.

[0244] Furthermore, when the operation mode switching lines CiM0 to CiMn transition to an "L" level, the operation mode switches to CiM mode. This transition can also occur at time t2.

[0245] On the other hand, in the column on the generation side of the reference potential, such as Figure 14B As shown, at time t1, the data setting lines B0 to Bn corresponding to the storage cells used to actually generate the reference potential change to the "H" level, and the corresponding storage cells change to the "L" level.

[0246] In addition, the precharge enable lines PRE0 to PREn switch to the "L" level, and the precharge ends.

[0247] Furthermore, the operation mode switching lines CiM0 to CiMn switch to an "L" level, and the operation mode switches to the reference potential supply mode corresponding to the CiM mode. The switch can also occur at time t2.

[0248] Then, at time t2, the word line switches to the "L" level.

[0249] When time t3 arrives, and column selection lines CSL1 to CSLn transition to the "H" level, in the columns on the operation side, the first local bit line LBLT and the second local bit line LBLB, corresponding to the memory cell that is actually being operated on, transition to the specified level corresponding to the operation result.

[0250] As a result, the first global bit line GBLT and the second global bit line GBLB of the column on the operation side are converted to the level corresponding to the operation result of the column on the operation side, and the operation result is output.

[0251] On the other hand, in the column on the reference potential generation side, the first local bit line LBLT and the second local bit line LBLB corresponding to the memory cell that generates the reference potential become charge-shared, and are transformed into the same specified level corresponding to the value of the reference potential, and the reference potential is output.

[0252] Then, at time t4, when the column selection lines CSL1 to CSLn change to the "L" level, the precharge enable lines PRE0 to PREn in the columns on the operation side change to the "H" level, and precharging begins.

[0253] Furthermore, when the operation mode switching lines CiM0 to CiMn change to the "H" level, the operation mode changes to the normal mode and the processing ends.

[0254] On the other hand, in the column on the reference potential generation side, the precharge enable lines PRE0 to PREn also change to the "H" level, and precharging begins.

[0255] Furthermore, when the operation mode switching lines CiM0 to CiMn change to the "H" level, the operation mode changes to the normal mode and the processing ends.

[0256] As explained above, the memory device can generate a highly reliable reference potential in a semiconductor integrated circuit with SRAM bit cells and perform highly reliable product operations on the semiconductor integrated circuit.

[0257] Figure 15A yes Figure 13 Timing diagram of the operation of the column on the operation side in CiM mode of the circuit (Part 2).

[0258] Figure 15B yes Figure 13Timing diagram of the operation of the column on the reference potential generation side in CiM mode of the circuit (Part 2).

[0259] exist Figure 15A , Figure 15B In, with Figure 14A , Figure 14B The difference is that in the column on the operation side, in the non-operation block, the word line is fixed at the "L" level, and instead, the data reset line A becomes the "H" level at time t1, setting the data of the corresponding memory cell to "0".

[0260] Other actions and Figure 14A , Figure 14B same.

[0261] Therefore, in Figure 15A , Figure 15B In the example, the memory device can also generate a highly reliable reference potential in a semiconductor integrated circuit with SRAM bit cells and perform highly reliable product summation operations on the semiconductor integrated circuit.

[0262] Figure 16 This is an explanatory diagram of the first connection example of the read circuit in a storage device.

[0263] exist Figure 16 In this context, it is assumed that the eight columns (columns 1 to 8, not shown) are connected to the global bit line precharge circuit 41.

[0264] The storage device 10 includes a global bit line precharge circuit 41, a column selector 42, a reference voltage generation circuit 43, a readout amplifier 44, and a load capacity adjustment unit 45.

[0265] The global bit line precharge circuit 41 precharges the first global bit line GBLT[0]~GBLT[7] and the second global bit line GBLB[0]~GBLB[7] corresponding to the 8 bits to the specified potential.

[0266] Column selector 42 selects the column from the 8 columns that contains the storage cell of the read object and connects it to the output line.

[0267] The reference voltage generation circuit section 43 includes a first reference voltage generation circuit 43-1, which performs charge sharing operation by using the voltage corresponding to the data of the memory cell corresponding to the first column of the first global bit line GBLT[0] and the second global bit line LBLB[0], and the voltage corresponding to the data of the memory cell corresponding to the fifth column of the first global bit line GBLT[4] and the second global bit line LBLB[4], and outputs a first reference voltage Ref1 as a reference potential.

[0268] In addition, the reference voltage generation circuit section 43 includes a second reference voltage generation circuit 43-2, which performs charge sharing operation by using the voltage corresponding to the second column of the first global bit line GBLT[1] and the second global bit line LBLB[1], and the voltage corresponding to the sixth column of the first global bit line GBLT[5] and the second global bit line LBLB[5], and outputs a second reference voltage Ref2 as a reference potential.

[0269] In addition, the reference voltage generation circuit section 43 includes a third reference voltage generation circuit 43-3, which performs charge sharing operation by using the voltage corresponding to the data of the storage cells in the third column corresponding to the first global bit line GBLT[2] and the second global bit line LBLB[2], and the voltage corresponding to the seventh column corresponding to the first global bit line GBLT[6] and the second global bit line LBLB[6], and outputs a third reference voltage Ref3 as a reference potential.

[0270] In addition, the reference voltage generation circuit section 43 includes a fourth reference voltage generation circuit 43-4, which performs charge sharing operation by using the voltage corresponding to the fourth column of the first global bit line GBLT[3] and the second global bit line LBLB[3], and the voltage corresponding to the eighth column of the first global bit line GBLT[7] and the second global bit line LBLB[7], and outputs a fourth reference voltage Ref4 as a reference potential.

[0271] The readout amplifier section 44 includes: a first readout amplifier 44-1, one end of which is connected to the first output line LO1 of the column selector 42 and the other end of which is connected to the first reference voltage generation circuit 43-1; and a second readout amplifier 44-2, one end of which is connected to the second output line LO2 of the column selector 42 and the other end of which is connected to the first reference voltage generation circuit 43-1.

[0272] Additionally, the readout amplifier section 44 includes: a third readout amplifier 44-3, one end of which is connected to the first output line LO1 of the column selector 42 and the other end of which is connected to the second reference voltage generation circuit 43-2; and a fourth readout amplifier 44-4, one end of which is connected to the second output line LO2 of the column selector 42 and the other end of which is connected to the second reference voltage generation circuit 43-2.

[0273] Additionally, the readout amplifier section 44 includes: a fifth readout amplifier 44-5, one end of which is connected to the first output line LO1 of the column selector 42 and the other end of which is connected to the third reference voltage generation circuit 43-3; and a sixth readout amplifier 44-6, one end of which is connected to the second output line LO2 of the column selector 42 and the other end of which is connected to the third reference voltage generation circuit.

[0274] Additionally, the readout amplifier section 44 includes: a seventh readout amplifier 44-7, one end of which is connected to the first output line LO1 of the column selector 42 and the other end of which is connected to the fourth reference voltage generation circuit 43-4; and an eighth readout amplifier 44-8, one end of which is connected to the second output line LO2 of the column selector 42 and the other end of which is connected to the fourth reference voltage generation circuit.

[0275] Furthermore, the readout amplifier section 44 may, as needed, include a ninth readout amplifier that operates in normal operating mode, with one end connected to the first output line LO1 of the column selector 42 and the other end connected to the second output line LO2 of the column selector 42.

[0276] The load capacity adjustment unit 45 includes a first load capacity adjustment circuit 45-1 to a fourth load capacity adjustment circuit 45-4 to adjust the difference in parasitic load between the first global bit line GBLT and the second global bit line GBLB. In this case, the first load capacity adjustment circuit 45-1 is connected to the output terminal of the first reference voltage generation circuit 43-1, the second load capacity adjustment circuit 45-2 is connected to the output terminal of the second reference voltage generation circuit 43-2, the third load capacity adjustment circuit 45-3 is connected to the output terminal of the third reference voltage generation circuit 43-3, and the fourth load capacity adjustment circuit 45-4 is connected to the output terminal of the fourth reference voltage generation circuit 43-4.

[0277] Figure 17 yes Figure 16 The diagram illustrates the relationship between the potential levels of the first global bit lines GBLT[0] to GBLT[7], the second global bit lines GBLB[0] to GBLB[7], and the reference voltage in the circuit.

[0278] like Figure 17 As shown, the slope of the reference voltage is approximately equal to the slope of the potential levels of the first global bit line GBLT[0] to GBLT[7] and the second global bit line GBLB[0] to GBLB[7]. Therefore, based on the connection state of the readout circuit of the above structure, when the reference voltage for data readout (the first reference voltage to the fourth reference voltage in the above example) is generated by removing the influence of the manufacturing deviation of the semiconductor integrated circuit through charge sharing operation, the influence of the difference in parasitic load between the first global bit line GBLT and the second global bit line GBLB can be reduced, and thus data readout can be performed more accurately and reliably.

[0279] Figure 18 This is an explanatory diagram of a second connection example of the readout circuit in a storage device.

[0280] exist Figure 18 In China, for the sake of Figure 16For identical parts, use the same reference numerals and provide detailed descriptions.

[0281] exist Figure 18 Nakaya and Figure 16 The same applies if we assume that the eight columns (columns 1 through 8) not shown are connected to the global bit line precharge circuit.

[0282] The storage device 10 includes a global bit line precharge circuit 41, a column selector 42, a reference voltage generation circuit 43, a first sense amplifier 44A, a second sense amplifier 44B, a third sense amplifier 44C, and a fourth sense amplifier 44D.

[0283] Figure 18 The second connection example and Figure 16 The difference in the first connection example is that it is equipped with a first readout amplifier section 44A, a second readout amplifier section 44B, a third readout amplifier section 44C, and a fourth readout amplifier section 44D instead. Figure 16 The readout amplifier section 44 and the load capacity adjustment section 45 are not provided.

[0284] The following only explains the differences.

[0285] The first sense amplifier section 44A includes: a first sense amplifier 44-1, which is connected to the first output line LO1 of the column selector 42 corresponding to the first global bit line GBLT[0] and the first global bit line GBLT[4] (corresponding to the first and fifth columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second sense amplifier 44-2, which is connected to the first output line LO1 of the column selector 42 corresponding to the first global bit line GBLT[0] and the first global bit line GBLT[4] (corresponding to the first and fifth columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0286] Additionally, the first sense amplifier section 44A includes: a third sense amplifier 44-3, which is connected to the first output line LO1 of the column selector 42 corresponding to the first global bit line GBLT[0] and the first global bit line GBLT[4] (corresponding to the first and fifth columns), and the other end is connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier 44-4, which is connected to the first output line LO1 of the column selector 42 corresponding to the first global bit line GBLT[0] and the first global bit line GBLT[4] (corresponding to the first and fifth columns), and the other end is connected to the fourth reference voltage generation circuit 43-4.

[0287] Additionally, the first sense amplifier section 44A includes: a first sense amplifier 44-11, which is connected to the second output line LO2 of the column selector 42 corresponding to the second global bit lines GBLB[0] and GBLB[4] (corresponding to the first and fifth columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second sense amplifier 44-12, which is connected to the second output line LO2 of the column selector 42 corresponding to the second global bit lines GBLB[0] and GBLB[4] (corresponding to the first and fifth columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0288] Additionally, the first sense amplifier section 44A includes: a third sense amplifier 44-13, which is connected to the second output line LO2 of the column selector 42 corresponding to the second global bit line GBLB[0] and the second global bit line GBLB[4] (corresponding to the first and fifth columns), and the other end is connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier 44-14, which is connected to the second output line LO2 of the column selector 42 corresponding to the second global bit line GBLB[0] and the second global bit line GBLB[4] (corresponding to the first and fifth columns), and the other end is connected to the fourth reference voltage generation circuit 43-4.

[0289] The second sense amplifier section 44B includes: a first sense amplifier 44-21, which is connected to the third output line LO3 of the column selector 42 corresponding to the first global bit line GBLT[1] and the first global bit line GBLT[5] (corresponding to the second and sixth columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second sense amplifier 44-22, which is connected to the third output line LO3 of the column selector 42 corresponding to the first global bit line GBLT[1] and the first global bit line GBLT[5] (corresponding to the second and sixth columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0290] Additionally, the second sense amplifier section 44B includes: a third sense amplifier 44-23, which is connected to the third output line LO3 of the column selector 42 corresponding to the first global bit line GBLT[1] and the first global bit line GBLT[5] (corresponding to the second and sixth columns), and the other end is connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier 44-24, which is connected to the third output line LO3 of the column selector 42 corresponding to the first global bit line GBLT[1] and the first global bit line GBLT[5] (corresponding to the second and sixth columns), and the other end is connected to the fourth reference voltage generation circuit 43-4.

[0291] Additionally, the second sense amplifier section 44B includes: a first sense amplifier 44-31, which is connected to the fourth output line LO4 of the column selector 42 corresponding to the second global bit lines GBLB[1] and GBLB[5] (corresponding to the second and sixth columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second sense amplifier 44-32, which is connected to the fourth output line LO4 of the column selector 42 corresponding to the second global bit lines GBLB[1] and GBLB[5] (corresponding to the second and sixth columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0292] Additionally, the second sense amplifier section 44B includes: a third sense amplifier 44-33, which is connected to the fourth output line LO4 of the column selector 42 corresponding to the second global bit line GBLB[1] and the second global bit line GBLB[5] (corresponding to the second and sixth columns), and the other end is connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier 44-34, which is connected to the fourth output line LO4 of the column selector 42 corresponding to the second global bit line GBLB[1] and the second global bit line GBLB[5] (corresponding to the second and sixth columns), and the other end is connected to the fourth reference voltage generation circuit 43-4.

[0293] The third readout amplifier section 44C has the same structure as the first readout amplifier section 44A. Although the figure is omitted, it includes: a first readout amplifier, which is connected to the fifth output line LO11 of the column selector 42 corresponding to the first global bit line GBLT[2] and the first global bit line GBLT[6] (corresponding to the third and seventh columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second readout amplifier, which is connected to the fifth output line LO11 of the column selector 42 corresponding to the first global bit line GBLT[2] and LBLT[6] (corresponding to the third and seventh columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0294] Additionally, the third sense amplifier section 44C includes: a third sense amplifier connected to the fifth output line LO11 of the column selector 42 corresponding to the first global bit line GBLT[2] and the first global bit line GBLT[6] (corresponding to the third and seventh columns), and the other end connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier connected to the fifth output line LO11 of the column selector 42 corresponding to the first global bit line GBLT[2] and the first global bit line GBLT[6] (corresponding to the third and seventh columns), and the other end connected to the fourth reference voltage generation circuit 43-4.

[0295] Additionally, the third readout amplifier section 44C includes: a first readout amplifier connected to the sixth output line LO12 of the column selector 42 corresponding to the second global bit lines GBLB[2] and GBLB[6] (corresponding to the third and seventh columns), and the other end connected to the first reference voltage generation circuit 43-1; and a second readout amplifier connected to the sixth output line LO12 of the column selector 42 corresponding to the second global bit lines GBLB[2] and GBLB[6] (corresponding to the third and seventh columns), and the other end connected to the second reference voltage generation circuit 43-2.

[0296] Additionally, the third sense amplifier section 44C includes: a third sense amplifier connected to the sixth output line LO12 of the column selector 42 corresponding to the second global bit line GBLB[2] and the second global bit line GBLB[6] (corresponding to the third and seventh columns), and the other end connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier connected to the sixth output line LO12 of the column selector 42 corresponding to the second global bit line GBLB[2] and the second global bit line GBLB[6] (corresponding to the first and fifth columns), and the other end connected to the fourth reference voltage generation circuit 43-4.

[0297] The fourth readout amplifier section 44D has the same structure as the first readout amplifier section 44A. Although the figure is omitted, it includes: a first readout amplifier, which is connected to the seventh output line LO13 of the column selector 42 corresponding to the first global bit line GBLT[3] and the first global bit line GBLT[7] (corresponding to the fourth and eighth columns), and the other end is connected to the first reference voltage generation circuit 43-1; and a second readout amplifier, which is connected to the seventh output line LO13 of the column selector 42 corresponding to the first global bit line GBLT[3] and LBLT[7] (corresponding to the fourth and eighth columns), and the other end is connected to the second reference voltage generation circuit 43-2.

[0298] Additionally, the fourth sense amplifier section 44D includes: a third sense amplifier connected to the seventh output line LO13 of the column selector 42 corresponding to the first global bit line GBLT[3] and the first global bit line GBLT[7] (corresponding to the fourth and eighth columns), with the other end connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier connected to the seventh output line LO13 of the column selector 42 corresponding to the first global bit line GBLT[3] and the first global bit line GBLT[7] (corresponding to the fourth and eighth columns), with the other end connected to the fourth reference voltage generation circuit 43-4.

[0299] Additionally, the fourth readout amplifier section 44D includes: a first readout amplifier connected to the eighth output line LO14 of the column selector 42 corresponding to the second global bit lines GBLB[3] and GBLB[7] (corresponding to the fourth and eighth columns), and the other end connected to the first reference voltage generation circuit 43-1; and a second readout amplifier connected to the eighth output line LO14 of the column selector 42 corresponding to the second global bit lines GBLB[3] and GBLB[7] (corresponding to the fourth and eighth columns), and the other end connected to the second reference voltage generation circuit 43-2.

[0300] Additionally, the fourth sense amplifier section 44D includes: a third sense amplifier connected to the eighth output line LO14 of the column selector 42 corresponding to the second global bit line GBLB[3] and the second global bit line GBLB[7] (corresponding to the fourth and eighth columns), and the other end connected to the third reference voltage generation circuit 43-3; and a fourth sense amplifier connected to the eighth output line LO14 of the column selector 42 corresponding to the second global bit line GBLB[3] and the second global bit line GBLB[7] (corresponding to the fourth and eighth columns), and the other end connected to the fourth reference voltage generation circuit 43-4.

[0301] According to the connection state of the readout circuit of the above structure, the first readout amplifiers 44-1, 44-11, 44-21, 44-31, the second readout amplifiers 44-2, 44-12, 44-22, 44-32, the third readout amplifiers 44-3, 44-13, 44-23, 44-33, and the fourth readout amplifiers 44-4, 44-14, 44-24, 44-34 are connected to the first reference voltage generation circuit 43-1 to the fourth reference voltage generation circuit 43-4. The first reference voltage Ref1 to the fourth reference voltage Ref4 generated by the reference voltage generation circuit 43-1 to the fourth reference voltage generation circuit 43-4 are generated by short-circuiting the corresponding first global bit line GBLT and the second global bit line GBLB. Therefore, one reference voltage supply line connects eight readout amplifiers.

[0302] Therefore, during charge sharing, the difference in parasitic load between the first global bit line GBLT and the second global bit line GBLB can be eliminated, enabling... Figure 15A and Figure 15B The slopes of the potential levels of the first global bit line GBLT and the second global bit line GBLB shown are consistent with the slope of the reference voltage. By eliminating the influence of manufacturing deviations in semiconductor integrated circuits through charge sharing, the error of the reference voltage (in the above example, the first reference voltage to the fourth reference voltage) used for data readout can be further reduced, thereby enabling more accurate and reliable data readout.

[0303] That is, according to the first embodiment, in a semiconductor integrated circuit that uses charge sharing to control the potential level, deviations in the readout current can be suppressed, and furthermore, in a semiconductor integrated circuit equipped with SRAM bit cells, product operations can be performed on the semiconductor integrated circuit.

[0304] Here, the product sum operation performed in the above embodiments will be explained.

[0305] Figure 19 This is a schematic diagram illustrating the digital multiplication and summation circuit.

[0306] The product summation circuit 50 includes a first adder 53 having two four-bit adders 51 and 52 and a second adder 55 having a five-bit adder 54.

[0307] exist Figure 18 In the example, assume that the four memory array blocks operate in CiM mode and each calculates a 3-bit multiplication result (product).

[0308] The four storage array blocks are divided into two groups of two, and the four-bit adders 51 and 52 of the first adder 53 are used to perform addition operations to obtain four-bit addition result data.

[0309] By utilizing the five-bit adder 54 of the second adder 55, the two four-bit addition results obtained as a result are added together to obtain a five-bit product sum result.

[0310] In this way, by combining the addition part in a digital manner, it is possible to perform multi-digit (multi-bit) product sum operations, which can be easily handled.

[0311] In the above structure, when performing multi-digit product summation or when outputting the product summation result, multiple readout amplifier circuits can simultaneously output multiple bits.

[0312] The above description describes a digital multiplication circuit. Although the detection accuracy is reduced, it can still perform analog multiplication, that is, add the voltage values ​​in analog order and perform analog-to-digital conversion.

[0313] In this case, it is also possible to achieve improved accuracy based on charge sharing.

[0314] [2] Second implementation method

[0315] Next, the second embodiment will be described.

[0316] First, the problem to be solved by the second embodiment will be explained.

[0317] In conventional charge collection (bit line capacitance sharing) circuits, when implementing CiM operation (charge sharing among multiple memory cells), depending on the bit line potential, local bit line pairs may be short-circuited, resulting in potential sharing.

[0318] This is because the existing technology envisions charge sharing operation for only one memory cell. Charge sharing operation for multiple memory cells is beyond the scope of this concept. In the case of charge sharing operation for multiple memory cells, the potential of the bit line pair changes during CiM operation (charge sharing operation). The bit line capacitance sharing circuit of both sides of the bit line pair is connected, causing the bit line pair to be short-circuited and no longer able to perform the desired operation.

[0319] Therefore, the object of this second embodiment is to provide a semiconductor integrated circuit that can operate correctly even when multiple memory cells share charge.

[0320] Figure 20 This is an explanatory diagram illustrating the specific circuit structure of the data readout section of the storage cell array in the storage device of the second embodiment.

[0321] exist Figure 20 The diagram shows the cell array blocks 61-0 to 61-n corresponding to (n+1) columns of [n: integers greater than 2].

[0322] In this case, since cell array blocks 61-0 to 61-n have the same structure, cell array block 61-0 will be used as an example for explanation.

[0323] The cell array block 61-0 includes a cell array (not shown), a pre-charge auxiliary circuit 62, an operation mode switching circuit 63, a latch circuit 64, a local column selector 65, a global bit line selector 66, a reference potential generation data setting circuit 67, and a data reset circuit 68.

[0324] The selected memory cell of the cell array (not shown) is connected to the first local bit line LBLT0 and the second local bit line LBLB0.

[0325] During pre-charging, the pre-charging auxiliary circuit 62 releases a charge corresponding to the change in bit line potential while the first local bit line LBLT0 and the second local bit line LBLB0 are short-circuited.

[0326] The operation mode switching circuit 63 sets the operation mode to either the normal mode, which performs read / write operations on the selected column as usual, or the CiM mode, which performs a product operation on the data of multiple memory cells.

[0327] As a result, in normal mode, the object's storage unit is connected to the first global bit line GBLT and the second global bit line GBLB via the first local bit line LBLT and the second local bit line LBLB for read or write processing.

[0328] In addition, in CiM mode, the data of multiple storage units of the object are multiplied and summed. The result of the multiplication and summation is output to the readout circuit RC via the first global bit line GBLT and the second global bit line GBLB selected by the global bit line selector 66.

[0329] The latching circuit 64 latches and holds the "H" / "L" state before the operation so that the connection state of the shared circuit during the CiM operation remains unchanged.

[0330] Column selector 65 selects the column of the read object or the column of the product sum operation object from the (n+1) columns corresponding to cell array blocks 61-0 to 61-n, and connects it to global bit line selector 66.

[0331] Global bit line selector 66 selects and connects the first global bit line GBLT and the second global bit line GBLB.

[0332] The reference potential generation data setting circuit 67 sets the data for generating the reference potential for the memory cell array.

[0333] When the cell array block becomes a non-operation block, the data reset circuit 68 resets the memory cell by setting "0" data.

[0334] Based on the above structure, it can operate correctly even when multiple storage cells share charge.

[0335] [2.1] First variation of the second embodiment

[0336] Figure 21 This is an explanatory diagram of a first variation of the second embodiment.

[0337] Figure 21 The first variation of the second embodiment and Figure 20 The difference in the second embodiment is that it has a latch circuit 64A with a different structure instead of latch circuit 64.

[0338] According to this structure, the same effect as the second embodiment can be obtained.

[0339] [2.2] Second variation of the second embodiment

[0340] Figure 22 This is an explanatory diagram of a second variation of the second embodiment.

[0341] Figure 22 The second variation of the second embodiment and Figure 20 The difference in the second embodiment is that the latch circuit 64B is configured to also function as a boost circuit, which is formed by adding a readout boost circuit 69 to the structure of the latch circuit 64 to improve the rise / fall speed of the signal and thus improve the readout speed.

[0342] The readout boost circuit 69 has a pair of transistors TR1 and TR2. When reading data, the boost readout control signal LSA2 is turned on to promote current supply and increase the rise / fall speed of the signal.

[0343] According to this structure, in addition to the effects of the second embodiment, an improvement in data readout speed can also be achieved.

[0344] [2.3] Operation of the second embodiment

[0345] Next, the specific actions will be explained.

[0346] Figure 23A yes Figure 21 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit.

[0347] Figure 23B yes Figure 21 The timing diagram of the operation of the column on the reference potential generation side in the CiM mode of the circuit.

[0348] In the columns on the computation side of CiM mode, such as Figure 23A As shown, at time t1, the word line WL corresponding to the memory cell that is actually being operated on changes to the "H" level. Based on the data held by the memory cell connected to the memory cell corresponding to the word line WL, the first local bit line LBLT or the second local bit line LBLB changes to the "L" level.

[0349] In addition, the precharge enable lines PRE0 to PREn switch to the "L" level, and the precharge ends.

[0350] Furthermore, the operation mode switching lines CiM0 to CiMn switch to the "L" level, and the operation mode switches to CiM mode.

[0351] On the other hand, in the column on the generation side of the reference potential, such as Figure 23B As shown, at time t1, the data setting lines B0 to Bn corresponding to the storage cells used to actually generate the reference potential change to the "H" level, and the corresponding storage cells change to the "L" level.

[0352] In addition, the precharge enable lines PRE0 to PREn switch to the "L" level, and the precharge ends.

[0353] Furthermore, the operation mode switching lines CiM0 to CiMn change to the "L" level, and the operation mode changes to the reference potential supply mode corresponding to the CiM mode.

[0354] Then, at time t2, the word line WL changes to the "L" level. Additionally, the boost readout control signals LSA0 to LSAn change to the "H" level, and the latch circuit 64 fetches data.

[0355] When time t3 arrives, column selection lines CSL1 to CSLn change to the "H" level. In the column on the operation side, via latch circuit 64, the first local bit line LBLT and the second local bit line LBLB corresponding to the memory cell that is actually being operated on change to the specified level corresponding to the operation result.

[0356] As a result, the first global bit line GBLT and the second global bit line GBLB of the column on the operation side are converted to the level corresponding to the operation result of the column on the operation side, and the operation result is output.

[0357] On the other hand, in the column on the reference potential generation side, the first local bit line LBLT and the second local bit line LBLB corresponding to the memory cell that generates the reference potential become charge-shared, and are transformed into the same specified level corresponding to the value of the reference potential, and the reference potential is output.

[0358] Then, at time t4, when the column selection lines CSL1 to CSLn change to the "L" level, at time t5, in the columns on the operation side, the precharge enable lines PRE0 to PREn change to the "H" level, and precharging begins.

[0359] Furthermore, when the operation mode switching lines CiM0 to CiMn change to the "H" level, the operation mode changes to the normal mode and the processing ends.

[0360] On the other hand, in the column on the reference potential generation side, at time t4, when the column selection lines CSL1 to CSLn change to the "L" level, at time t5, the precharge enable lines PRE0 to PREn change to the "H" level, and precharging begins.

[0361] Furthermore, when the operation mode switching lines CiM0 to CiMn change to the "H" level, the operation mode changes to the normal mode and the processing ends.

[0362] As explained above, in a semiconductor integrated circuit with SRAM bit cells, the memory device can operate correctly even when multiple memory banks share charge, generate a highly reliable reference potential, and perform highly reliable product operations on the semiconductor integrated circuit.

[0363] [2.4] Effects of the second embodiment

[0364] Here, the effects of the second embodiment will be explained.

[0365] Figure 24A This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB for each local block in an 8-bit CiM without the use of charge collection circuitry.

[0366] Figure 24B This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block in an 8-bit CiM circuit where a charge collection circuit is used to share bit lines between two columns.

[0367] Figure 24C This is an illustration of the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block in an 8-bit CiM circuit where bit lines are shared across four columns using a charge collection circuit.

[0368] exist Figures 24A-24C In the diagram, the vertical axis represents the potential of either the first global bit line GBLT or the second global bit line GBLB, with the unit being V.

[0369] Additionally, the horizontal axis represents the stored data values ​​(0-8) of the local block.

[0370] In this case, with the local bit line capacitance set to LBC, the global bit line capacitance set to GBC, and the power supply voltage set to PWV, the bit line potential VBL, which is the potential of the first global bit line GBLT or the second global bit line GBLB, is calculated by the following formula.

[0371] VBL=(1-(LBC / (GBC+LBC))×PWV

[0372] like Figure 24A As shown, the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block without the use of a charge collection circuit is ΔV1[V].

[0373] In contrast, such as Figure 24B As shown, when bit lines are shared between two columns using a charge collection circuit, the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block is ΔV2[V] (>ΔV1[V]).

[0374] Moreover, such as Figure 24CAs shown, when bit lines are shared among the four columns using a charge collection circuit, the potential difference between the first global bit line GBLT and the second global bit line GBLB of each local block is ΔV3[V] (>ΔV2[V]>ΔV1[V]).

[0375] That is, it can be seen that the more shared objects and bit lines there are, the greater the potential difference between the potential of the first global bit line GBLT and the potential of the second global bit line GBLB of each local block.

[0376] As explained above, by increasing the number of shared columns, the bit line potential difference of each local block increases.

[0377] [2.5] Specific example of the second embodiment with a storage unit

[0378] [2.5.1.] First example of composition

[0379] Figure 25 This is an explanatory diagram of a first configuration example of a memory cell array in the case of 8-bit CiM.

[0380] Figure 25 This is an example of a column consisting of two interconnected arrays of eight memory cells.

[0381] Column C0 has local arrays LA_00 to LA_07.

[0382] In addition, column C1 has local arrays LA_10 to LA_17.

[0383] exist Figure 25 For example, the description "H / HL / H" in the right box of local arrays LA_02 and LA_12 indicates that the potential level of the first local bit line LBLT of local array LA_02 is "H" level and the potential level of the second local bit line LBLB of local array LA_02 is "H" level, the potential level of the first local bit line LBLT of local array LA_12 is "L" level and the potential level of the second local bit line LBLB of local array LA_12 is "H" level.

[0384] In addition, Figure 25 For example, the description of "charge collector" outside the right frame of local arrays LA_02 and LA_12 indicates that charge collection circuits are used in local arrays LA_02 and LA_12, with bit lines shared between the two columns.

[0385] exist Figure 25The reason why there are parts where bit lines are shared between two columns and parts where bit lines are not shared between two columns is to clearly identify the difference when the two local arrays of an object are at different levels.

[0386] As a result, it is not necessary to connect the global bit lines to generate a reference potential. Different reference potentials can be generated on the first global bit line GBLT and the second global bit line GBLB. Therefore, data can be reliably read out over a small area, and the product sum operation results can be obtained correctly.

[0387] [2.5.2] Second Construction Example

[0388] Figure 26 This is an explanatory diagram of a second configuration example of a memory cell array in the case of 8-bit CiM.

[0389] Figure 26 This is an example of a column consisting of two interconnected arrays of eight memory cells.

[0390] Column C0 has local arrays LA_00 to LA_07.

[0391] In addition, column C1 has local arrays LA_10 to LA_17.

[0392] exist Figure 26 In the same situation as Figure 25 The situation is similar; there is no need to connect the global bit lines to generate a reference potential. Different reference potentials can be generated on the first global bit line GBLT and the second global bit line GBLB. Therefore, data can be reliably read out with a small area, and the product sum operation results can be obtained correctly.

[0393] [2.5.3] Third example

[0394] Figure 27 This is an explanatory diagram of a third configuration example of a memory cell array in the case of 8-bit CiM.

[0395] exist Figure 27 In the example, the difference from the above-mentioned examples is that it includes... Figure 25 , Figure 26 The same applies to the case of using charge collection circuitry to share bit lines between two columns and the case of using two adjacent columns (not shown) to share bit lines between four columns.

[0396] Column C0 has local arrays LA_00 to LA_07.

[0397] In addition, column C1 has local arrays LA_10 to LA_17.

[0398] exist Figure 25 For example, the description of "charge collector" outside the right frame of local arrays LA_02 and LA_12 indicates that charge collection circuits are used in local arrays LA_02 and LA_12, with bit lines shared between the two columns.

[0399] exist Figure 27 The reason why there are parts where bit lines are shared between four columns, parts where bit lines are shared between two columns, and parts where bit lines are not shared between two columns is to make the level difference between the two local arrays of the object clearer.

[0400] As a result, it is not necessary to connect the global bit lines to generate a reference potential. Different reference potentials can be generated on the first global bit line GBLT and the second global bit line GBLB. Therefore, data can be reliably read out with a small area, and the product sum operation results can be obtained correctly.

[0401] [3] Third implementation method

[0402] Next, the third embodiment will be described.

[0403] First, the problem to be solved by the third embodiment will be explained.

[0404] As mentioned above, by adopting a charge-sharing structure, the signal amplitude of the global bit line can be improved. However, in order to avoid changing the connection state of the common circuit during CiM operation, a latching circuit is required for each bit line to latch the "H" level / "L" level state before the operation. This increases the circuit area and makes it difficult to construct in a small area.

[0405] Furthermore, when the target bit cell is of high density, the area of ​​the structure with latch circuits set for each bit line increases, so it is necessary to suppress the increase in area caused by setting latch circuits via local column selectors.

[0406] However, there are concerns about degraded write performance due to the setting of local column selectors.

[0407] Therefore, the object of this third embodiment is to provide a semiconductor integrated circuit that can obtain the same signal amplitude of the bit line as in the case of charge sharing without charge sharing.

[0408] In addition, such as Figures 24A-24C As shown, when using charge harvesting technology, with the local bit line capacitance set to LBC, the global bit line capacitance set to GBC, and the power supply voltage set to PWV, the potential of the first global bit line GBLT or the potential of the second global bit line GBLB, i.e., the bit line potential VBL, can be calculated using the following formula.

[0409] VBL=(1-(LBC / (GBC+LBC))×PWV

[0410] According to this formula, charge harvesting technology improves the signal amplitude of the global bit line by increasing the size of the molecule part of the formula.

[0411] Therefore, as can be seen from this equation, in order to improve the signal amplitude of the global bit line, even reducing the denominator of the equation can improve the signal amplitude of the global bit line.

[0412] That is, as long as the sum of the local bit line capacitance LBC and the global bit line capacitance GBC decreases, it is sufficient.

[0413] Figure 28 This is an explanatory diagram of the main parts of the storage device that is the application object of the third embodiment.

[0414] The storage device 10A includes n+1 (n is an integer greater than or equal to 2) local arrays LA_0 to LA_n, a first global bit line GBLT, a second global bit line GBLB, and a readout circuit RC.

[0415] Each local array LA_x has a first local bit line LBLTx, a second local bit line LBLBx, memory cells Cell0 to Celln, a latch circuit LAT, a first switch swTx, and a second switch swBx.

[0416] In the above structure, each memory cell Cell0 to Celln is connected between the first local bit line LBLTx and the second local bit line LBLBx.

[0417] In addition, the first local bit line LBLTx is connected to the readout circuit RC via the latch circuit LAT and the first switch swTx.

[0418] Furthermore, the second local bit line LBLBx is connected to the readout circuit RC via the latch circuit LAT and the second switch swBx.

[0419] Furthermore, when the first switch swTx and the second switch swBx are selected according to the state of the local bit line through the column selection line CSL[x], they become in the on state. The first local bit line LBLTx, which will be in the "L" state, is connected to the corresponding global bit line GBLT, and the second local bit line LBLBx is connected to the second global bit line GBLB.

[0420] Next, the operation of the third embodiment will be explained.

[0421] Figure 29 yes Figure 28 The timing diagram of the operation of the column on the operation side in CiM mode of the circuit.

[0422] In the columns on the computation side of CiM mode, such as Figure 29 As shown, at time t1, the word lines WL0[0] to WL1[0] corresponding to the memory cell that is actually being operated on change to the "H" level, and the corresponding local bit lines change to the "L" level according to the data held by the memory cell.

[0423] In this state, the action mode switches to CiM mode.

[0424] Then, at time t2, word lines WL0[0] to WL1[0] change to the "L" level.

[0425] When the boost readout control signals LSA0 to LSA1 change to the "H" level at time t3, in the column on the operation side, at time t4, the first local bit lines LBLT0 and LBLT1 and the second local bit lines LBLB0 and LBLB1 corresponding to the memory cell that is actually being operated on change to the specified level corresponding to the operation result.

[0426] Then, at time t5, the boost readout control signals LSA0 to LSA1 change to the "L" level.

[0427] In this case, in the third embodiment, among the first local bit line LBLT and the second local bit line LBLB corresponding to the memory cell that is actually being operated on, only the first local bit line LBLT or the second local bit line LBLB with the "L" level is connected to the first global bit line GBLT and the second global bit line GBLB, and the first local bit line LBLT and the second local bit line LBLB with the "H" level are not connected to the first global bit line GBLT and the second global bit line GBLB.

[0428] On the other hand, in the existing example where only the first local bit line LBLT and the second local bit line LBLB corresponding to the memory cells of all operands are connected to the first global bit line GBLT and the second global bit line GBLB, charge sharing must be performed when the first local bit line LBLT is at a "H" level and the second local bit line LBLB is at a "H" level. Furthermore, this state is a so-called floating state, therefore coupling noise countermeasures are required depending on various signal transitions.

[0429] In contrast, in the third embodiment, since the above-mentioned state does not occur in principle, the existing circuit can be reused or shared, and the affinity with the normal operating mode is also increased.

[0430] As a result, it is not necessary to set up latch circuits for each bit line, which can reduce the circuit area and allow the circuit to be constructed in a small area.

[0431] Furthermore, even when the target bit cell is of high density, there is no need to set up latch circuits for each bit line, nor is there a need to set up local column selectors, so the write characteristics will not deteriorate.

[0432] [4] Fourth implementation method

[0433] Next, the fourth embodiment will be described.

[0434] First, the problem to be solved by the fourth embodiment will be explained.

[0435] Figure 30 This is an illustration diagram of a conventional latch-type decision circuit.

[0436] When the potential between the source and drain terminals of the transistor constituting the differential input section (RBLT, Ref) changes from the initial intermediate potential or power supply potential to the low-potential side power supply VSS potential at the rising moment of the sense amplifier enable signal SAE, the gate potential of the differential input section also decreases due to coupling noise.

[0437] Therefore, when performing CiM operations, the potential of the bit lines varies depending on the state of the data of the operand, and the influence of coupling noise is not constant. Thus, the CiM operation itself may not be the intended operation.

[0438] Figure 31 This is an explanatory diagram of the signal states of each part of a conventional latch-type decision circuit.

[0439] For example, since the reference potential Ref changes according to the state of the data of the operand, therefore... Figure 31 As shown in the dashed circle, when making a determination without a potential difference, the determination of the input bit line potential RBLT may be a false determination.

[0440] Figure 32 This is an explanatory diagram of a circuit example of the latch-type determination circuit according to the fourth embodiment.

[0441] like Figure 32 As shown, by setting the initial potential of the source-drain terminals of transistors TR1 and TR2, which constitute the differential input section, to the low-potential side power supply potential VSS, the power supply fluctuations when transistors TR1 and TR2 operate are reduced, and the influence of coupling noise is suppressed.

[0442] In this case, the increase in bias voltage is attributed to manufacturing deviations in transistors TR1 and TR2.

[0443] However, in the fourth embodiment, by increasing the size of transistors TR1 and TR2, the bias voltage can be reduced, thereby significantly reducing the effects of power supply fluctuations and suppressing coupling noise during the operation of transistors TR1 and TR2.

[0444] [5] Fifth implementation method

[0445] The fifth embodiment is an implementation that, when multiple data readout circuits for reading out are provided, suppresses noise variations associated with physical configuration constraints and enables correct reading out determination.

[0446] Here, the lower the potential level, the smaller the potential difference (read margin) between the read bit line (global bit line) and the reference bit line.

[0447] Therefore, in this fifth embodiment, the data readout circuit that uses a reference bit line potential with a smaller assumed readout margin for readout determination is configured in a location that is less susceptible to noise variations.

[0448] The following is a more detailed explanation.

[0449] Figure 33 This is a graph illustrating the potential simulation results of the global bit line and the reference bit line.

[0450] Regarding the potential level curve of the global bit line, such as Figure 33 As shown, the lower the potential level, the smaller the slope.

[0451] Therefore, it can be concluded that the lower the potential level, the smaller the potential difference between the global bit lines RBLT and RBLB and the reference bit line REF, and the smaller the read margin.

[0452] A small read margin means that it is more susceptible to noise variations.

[0453] That is, in the first aspect of the fifth embodiment described below, the data readout circuit connected to the reference bit line with the assumed small readout margin is configured in a physical location close to the readout circuit drive buffer (configured to operate at the beginning).

[0454] Furthermore, the potential line potential (BLV) is represented by the following formula.

[0455] Potential line potential BLV = (1 - (CLB / (CGB+CLB)) × PWV)

[0456] Here, CLB is the capacitance of the local bit line, CGB is the capacitance of the global bit line, and PWV is the power supply voltage.

[0457] Therefore, in the second aspect of the fifth embodiment described below, the circuit that uses a reference bit line potential with a small assumed readout margin to determine readout is configured in a location with a large wiring load.

[0458] [5.1] First form of the fifth embodiment

[0459] Figure 34 This is an explanatory diagram of the first aspect of the fifth embodiment.

[0460] Figure 34 This refers to the case where 32 data readout circuits DRC1 to DRC32 are set up to read out 32 values ​​simultaneously when performing 8-bit product sum operations.

[0461] exist Figure 34 In this circuit, the drive signal DRV from the data readout circuit drive buffer circuit is supplied in parallel to eight data readout circuits DRC1 to DRC8, DRC9 to DRC16, DRC17 to DRC24, and DRC25 to DRC32.

[0462] Therefore, for example, in the data readout circuits DRC1 to DRC8, affected by the wiring load caused by the wiring length, the data readout circuits DRC1 → DRC2 → … → DRC7 → DRC8 operate in sequence.

[0463] As mentioned above, the lower the reference bit line potential, the smaller the read margin, and therefore the more susceptible it is to noise fluctuations. Therefore, by configuring it to be located physically closer to the data readout circuit drive buffer circuit, it can start operating earlier.

[0464] Therefore, in Figure 34 In the example case, a reference potential Ref4 is supplied to the first driven readout circuit group DRCG1, which is located physically closest to the data readout circuit drive buffer circuit DRDV.

[0465] Furthermore, a reference potential Ref3 is supplied to the readout circuit group DRCG2, which is located physically closer to the data readout circuit drive buffer circuit and is driven next to the readout circuit group DRCG1.

[0466] Similarly, a reference potential Ref2 is supplied to the readout circuit group DRCG3.

[0467] Furthermore, a reference potential Ref1 is supplied to the last-driven readout circuit group DRCG4, which is located at the position furthest from the data readout circuit drive buffer circuit in physical terms.

[0468] Therefore, it is possible to reduce the impact of noise variations caused by the operation of other readout circuits throughout the entire readout circuit, and to perform accurate data readout.

[0469] [5.2] Second form of the fifth embodiment

[0470] Figure 35 This is an explanatory diagram of the second aspect of the fifth embodiment.

[0471] Figure 35 It also includes the case where 32 data readout circuits DRC1 to DRC32 are set up to read out 32 values ​​simultaneously when performing 8-bit product summation operations.

[0472] As described above, the data readout circuit connected to the reference bit line with the assumed small readout margin is configured in a physical location close to the readout circuit drive buffer (configured for initial operation).

[0473] Furthermore, it is preferable to configure the data readout circuit connected to the reference bit line with the assumed small readout margin at a location far from the memory cell array.

[0474] This is because the more the readout circuit is located physically away from the cell array, the greater the wiring load (the greater the global bit line capacitance CGB in the above formula), and therefore the higher the bit line potential BLV is assumed to be.

[0475] In addition, Figure 35 In this process, the drive signal DRV from the data readout circuit drive buffer circuit is supplied in the order of data readout circuit group DRCG11 → data readout circuit group DRCG12 → data readout circuit group DRCG13 → data readout circuit group DRCG14.

[0476] Therefore, in the data readout circuit groups DRCG11 to DRCG14, affected by the wiring load caused by the wiring length, they operate sequentially in the order of data readout circuit group DRCG11 → data readout circuit group DRCG12 → data readout circuit group DRCG13 → data readout circuit group DRCG14.

[0477] As mentioned above, the lower the reference bit line potential, the smaller the read margin, and therefore the more susceptible it is to noise fluctuations. Therefore, by configuring it to be located physically closer to the data readout circuit drive buffer circuit, it can start operating earlier.

[0478] Furthermore, the further the read circuit is located physically from the memory cell array MCA, the greater the wiring load (the greater the global bit line capacitance CGB in the above formula), and therefore the higher the bit line potential BLV is assumed to be.

[0479] Therefore, for the data readout circuit group DRCG11 (= data readout circuits DRC25~DRC32) which is located at the position furthest from the memory cell array MCA, the reference potential Ref4 with the lowest potential is supplied at the position closest to the data readout circuit drive buffer circuit.

[0480] Furthermore, a reference potential Ref3 is supplied to the readout circuit group DRCG12 (= data readout circuits DRC17 to DRC24), which is located at the second farthest position from the memory cell array MCA and is driven below the readout circuit group DRCG11.

[0481] Similarly, a reference potential Ref2 is supplied to the readout circuit group DRCG3 (=data readout circuits DRC9~DRC16).

[0482] Furthermore, a reference potential Ref1 is supplied to the last-driven readout circuit group DRCG14 (= data readout circuits DRC1 to DRC8), which is located physically closest to the memory cell array MCA.

[0483] Therefore, it is possible to reduce the impact of noise variations caused by the operation of other readout circuits throughout the entire readout circuit, and to perform accurate data readout.

[0484] [6] Effects of the implementation method

[0485] As explained above, according to various embodiments, in a semiconductor integrated circuit that uses charge sharing to control the potential level, deviations in the readout current can be suppressed, and thus, summation operations can be performed on the semiconductor integrated circuit in a semiconductor integrated circuit equipped with SRAM bit cells.

[0486] In addition, by increasing the number of global circuit blocks (columns) shared during charge sharing, the bit line potential difference of each local circuit block is increased, enabling reliable determination.

[0487] Moreover, even without charge sharing, it is possible to obtain the same bit line signal amplitude as when charge sharing is performed.

[0488] In addition, the bias voltage in the determination circuit can be reduced, thereby reducing power supply fluctuations when the input transistor operates, suppressing the influence of coupling noise, and enabling accurate determination.

[0489] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0490] For example, the above description states that the number of memory cells connected to the local bit lines is the same in each local cell array, but it can also be configured to vary for each local array. This structure increases the design flexibility.

Claims

1. A semiconductor integrated circuit that uses charge sharing to control the potential level, characterized in that, The semiconductor integrated circuit operates within a semiconductor correction circuit using a potential level controlled by charge sharing between multiple circuit blocks and a global circuit block. The circuit block contains multiple storage units. The potential level is set to the potential level of the read line used to read data provided according to the state of the storage cell.

2. The semiconductor integrated circuit according to claim 1, characterized in that, The semiconductor integrated circuit includes a potential level control unit that, during operation, causes the circuit blocks that are not the objects of the operation to output a potential level equivalent to "L" or "H".

3. The semiconductor integrated circuit according to claim 1, characterized in that, The potential level obtained by the operation using the potential level provided by the charge sharing is compared with the reference potential level obtained using the potential level provided by the charge sharing, and the result is output as the operation result.

4. The semiconductor integrated circuit according to claim 3, characterized in that, The circuit block comprises multiple memory cells with complementary pairs of bit lines, and the global circuit block has complementary pairs of bit lines. The semiconductor integrated circuit includes a switching circuit that short-circuits the bit lines of the complementary pair when the reference potential level is generated.

5. The semiconductor integrated circuit according to claim 3, characterized in that, The reference potential level is generated using the circuit block that does not perform any calculations.

6. The semiconductor integrated circuit according to claim 3, characterized in that, The semiconductor integrated circuit has a circuit block for generating the reference potential level.

7. The semiconductor integrated circuit according to claim 3, characterized in that, The potential level within the circuit block used to generate the reference potential level varies depending on the generated reference potential level.

8. The semiconductor integrated circuit according to claim 4, characterized in that, The switching circuit that short-circuits the bit lines is located in one of the circuit blocks or the global circuit blocks.

9. The semiconductor integrated circuit according to claim 1, characterized in that, The semiconductor integrated circuit has a latching circuit that maintains the state before processing until the data processing is completed when charge sharing occurs between the circuit block and the global circuit block.

10. The semiconductor integrated circuit according to claim 9, characterized in that, The semiconductor integrated circuit includes a switching circuit that connects bit lines between multiple adjacent circuit blocks based on the holding data of the latch circuit.

11. The semiconductor integrated circuit according to claim 10, characterized in that, Based on the state of the latch circuit, the number of bit lines connected to adjacent circuit blocks is set.

12. The semiconductor integrated circuit according to claim 11, characterized in that, The number of bit lines connected in the adjacent multiple circuit blocks is set only when generating a reference potential level.

13. The semiconductor integrated circuit according to claim 3, characterized in that, Based on the state of the circuit block, switch whether one of the bit lines of the complementary pair between the circuit block and the global circuit block can be connected.

14. The semiconductor integrated circuit according to claim 3, characterized in that, The reference potential level is used to determine the potential level of multiple calculation results.

15. The semiconductor integrated circuit according to claim 3, characterized in that, The semiconductor integrated circuit has a circuit that performs calculations on "H" level data or "L" level data output based on the reference potential level and the potential level of the calculation result.

16. The semiconductor integrated circuit according to claim 1, characterized in that, The initial potential of the source-drain terminals of the MOS transistor constituting the differential input section is set to the power supply potential on the substrate terminal side of the MOS transistor.

17. The semiconductor integrated circuit according to claim 1, characterized in that, The readout circuit group is configured to operate first in a readout circuit group having multiple readout circuits for reading data provided according to the state of the storage cell, and connected to a lower of a plurality of reference potential levels obtained by using the potential level provided by the charge sharing.

18. The semiconductor integrated circuit according to claim 1, characterized in that, A lower reference potential level is connected to the readout circuit group with a higher wiring load between the readout circuit group and the memory cell, which has multiple readout circuits for reading data provided according to the state of the memory cell.

19. The semiconductor integrated circuit according to claim 17, characterized in that, The group of readout circuits connected to a lower reference potential level is positioned in a location with less wiring load between it and the drive buffer circuit of the drive data readout circuit.

20. The semiconductor integrated circuit according to claim 18, characterized in that, The group of readout circuits connected to a lower reference potential level is positioned in a location with less wiring load between it and the drive buffer circuit of the drive data readout circuit.

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