Electrical timing and protocol analysis methods and systems for DRAM testing

Abstract

This invention provides an electrical timing and protocol analysis method and system for DRAM testing, belonging to the field of semiconductor chip testing technology. The method includes: generating multiple equiphase sampling clocks with the same frequency as the interface signal of the DRAM under test through a configurable clock delay chain or phase interpolator; performing time-division sampling of the interface signal using the multiple equiphase sampling clocks to obtain multiple corresponding phase sampling points within a unit interval; selecting signal sampling points from the multiple phase sampling points to obtain sampled signals for electrical characteristic checks and timing protocol checks; the electrical characteristic checks include at least one of setup and hold time checks, duty cycle checks, and signal eye diagram quality checks; the timing protocol checks include inter-instruction timing checks and / or instruction and data timing checks; triggering an exception report and saving the on-site sampled waveform when the check result is abnormal. This invention achieves real-time on-chip electrical characteristic and protocol analysis without the need for external instruments.

Description

Technical Field

[0001] This invention relates to the technical field of semiconductor chip testing, and in particular to an electrical timing and protocol analysis method and system for DRAM testing. Background Technology

[0002] With advancements in semiconductor technology and increasing chip integration, the data transfer rate of Dynamic Random Access Memory (DRAM) continues to climb. Interfaces such as DDR4, DDR5, LPDDR4, and LPDDR5 are widely used in high-performance computing, mobile devices, and data centers. In the automated testing (ATE) process of DRAM chips, verifying the signal integrity and protocol timing of high-speed interfaces has become particularly critical. Signal quality issues (such as eye diagram closure, insufficient setup / hold time, and duty cycle distortion) or protocol timing violations (such as read / write command intervals, inconsistent preambles, and burst length errors) can all lead to test failures and make it difficult to quickly pinpoint the root cause of the fault.

[0003] Currently, the industry primarily relies on external testing instruments (such as high-speed oscilloscopes and dedicated protocol analyzers) to acquire and analyze DRAM interface signals. This method typically requires inserting an interposer or using probes between the testing equipment and the chip under test (DUT) to extract the signal. However, introducing interposers and interconnects introduces significant parasitic inductance and capacitance, altering the signal transmission path characteristics. Especially with GHz-level high-speed signals, this can severely impact the accuracy of signal quality measurements, leading to distorted measurement results.

[0004] Furthermore, external oscilloscopes typically have a limited number of channels, making it impossible to simultaneously acquire and analyze all DRAM pins (such as CA, DQ, DQS, etc.). They also generally only offer electrical characteristic analysis capabilities, lacking the ability to perform real-time parsing and verification of DRAM protocol timing (such as write instructions, read instructions, preambles, and instruction sequence compliance). In high-speed batch testing scenarios, external devices cannot achieve parallel testing and analysis of multiple chips, severely limiting testing efficiency and automation levels.

[0005] In view of this, an electrical timing and protocol analysis method and system for DRAM testing is proposed to solve all or part of the above problems. Summary of the Invention

[0006] To address at least one of the aforementioned problems and deficiencies in the prior art, embodiments of the present invention provide an electrical timing and protocol analysis method and system for DRAM testing. By integrating the electrical timing and protocol analysis system within the test equipment or test chip, in-situ real-time signal data analysis is achieved without external instruments or signal interference. Employing a configurable high-precision delay chain combination, it supports simultaneous collaborative checking of electrical characteristics (such as eye diagrams, setup and hold times, duty cycles) and protocol timing (such as instruction sequences, preambles, and burst lengths) across multiple channels, enabling accurate differentiation and location of faults caused by signal quality or protocol violations. In batch testing, it improves testing efficiency and automation levels, significantly reducing testing costs. The technical solution is as follows:

[0007] According to one aspect of the present invention, an electrical timing and protocol analysis method for DRAM testing is provided, which is executed in a signal detection and analysis module inside a test device. The electrical timing and protocol analysis method specifically includes:

[0008] Multiple equal-phase sampling clocks with the same frequency as the interface signal of the DRAM under test can be generated by a configurable clock delay chain or phase interpolator.

[0009] The interface signal is sampled in a time-division manner using multiple equal-phase sampling clocks to obtain multiple corresponding phase sampling points within a unit interval;

[0010] Signal sampling points are selected from multiple phase sampling points, and the corresponding sampled signals are obtained for electrical characteristic checks and timing protocol checks; among which...

[0011] Electrical characteristic checks include at least one of setup and hold time checks, duty cycle checks, and signal eye diagram quality checks;

[0012] Timing protocol checks include inter-instruction timing checks and / or instruction-data timing checks;

[0013] When the inspection result is abnormal, an abnormality report is triggered and the on-site sampled waveform is saved.

[0014] According to another aspect of the present invention, an electrical timing and protocol analysis system for DRAM testing is provided, integrated into a test device or test chip. The electrical timing and protocol analysis system specifically includes:

[0015] The clock generation module is configured to generate multiple equal-phase sampling clocks that are in the same frequency as the interface signal of the DRAM under test through a configurable clock delay chain or phase interpolator.

[0016] The signal sampling module is configured to perform time-division sampling of the interface signal using multiple equal-phase sampling clocks to acquire multiple corresponding phase sampling points within a unit interval;

[0017] The signal acquisition and selection module is configured to select signal sampling points from multiple phase sampling points for electrical characteristic checks and timing protocol checks, and obtain the corresponding sampled signals.

[0018] The electrical characteristic checking module is configured to perform at least one of the following checks on the selected sampled signal: setup time and hold time check, duty cycle check, and signal eye diagram quality check;

[0019] The timing protocol checking module is configured to perform inter-instruction timing checks and / or instruction-data timing checks on the selected sampled signals;

[0020] The control and reporting module is configured to trigger an exception report and save the on-site sampled waveform when an anomaly is detected.

[0021] The electrical timing and protocol analysis method and system for DRAM testing provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0022] (1) By integrating electrical characteristic inspection modules (such as setup / hold time, eye diagram quality, duty cycle inspection) into the test equipment, there is no need for external oscilloscopes, intermediate structural layers, probe contacts, etc., which eliminates signal interference and distortion introduced by external connections, realizes in-situ, real-time, and high-precision detection of DRAM interface signal quality, and significantly improves test efficiency and the authenticity and reliability of test results.

[0023] (2) By integrating the electrical timing and protocol analysis system into the test chip through circuit design, multiple DRAM interface signals (CA, DQ, DQS, etc.) can be processed in parallel, overcoming the limitation of the number of external oscilloscope channels. Especially when testing multiple DRAM chips in batches, testing, analysis and diagnosis can be carried out simultaneously, greatly shortening the overall test time and improving the test throughput and automation level.

[0024] (3) By integrating the electrical characteristic inspection module and the timing protocol inspection module, the verification of signal integrity indicators (such as eye diagram, setup and hold time) and DRAM protocol compliance (such as instruction sequence, preamble, burst length, instruction interval) can be completed simultaneously. This collaborative analysis capability can quickly distinguish whether the fault is caused by signal quality problems or protocol timing errors, and achieve accurate fault location.

[0025] (4) A configurable high-precision delay chain is adopted. Through the combination structure of coarse and fine delay chains and closed-loop calibration logic, the total delay can be precisely configured as a unit interval within an extremely wide test frequency range (such as 100MHz-10GHz), and multiple equal-phase sampling points can be uniformly acquired within this unit interval, providing a high-quality data foundation for subsequent electrical testing and timing analysis.

[0026] (5) The timing protocol checking module can decode DRAM instructions in real time and accurately measure the timing relationship between instructions and between instructions and data through a counter. Once a timing error that violates the JEDEC specification (such as tRCD, tWL, tRL not being satisfied, or errors in the preamble and preamble) is detected, it can immediately report to the test system through an interrupt signal and trigger the saving of abnormal waveforms, which greatly shortens the debugging and problem location cycle.

[0027] (6) By integrating the electrical timing and protocol analysis system into the test equipment, the cost of purchasing and using external high-speed oscilloscopes, protocol analyzers and special test fixtures is eliminated. At the same time, the test equipment is miniaturized and cost is optimized. It is especially suitable for large-scale mass production chip testing scenarios, reducing test costs and having significant economic benefits. Attached Figure Description

[0028] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0029] Figure 1 This is a flowchart illustrating the overall steps of an electrical timing and protocol analysis method according to an embodiment of the present invention.

[0030] Figure 2 This is a schematic diagram of an electrical timing and protocol analysis system integrated within a test device or test chip for implementing an electrical timing and protocol analysis method according to an embodiment of the present invention.

[0031] Figure 3 for Figure 2 A schematic diagram of the circuit structure of a clock generation module in one embodiment of an electrical timing and protocol analysis system;

[0032] Figure 4 for Figure 3 A schematic diagram of the circuit structure of the configurable clock delay chain in the clock generation module;

[0033] Figure 5 for Figure 2 A schematic diagram of the circuit structure of the clock generation module and signal sampling module in another embodiment of the electrical timing and protocol analysis system;

[0034] Figure 6 for Figure 5 A schematic diagram illustrating the effect of setting a decision feedback equalizer on the detected eye diagram in the signal sampling module.

[0035] Figure 7 for Figure 2 A schematic diagram of the principle structure of the signal acquisition and selection module in one embodiment of an electrical timing and protocol analysis system;

[0036] Figure 8 for Figure 7 A schematic diagram of the circuit structure of the three-stage MUX selector unit in the signal acquisition and selection module;

[0037] Figure 9 for Figure 2 A schematic diagram of the circuit structure of the electrical characteristic checking module in one embodiment of an electrical timing and protocol analysis system;

[0038] Figure 10 for Figure 9 A schematic diagram illustrating the principle of sampling window offset in one embodiment of the electrical characteristic inspection module;

[0039] Figure 11 This is a schematic diagram illustrating the principle for determining high and low levels in the actual waveform during electrical characteristic checks.

[0040] Figure 12 Here is a signal quality statistics histogram for each UI of the signal in one embodiment;

[0041] Figure 13 To Figure 12 A schematic diagram illustrating signal quality eye diagram determination using histograms;

[0042] Figure 14 This is a schematic diagram of the electrical characteristic checking module for DQ / DQS signal setup time and hold time decision checking, implemented in one embodiment.

[0043] Figure 15 for Figure 2 A schematic diagram of the principle structure of a timing protocol checking module in one embodiment of an electrical timing and protocol analysis system;

[0044] Figure 16 For use Figure 15 The schematic diagram of the timing protocol checking module performing inter-instruction timing checks in the DRAM instruction and instruction timing parameter checking logic;

[0045] Figure 17 For use Figure 15 The schematic diagram shows the instruction and data timing checks performed by the timing protocol checking module in the DRAM instruction and data timing parameter checking logic. Detailed Implementation

[0046] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0047] Embodiments of the present invention provide an electrical timing and protocol analysis method and system for DRAM testing. By integrating the electrical timing and protocol analysis system within the test equipment or test chip, in-situ real-time signal data analysis without external instruments or signal interference is achieved. Employing a configurable high-precision delay chain, it supports simultaneous collaborative checking of electrical characteristics (such as eye diagrams, setup and hold times, duty cycles) and protocol timing (such as instruction sequences, preambles, and burst lengths) across multiple channels, enabling accurate differentiation and location of faults caused by signal quality or protocol violations. In batch testing, it improves testing efficiency and automation levels, significantly reducing testing costs.

[0048] See Figure 1 The overall steps of the electrical timing and protocol analysis method of the present invention are shown.

[0049] Step S110: Generate multiple equal-phase sampling clocks that are in sync with the interface signal of the DRAM under test by using a configurable clock delay chain or phase interpolator.

[0050] Step S120: The interface signal is sampled in a time-division manner using multiple equal-phase sampling clocks to obtain multiple corresponding phase sampling points within a unit interval.

[0051] Step S130: Select a signal sampling point from multiple phase sampling points, obtain the corresponding sampling signal, and perform electrical characteristic checks and timing protocol checks;

[0052] The electrical characteristic checks include at least one of setup and hold time checks, duty cycle checks, and signal eye diagram quality checks; the timing protocol checks include inter-instruction timing checks and / or instruction and data timing checks.

[0053] Step S140: When the inspection result is abnormal, trigger an abnormal report and save the on-site sampled waveform.

[0054] See Figure 2 An embodiment of an electrical timing and protocol analysis system 200 integrated within a test device or test chip is shown for implementing electrical timing and protocol analysis methods.

[0055] The electrical timing and protocol analysis system 200 mainly includes:

[0056] Clock generation module 210 is configured to use a configurable clock delay chain or phase interpolator (e.g., Figure 2 The configurable delay control chain 0, delay control chain 1, delay control chain 2, etc. shown generate multiple equal-phase sampling clocks with the same frequency as the interface signal of the DRAM under test;

[0057] The signal sampling module 220 is configured to perform time-division sampling of the interface signal using multiple equal-phase sampling clocks to acquire multiple corresponding phase sampling points within a unit interval;

[0058] The signal acquisition and selection module 230 is configured to select signal sampling points from multiple phase sampling points for electrical characteristic checks and timing protocol checks and obtain the corresponding sampling signals.

[0059] Electrical characteristic inspection module 240 is configured to perform at least one of setup time and hold time inspection, duty cycle inspection and signal eye diagram quality inspection on the selected sampled signal;

[0060] Timing protocol checking module 250 is configured to perform inter-instruction timing checks and / or instruction and data timing checks on the selected sampled signals;

[0061] The control and reporting module 260 is configured to trigger an anomaly reporting and save the on-site sampled waveform when an anomaly is detected.

[0062] Combination Figure 1 and Figure 2 The core process of the electrical timing and protocol analysis method of the present invention includes:

[0063] First, the interface signals between the DRAM under test and the test equipment or test chip are sampled by the clock generation module 210 and the signal sampling module 220. Multiple phase sampling points of each interface signal are acquired within a unit interval (UI). These phase sampling points contain the level information of the interface signal at different time points within one bit cycle.

[0064] The interface signals mainly include data signals (such as data bus signal DQ, data strobe signal DQS, etc.) and other signals (such as command / address bus signal CA, chip select signal CS_n, test clock signal TCK, etc.). Those skilled in the art will understand that various interface signals will be generated during DRAM testing according to test requirements. This example is merely illustrative and should not be construed as a limitation of the invention.

[0065] Specifically, based on the clock generation module 210, embodiments of the present invention provide three methods for interface signal sampling. The first method uses a configurable clock delay chain to delay the sampled signal to achieve multiple signal sampling points. The second method uses a configurable clock delay chain to generate multiple equal-phase clocks corresponding to the total number of phases within a unit interval (for example, if a UI has 32 phases, 32 equal-phase clocks are generated). The third method uses analog circuitry to implement a phase interpolator to generate multiple equal-phase clocks.

[0066] Next, the signal acquisition and selection module 230 selects the signal sampling points for analysis from these multiple parallel phase sampling points. Subsequently, two types of checks are performed in parallel: electrical characteristic checks are performed in the electrical characteristic check module 240, and timing protocol checks are performed in the timing protocol check module 250.

[0067] The electrical characteristic checks may include at least one of the following: setup and hold time checks, duty cycle checks, and signal eye diagram quality checks. That is, these characteristic checks can be performed on only one of them, two of them, or all three can be performed in parallel and simultaneously. Timing protocol checks include timing checks between DRAM instructions (inter-instruction timing checks) and / or timing checks between DRAM instructions and their corresponding data (instruction and data timing checks).

[0068] Finally, when any of the above checks results are abnormal (such as not meeting the preset threshold or instruction specifications), the control and reporting module 260 will immediately trigger the abnormal reporting mechanism to notify the upper-level test system, and at the same time control the sampling waveform caching module 270 to save the on-site sampling waveforms before and after the abnormality occurred for subsequent in-depth analysis.

[0069] This electrical timing and protocol analysis method can flexibly support various DRAM types such as DDR4, DDR5, LPDDR4, and LPDDR5 by configuring register lookup tables, enabling seamless switching between different protocols.

[0070] Sampling the interface signals between the DRAM under test and the test equipment or test chip using the clock generation module 210 and the signal sampling module 220 is a crucial foundation for subsequent electrical characteristic checks and timing protocol checks. The following describes in detail the three methods for implementing interface signal sampling.

[0071] See Figure 3 The circuit structure of the clock generation module 210 in an electrical timing and protocol analysis system 200 according to one embodiment is shown.

[0072] See Figure 4 The diagram illustrates the circuit structure of a configurable clock delay chain 211 in a clock generation module 210 of one embodiment.

[0073] Combination Figure 3 and Figure 4 As shown, the configurable clock delay chain 211 and the delay calibration module 212 for clock calibration and delay parameter configuration are key to achieving high-precision signal sampling in this invention. In particular, the configurable clock delay chain 211 is further composed of a coarse delay chain module 2111 and a fine delay chain module 2112 connected in circuit.

[0074] In one example, the coarse delay chain module 2111 is used to implement large-step delay adjustment. It consists of multiple coarse delay units connected in series. Each coarse delay unit corresponds to a coarse delay control code and a first selector (such as a 2-to-1 MUX). When the coarse delay control code configured for a coarse delay unit in the coarse delay chain module 2111 is configured to a valid value, its corresponding first selector will conduct the signal path, allowing the coarse delay unit to access the delay link; otherwise, it will bypass the coarse delay unit. For example, setting the logic '1' means that when the coarse delay control code is 1, the coarse delay unit will be added to the delay link; when it is 0, the current coarse delay unit will not be added to the delay link. By configuring multiple coarse delay control codes, the number of coarse delay units accessing the link can be flexibly controlled, thereby achieving a large-range delay adjustment on the nanosecond scale.

[0075] In one example, the fine delay chain module 2112 is used to implement high-precision, small-step delays. Each fine delay chain is connected to the output tap of a coarse delay unit. Each fine delay chain is internally composed of multiple fine delay units connected in series. Similar to the coarse delay unit, each fine delay unit corresponds to a fine delay control code and a second selector (such as a 2-to-1 MUX) to control whether the fine delay unit is connected to the delay chain. The delay accuracy of the fine delay unit can reach the picosecond or even femtosecond level.

[0076] In one example, delay calibration module 212 is used to ensure that the total delay of the configurable clock delay chain 211 is exactly equal to one UI. The delay calibration module 212 includes:

[0077] Phase detector 2121 is used to compare the phase difference between the original input signal and the output signal after passing through the configurable clock delay chain 211, and generate an error signal proportional to the phase difference.

[0078] The coarse adjustment counter 2122 is used to adjust the value of the coarse delay control code input to the coarse delay chain module 2111 according to the error signal;

[0079] The fine-tuning counter 2123 is used to adjust the value of the fine delay control code input to the fine delay chain module 2112 according to the error signal;

[0080] The calibration state machine 2124 is used to manage the calibration process (such as initial power-on calibration, periodic calibration, or calibration triggered by PVT changes).

[0081] The delay chain configuration register 2125 is used to send delay configuration parameters to the configurable clock delay chain 211 according to the delay calibration logic.

[0082] In this signal sampling method, the signal sampling module 220 can be integrated with the configurable clock delay chain 211. After synchronously sampling the interface signal according to the delay calibration logic composed of phase detector 2121, coarse adjustment counter 2122 and fine adjustment counter 2123, it outputs a multi-phase phase signal.

[0083] The delay calibration process (i.e., delay calibration logic) is as follows: first, the coarse adjustment counter 2122 is used to quickly approach the target phase, and then the fine adjustment counter 2123 is used to make fine adjustments until the phase difference output by the phase detector 2121 is zero. At this time, the corresponding delay configuration code is saved to the delay chain configuration register 2125 to complete the calibration.

[0084] In one example, after the calibration process described above, a specific delay control code can be output through the delay chain configuration register 2125 to connect the tail and head of two adjacent sets of fine delay chains in the fine delay chain module 2112. This allows for the construction of a high-precision delay chain composed entirely of fine delay units at extremely high test rates (when a UI is very short), avoiding the inability to accurately match a UI due to excessively large step sizes of coarse delay units.

[0085] See Figure 5 The circuit structure of the clock generation module 210' and signal sampling module 220' in the electrical timing and protocol analysis system 200 of another embodiment is shown.

[0086] In one example, a configurable clock delay chain 211' generates multiple equal-phase clocks corresponding to the total number of phases within a UI. This signal sampling method does not delay the sampled signal; instead, it generates multiple equal-phase sampling clocks through the configurable clock delay chain 211'.

[0087] Taking 32-phase (UI / 32) high-resolution sampling as an example, the DRAM interface under test needs to implement 32 equal-phase sampling clocks with the same frequency as its test rate to sample the signal value of the UI / 32 sampling point of each interface signal.

[0088] This method is easier to implement in terms of circuit structure, allowing interface signals to be transmitted through... Figure 3 The configurable clock delay chain 211 shown is used for delay, adjusted to allow the sampling clock of the interface signal to be used. Figure 5The configurable clock delay chain 211' shown provides a delay to generate multiple sampling clocks that are in phase and at the same frequency as the DRAM under test. For example, if there are 32 phases, then 32 clocks in phase and at the same frequency are generated, and the same DRAM interface signal is sampled sequentially in a time-division manner under the 32 clocks.

[0089] In one example, the coarse delay chain module 2111 and the fine delay chain module 2112 can be reused. Figure 4 The circuit structure shown is configured. Simultaneously, delay configuration codes control whether each coarse delay unit and / or fine delay unit participates in the delay link. It supports testing under a wide range of DRAM speed conditions; for example, at low speeds, the delay link control is formed by the coarse delay chain module 2111; at high speeds, it is formed by a single fine delay chain module 2112; and at intermediate speeds, it can be formed by a combination of coarse and fine delay chain modules 2111 and 2112.

[0090] In one example, specifically, the multi-channel sampling clock or multi-channel equal-phase clock output through the configurable clock delay chain 211' continues to be output to the signal sampling module 220'. The configurable clock delay chain 211' generates m sampling clocks (assuming each UI has m sampling phases), and the m sampling clocks are time-division multiplexed to sample the signal. Simultaneously, the data signal (DQS / DQ) and other signals (CA / CS_n / TCK) are input to the signal sampling module 220' respectively.

[0091] Preferably, a decision feedback equalizer (DFE) is provided before the data signal is input to the signal sampling module 220', that is, the data signal first enters the decision feedback equalizer 221 and then enters the signal sampling module 220'.

[0092] See Figure 6 This illustrates the effect of setting the decision feedback equalizer 221 before the signal sampling module 220' on the detected eye diagram.

[0093] In one example, the decision feedback equalizer 221 is a core equalization module in high-speed serial communication (such as DDR series, PCIe, Ethernet, etc.) used to compensate for signal distortion caused by the channel and improve signal integrity. In this signal sampling method, adding the decision feedback equalizer 221 can be used to solve the "phantom" of the eye diagram generated during signal sampling.

[0094] The decision feedback equalizer 221, by using signal feedback technology, can adjust the decision threshold of the current bit based on the previously received bit value ('1' or '0'). In high-speed transmission, signals can experience trailing due to channel loss, reflection, and other factors, interfering with subsequent signals. The decision feedback equalizer 221 sharpens the signal waveform and eliminates interference between signals by feeding back the decided signal and predicting and subtracting the backward interference affecting the current signal in real time.

[0095] The horizontal eye opening (time tolerance) and vertical eye opening (amplitude tolerance) directly reflect signal quality. The decision feedback equalizer 221 sharpens the signal waveform and eliminates interference between signals, which can effectively reduce eye closure, increase eye opening, and reduce the bit error rate.

[0096] The result is that in a device or module capable of displaying eye diagrams (such as an oscilloscope screen), an eye diagram that appears completely "closed" (e.g., ...) Figure 6 The unqualified eye diagram, after being processed by the decision feedback equalizer 221, may appear as a wide "opening and closing" state when viewed from the perspective of the DRAM chip (e.g., Figure 6 (A qualified eye diagram). However, if the eye diagram is measured directly without setting the decision feedback equalizer 221, an "eye diagram illusion" may occur, which may lead to the incorrect rejection of a well-designed one.

[0097] In one example, a phase interpolator implemented using analog circuitry can generate multiple equal-phase clocks to sample the signal. An analog-based phase interpolator (e.g., a current-mode logic (CML) based phase interpolator), combined with a phase calibration loop, can achieve very high-precision equal-phase clocks, improving the accuracy of signal sampling.

[0098] For example, taking 32-phase (UI / 32) high-resolution sampling as an example, firstly, a high-precision phase-locked loop (PLL) generates four reference clocks with a phase difference of 90°. These reference clocks provide time and amplitude references for subsequent analog interpolation. Then, based on the four reference clocks, a two-stage CML phase interpolator performs cross-mixing and analog linear interpolation on the reference clocks to generate 32 equal-phase clocks.

[0099] Furthermore, to ensure that all clocks are strictly in phase, an integrated phase calibration loop is preferred to sample the phase difference between adjacent clocks in real time, and then dynamically fine-tune the CML phase interpolator through the error signal. This can eliminate phase errors caused by process deviations and temperature drift.

[0100] See Figure 7 The diagram illustrates the principle structure of a signal acquisition and selection module 230 according to one embodiment.

[0101] The signal acquisition and selection module 230 is used to select some or all of the multiple parallel sampling points transmitted from the clock generation module 210 and the signal sampling module 220 as inputs for electrical signal analysis and timing protocol analysis, and also determines which sampling signals are used as inputs for the sampling waveform.

[0102] In one example, the signal acquisition and selection module 230 includes two parts: an electrical characteristic / timing protocol sampling selection unit 231 and a sampling signal waveform buffer selection unit 232. The selection signal of each selector (e.g., using a multiplexer) is configured through a register. By modifying the selection signal of the multiplexer, the test system can select which signals participate in electrical characteristic / timing analysis and waveform sampling.

[0103] See Figure 8 , showed Figure 7 The circuit structure of a three-level MUX selector unit in one embodiment.

[0104] In one example, the first-stage MUX selector unit first selects appropriate phase signals from the sampled signals as input signals for subsequent electrical characteristic checks and timing checks, based on different DRAM test rates and checking accuracies (e.g., checking at UI / 16 or UI / 32 accuracy). For example, it selects n phase signals from m phase signals of the command / address bus (CA signal), n phase signals from m phase signals of the data bus (DQ signal), and n phase signals from m phase signals of the data strobe signal (DQS signal).

[0105] Next, the second-stage MUX selector unit continues to select the signal with the best sampling phase from each phase of the n input CA signals, DQ signals, and DQS signals, as the input to the subsequent timing protocol checking module 250.

[0106] Finally, the third-level MUX selector unit is used to select a portion of the signals from the CA, DQ, and DQS input signals as inputs to the sampled waveform buffer. Sometimes, the test system does not buffer all the sampled waveforms, but only the parts that require special attention. Therefore, the MUX selector is needed to select a portion of the signals from multiple sampled signals (e.g., selecting only the CA signal, selecting a portion of the CA signal, selecting a portion of the DQ signal, selecting all the DQ signals, or selecting the DQS signal, etc.) and store them in the sampled waveform buffer module 270 for testing personnel to use during debugging.

[0107] See Figure 9 The circuit structure of an electrical characteristic checking module 240 according to one embodiment is shown.

[0108] The electrical characteristic checking module 240 includes setup and hold time checks, duty cycle checks, and signal quality eye diagram checks. The principle structure and implementation of each circuit unit are as follows:

[0109] The control / status register unit 241 is responsible for configuring and managing the entire electrical characteristic inspection module 240. It is equipped with a control / status register and interacts with the control and reporting module 260 through, for example, the APB interface. The control and reporting module 260 can configure the APB through the APB interface. At the same time, the electrical characteristic inspection will store the test results in the control / status register and transmit them to the control and reporting module 260 through the APB interface. The control and reporting module 260 will then report to the test system.

[0110] Sampling window offset logic 242: Since the DRAM interface sampling signals (CA / DQ / DQS / CS / TCK, etc.) are externally output signals, the complete UI signal received by the electrical characteristic check module 240 will span between the currently selected phases and the next selected phases.

[0111] See Figure 10 The diagram illustrates the principle of sampling window offset in one embodiment.

[0112] Ideally, a complete signal level is sampled between the P0-Pm phases, but in actual use, there is usually a deviation, with the complete signal level spanning between the two samples. Therefore, the complete sampled signal level needs to be shifted to the sampling phases between P0-Pm using the sampling window offset logic 242.

[0113] The sampling window offset logic 242 is achieved through a shift register (e.g., Figure 9 The CA sampling signal shift register 2421, CS sampling signal shift register 2422, TCK sampling signal shift register 2423, DQ sampling signal shift register 2424, DQS sampling signal shift register 2425, etc., are used to adjust the phase offset. The shift length is obtained based on the sampling signal center phase decision logic.

[0114] The signal quality statistics counter unit 243 is used to count the high or low levels transmitted by the current signal during a specified statistical window. Internally, it includes a sampling signal level decision unit to determine whether the current sampled signal is high or low. The decision is based on selecting the center phase point and several surrounding phase points of the sampled signal (the specific number of points can be controlled by a control register). If all selected phase values ​​are high, the currently transmitted signal is considered high, and the high-level statistics counter is active. When the sampling phase value is 1, the corresponding high-level statistics counter is incremented by 1; otherwise, it remains unchanged. Conversely, if all selected phase values ​​are low, the currently transmitted signal is considered low, and the low-level statistics counter is active. When the sampling phase value is 1, the corresponding low-level statistics counter is incremented by 1; otherwise, it remains unchanged.

[0115] The eye diagram statistics control logic 244 is used to control when to start eye diagram statistics. It can control the size of the time window for eye diagram statistics and the interval period for eye diagram statistics. After the eye diagram statistics are completed, the statistical results of each signal are saved in the register for eye diagram quality detection or reported to the test system for signal quality diagnosis.

[0116] The sampling signal center phase decision logic 245 is used to determine the high-level and low-level statistical values ​​of each phase after the statistical window ends. For example, it compares the statistical value of the center phase with the statistical values ​​of other phases to determine if the statistical value of the center phase is the maximum. If it is not the maximum, then it is considered that there is a deviation between the currently selected sampling window and the actual transmitted signal window. The phase with the largest statistical value is the actual center phase. The sampling window shift register is configured to offset the sampling window, and the phase with the largest sampled value is taken as the sampling center phase. If there are multiple consecutive sampling statistical maximum value phases, then the middle phase of the sampling statistical maximum value is selected as the center phase.

[0117] After determining the center phase, the offset value of the sampling window offset register is stored in the status register for subsequent functional analysis. The sampling center phase decision logic only needs to run once after the chip is powered on, and the decision result can be stored in the register. In addition, the continuous alternating 1 / 0 changes of the sampling signal (similar to a clock signal) can speed up the determination of the sampling center phase.

[0118] The eye diagram signal quality check logic 246 is based on the statistical values ​​of whether each phase is 1 or 0 when the signal transmits a high level and a low level within 1 UI. The sampled signal has an optimal sampling phase - the center phase - within 1 UI. The closer the phase is to this sampling phase, the more accurate the sampled value, and the higher the count value of the sampling statistics counter. The farther the phase is from the optimal sampling phase, the greater the sampling error, and the lower the count value of the sampling statistics counter.

[0119] See Figure 11 The diagram illustrates the principle of high and low level determination in an actual waveform of an embodiment.

[0120] The voltage of the input signal is compared with the VIH threshold voltage. When the voltage of the input signal exceeds the threshold voltage VIH, the signal is determined to be 1. When the voltage of the input signal is lower than the VIL threshold voltage, the signal is determined to be 0. The phase between VIH and VIL may be sampled as high level or low level.

[0121] See Figure 12 This illustrates a signal quality statistics histogram for each UI of a signal in one embodiment.

[0122] Figure 12 The display shows the high-level and low-level statistical counter values ​​for each phase within a UI. Higher count values ​​indicate smaller deviations between the statistical value and the actual value for each phase, signifying higher signal transmission reliability, better signal eye diagram quality, and a more stable signal.

[0123] See Figure 13 This shows the Figure 12 A schematic diagram of signal quality eye diagram determination using histogram.

[0124] The eye diagram inspection unit configures a set of eye diagram quality inspection mask parameters through the configuration register, which are the threshold parameters for judging eye diagram quality. The comparator logic implemented inside the eye diagram inspection unit compares the eye diagram counter statistics of each phase with the mask parameters. If the counter value is higher than the mask parameters, it means that the signal quality is good; otherwise, it means that the signal quality is poor.

[0125] In one example, eye diagram checking is based on a signal quality statistics counter. Within a preset statistical time window (e.g., 1024 consecutive UIs), the level of each phase sampling point (e.g., P0 to P31) is determined and counted. The sampling signal decision module uses the values ​​of a phase point and several adjacent points (windows) to comprehensively determine whether the current UI at that position is '1' or '0'. For example, if the center phase point and one point before and after it are all high, it is determined as '1', and the high-level counter for that phase is incremented by 1; otherwise, the low-level counter is incremented by 1. After the statistics are completed, each phase point will have a high-level count value and a low-level count value. Based on this data, an eye diagram histogram can be generated. The eye diagram quality checking logic presets a set of eye diagram quality mask thresholds, which define the minimum acceptable high-level count and the maximum acceptable low-level count (or vice versa) at each phase point. During the check, the actual statistical value of each phase is compared with the corresponding mask threshold using a comparator. If the statistical value of a certain phase exceeds the "eye diagram opening" area specified by the mask threshold (e.g., the high-level count value is below the lower limit, or the low-level count value is above the upper limit), the signal quality at that point is determined to be unqualified. If the number of unqualified points exceeds a certain amount or is located in the critical phase area, the overall signal eye diagram quality is determined to be abnormal.

[0126] See Figure 14 The diagram illustrates the principle of DQ / DQS setup time and hold time decision check implemented by the electrical characteristic check module 240 of one embodiment.

[0127] Taking the checking of the DQ signal relative to its strobe clock DQS as an example, the checking logic first needs to determine the position of the DQS clock signal's transition edge. In a system using UI / 32 precision sampling, this is done by detecting the phase of the first transition edge from 0 to 1 in the DQS signal sample sequence (e.g., the Nth sample point). Similarly, the phase of the second transition edge of the DQ signal is determined (for setup time, the last transition edge before the data of interest becomes valid; for hold time, the first transition edge before the data of interest becomes invalid).

[0128] The actual setup time is calculated as follows: DQS transition edge phase minus the transition edge phase before the valid start of DQ data, multiplied by the actual time width of a single phase.

[0129] The actual hold time is calculated as follows: the phase of the DQS transition edge after the DQ data is valid is subtracted from the phase of the DQS transition edge, and then multiplied by the actual time width of a single phase.

[0130] Those skilled in the art will understand that the setup and hold time can be clock relative to data, clock relative to signal, or DQS relative to DQ. For example, in the case of clock relative to data, it is necessary to detect the first and second transition phases of the data, and then the setup time = the first transition phase of the clock - the first transition phase of the data; the hold time = the second transition phase of the data - the first transition phase of the clock.

[0131] Finally, the calculated actual setup / hold time value is compared with a threshold preset according to JEDEC specifications or test requirements. If the actual value is less than the threshold, the timing requirements are deemed not met. Considering signal jitter, statistics can be performed over multiple consecutive cycles. Only when more than a certain proportion of cycles fail to meet the conditions is it ultimately determined to be an anomaly, triggering reporting and waveform saving.

[0132] In one example, the duty cycle check reuses, such as Figure 9 The signal quality statistical counter unit 243 in the electrical characteristic inspection module 240 shown above performs the following: After completing the counting of a statistical time window, the high-level counter values ​​of all phases (e.g., 32 phases) are summed to obtain the total high-level count (Sum_H); similarly, the low-level counter values ​​of all phases are summed to obtain the total low-level count (Sum_L). The measured duty cycle can be calculated using the formula Sum_H / (Sum_H+Sum_L), or by directly comparing the ratio of Sum_H to Sum_L. The duty cycle inspection logic 247 compares the calculated measured duty cycle with a preset duty cycle threshold range (e.g., for an ideal clock, the expectation is 50%, and the allowable deviation range can be set to 45%-55%). If the measured duty cycle deviates significantly from the preset range, it is determined that the duty cycle does not meet the requirements, and an abnormal handling process is triggered.

[0133] See Figure 15 The diagram shows the schematic structure of a timing protocol checking module 250 according to one embodiment.

[0134] In one example, the timing protocol checking module 250 includes a timing protocol checking control / status register 251 (hereinafter referred to as the control / status register), a DRAM instruction decoder 252, DRAM instruction and instruction timing parameter checking logic 253, and DRAM instruction and data timing parameter checking logic 254.

[0135] The timing protocol check control / status register 251 communicates with the test system control and reporting module 260 via, for example, the APB interface, to realize the configuration management of the timing protocol check module 250, the storage of measurement results, and the reporting to the test system.

[0136] The DRAM instruction decoder 252 receives DRAM instruction signals, such as CA / CS signals, and compares them with the command encoding settings in the control / status register 251 to detect the current DRAM command sequence for subsequent timing analysis. Different combinations of CA and CS encodings can constitute different DRAM instructions. The DRAM instruction decoder 252 reverse-decodes CA and CS to parse the current DRAM instruction as a DRAM write instruction, a DRAM read instruction, or another type of DRAM instruction. If it detects that the current encoding does not belong to the instruction defined in the DRAM specification, it reports the detection of an abnormal instruction to the test system.

[0137] Those skilled in the art will understand that the instruction signals received from the DRAM can be extended to any JEDEC-defined DRAM interface signal, i.e., instruction parsing is performed according to a user-defined instruction truth table. This example is merely illustrative and should not be construed as a limitation of the invention.

[0138] See Figure 16 The diagram shows the schematic of the inter-instruction timing check performed in the DRAM instruction and instruction timing parameter check logic 253.

[0139] DRAM instruction and instruction timing check logic 253 checks whether the time interval between DRAM instructions meets the timing specification requirements defined by DAM. Since DRAM read, write, refresh, activation and other operations require specific time to complete, if the command operations are too intensive, it will lead to the inability to correctly parse the commands, or if the refresh command interval is too far, it will lead to the loss of data inside the DRAM.

[0140] The DRAM instruction and instruction timing check logic 253 implements an instruction and instruction timing check state machine, which manages which instruction timings are checked, when they are checked, and whether to report abnormal results. The module's functionality is enabled via the enable signal, and the state machine is started for checking via the start signal.

[0141] The DRAM instruction and instruction timing check logic 253 implements various timing check counters to count the minimum or maximum boundary time between each command. If the minimum or maximum boundary time between commands exceeds the DRAM timing specification, it will report to the test system through an interrupt output and trigger the saving of the timing abnormal waveform through a trigger output for convenient timing analysis.

[0142] In one example, the DRAM instruction decoder 252 parses signals such as CA and CS_n in real time to identify the current DRAM operation instructions (such as ACT activation, PRE precharge, WR write, RD read, REF refresh, etc.). The instruction and instruction timing check logic 253 internally sets up dedicated counters for the instruction pairs that need to be monitored. For example, it checks the interval tRCD between the ACT command and the READ command. When an ACT command is detected, the corresponding counter starts counting (in system clock or UI units). When a subsequent READ command is detected, counting stops and the count value is read. After converting the count value to actual time, it is compared with the minimum (or maximum, such as the maximum interval tREFI for refresh commands) value defined in the DRAM-JEDEC specification. If the actual interval is less than the specified minimum boundary time or greater than the specified maximum boundary time, a timing violation is determined. The instruction and instruction timing check logic 253 immediately reports to the test system via an interrupt signal and sends a trigger signal to save the relevant signal waveforms before and after the violation occurred.

[0143] See Figure 17 The diagram shows the schematic of instruction and data timing checks performed in the DRAM instruction and data timing parameter checking logic 254.

[0144] The DRAM instruction and data timing parameter checking logic 254 includes a write wait time counter (WL counter), a read wait time counter (RL counter), a preamble and preamble checking submodule, and a burst length checking submodule.

[0145] Write operation check process: When the instruction decoder 252 detects a write instruction (WR), it immediately starts the WL counter. When the counter reaches the expected start position of the write preamble, the preamble and preamble check submodule begins to check whether the DQS signal conforms to the configured preamble pattern (e.g., logic low level). The WL counter continues to count, and when it reaches the count value corresponding to the write delay tWL, it marks the start of the valid data window, and the check submodule verifies that the preamble has ended correctly. Subsequently, the burst length check submodule begins to count the amount of data transmitted on the DQ line and compares it with the burst length (BL) specified in the write instruction to confirm whether the data amount matches. After the data burst transmission is completed, the write postamble is checked to ensure it conforms to the configuration. Failure at any step of the check (e.g., mismatched preamble and preamble, incorrect data amount) will trigger an exception.

[0146] Read operation check process: Similar to write operation, when a read command (RD) is detected, the RL counter is started. After a tRL delay, the read preamble is checked. Subsequently, the read data is sampled on the DQ line, and the amount of data read is verified by the burst length check submodule to ensure it matches the BL specified in the command. Finally, the read postamble is checked. Any abnormality during the check process will be immediately reported via an interrupt and waveform saving will be triggered.

[0147] For example, the control and reporting module 260 is responsible for receiving the configuration of the test system through, for example, the APB interface, transmitting waveform data through, for example, the AXI interface, and generating an interrupt signal to report to the test system and triggering waveform buffering action when the electrical characteristic check module 240 and / or the timing protocol check module 250 issue an abnormal signal.

[0148] For example, embodiments of the present invention also provide a DRAM testing system, including a testing machine and the electrical timing and protocol analysis system of the above embodiments.

[0149] The test equipment, as the core of the test system, includes components such as the main controller, test vector generator, power and timing management module. It is responsible for executing the test program and applying precise test instructions, addresses, data and clock signals to the DRAM chip under test.

[0150] The electrical timing and protocol analysis system can be implemented as a standalone chip or integrated into the interface board, load board, or socket interface of the chip under test (DUT) of a test equipment. During testing, the device continuously captures all critical signals (such as CA, DQ, DQS, CS_n, etc.) exchanged between the test equipment and the DUT in real time, and uses its internal parallel hardware inspection pipeline to simultaneously perform signal integrity analysis and protocol timing verification. If any electrical parameter exceedance or protocol violation is detected, the device immediately reports the specific anomaly type and location information to the test equipment's main controller via an interrupt signal and triggers the saving of the on-site waveform. The main controller can then adjust the test strategy, record failure logs, or sort chips in real time, thus forming a complete automated closed loop of "test execution - real-time monitoring - immediate diagnosis - feedback control," greatly improving the intelligence of testing and diagnostic efficiency.

[0151] The electrical timing and protocol analysis method and system for DRAM testing provided by embodiments of the present invention have at least one or a portion of the following advantages:

[0152] (1) By integrating an electrical characteristic inspection module (such as setup / hold time, eye diagram quality, duty cycle inspection) inside the test chip, there is no need for an external oscilloscope, intermediate structure layer, probe contact, etc., which eliminates signal interference and distortion introduced by external connection, realizes in-situ, real-time, and high-precision detection of DRAM interface signal quality, and significantly improves test efficiency and the authenticity and reliability of test results.

[0153] (2) By integrating the electrical timing and protocol analysis system into the test chip through circuit design, multiple DRAM interface signals (CA, DQ, DQS, etc.) can be processed in parallel, overcoming the limitation of the number of external oscilloscope channels. Especially when testing multiple DRAM chips in batches, testing, analysis and diagnosis can be carried out simultaneously, greatly shortening the overall test time and improving the test throughput and automation level.

[0154] (3) By integrating the electrical characteristic inspection module and the timing protocol inspection module, the verification of signal integrity indicators (such as eye diagram, setup and hold time) and DRAM protocol compliance (such as instruction sequence, preamble, burst length, instruction interval) can be completed simultaneously. This collaborative analysis capability can quickly distinguish whether the fault is caused by signal quality problems or protocol timing errors, and achieve accurate fault location.

[0155] (4) A configurable high-precision delay chain is adopted. Through the combination structure of coarse and fine delay chains and closed-loop calibration logic, the total delay can be precisely configured as a unit interval within an extremely wide test frequency range (such as 100MHz-10GHz), and multiple high-precision phase sampling points can be uniformly acquired within this unit interval, providing a high-quality data foundation for subsequent electrical testing and timing analysis.

[0156] (5) The timing protocol checking module can decode DRAM instructions in real time and accurately measure the timing relationship between instructions and between instructions and data through a counter. Once a timing error that violates the JEDEC specification (such as tRCD, tWL, tRL not being satisfied, or errors in the preamble and preamble) is detected, it can immediately report to the test system through an interrupt signal and trigger the saving of abnormal waveforms, which greatly shortens the debugging and problem location cycle.

[0157] (6) By integrating the built-in electrical timing and protocol analysis system and circuit, the cost of purchasing and using external high-speed oscilloscopes, protocol analyzers and special test fixtures is eliminated. At the same time, the miniaturization and cost optimization of the test equipment are realized. It is especially suitable for large-scale mass production chip testing scenarios, reducing test costs and having significant economic benefits.

[0158] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. An electrical timing and protocol analysis method for DRAM testing, executed within a signal detection and analysis module of a test device, characterized in that, The electrical timing and protocol analysis method includes: Multiple equal-phase sampling clocks, synchronized with the interface signal of the DRAM under test, are generated using a configurable clock delay chain or phase interpolator; among which... The configurable clock delay chain includes a coarse delay chain that implements large step delay and a fine delay chain that implements high-precision small step delay. The clock signal of the configurable clock delay chain is processed and calibrated by delay calibration logic so that the total phase difference of the multiple equal-phase sampling clocks covers a unit interval. The interface signal is sampled in a time-division manner using the multiple equal-phase sampling clocks to obtain multiple corresponding phase sampling points within a unit interval; Signal sampling points are selected from the plurality of phase sampling points, and the corresponding sampled signals are obtained for electrical characteristic checks and timing protocol checks. Before the electrical characteristic checks, the sampled signals are subjected to decision feedback equalization processing to compensate for channel distortion; wherein The electrical characteristic checks include at least one of setup and hold time checks, duty cycle checks, and signal eye diagram quality checks. The timing protocol check includes inter-instruction timing check and / or instruction and data timing check; When the inspection result is abnormal, an abnormality report is triggered and the on-site sampled waveform is saved.

2. The electrical timing and protocol analysis method according to claim 1, characterized in that, The delay calibration logic adjusts the configuration codes of the coarse delay chain and the fine delay chain by comparing the phase difference between the reference clock signal and the clock signal processed by the configurable clock delay chain, until the phase difference meets the preset condition.

3. The electrical timing and protocol analysis method according to claim 2, characterized in that, The coarse delay chain connects multiple coarse delay units in series. Each coarse delay unit corresponds to a coarse delay control code and a first selector. When the coarse delay control code is a valid value, the coarse delay unit is added to the delay chain.

4. The electrical timing and protocol analysis method according to claim 3, characterized in that, The coarse delay chain is connected in series with a set of fine delay chains at the output tap position of each coarse delay unit; Each fine delay chain connects multiple fine delay units in series. Each fine delay unit corresponds to a fine delay control code and a second selector. When the fine delay control code is valid, the fine delay unit is added to the delay chain.

5. The electrical timing and protocol analysis method according to claim 4, characterized in that, Adjacent sets of fine delay chains can be configured to be connected in series via delay control codes to build delay links consisting only of fine delay chains during high-speed testing.

6. The electrical timing and protocol analysis method according to any one of claims 1-5, characterized in that, The setup time and hold time checks include: Determine the phase of the first transition edge of the reference signal; Determine the phase of the second transition edge of the signal under test; The actual setup time and hold time are calculated based on the phase difference between the first transition edge phase and the second transition edge phase. The actual setup time and hold time are compared with a preset threshold to determine whether the timing requirements are met. The reference signal is a clock signal and / or a data strobe signal, and the signal under test is a data signal and / or a command signal.

7. The electrical timing and protocol analysis method according to claim 6, characterized in that, The signal eye diagram quality check includes: Count the high-level and low-level counts for each phase within a preset time window; Generate an eye diagram histogram based on statistical results; The statistical values ​​of each phase are compared with the preset eye diagram quality mask threshold to determine whether the signal quality is qualified.

8. The electrical timing and protocol analysis method according to claim 6, characterized in that, The duty cycle check includes: The signal quality statistical counter in the multiplexing electrical characteristic check is used to obtain the sum of the high-level counter values ​​and the sum of the low-level counter values ​​of all phases within a preset time window; Calculate the ratio of the sum of the high-level counter values ​​to the sum of the low-level counter values ​​to obtain the measured duty cycle; The measured duty cycle is compared with a preset duty cycle threshold. If the measured duty cycle deviates from the preset duty cycle threshold, the duty cycle is determined to be non-compliant, and an anomaly is triggered and the on-site sampled waveform is saved.

9. The electrical timing and protocol analysis method according to claim 6, characterized in that, The inter-instruction timing check includes: The time interval between two DRAM instructions is counted using a counter. Determine whether the time interval meets the minimum or maximum boundary time defined in the DRAM specification; If it does not meet the requirements, an exception will be reported and the on-site sampled waveform will be saved.

10. The electrical timing and protocol analysis method according to claim 6, characterized in that, The instruction and data timing check includes: After a write command is detected, the write wait time counter is started. When it reaches the preset value of the write command, the preamble and the burst length are checked to see if they match the configuration. Otherwise, an exception is reported and the on-site sampled waveform is saved. After a read command is detected, a read wait time counter is started. When the read command preset value is reached, the preamble and the burst length are checked to see if they match the configuration. Otherwise, an exception is reported and the on-site sampled waveform is saved.

11. An electrical timing and protocol analysis system for DRAM testing, integrated into a test device or test chip, characterized in that, The electrical timing and protocol analysis system includes: The clock generation module is configured to generate multiple equal-phase sampling clocks that are in sync with the interface signal of the DRAM under test, using a configurable clock delay chain or phase interpolator; wherein... The configurable clock delay chain includes a coarse delay chain that implements large step delay and a fine delay chain that implements high-precision small step delay. The clock signal of the configurable clock delay chain is processed and calibrated by delay calibration logic so that the total phase difference of the multiple equal-phase sampling clocks covers a unit interval. The signal sampling module is configured to perform time-division sampling of the interface signal using the plurality of equal-phase sampling clocks to acquire the corresponding plurality of phase sampling points within a unit interval; The signal acquisition and selection module is configured to select signal sampling points from the plurality of phase sampling points for electrical characteristic checks and timing protocol checks and obtain corresponding sampling signals, and to perform decision feedback equalization processing on the sampling signals before the electrical characteristic checks to compensate for channel distortion. The electrical characteristic checking module is configured to perform at least one of the following checks on the selected sampled signal: setup time and hold time check, duty cycle check, and signal eye diagram quality check; The timing protocol checking module is configured to perform inter-instruction timing checks and / or instruction-data timing checks on the selected sampled signals; The control and reporting module is configured to trigger an exception report and save the on-site sampled waveform when an anomaly is detected.

12. The electrical timing and protocol analysis system according to claim 11, characterized in that, The clock generation module includes: A configurable clock delay chain submodule, comprising a series-connected coarse delay unit group and a fine delay chain group connected to the output of the coarse delay unit group, is used to generate the plurality of equal-phase sampling clocks; or, The analog phase interpolator submodule includes a phase-locked loop, a multi-level current-mode logic phase interpolator, and a phase calibration loop, used to generate the multiple equal-phase sampling clocks.

13. The electrical timing and protocol analysis system according to claim 12, characterized in that, The clock generation module further includes a delay calibration submodule, which is configured to calibrate the phase relationship of the plurality of equal-phase sampling clocks by detecting the phase difference between the reference clock and the generated clock and adjusting the configuration of the configurable clock delay chain submodule or the analog phase interpolator submodule.

14. The electrical timing and protocol analysis system according to claim 13, characterized in that, The delay calibration submodule includes: A phase detector is configured to detect the phase difference between the input signal and the delayed output signal; A coarse adjustment counter is configured to adjust the delay configuration code of the coarse delay unit group according to the phase difference; A fine-tuning counter is configured to adjust the delay configuration code of the fine delay chain group according to the phase difference; The calibration state machine is configured to control the start and stop of the delayed calibration process.

15. The electrical timing and protocol analysis system according to claim 11, characterized in that, The electrical timing and protocol analysis system also includes a decision feedback equalizer module. The decision feedback equalizer module is connected between at least a portion of the interface signal of the DRAM under test and the signal sampling module, and is configured to perform equalization processing on the input signal to compensate for channel distortion.

16. The electrical timing and protocol analysis system according to any one of claims 11-15, characterized in that, The electrical characteristic checking module includes: The sampling window offset unit is configured to correct the sampling phase offset according to the sampling window offset logic; The signal quality statistics counter is configured to count the high and low levels of each phase; The eye diagram inspection unit is configured to compare statistical values ​​with eye diagram mask thresholds according to eye diagram inspection logic; The setup time and hold time checking unit is configured to calculate the actual setup time and hold time based on the phase difference of the transition edge according to the setup time and hold time checking logic.

17. The electrical timing and protocol analysis system according to any one of claims 11-15, characterized in that, The timing protocol checking module includes: The DRAM instruction decoder is configured to parse signals from the DRAM interface under test to obtain the current instruction based on a predefined instruction truth table. The instruction timing check unit is configured to measure the instruction interval by setting multiple counters; The instruction and data timing check unit, including a write wait time counter, a read wait time counter, a preamble and prefix check submodule, and a burst length check submodule, is configured as follows: After a write command is detected, the write wait time counter is started. When it reaches the preset value of the write command, the preamble and the burst length are checked to see if they match the configuration. Otherwise, an exception is reported and the on-site sampled waveform is saved. After a read command is detected, a read wait time counter is started. When the read command preset value is reached, the preamble and the burst length are checked to see if they match the configuration. Otherwise, an exception is reported and the on-site sampled waveform is saved.

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