CIS chip image test method and device and ATE system

Abstract

The invention is suitable for the technical field of semiconductor chip testing, and provides a CIS chip image testing method and device and an ATE system.The method comprises the steps that preprocessing configuration from an upper computer is received, and the preprocessing configuration at least comprises a preprocessing type and a target frame number; based on the preprocessing type and a hardware platform of the image acquisition equipment, an objective function set corresponding to the hardware platform is selected from a plurality of platform classes of the first application program, and the objective function set comprises an objective function used for decoding and format conversion and an instruction set function used for preprocessing operation; original image data of the CIS chip are collected according to the target frame number, the target function set is called in the collection process to preprocess the original image data, and at least one preprocessed image frame is generated and then sent to an upper computer for testing. According to the scheme, high throughput acquisition, stable transmission and the processing efficiency of the upper computer side can be considered on the premise that the complexity and cost of the system are not obviously increased.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor chip testing, and particularly relates to a CIS chip image testing method, device and ATE system. BACKGROUND

[0002] In the research and development and mass production testing of high-end CIS (CMOS Image Sensor, image sensor) chips, an automatic test equipment (ATE) is usually used to cooperate with an image acquisition device to complete large-scale data acquisition and uploading, and a host computer side executes image restoration and defect detection processes. With the improvement of CIS resolution, frame rate and the popularization of multi-chip parallel testing, the test link and the host computer processing are under higher data throughput and real-time pressure; at the same time, the test task often involves continuous multi-frame acquisition and multiple pixel formats, which further increases the burden of the system in terms of bandwidth occupation, cache management and processing thread arrangement.

[0003] The common practice of the existing platform is to expand the capacity by improving the physical transmission capacity or increasing the hardware configuration of the host computer and the acquisition end, such as a faster transmission channel, a larger cache or a higher specification processing unit. Although this kind of solution can alleviate the throughput bottleneck to a certain extent, it often brings about cost increase, power consumption increase and engineering constraints in structure integration and signal integrity; in the multi-channel concurrent and long frame sequence scene, problems such as increased receiving pressure and processing delay accumulation caused by link fluctuation may still occur.

[0004] Therefore, how to balance high-throughput acquisition, stable transmission and processing efficiency of the host computer side without significantly increasing the system complexity and cost has become a technical problem to be solved in the field of CIS chip testing. SUMMARY

[0005] Therefore, the embodiments of the application provide a CIS chip image testing method, device and ATE system, which can balance high-throughput acquisition, stable transmission and processing efficiency of the host computer side without significantly increasing the system complexity and cost.

[0006] A first aspect of the embodiments of the application provides a CIS chip image testing method applied to an image acquisition device in an ATE, wherein the image acquisition device is installed with a first application program, and the first application program is used to acquire image data of the CIS chip and pre-process the image data. The CIS chip image testing method comprises the following steps. receiving a pre-processing configuration from a host computer, wherein the pre-processing configuration at least includes a pre-processing type and a target frame number; selecting, based on the pre-processing type and a hardware platform of the image acquisition device, a target function set corresponding to the hardware platform from a plurality of platform categories of the first application program, the target function set including a target function for decoding and format conversion and an instruction set function for the pre-processing operation; acquiring original image data of the CIS chip according to the target frame number, and calling the target function set to pre-process the original image data during the acquisition process, and sending at least one pre-processed image frame to the host computer for testing.

[0007] In the embodiments of the present application, first, the image acquisition end generates and sends pre-processed image frames according to the pre-processing type and the target frame number issued by the host computer, and calls the target function set matched with the hardware platform of the image acquisition device during the acquisition process to complete decoding, format conversion and pre-processing in the same processing link, reduces intermediate data handling and waiting, moves the pre-processing calculation to the image acquisition end, and reduces the single frame processing delay. Second, only the pre-processed image frames are generated and sent according to the target frame number, which significantly reduces the amount of data sent, relieves the link bandwidth pressure, and improves the transmission stability in the multi-channel concurrent scenario. In this way, the host computer side directly implements detection on the pre-processed frames, avoids repeated decoding, format conversion and multi-frame statistical pre-processing, reduces the computing burden of the host computer and improves the overall test throughput. In summary, without significantly increasing the system complexity and cost, the method realizes the synergistic effect of efficient pre-processing at the acquisition end, reduced transmission load and lightweight processing at the host computer side, so as to balance high-throughput acquisition, stable transmission and processing efficiency at the host computer side.

[0008] In a possible implementation, the pre-processing configuration is transmitted in the form of a message, and the receiving of the pre-processing configuration from the host computer includes: receiving a request instruction message from the host computer, the request instruction message being composed of a header field and payload data in byte sequence; parsing the request instruction message, reading the payload data according to the length of the payload data in the header field, and obtaining the byte values of the pre-processing type field and the target frame number field from the payload data to determine the pre-processing configuration.

[0009] In a possible implementation, the method further includes: suspending the real-time continuous acquisition and transmission thread in response to the pre-processing configuration; generating and sending a response instruction message to indicate the execution result of the corresponding request instruction.

[0010] In a possible implementation, the acquiring of the original image data of the CIS chip according to the target frame number includes: Based on the target number of frames and the image size, an image cache queue for preprocessing is constructed. The cache queue consists of multiple cache units, and each cache unit contains at least a frame number, pixel format, width, height, and data pointer. The acquired raw image data of each frame is written sequentially into an idle buffer unit, and the status of the buffer unit is confirmed to be ready. Once any cached unit has been written, it is submitted to the preprocessing channel for processing by calling the target function set, and the cumulative frame count processed is recorded. Once the cumulative frame count reaches the target frame count, the cache units related to this preprocessing are frozen, the intermediate results used to generate the preprocessed image frames are retained, and the remaining cache units are released to an idle state.

[0011] In one possible implementation, the acquisition process involves calling the target function set to preprocess the raw image data, including: The target function for decoding and format conversion in the target function set is called on the submitted cache unit. In the same function call, the shifting and image format conversion related to the hardware platform are completed, and the original image data in the cache unit is converted into the internal processing format. According to the preprocessing type, the instruction set function in the target function set is called to perform the corresponding preprocessing operation on the image data of the internal processing format, and the operation result is written into the intermediate result buffer; When the cumulative number of frames corresponding to the intermediate result buffer reaches the target number of frames, the preprocessed image frame is output.

[0012] A second aspect of this application provides a CIS chip image testing method, applied to a host computer, wherein the host computer is equipped with a second application program, the second application program being used to configure the image data preprocessing of the CIS chip and the image testing of the CIS chip; The CIS chip image testing method includes: In response to a test task from the second application, a preprocessing configuration is sent to the image acquisition device, the preprocessing configuration including at least a preprocessing type and a target number of frames; Receive at least one preprocessed image frame sent by the image acquisition device; Image testing is performed on the at least one preprocessed image frame based on the preprocessing type.

[0013] In this embodiment, the host computer generates and distributes a preprocessing configuration containing the preprocessing type and target frame number, enabling the image acquisition end to complete decoding, format conversion, and corresponding preprocessing at the source. The host computer only receives the preprocessed frames and directly enters the detection process according to the type, thus transforming the organization method of "continuously transmitting raw frames and completing preprocessing locally" into a lightweight path of "only transmitting necessary preprocessed result frames and directly performing detection." This significantly reduces the amount of data sent and the host computer's preprocessing overhead, alleviating bandwidth and CPU usage and shortening the response time from reception to detection. Furthermore, it reduces cache and scheduling pressure in multi-chip parallel scenarios, improving stable reception and timely processing capabilities. Overall, this organization method achieves efficient collaboration with the image acquisition end without significantly increasing system complexity and cost, balancing high-throughput acquisition, stable transmission, and host computer-side processing efficiency.

[0014] In one possible implementation, the image acquisition device and the host computer transmit information via messages, and before receiving at least one preprocessed image frame sent by the image acquisition device, the method further includes: Receive the response instruction message returned by the image acquisition device based on the preprocessing configuration; Based on the response instruction message, a acquisition control instruction is sent to the image acquisition device to trigger the image acquisition device to acquire images according to the target number of frames and perform the preprocessing.

[0015] In one possible implementation, the preprocessed image frame is an image transmitted in fragments according to image data stream packet messages. The image data stream packet messages include a header packet, data packets, and a trailer packet. The header packet includes a frame sequence number field and a packet sequence number field for sequential reassembly. The CIS chip image testing method further includes: Based on the packet sequence number field, the received image data stream packets are checked for sequence order. When a discontinuous sequence is detected, the missing packet sequence number and its corresponding frame sequence number are determined. Generate and send a retransmission request message, carrying the missing packet sequence number and its corresponding frame sequence number in the payload data; Receive the retransmitted image data stream packet message returned for the missing packet sequence number, verify that its frame sequence number and packet sequence number are consistent with the retransmission request, and fill the data packet back into the data stream position of the current frame according to the sequence number. The order of the preprocessed image frames is reassembled based on the completed packet sequence.

[0016] A third aspect of this application provides a CIS chip image testing device, an image acquisition device configured in an ATE, wherein the image acquisition device is equipped with a first application program, the first application program being used to acquire image data of the CIS chip and preprocess the image data; The CIS chip image testing device includes: A receiving module is used to receive preprocessing configuration from a host computer, wherein the preprocessing configuration includes at least a preprocessing type and a target number of frames; The function selection module is used to select a set of target functions corresponding to the hardware platform from multiple platform classes of the first application based on the preprocessing type and the hardware platform of the image acquisition device. The set of target functions includes target functions for decoding and format conversion and instruction set functions for preprocessing operations. The preprocessing module is used to acquire the raw image data of the CIS chip according to the target number of frames. During the acquisition process, the target function set is called to preprocess the raw image data, and at least one preprocessed image frame is generated and sent to the host computer for testing.

[0017] A fourth aspect of this application provides an ATE system, the ATE system including an image acquisition device in the ATE and a host computer for controlling the ATE; The image acquisition device is used to receive a preprocessing configuration from a host computer. The preprocessing configuration includes at least a preprocessing type and a target frame number. Based on the preprocessing type and the hardware platform of the image acquisition device, it selects a target function set corresponding to the hardware platform from multiple platform classes of the first application. The target function set includes target functions for decoding and format conversion, and instruction set functions for the preprocessing operations. It acquires raw image data of the CIS chip according to the target frame number. During the acquisition process, it calls the target function set to preprocess the raw image data, generates at least one preprocessed image frame, and sends it to the host computer for testing. The host computer is configured to send a preprocessing configuration to the image acquisition device in response to a test task from the second application, the preprocessing configuration including at least a preprocessing type and a target number of frames; receive at least one preprocessed image frame sent by the image acquisition device; and perform image testing on the at least one preprocessed image frame based on the preprocessing type.

[0018] The fifth aspect of this application provides a semiconductor testing device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the CIS chip image testing method described in the first aspect above, or implements the CIS chip image testing method described in the second aspect above.

[0019] A sixth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the CIS chip image testing method described in the first aspect above, or implements the CIS chip image testing method described in the second aspect above.

[0020] A seventh aspect of this application provides a computer program product that, when run on a semiconductor testing device, causes the semiconductor testing device to execute the CIS chip image testing method described in the first aspect, or to execute the CIS chip image testing method described in the second aspect. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an ATE system provided in an embodiment of this application; Figure 2 This is a flowchart illustrating the parallel algorithm calculation and testing process of the ATE system; Figure 3 This is a flowchart illustrating a CIS chip image testing method provided in an embodiment of this application; Figure 4 This is a flowchart illustrating another CIS chip image testing method provided in an embodiment of this application; Figure 5 This is a schematic diagram of the control command instruction transmission format in the second application of the host computer; Figure 6 This is a schematic diagram of the transmission format of image data packets in the second application of the host computer; Figure 7 This is a schematic diagram of the structure of a CIS chip image testing device provided in an embodiment of this application; Figure 8 This is a schematic diagram of another CIS chip image testing device provided in an embodiment of this application; Figure 9 This is a schematic diagram of the structure of the semiconductor testing equipment provided in the embodiments of this application. Detailed Implementation

[0023] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0024] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0025] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0026] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0027] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0028] It should be understood that the sequence number of each step in this embodiment does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this application embodiment.

[0029] In the R&D and mass production testing of high-end CIS (CMOS Image Sensor) chips, automated test equipment (ATE) is typically used in conjunction with image acquisition equipment to complete the acquisition and transmission of large-scale data. The host computer then performs processes such as image reconstruction and defect detection. With the increase in CIS resolution and frame rate, as well as the widespread use of parallel testing of multiple chips, the test link and host computer processing face higher data throughput and real-time pressures. At the same time, test tasks often involve continuous multi-frame acquisition and multiple pixel formats, further increasing the burden on the system in terms of bandwidth usage, cache management, and processing thread arrangement.

[0030] The common practice in existing platforms is to expand capacity by improving physical transmission capabilities or upgrading the hardware configuration of the host computer and the acquisition terminal, such as through higher-speed transmission channels, larger buffers, or higher-specification processing units. While such solutions can alleviate throughput bottlenecks to some extent, they often lead to increased costs, higher power consumption, and engineering constraints related to structural integration and signal integrity. In scenarios with multi-channel concurrency and long frame sequences, problems such as increased receiving pressure and accumulated processing delays due to link fluctuations may still occur.

[0031] Therefore, how to balance high-throughput acquisition, stable transmission, and processing efficiency on the host computer side without significantly increasing system complexity and cost has become a pressing technical problem in the field of CIS chip testing.

[0032] To address the aforementioned issues, this application provides a CIS chip image testing method, apparatus, and ATE system. In the CIS chip image testing method, firstly, the image acquisition end, based on the preprocessing type and target frame number issued by the host computer, calls a target function set matching the hardware platform of the image acquisition device during the acquisition process. Decoding and format conversion are completed within the same processing link, and preprocessing is executed using instruction set functions, reducing intermediate data handling and waiting time. This shifts preprocessing calculations to the image acquisition end, reducing single-frame processing latency. Secondly, preprocessed image frames are generated and sent only according to the target frame number, significantly reducing the amount of data transmitted, alleviating link bandwidth pressure, and improving transmission stability in multi-channel concurrent scenarios. This allows the host computer to directly perform detection on the preprocessed frames, avoiding repetitive decoding, format conversion, and multi-frame statistical preprocessing, reducing the host computer's computational burden and improving overall test throughput. In summary, without significantly increasing system complexity and cost, this method achieves a synergistic effect of efficient preprocessing at the acquisition end, reduced transmission load, and lightweight processing on the host side, thus balancing high-throughput acquisition, stable transmission, and host computer-side processing efficiency.

[0033] The following description, with reference to the accompanying drawings, details the CIS chip image testing method, apparatus, ATE system, semiconductor testing equipment, storage medium, and computer program provided in the embodiments of this application.

[0034] See Figure 1 The diagram illustrates a structural schematic of an ATE system provided in an embodiment of this application. The ATE system includes an image acquisition device within the ATE and a host computer for controlling the ATE. The image acquisition device is equipped with a first application program for acquiring image data from a CIS chip and performing image data preprocessing. The host computer is equipped with a second application program for configuring image data preprocessing of the CIS chip and image testing of the CIS chip.

[0035] It should be noted that the CIS chip in this application may refer to the image sensor chip under test, such as the CIS chip under test.

[0036] In this embodiment, the second application is used to generate a preprocessing configuration based on the test task. The preprocessing configuration includes at least a preprocessing type and a target frame number. The second application encapsulates the preprocessing configuration into a request instruction message and sends it to the image acquisition device. The first application is used to receive the request instruction message from the host computer. The request instruction message consists of a header field and payload data in byte sequence. The first application parses the request instruction message, reads the payload data according to the length of the payload data in the header field, and obtains the byte values ​​of the preprocessing type field and the target frame number field from the payload data to determine the preprocessing configuration. In response to the preprocessing configuration, the first application pauses the real-time continuous acquisition transmission thread and generates and sends a response instruction message to indicate the execution result of the corresponding request instruction.

[0037] After determining the preprocessing configuration, the first application selects a set of target functions corresponding to the hardware platform from multiple platform classes of the first application, based on the preprocessing type and the hardware platform of the image acquisition device. The target function set includes target functions for decoding and format conversion, as well as instruction set functions for preprocessing operations. Subsequently, the first application constructs an image buffer queue for preprocessing according to the target number of frames and image size. The buffer queue consists of multiple buffer units, each of which contains at least a frame number, pixel format, width, height, and data pointer. The acquisition thread is then started to acquire the raw image data of the CIS chip according to the target number of frames.

[0038] During the acquisition process, the first application sequentially writes each frame of raw image data acquired into an idle buffer unit and confirms that the buffer unit is ready. Once any buffer unit has been written, it is submitted to the preprocessing channel for processing by calling the target function set, and the cumulative processed frame count is recorded. Specifically, the decoding and format conversion target functions in the target function set are called for the submitted buffer unit. In the same function call, the hardware platform-related shifting and image format conversion are completed, converting the raw image data in the buffer unit into the internal processing format. According to the preprocessing type, the instruction set functions in the target function set are called to perform the corresponding preprocessing operations on the image data in the internal processing format, and the operation results are written to the intermediate result buffer. When the cumulative frame count corresponding to the intermediate result buffer reaches the target frame count, the preprocessed image frame is output.

[0039] For transmission, the first application encapsulates the preprocessed image frame into an image data stream packet. This packet includes a header, data packets, and a trailer packet. The header contains a frame sequence number field and a packet sequence number field for reassembly. The first application initiates a transmission thread to send the image data stream packet to the host computer. The second application receives the image data stream packet and performs sequence verification and reassembly based on the frame and packet sequence number fields to restore the single preprocessed image frame. The second application also performs image testing on the preprocessed image frame based on its preprocessing type.

[0040] In some optional embodiments, when the host computer detects a discontinuity in the sequence during sequence verification, the second application generates and sends a retransmission request message, carrying the missing packet sequence number and its corresponding frame sequence number in the payload data; after receiving the retransmission request message, the first application only retransmits the missing data packet and keeps its frame sequence number and packet sequence number unchanged; after receiving the retransmission image data stream packet message and filling it back into the corresponding position, the second application completes the sequential reassembly of the single-frame preprocessed image frames according to the completed packet sequence.

[0041] In the aforementioned ATE system, the host computer issues a preprocessing configuration containing the preprocessing type and target frame number via a second application. Upon receiving the request instruction message, the first application pauses the real-time continuous acquisition and transmission thread and returns a response instruction message. Subsequently, based on the hardware platform, it selects the target function set from the platform class. During the acquisition process, preprocessing is completed using decoding and format conversion target functions and instruction set functions, generating and sending only preprocessed image frames. The preprocessed image frames are transmitted in fragmented image data stream packets, with frame sequence number and packet sequence number fields in the packet header, enabling the host computer to sequentially reassemble and directly enter the test process. This system arrangement moves preprocessing forward to the image acquisition device side, reducing the amount of raw data sent and lowering the preprocessing burden on the host computer. Platform-based matching of platform class and target function set reduces intermediate conversion and handling overhead. The image buffer queue and fragmented packet organization enhance the continuity and controllability of the data path. If necessary, retransmission request messages can be used for targeted packet replacement to ensure frame data integrity. Thus, without significantly increasing system complexity and cost, it achieves the synergy of efficient preprocessing at the acquisition end, stable transmission, and simplified detection on the host computer side, balancing high-throughput acquisition, transmission stability, and host computer processing efficiency.

[0042] Based on the above system implementation, see Figure 2 A schematic diagram of the process of parallel algorithm calculation and testing in an ATE system is shown. Figure 2 Taking multiple channels as an example, this demonstrates the parallel processing of channels 1 to n under the same test task. The second application and the first application work together on their respective sides to complete control and data processing. The specific process is as follows: The second application generates a preprocessing configuration based on the test task, encapsulates it into a request instruction message, and sends it to the image acquisition device channel by channel; the first application receives and parses the request instruction message in each channel, determines the preprocessing type and target frame number based on the payload data, pauses the real-time continuous acquisition and transmission thread, and returns a response instruction message.

[0043] The first application constructs an image cache queue ("circular queue" in the figure) for preprocessing based on the image size and the target number of frames. The queue consists of multiple cache units. At the same time, it selects the target function set corresponding to the platform from multiple platform classes according to the preprocessing type and the native hardware platform.

[0044] In each channel, the first application acquires the raw image data output by the CIS chip according to the target frame number (the "acquisition thread" in the figure is used to implement this acquisition action), writes each frame of raw image data into the idle buffer unit of the buffer queue in sequence and sets it to ready; when any buffer unit is written, it is submitted to the preprocessing channel, and the decoding and format conversion target functions in the target function set are called to complete the hardware platform-related shift processing and image format conversion in the same function call, and then the instruction set function in the target function set is called to perform the operation corresponding to the preprocessing type, and the result is written to the intermediate result buffer; when the cumulative frame number reaches the target frame number, the preprocessed image frame is output.

[0045] The first application encapsulates the preprocessed image frames into image data stream packets, fragmenting them into header packets, data packets, and tail packets. It writes frame sequence number fields and packet sequence number fields for sequential reassembly into the packet header. Then, it starts the transmission process in each channel ("Start Transmission Thread" in the figure) and sends the image data stream packets in parallel.

[0046] The host computer establishes a receiving process for each channel ("Start Receiving Thread" in the figure). Based on the frame sequence number field and packet sequence number field, it performs sequence verification and reassembly on the received image data stream packets to obtain a single pre-processed image frame. When a packet sequence discontinuity is detected, a retransmission request message is generated and sent. The payload data carries the missing packet sequence number and its corresponding frame sequence number. After receiving the missing data packet, it is filled back into the corresponding position to complete the sequence reassembly of the frame.

[0047] The second application sends the reconstructed preprocessed image frames into the corresponding image test process according to the preprocessing type. Channels 1 to n are executed in parallel until each channel reaches the target number of frames and completes the test task.

[0048] It should be noted that, Figure 2The “circular queue” is the “image buffer queue”, “algorithm processing” corresponds to “calling the target function set to preprocess the original image data”, “preprocessing encapsulation and packaging” means “encapsulating the preprocessed image frame into an image data stream packet”, and “start transmission thread / start receiving thread” are the implementation methods of “sending to the host computer for testing / receiving preprocessed image frames” respectively.

[0049] The above steps are run independently on each channel, enabling parallel testing for multiple channels.

[0050] See Figure 3 This document illustrates a flowchart of a CIS chip image testing method provided in an embodiment of this application. This method is applied to the image acquisition device in the aforementioned ATE system, such as... Figure 3 As shown, the method may include the following steps: Step 301: Receive preprocessing configuration from the host computer. The preprocessing configuration includes at least the preprocessing type and the target number of frames.

[0051] In this embodiment, the second application installed on the host computer generates a preprocessing configuration based on the test task and sends it to the image acquisition device in the ATE; the first application on the image acquisition device receives and parses the preprocessing configuration, obtains the preprocessing type and target frame number, and registers it locally as the basis for subsequent selection of target function set, construction of image cache queue, and acquisition and preprocessing according to target frame number.

[0052] Among them, the preprocessing configuration refers to the set of parameters used to instruct the first application what kind of data preprocessing to perform during the acquisition process and its frame count requirements; The preprocessing type indicates the category of preprocessing operations; The target frame number is used to determine the number of consecutive frames that participate in this preprocessing operation.

[0053] For example, in a test scenario that requires statistical processing of 32 consecutive frames of images, the preprocessing configuration generated by the second application can set the "preprocessing type" to the corresponding statistical class identifier and the "target frame number" to thirty-two. After receiving and parsing the configuration, the first application selects the target function set corresponding to the local hardware platform in subsequent steps and configures the acquisition and preprocessing process according to the target frame number.

[0054] The above examples are only used to illustrate the meaning of the preprocessing configuration and its role in this method, and do not constitute a limitation on the claims.

[0055] In one possible implementation, the preprocessing configuration is transmitted in the form of a message, and receiving the preprocessing configuration from the host computer includes: Receive request instruction messages from the host computer. The request instruction message consists of a header field and payload data in byte sequence. The request instruction message is parsed, the payload data is read according to the length of the payload data in the header field, and the byte values ​​of the preprocessing type field and the target frame number segment are obtained from the payload data to determine the preprocessing configuration.

[0056] In this embodiment, the preprocessing configuration is transmitted between the host computer and the image acquisition device in the ATE via messages. Specifically, the first application on the image acquisition device receives a request instruction message from the host computer through its network interface. The request instruction message consists of a header field and payload data in byte sequence. The header field is used to identify message attributes and includes at least a field indicating the length of the payload data, which carries control parameters. The first application parses the header fields sequentially according to the message format and reads the payload data based on the payload data length in the header field. Subsequently, it extracts the byte values ​​of the preprocessing type field and the target frame digital segment from the payload data to determine the preprocessing configuration. This preprocessing configuration is registered locally by the first application and serves as the basis for subsequent steps such as selecting the target function set, configuring the acquisition process, and constructing the image buffer queue.

[0057] For example, the payload data can adopt a compact byte layout: the first byte is a preprocessing type field (used to identify the preprocessing operation category), followed by a target frame number field (used to indicate the number of consecutive frames participating in preprocessing); after the first application completes parsing, it can perform subsequent processing based on the determined preprocessing type and target frame number. The above field naming and values ​​are merely illustrative and do not constitute a limitation on the scope of the claims of this application.

[0058] In another possible implementation, the method further includes: In response to the preprocessing configuration, pause the real-time continuous acquisition and transmission thread; Generate and send a response instruction message to indicate the execution result of the corresponding request instruction.

[0059] Specifically, this application operates on top of the standard Ethernet protocol stack (physical layer, data link layer, network layer, transport layer, session layer, presentation layer, and application layer), with the transport layer employing connectionless user data packet communication. The control plane is used for configuration and command interaction, while the data plane is used to carry image data stream transmission. The messages involved in the control plane are called "request command messages" and "response command messages," while the messages involved in the data plane are called "image data stream packet messages." The fields used for frame-level and packet-level identification are respectively called "frame sequence number field" and "packet sequence number field."

[0060] On the control plane, the second application generates a preprocessing configuration based on the test task and sends it to the image acquisition device. The first application receives request command messages from the host computer via the network interface and parses the user data portion in the order of "command header + payload data". The command header is used to identify the control semantics and length, and at least includes the fixed field Fixed0x42, control flag Flag, command type Command, payload length Length, and request sequence number ReqId. The first application reads the payload data based on the length, extracts the preprocessing type field and the byte value of the target frame digital segment, determines the preprocessing configuration accordingly, and registers it locally. This configuration serves as the basis for subsequent selection of the target function set, configuration of the acquisition process, and construction of the image buffer queue.

[0061] After the preprocessing configuration takes effect, the first application enters the preprocessing preparation stage: in response to the preprocessing configuration, the real-time continuous acquisition and transmission thread is paused to avoid the existing data path affecting the subsequent acquisition and preprocessing performed according to the target frame number; then, an acknowledgment command message is generated and sent to provide feedback on the execution result. The user data portion of the acknowledgment command message is organized in the order of "acknowledgment header + payload data". The acknowledgment header at least includes the execution status (Status), acknowledgment type (Acknowledge), payload length (Length), and acknowledgment sequence number (AckId) to match the aforementioned ReqId; the payload data is used to transmit necessary status or parameter information so that the host computer can arrange subsequent control accordingly.

[0062] It should be noted that after receiving the response command message, the host computer can instruct the image acquisition device to perform image acquisition and preprocessing according to the preprocessing configuration.

[0063] Step 302: Based on the preprocessing type and the hardware platform of the image acquisition device, select the target function set corresponding to the hardware platform from multiple platform classes of the first application.

[0064] In this embodiment, the first application pre-organizes various "platform classes" in an object-oriented manner to abstract the differences in data layout and instruction set architecture between different hardware platforms. For example, the Base platform class is used as the base class, providing general conversion functions (such as shift calculations) in a standard format. Platform classes such as OX2, TG3, and RB4 correspond to different image acquisition device hardware platforms, and each class provides conversion calculations and preprocessing implementations that match the characteristics of that platform. Based on this mapping relationship, after obtaining the preprocessing type and the read local hardware platform information in step 301, the first application can locate the corresponding platform class and load its target function set.

[0065] The objective function set includes at least two types of functions: first, decoding and format conversion objective functions that simultaneously perform platform-specific shifting and image format conversion within a single function call, avoiding the intermediate data transfer and additional overhead caused by first uniformly shifting data from different platforms and then performing separate format conversion; second, instruction set functions corresponding to the preprocessing type, which use vectorized parallel processing to perform batch operations on data blocks to improve computational throughput. These instruction set functions leverage the instruction-level parallelism supported by the hardware platform to accelerate the core vector operations in the preprocessing process.

[0066] For example, if the hardware platform is "OX2", the first application selects the target function set of "OX2 platform class": calling the decoding and format conversion target functions to directly convert the input data into the internal processing format, while completing the bit width / alignment processing related to the "OX2" platform; then, according to the preprocessing type, calling the corresponding instruction set function in "OX2 platform class" to perform preprocessing operations. If the hardware platform is "TG3" or "RB4", the target function set of "TG3 platform class" or "RB4 platform class" is selected in the same way, so that the decoding / conversion path and the preprocessing path are both matched with the characteristics of the hardware platform, providing a unified and efficient execution unit for the acquisition and preprocessing in subsequent steps.

[0067] Step 303: Collect the raw image data of the CIS chip according to the target frame number. During the acquisition process, call the target function set to preprocess the raw image data, generate at least one preprocessed image frame, and send it to the host computer for testing.

[0068] In this embodiment, the first application starts the acquisition process to obtain raw image data from the CIS chip, using the target frame number determined in step 301 as the acquisition termination condition. Simultaneously with the acquisition, for each arriving frame of raw image data, the target function set loaded in step 302 is called sequentially: first, the decoding and format conversion target functions within the set complete the hardware platform-related shifting and format conversion within a single function call, transforming the input data into an internal processing format; then, according to the preprocessing type, the instruction set functions in the target function set are called to perform the corresponding preprocessing operations on the frame data. As frame data arrives continuously, the first application completes the above processing frame by frame. When the cumulative number of processed frames reaches the target frame number, at least one preprocessed image frame is generated based on the completed preprocessing operation results; the preprocessed image frame is then sent to the host computer for testing.

[0069] For example, when the preprocessing type is continuous multi-frame statistics and the target number of frames is 32, the first application sequentially completes the decoding / format conversion and corresponding preprocessing calculations for the first 32 frames. When the target number of frames is reached, a preprocessed image frame is generated and sent, and the host computer enters the subsequent image testing process accordingly.

[0070] Based on the data plane described in step 301 above, the message involved is called "image data stream packet message". It can be understood that at least one preprocessed image frame generated in step 303 can be transmitted to the host computer in the form of image data stream packets.

[0071] Specifically, after completing the acquisition and preprocessing, the first application organizes the preprocessed image frames into image data stream packets for transmission. To facilitate sequential reassembly, a single frame of data is fragmented into three types of protocol packets: header frames, intermediate frames, and tail frames. The header frame describes the basic information of the image frame, including at least the image width, image height, image format and mode, frame sequence number, and start and end timestamps. The intermediate frames divide the image data into several data segments based on the transport layer load, with each segment carrying a packet sequence number and corresponding data. The tail frame indicates the end of data transmission for the image frame. For unified parsing, the header of the image data stream packets may include a packet status (Status), a packet flag (Flag), extended information (EI), a packet format (PacketFormat), a frame-level identifier (BlockId), and a packet-level identifier (PacketId), where BlockId corresponds to the frame sequence number field in the specification and claims, and PacketId corresponds to the packet sequence number field in the specification and claims. The host computer receiver performs sequence verification and reassembly based on the frame sequence number field and packet sequence number field to obtain a complete preprocessed image frame and proceed to the subsequent testing process.

[0072] The naming and specific values ​​of the above fields can be trimmed or extended according to the engineering implementation, but this does not affect the implementation of the functions of "transmitting and parsing the preprocessing configuration in the form of a message" and "sending the preprocessed image frame to the host computer for testing".

[0073] In one possible implementation, raw image data of the CIS chip is acquired according to the target frame number, including: Based on the target number of frames and image size, construct an image buffer queue for preprocessing; The acquired raw image data of each frame is written sequentially into an idle buffer unit, and the status of the buffer unit is confirmed to be ready. Once any buffer unit has been written, it is submitted to the preprocessing channel for processing by calling the target function set, and the cumulative frame count processed is recorded. Once the cumulative frame count reaches the target frame count, the cache units related to this preprocessing are frozen, the intermediate results used to generate the preprocessed image frames are retained, and the remaining cache units are released to an idle state.

[0074] Specifically, firstly, the first application constructs an image cache queue in memory for preprocessing based on the target number of frames and image size. This cache queue consists of multiple cache units, each containing at least fields such as frame number, pixel format, width, height, and data pointer, used to carry the raw image data of a single frame and its necessary descriptive information, and maintaining status indicators such as idle, ready, and processing at the queue level.

[0075] During the acquisition phase, each frame of raw image data from the CIS chip is written sequentially to idle buffer units in the buffer queue. After a frame is written, the first application sets the status of that buffer unit to ready, indicating that the unit can be submitted to the preprocessing channel. To avoid writing and processing blocking each other, the buffer queue can employ a sequential allocation and ready reclamation mechanism to ensure timely replenishment of idle units and orderly submission of ready units.

[0076] Once any buffer unit has been written to and marked as ready, the first application submits it to the preprocessing channel and calls the target function set determined in step 302 for processing. During processing, the hardware platform-related shifting and format conversion are first completed in a single function call using the decoding and format conversion target functions. Then, according to the preprocessing type, the corresponding preprocessing operations are performed on the frame data using the instruction set functions. After processing each ready unit, the first application updates the cumulative processed frame count and releases the state of the buffer unit from processing back to idle, so that it can be reused by subsequent frames.

[0077] When the cumulative frame count reaches the target frame count, the first application freezes the cache units related to this preprocessing and retains the intermediate results to generate preprocessed image frames; the remaining cache units unrelated to this preprocessing are restored to an idle state, freeing up space for the next round of acquisition and preprocessing. Subsequently, at least one preprocessed image frame is generated based on the intermediate results, and the process proceeds to subsequent transmission and host computer testing.

[0078] For example, in a scenario where 32 consecutive frames participate in preprocessing, the target frame number is 32, the image size is 1920×1080, and the pixel format is RAW10. The first application configures at least 32 buffer units for the buffer queue accordingly. Each unit records the frame number, pixel format, width, height, and data pointer of the frame. After acquisition begins, frames 1 to 32 are sequentially written to idle buffer units and marked as ready. Ready units are submitted to the preprocessing channel, where the target function set performs decoding and format conversion for each frame, as well as instruction set operations corresponding to the preprocessing type, while updating the cumulative processed frame count. When the count reaches 32, the buffer units related to this preprocessing are frozen, and preprocessed image frames are generated using the accumulated intermediate results. Subsequently, buffer units unrelated to this preprocessing are restored to idle status, providing capacity for the next round of acquisition and preprocessing.

[0079] In another possible implementation, the target function set is invoked during the acquisition process to preprocess the raw image data, including: The target function for decoding and format conversion in the target function set is called on the submitted cache unit. In the same function call, the hardware platform-related shifting and image format conversion are completed, and the original image data in the cache unit is converted into the internal processing format. Based on the preprocessing type, the instruction set function in the target function set is called to perform the corresponding preprocessing operation on the image data of the internal processing format, and the operation result is written to the intermediate result buffer; When the cumulative number of frames corresponding to the intermediate result buffer reaches the target number of frames, the preprocessed image frame is output.

[0080] Specifically, the preprocessing of raw image data by calling the target function set during the acquisition process can be implemented as follows: First, for the submitted ready buffer unit, the first application calls the decoding and format conversion target functions in the target function set. In the same function call, the shifting processing and image format conversion related to the hardware platform are completed simultaneously, converting the raw image data in the buffer unit into an internal processing format for subsequent operations. Then, according to the preprocessing type determined in step 301, the instruction set functions in the target function set are called to perform the corresponding preprocessing operations on the data in the internal processing format, and the operation results are written to the intermediate result buffer for accumulation and merging. As frame data continues to arrive, the first application continuously updates the cumulative frame number corresponding to the intermediate result buffer; when the cumulative frame number corresponding to the intermediate result buffer reaches the target frame number, the preprocessed image frame is output, completing this round of preprocessing.

[0081] In the above method embodiment, firstly, the image acquisition end, based on the preprocessing type and target frame number issued by the host computer, calls a target function set matching the hardware platform of the image acquisition device during the acquisition process. Decoding and format conversion are completed within the same processing link, and preprocessing is executed using instruction set functions. This reduces intermediate data handling and waiting, moving preprocessing calculations forward to the image acquisition end and reducing single-frame processing latency. Secondly, preprocessed image frames are generated and sent only according to the target frame number, significantly reducing the amount of data transmitted, alleviating link bandwidth pressure, and improving transmission stability in multi-channel concurrent scenarios. This allows the host computer to directly perform detection on the preprocessed frames, avoiding repetitive decoding, format conversion, and multi-frame statistical preprocessing, reducing the host computer's computational burden and improving overall test throughput. In summary, without significantly increasing system complexity and cost, this method achieves a synergistic effect of efficient preprocessing at the acquisition end, reduced transmission load, and lightweight processing on the host side, thus balancing high-throughput acquisition, stable transmission, and processing efficiency on the host computer side.

[0082] In one possible implementation, the image acquisition device needs to be initialized before the sensor is turned on.

[0083] The step of activating the image sensor, and the host computer initialization command flow, may include: 1. Start Process Trigger "Start Lighting Operation".

[0084] 2. Initialize Sensor Hardware Configuration Call Crmi_SaSensorPower: Power on the sensor.

[0085] Call Crmi_SaSensorClock: Configure the sensor clock.

[0086] Call Crmi_SaSensorGridPink.exe: Initialize sensor GPIO functionality.

[0087] Call Crmi_ReadDecretel2C: Read C register parameters (possibly for verification).

[0088] 3. Parameter writing and configuration Write basic parameters: Write the sensor voltage (in mV); Write Sensor time (in 100kHz). Write the Sensor GPIO value.

[0089] Call Crmi_SafframeParam: Set the image frame parameters.

[0090] 4. MPI and Interface Configuration Call Crmi_SafMipParam: Sets MPI (Image Transfer Protocol) parameters.

[0091] Optional operations: Call Crmi_SafMipReserverMode: Sets the MPI receive mode (only executes when needed).

[0092] Call Crmi_SafGridTimeout: Set the Gras timeout.

[0093] Call Crmi_SaSensorInterface: Configure the Sensor interface type.

[0094] 5. Registers and Function Control Calling Crmi_WriteDecretel2C: Writes I2C register parameters, turns on the sensor and displays the image.

[0095] 6. Start data transmission and control Calling Crmi_VideoControl: Sends control command 1 to open the video stream.

[0096] Calling Crmi_Transmit: Sends control command 1 to start data transmission.

[0097] 7. Process complete Once all operations are completed, the process terminates.

[0098] It should be understood that image acquisition can be performed in the above embodiments after the lighting operation is completed.

[0099] See Figure 4 This illustration shows a flowchart of another CIS chip image testing method provided in an embodiment of this application. This method is applied to the host computer in the aforementioned ATE system, such as... Figure 4 As shown, the method may include the following steps: Step 401: In response to a test task from the second application, a preprocessing configuration is sent to the image acquisition device. The preprocessing configuration includes at least the preprocessing type and the target number of frames.

[0100] Step 402: Receive at least one preprocessed image frame sent by the image acquisition device.

[0101] Step 403: Perform image testing on at least one preprocessed image frame based on the preprocessing type.

[0102] In this embodiment, the communication between the host computer and the image acquisition device in the ATE adopts a communication organization that separates the control plane and the data plane. When the task starts, the second application on the host computer generates a set of data preprocessing parameters for execution at the acquisition end, i.e., the preprocessing configuration, and sends it to the image acquisition device according to the control command instructions; the first application on the image acquisition device receives and parses the preprocessing configuration, and then completes the acquisition and preprocessing according to the target frame number, generates preprocessed image frames, and sends them back to the host computer to enter the test process.

[0103] See Figure 5 The diagram illustrates the control command transmission format in the second application of the host computer. The second application forms data units containing control semantics and parameters at the application layer, adding a control protocol header field to the front as a combination of the application layer header and data. This combination is then appended with a connectionless transmission header at the transport layer, a network layer header at the network layer, and a network interface header at the network interface layer before being sent by the physical network card. The image acquisition device receives the data and performs reverse decapsulation layer by layer, sequentially removing the headers of the network interface layer, network layer, and transport layer to restore the application layer header and data. The first application reads the preprocessing type and target frame number, determines the preprocessing configuration, and pauses the real-time continuous acquisition transmission thread if necessary. Simultaneously, it generates a response command message and returns along the same stack path, allowing the host computer to confirm whether the configuration has taken effect.

[0104] See Figure 6 This diagram illustrates the transmission format of image data packets in the second application of the host computer. After completing acquisition and preprocessing, the first application organizes a single preprocessed image frame into an image data stream packet: at the application layer, a combination consisting of a header and image data is formed, with the header containing frame sequence number and packet sequence number fields for sequential reassembly; this combination is then sent after adding corresponding headers at the transport layer, network layer, and network interface layer. The host computer's receiving path is the reverse of the control command instructions, reconstructing the application layer's header and image data layer by layer, and performing sequence verification and reassembly based on the frame sequence number and packet sequence number fields to obtain a complete preprocessed image frame, which then directly enters the image testing process according to the preprocessing type.

[0105] Through the above implementation, control commands and image data packets are encapsulated, transmitted, and decapsulated along the same network protocol stack. The control plane is used to issue preprocessing configurations and obtain execution confirmations, while the data plane is used to carry preprocessed image frames segmented into frames. This ensures both the determinism of configuration issuance and the reconfigurability and traceability of image data transmission, facilitating stable throughput and timely detection in multi-channel parallel testing scenarios.

[0106] In one possible implementation, the image acquisition device and the host computer transmit information via messages. Before receiving at least one preprocessed image frame sent by the image acquisition device, the method further includes: Receive response command messages returned by the image acquisition device based on the preprocessing configuration; Based on the response command message, a acquisition control command is sent to the image acquisition device to trigger the image acquisition device to acquire images according to the target number of frames and perform preprocessing.

[0107] Specifically, the second application receives and parses the status information in the response instruction message and matches it with the previous configuration request for confirmation. If the configuration is confirmed to be effective, the second application sends an acquisition control instruction to the image acquisition device to trigger the image acquisition device to acquire images according to the target number of frames and perform preprocessing. If the status shows that the configuration is not effective or abnormal, the preprocessing configuration can be resent or an abnormality handling prompt can be given as needed.

[0108] In another possible implementation, the preprocessed image frame is an image transmitted in fragments according to image data stream packet messages. Each image data stream packet message includes a header packet, data packets, and a trailer packet. The header includes a frame sequence number field and a packet sequence number field for sequential reassembly. The CIS chip image testing method further includes: The received image data stream packets are checked for sequence number based on the packet sequence number field. When a discontinuity in the sequence is detected, the missing packet sequence number and its corresponding frame sequence number are determined. Generate and send a retransmission request message, carrying the missing packet sequence number and its corresponding frame sequence number in the payload data; Receive the retransmitted image data stream packet message returned for the missing packet sequence number, verify that its frame sequence number and packet sequence number are consistent with the retransmission request, and fill the data packet back into the data stream position of the current frame according to the sequence number; The order of the preprocessed image frames is reassembled based on the completed packet sequence.

[0109] Specifically, preprocessed image frames are transmitted between the acquisition terminal and the host computer in the form of image data stream packets. After completing preprocessing, the first application on the acquisition terminal starts a transmission thread, fragmenting a single preprocessed image frame into three types of packets: header packets, data packets, and tail packets. The header carries frame sequence number and packet sequence number fields for sequential reassembly. The frame sequence number field uniquely identifies a frame, and the packet sequence number field identifies the position of each data packet within that frame. The second application on the host computer starts a data receiving thread, parses and buffers the arriving image data stream packets, and performs sequential verification and reassembly based on the frame sequence number and packet sequence number fields.

[0110] During the reception and assembly process, when sequence verification detects a discontinuity in packet sequence numbers, the host computer determines the missing packet sequence number and its corresponding frame sequence number, and generates a retransmission request message which is sent to the acquisition end. The payload data of this retransmission request message carries the missing packet sequence number and its corresponding frame sequence number to accurately indicate the data that needs to be retransmitted. After receiving the retransmission request, the acquisition end only retransmits the missing data packet, keeping the frame sequence number and packet sequence number fields of the data packet unchanged. After receiving the retransmitted data packet, the host computer verifies that its frame sequence number and packet sequence number are consistent with the retransmission request, fills the data packet back into the corresponding position of the current frame, and continues to complete the sequence reassembly of the frame.

[0111] Through the above-mentioned packet-based fixed-point retransmission mechanism, the host computer can complete the missing data without retransmitting the entire frame. This avoids bandwidth waste and network congestion, reduces CPU usage on the host computer side, and improves the real-time performance of receiving complete frame data. In multi-chip parallel testing scenarios, it can improve the complete delivery rate of preprocessed image frames, thereby ensuring the stable parallel execution of subsequent image testing processes.

[0112] See Figure 7 The diagram shows a structural schematic of a CIS chip image testing device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0113] The CIS chip image testing device 700 is configured in the image acquisition device of the ATE. The image acquisition device is equipped with a first application program, which is used to acquire image data of the CIS chip and preprocess the image data. The CIS chip image testing device 700 includes: The receiving module 701 is used to receive the preprocessing configuration from the host computer. The preprocessing configuration includes at least the preprocessing type and the target number of frames. The function selection module 702 is used to select a set of target functions corresponding to the hardware platform from multiple platform classes of the first application based on the preprocessing type and the hardware platform of the image acquisition device. The set of target functions includes target functions for decoding and format conversion and instruction set functions for preprocessing operations. The preprocessing module 703 is used to acquire the raw image data of the CIS chip according to the target frame number. During the acquisition process, the target function set is called to preprocess the raw image data, and at least one preprocessed image frame is generated and sent to the host computer for testing.

[0114] In this embodiment of the application, the preprocessing configuration is transmitted in the form of a message, and the receiving module 701 includes: The request message receiving unit is used to receive request instruction messages from the host computer. The request instruction message consists of a header field and payload data in byte sequence. The request message parsing unit is used to parse the request instruction message, read the payload data according to the length of the payload data in the header field, and obtain the byte values ​​of the preprocessing type field and the target frame digital segment from the payload data to determine the preprocessing configuration.

[0115] In this embodiment of the application, the CIS chip image testing apparatus 700 further includes: The data acquisition pause module is used to pause the real-time continuous data acquisition and transmission thread in response to the preprocessing configuration. The response module is used to generate and send response instruction messages to indicate the execution result of the corresponding request instruction.

[0116] In this embodiment of the application, the preprocessing module 703 includes: The building unit is used to construct an image cache queue for preprocessing based on the target number of frames and image size. The cache queue consists of multiple cache units, and each cache unit contains at least the frame number, pixel format, width, height and data pointer. The writing unit is used to write the acquired raw image data of each frame sequentially into an idle buffer unit and to confirm that the buffer unit is ready. The processing unit is used to submit any cached unit to the preprocessing channel for processing by calling the target function set after any cached unit has been written, and to record the cumulative frame count processed. The buffer unit is used to freeze the buffer units related to this preprocessing when the cumulative processed frame count reaches the target frame count, retain the intermediate results used to generate preprocessed image frames, and release the remaining buffer units to an idle state.

[0117] In this embodiment of the application, the preprocessing module 703 further includes: The format conversion unit is used to call the decoding and format conversion target functions in the target function set for the submitted cache unit. In the same function call, it completes the hardware platform-related shift processing and image format conversion, and converts the original image data in the cache unit into the internal processing format. The function call unit is used to call the instruction set function in the target function set according to the preprocessing type, perform the corresponding preprocessing operation on the image data of the internal processing format, and write the operation result into the intermediate result buffer; The image output unit is used to output preprocessed image frames when the cumulative number of frames corresponding to the intermediate result buffer reaches the target number of frames.

[0118] The CIS chip image testing apparatus 700 provided in this application embodiment can be applied to the CIS chip image testing method provided in the foregoing embodiment. For details, please refer to the description of the CIS chip image testing method provided in the above embodiment, which will not be repeated here.

[0119] SeeFigure 8 This diagram illustrates another CIS chip image testing device provided in an embodiment of this application. For ease of explanation, only the parts related to the embodiments of this application are shown.

[0120] The CIS chip image testing device 800 is applied to a host computer, which has a second application program installed. The second application program is used to configure the image data preprocessing of the CIS chip and the image testing of the CIS chip. The CIS chip image testing device 800 includes: The sending module 801 is used to send a preprocessing configuration to the image acquisition device in response to a test task from the second application. The preprocessing configuration includes at least the preprocessing type and the target number of frames. The frame receiving module 802 is used to receive at least one preprocessed image frame sent by the image acquisition device; Test module 803 is used to perform image testing on at least one preprocessed image frame based on the preprocessing type.

[0121] In this embodiment, the image acquisition device and the host computer transmit information via messages. The CIS chip image testing device 800 also includes: The response receiving module is used to receive response command messages returned by the image acquisition device based on the preprocessing configuration; The control sending module is used to send acquisition control commands to the image acquisition device based on the response command message, so as to trigger the image acquisition device to acquire and perform preprocessing according to the target number of frames.

[0122] In this embodiment, the preprocessed image frame is an image transmitted in fragments according to image data stream packets. The image data stream packets include header packets, data packets, and tail packets. The packet header has a frame sequence number field and a packet sequence number field for sequential reassembly. The CIS chip image testing device 800 also includes: The verification module is used to perform sequential verification on the received image data stream packets based on the packet sequence number field. When a discontinuous sequence is detected, the missing packet sequence number and its corresponding frame sequence number are determined. The retransmission message sending module is used to generate and send retransmission request messages, which carry the missing packet sequence number and its corresponding frame sequence number in the payload data. The retransmission packet receiving module is used to receive retransmission image data stream packet messages returned for missing packet sequence numbers, verify that the frame sequence number and packet sequence number are consistent with the retransmission request, and fill the data packet back into the data stream position of the current frame according to the sequence number. The reassembly module is used to reassemble the order of preprocessed image frames in a single frame based on the completed packet sequence.

[0123] The CIS chip image testing apparatus 800 provided in this application embodiment can be applied to the CIS chip image testing method provided in the foregoing embodiment. For details, please refer to the description of the CIS chip image testing method provided in the above embodiment, which will not be repeated here.

[0124] Figure 9 This is a schematic diagram of the semiconductor testing equipment provided in an embodiment of this application. Figure 9 As shown, the semiconductor testing equipment 900 of this embodiment includes: at least one processor 910 ( Figure 9 Only one is shown in the diagram), memory 920, and computer program 921 stored in memory 920 and executable on at least one processor 910, wherein processor 910 executes computer program 921 to implement the steps in the above embodiments of the CIS chip image testing method.

[0125] The semiconductor testing equipment 900 can be a server, physical server, or computing device, etc. This semiconductor testing equipment may include, but is not limited to, a processor 910 and a memory 920. Those skilled in the art will understand that... Figure 9 This is merely an example of semiconductor test equipment 900 and does not constitute a limitation on semiconductor test equipment 900. It may include more or fewer components than shown, or combine certain components, or use different components.

[0126] The processor 910 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0127] In some embodiments, the memory 920 may be an internal storage unit of the semiconductor testing equipment 900, such as a hard disk or memory of the semiconductor testing equipment 900. In other embodiments, the memory 920 may be an external storage device of the semiconductor testing equipment 900, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the semiconductor testing equipment 900. Furthermore, the memory 920 may include both internal and external storage units of the semiconductor testing equipment 900. The memory 920 is used to store operating systems, applications, bootloaders, data, and other programs, such as the program code of computer programs. The memory 920 can also be used to temporarily store data that has been output or will be output.

[0128] In specific implementations, the processor 910, memory 920, and computer program 921 described in the embodiments of this application can execute the embodiments of the CIS chip image testing method of this application, which will not be repeated here.

[0129] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0130] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0131] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0132] In the embodiments provided in this application, it should be understood that the disclosed apparatus / semiconductor testing equipment and methods can be implemented in other ways. For example, the apparatus / semiconductor testing equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0133] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0134] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0135] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0136] The implementation of all or part of the processes in the methods of the above embodiments can also be accomplished by a computer program product. When the computer program product is run on a semiconductor testing device, the semiconductor testing device can implement the steps in the various method embodiments described above.

[0137] The embodiments described above are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for testing CIS chip images, characterized in that, An image acquisition device used in ATE, wherein the image acquisition device is equipped with a first application program, the first application program being used to acquire image data of the CIS chip and preprocess the image data; The CIS chip image testing method includes: Receive a preprocessing configuration from the host computer, the preprocessing configuration including at least the preprocessing type and the target number of frames; Based on the preprocessing type and the hardware platform of the image acquisition device, a target function set corresponding to the hardware platform is selected from multiple platform classes of the first application. The target function set includes target functions for decoding and format conversion, and instruction set functions for preprocessing operations. The raw image data of the CIS chip is acquired according to the target frame number. During the acquisition process, the target function set is called to preprocess the raw image data, and at least one preprocessed image frame is generated and sent to the host computer for testing.

2. The CIS chip image testing method as described in claim 1, characterized in that, The preprocessing configuration is transmitted in the form of a message, and receiving the preprocessing configuration from the host computer includes: Receive a request instruction message from the host computer, the request instruction message consisting of a header field and payload data in byte sequence; The request instruction message is parsed, the payload data is read according to the length of the payload data in the header field, and the byte values ​​of the preprocessing type field and the target frame number segment are obtained from the payload data to determine the preprocessing configuration.

3. The CIS chip image testing method as described in claim 2, characterized in that, The method further includes: In response to the preprocessing configuration, the real-time continuous acquisition and transmission thread is paused; Generate and send a response instruction message to indicate the execution result of the corresponding request instruction.

4. The CIS chip image testing method as described in claim 1, characterized in that, The process of acquiring the raw image data of the CIS chip according to the target frame number includes: Based on the target number of frames and the image size, an image cache queue for preprocessing is constructed. The cache queue consists of multiple cache units, and each cache unit contains at least a frame number, pixel format, width, height, and data pointer. The acquired raw image data of each frame is written sequentially into an idle buffer unit, and the status of the buffer unit is confirmed to be ready. Once any cached unit has been written, it is submitted to the preprocessing channel for processing by calling the target function set, and the cumulative frame count processed is recorded. Once the cumulative frame count reaches the target frame count, the cache units related to this preprocessing are frozen, the intermediate results used to generate the preprocessed image frames are retained, and the remaining cache units are released to an idle state.

5. The CIS chip image testing method as described in claim 4, characterized in that, The acquisition process involves calling the target function set to preprocess the raw image data, including: The target function for decoding and format conversion in the target function set is called on the submitted cache unit. In the same function call, the shifting and image format conversion related to the hardware platform are completed, and the original image data in the cache unit is converted into the internal processing format. According to the preprocessing type, the instruction set function in the target function set is called to perform the corresponding preprocessing operation on the image data of the internal processing format, and the operation result is written into the intermediate result buffer; When the cumulative number of frames corresponding to the intermediate result buffer reaches the target number of frames, the preprocessed image frame is output.

6. A method for testing CIS chip images, characterized in that, The application is used in a host computer, which has a second application program installed. The second application program is used to configure the image data preprocessing of the CIS chip and the image testing of the CIS chip. The CIS chip image testing method includes: In response to a test task from the second application, a preprocessing configuration is sent to the image acquisition device, the preprocessing configuration including at least a preprocessing type and a target number of frames; Receive at least one preprocessed image frame sent by the image acquisition device; Image testing is performed on the at least one preprocessed image frame based on the preprocessing type.

7. The CIS chip image testing method as described in claim 6, characterized in that, The image acquisition device and the host computer transmit information via messages. Before receiving at least one preprocessed image frame sent by the image acquisition device, the method further includes: Receive the response instruction message returned by the image acquisition device based on the preprocessing configuration; Based on the response instruction message, a acquisition control instruction is sent to the image acquisition device to trigger the image acquisition device to acquire images according to the target number of frames and perform the preprocessing.

8. The CIS chip image testing method as described in claim 6, characterized in that, The preprocessed image frame is an image transmitted in fragments according to image data stream packet messages. The image data stream packet message includes a header packet, a data packet, and a tail packet. The header packet of the message has a frame sequence number field and a packet sequence number field for sequential reassembly. The CIS chip image testing method further includes: Based on the packet sequence number field, the received image data stream packets are checked for sequence order. When a discontinuous sequence is detected, the missing packet sequence number and its corresponding frame sequence number are determined. Generate and send a retransmission request message, carrying the missing packet sequence number and its corresponding frame sequence number in the payload data; Receive the retransmitted image data stream packet message returned for the missing packet sequence number, verify that its frame sequence number and packet sequence number are consistent with the retransmission request, and fill the data packet back into the data stream position of the current frame according to the sequence number. The order of the preprocessed image frames is reassembled based on the completed packet sequence.

9. A CIS chip image testing device, characterized in that, An image acquisition device configured in the ATE, the image acquisition device having a first application installed, the first application being used to acquire image data of the CIS chip and preprocess the image data; The CIS chip image testing device includes: A receiving module is used to receive preprocessing configuration from a host computer, wherein the preprocessing configuration includes at least a preprocessing type and a target number of frames; The function selection module is used to select a set of target functions corresponding to the hardware platform from multiple platform classes of the first application based on the preprocessing type and the hardware platform of the image acquisition device. The set of target functions includes target functions for decoding and format conversion and instruction set functions for the preprocessing operation. The preprocessing module is used to acquire the raw image data of the CIS chip according to the target number of frames. During the acquisition process, the target function set is called to preprocess the raw image data, and at least one preprocessed image frame is generated and sent to the host computer for testing.

10. An ATE system, characterized in that, The ATE system includes an image acquisition device in the ATE and a host computer for controlling the ATE; The image acquisition device is used to receive preprocessing configuration from a host computer, the preprocessing configuration including at least a preprocessing type and a target number of frames; Based on the preprocessing type and the hardware platform of the image acquisition device, a target function set corresponding to the hardware platform is selected from multiple platform classes of the first application. The target function set includes target functions for decoding and format conversion, and instruction set functions for preprocessing operations. The raw image data of the CIS chip is acquired according to the target frame number. During the acquisition process, the target function set is called to preprocess the raw image data, and at least one preprocessed image frame is generated and sent to the host computer for testing. The host computer is used to send a preprocessing configuration to the image acquisition device in response to a test task from the second application. The preprocessing configuration includes at least a preprocessing type and a target number of frames. Receive at least one preprocessed image frame sent by the image acquisition device; Image testing is performed on the at least one preprocessed image frame based on the preprocessing type.

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