Memory circuitry and methods for forming memory circuitry

Abstract

Memory circuitry and methods for forming memory circuitry are disclosed. Memory circuitry includes vertically alternating insulation levels and memory cell levels. Memory cells in the memory cell level individually include a horizontal transistor, a capacitor on a capacitor side of the horizontal transistor, and a portion of a digital line on a digital line side of the horizontal transistor. An insulator material extends from the capacitor side of a top gate horizontally in a lower memory cell level through the insulation level between an upper memory cell level and a lower memory cell level to the capacitor side of a bottom gate horizontally in the upper memory cell level. The insulator material in the upper memory cell level and in the lower memory cell level has a laterally outer linear straight surface in a vertical cross-section that passes through and extends horizontally along an axis.

Description

Technical Field

[0001] The embodiments disclosed herein relate to memory circuit systems and methods for forming memory circuit systems. Background Technology

[0002] Memory is a type of integrated circuit system used to store data in a computer system. Memory can be manufactured as one or more arrays of individual memory cells. Memory cells can be written to or read from using digital lines (also called bit lines, data lines, or sense lines) and access lines (also called word lines). Sense lines electrically interconnect memory cells along the columns of the array, and access lines electrically interconnect memory cells along the rows of the array. Each memory cell can be uniquely addressed through a combination of sense lines and access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for extended periods without power. Non-volatile memory is typically defined as memory with a retention period of at least approximately 10 years. Volatile memory dissipates energy and is therefore refreshed / rewritten to maintain data storage. Volatile memory can have a retention period of a few milliseconds or less. Regardless, memory cells are configured to maintain or store memory in at least two distinct optional states. In binary systems, the state is considered either "0" or "1". In other systems, at least some individual memory cells can be configured to store more than two information levels or states.

[0004] Memory cells can be arranged or arranged in several ways, including, for example, in a vertical stack (e.g., along the z-direction), the vertical stack comprising a three-dimensional (3D) memory array region having horizontal hierarchies in which individual memory cells are received (e.g., arranged in the x and y directions). The stack in the 3D memory array region includes vertically alternating insulating and conductive levels (e.g., as part of a memory cell hierarchy) extending into a stepped region. The stepped region contains individual “steps” (alternatively referred to as “steps” or “staircases”) that define contact areas for conductive lines of individuals in the conductive levels, with vertical conductive paths contacting these contact areas to provide electrical access to / from those conductive lines. Summary of the Invention

[0005] In some embodiments, a method for forming a memory circuit system includes forming a vertically alternating layer comprising silicon and silicon-germanium materials directly above a substrate. The silicon material layer includes portions of horizontal transistors in the finished configuration of the memory circuit system. Individual memory cells of the memory circuit system include one of the horizontal transistors, a capacitor on the capacitor side of the horizontal transistor, and portions of digital lines on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portions are horizontally spaced relative to each other along an axis. The horizontal transistor has a gate including a top gate and a bottom gate, and a channel material comprising the silicon material is present between the top gate and the bottom gate. The horizontal portion of the layer comprising the silicon-germanium material is removed from the digital line side. After removal, the horizontal portion of the silicon material layer is vertically thinned from the digital line side to form a thinned portion of the silicon material in one of the individual silicon material layers. The thinned portion extends from the digital line side to the capacitor side. The vertical thinning forms a linear straight surface of the silicon material above and below the thinned portion on the capacitor side in a vertical cross-section that passes through and extends horizontally along the axis. The linear straight surface is one of the following: vertical, at an angle of no more than 40° away from the capacitor side, or at an angle of no more than 30° towards the capacitor side.

[0006] In some embodiments, a memory circuit system includes vertically alternating insulating layers and memory cell layers. Each memory cell in a memory cell layer includes a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis. The horizontal transistor has a gate, including a top gate and a bottom gate, with a channel material between the top gate and the bottom gate. Vertically adjacent layers in the memory cell layers include an upper memory cell layer and a lower memory cell layer. An insulating material extends horizontally from beside the capacitor side of the top gate in the lower memory cell layer through the insulating layer between the upper and lower memory cell layers to beside the capacitor side of the bottom gate in the upper memory cell layer. The insulating material in the upper and lower memory cell layers has a laterally linear straight surface in a vertical cross-section extending horizontally along the axis. The transverse outer linear straight surface is one of the following: vertical, at an angle of no more than 40° to the vertical towards the capacitor side, or at an angle of no more than 30° to the vertical away from the capacitor side.

[0007] In some embodiments, a memory circuit system includes vertically alternating insulating layers and memory cell layers comprising silicon dioxide. Each memory cell in a memory cell layer individually includes a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis. Vertically adjacent layers in the memory cell hierarchy include an upper memory cell layer and a lower memory cell layer. The horizontal transistor has a gate including a top gate as a portion of one of a plurality of top horizontal conductive access lines and a bottom gate including a portion of one of a plurality of bottom horizontal conductive access lines. The top horizontal conductive access line and the bottom horizontal conductive access line together directly electrically couple multiple top and bottom gates of different horizontal transistors in the same memory cell layer. The silicon nitride extends horizontally from the capacitor side of the top gate in the lower memory cell layer, through the silicon dioxide of the insulating layer between the upper and lower memory cell layers, to the capacitor side of the bottom gate in the upper memory cell layer. The silicon nitride in both the upper and lower memory cell layers has a laterally outer linear straight surface in a vertical cross-section that passes through and extends horizontally along the axis. This laterally outer linear straight surface is one of the following: vertical, at an angle not exceeding 40° away from the capacitor side, or at an angle not exceeding 30° towards the capacitor side. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of a DRAM memory array and peripheral circuit system based on the prior art and embodiments of the present invention.

[0009] Figure 2 yes Figure 1 A magnified view of a portion of it.

[0010] Figure 3 and 4 This is a schematic cross-sectional view of a portion of a circuit system according to an embodiment of the present invention.

[0011] Figures 5 to 27 It is in the process according to some embodiments of the present invention Figure 3 and 4 Sequential cross-sections and / or enlarged views of the construction or its parts, alternatives and / or additional embodiments thereof. Detailed Implementation

[0012] Embodiments of the present invention cover memory circuit systems (e.g., DRAM) having vertically alternating layers of insulating material and layers of memory cells, wherein the memory cells individually include capacitors and horizontally oriented transistors. Embodiments of the present invention also cover methods for forming such memory circuit systems. Reference is made first to... Figures 1 to 27 Describe the example method implementation.

[0013] Figure 1 and 2 Examples of DRAM circuit systems, prior art, and schematic diagrams according to embodiments of the present invention are shown in the figure. Figure 2 An example memory cell MC is shown, comprising a transistor T and a capacitor C. One electrode of capacitor C is directly electrically coupled to a suitable potential (e.g., ground), and the other electrode of capacitor C is in contact with or includes one of the source / drain regions of transistor T. The other source / drain region of transistor T is directly electrically coupled to digital line / sensor line 130 or 131 (also individually designated DL). The gate of transistor T is directly electrically coupled to (e.g., including a portion thereof) the word line / access line WL. Figure 1 Digital lines 130 and 131 are shown extending from one of the opposite sides 100 and 200 of the memory array region 10 into a peripheral circuitry system region 113 adjacent to the memory array region 10. Digital lines 130 and 131 are individually and directly electrically coupled to sense amplifiers SA on the opposite sides 100 and 200 of the array region 10 within the peripheral circuitry system region 113. The sense amplifiers SA may be located only on one side or entirely above or below the memory array region 10. As described herein... Figure 3 The non-schematic structural embodiment shown in the figure has horizontally extending word lines / access lines and vertically extending digital lines / sensor lines.

[0014] refer to Figure 3 and 4 The example substrate construction 8 in the process includes an array or array region 10 fabricated relative to a base substrate 11. The substrate 11 may include any or more of conductive / conductive / conductive, semiconductive / semiconductor / semiconductive, and insulating / insulator / insulatory (i.e., electrically insulating herein) materials. The materials may be... Figure 3 and 4The material depicted may be adjacent to, vertically inward, or vertically outward. For example, other partially or wholly manufactured components of the integrated circuit system may be disposed somewhere above, around, or inside the substrate 11. Control and / or other peripheral circuitry systems for operating components within the memory array may also be manufactured and may or may not be wholly or partially within the memory array or subarray. Furthermore, multiple subarrays may be manufactured and operated independently, in series, or otherwise relative to each other. As used herein, "subarray" may also be considered an array. Example configuration 8 includes a semiconductor substrate 12 (e.g., monocrystalline silicon 14) having an insulating material 24 (e.g., silicon dioxide) thereon.

[0015] Structure 8 has been formed directly above substrate 11 comprising silicon material 14 (e.g., elemental single crystal, epitaxial, or polycrystalline silicon, which may contain one or more additional elements) and silicon-germanium material 19 (e.g., Si). 1-x Ge x And it may contain one or more additional elements) of vertically alternating layers (e.g., in a vertical stack). An example hard mask 91 (e.g., silicon dioxide) is on top of construction 8. In the finished memory circuit system construction, and in one embodiment, the memory cell (not shown) of the memory circuit system individually includes a horizontal transistor (not shown) that includes a portion of silicon material 14 and has a top gate (not shown), a bottom gate (not shown), a channel material including silicon material 14 between the top and bottom gates, a capacitor side (e.g., 80), and a digital line side (e.g., 90). Such a memory cell will include a capacitor (not shown) on the capacitor side and a digital line (not shown) on the digital line side. The horizontal transistor and digital line portions will be along axis 35 (for clarity, Figure 3 (Only four are specified in the text) are horizontally spaced relative to each other. In one embodiment, and as shown, a horizontally elongated groove 74 has been formed through the construction 8 on the digital line side 90.

[0016] refer to Figure 5 The horizontal portion 13 of the layer including silicon-germanium material 19 has been removed from the digital line side 90 (e.g., by trench 74; e.g., by isotropic etching, which may be selective or partially non-selective relative to silicon material 14).

[0017] refer to Figure 6 and 7 And in Figure 5 After removal, the horizontal portion 21 of the silicon material layer 14 has been vertically thinned (e.g., by etching) from the digital line side 90 to form thinned portions 31 of the silicon material 14 in individual cells of the silicon material layer 14. The thinned portions 31 extend from the digital line side 90 to the capacitor side 80. Vertical thinning occurs in a vertical cross-section that passes through and extends horizontally along the axis 35 (e.g., ...). Figure 6 Above (e.g., 75a) and below (e.g., 75b) the thinned portion 31 on the capacitor side 80 in this cross-section, a linear straight surface 75* of silicon material 14 is formed (* is used as a suffix to encompass all such identically numbered structures or portions thereof that may or may not have other suffixes). Those skilled in the art can select various etching chemicals to achieve the various results described in this document. For example, and by way of example only, those skilled in the art will understand that silicon can be wet- or dry-etched using suitable fluorinated precursors. In one embodiment, silicon material 14 is vertically thinned using dry etching with an etching chemical comprising fluorinated precursors (e.g., fluorocarbons such as CF4, C2F6, C3F8, etc., hydrofluorocarbons such as H3CF, H2CF2, H2C2F4, etc., and F2), and may or may not contain one or more other non-fluorinated precursors. The linear straight surface 75* is one of the following: vertical, at an angle of no more than 40° away from the capacitor side 80, or at an angle of no more than 30° toward the capacitor side 80.

[0018] In one embodiment, the linear straight surface is vertical, such as... Figure 6 and 7 As shown in the image. Figure 8 and 9 Examples of alternative embodiments, 8c and 8d, are shown respectively. Where appropriate, similar figures from the embodiments described above have been used, with some construction differences indicated by the suffix "c" or "d," respectively. In one embodiment, the linear straight surface 75* is at an angle of no more than 40° from the vertical away from the capacitor side 80 (…). Figure 8 In one embodiment, the angle is no more than 25°; in another embodiment, no more than 10°; and in yet another embodiment, no more than 5° (15° is shown). In one embodiment, the linear straight surface 75* faces the capacitor side 80 at an angle of no more than 30° to the vertical. Figure 9 In one embodiment, the angle is no more than 20°; in another embodiment, no more than 10°; and in yet another embodiment, no more than 5° (10° is shown). Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0019] refer to Figure 10 and 11The vertically adjacent thinned portions 31 (with no other thinned portions between them) can be considered to have a space 81 between them, this space 81 having sides 82, a top 83, and a bottom 84. In one embodiment and as shown, the sides 82, top 83, and bottom 84 of the space 81 are padded with an insulating material 40 (e.g., silicon nitride) adjacent (e.g., directly abutting) to a linear straight surface 75b extending downward from the upper portion of the vertically adjacent thinned portion 31 and adjacent (e.g., directly abutting) to a linear straight surface 75a extending upward from the lower portion of the vertically adjacent thinned portion 31. The insulating material 40 may be conformally deposited within the trench 74 and the space 81, and subsequently removed from the trench 74 (e.g., by anisotropic etching), as shown. In some embodiments, surface 75a is referred to as upper linear straight surface 75a, and surface 75b is referred to as lower linear straight surface 75b.

[0020] refer to Figure 12 and 13 The finished memory circuit system will include vertically alternating memory cell layers 22* comprising silicon material 14 and insulating layers 20. In one embodiment, and as shown, the insulating material 24 of the insulating layer 20 has been formed in the remainder of space 81 after padding in the sides 82, top 83, and bottom 84 of space 81. In this embodiment, the insulating material 24 and the insulating material 40 have different compositions relative to each other. The insulating material 24 may be conformally deposited in trench 74 and the remainder of space 81, and subsequently removed from trench 74 (e.g., by anisotropic etching), as shown.

[0021] refer to Figures 14 to 16 The gate insulator 32 (e.g., silicon dioxide, hafnium oxide, silicon nitride, etc.) and gate 30* of the horizontal transistor have been formed, wherein gate 30* includes a top gate 30t and a bottom gate 30b (e.g., after the formation of the thinned portion 31). In one embodiment, the top gate 30t is part of one of a plurality of top horizontal conductive access lines WLt, and the bottom gate 30b is part of one of a plurality of bottom horizontal conductive access lines WLb, wherein a top horizontal conductive access line and a bottom horizontal conductive access line together directly electrically couple multiple top and bottom gates of different horizontal transistors formed in the same memory cell level 22*. By way of example only, selective etchback can be performed relative to silicon material 14, gate insulator 32, and insulating material 24. Figure 12 and 13An insulating material 40 is used to form the top gate 30t and the bottom gate 30b. Afterwards, conductive materials for the top and bottom gates can be deposited into the voids left by etching back the insulating material 40, and then this conductive material is etched back to create the outlines of the top gate 30t and the bottom gate 30b, as shown. Next, an insulating material 86 (e.g., silicon nitride) can be deposited to fill the remaining volume of the voids on the digital line side 90 of the top gate 30t and the bottom gate 30b, padding but not filling the trench 74. Afterwards, more insulating material 24 can be deposited to fill the remaining volume of the trench 74, as shown. Subsequently, a horizontally elongated trench 87 has been formed on the capacitor side 80 through the configuration 8. The gate insulator 32 may be formed prior to the formation of the insulating material 40 (not shown), by oxidation (when this includes insulating oxide) of the exposed surface of the thinned portion 31, whenever this is done, and / or by depositing this into the void space described above and then immediately forming the conductive material of the gate 30* therein.

[0022] In one embodiment and as shown, the length L1 of the upper linear straight surface 75a and the length L2 of the lower linear straight surface 75b (L1 and L2 may be equal or unequal) are individually greater than the vertical thicknesses T1 and T2 of each of the top gate 30t and the bottom gate 30b (which may be equal or unequal). In any case, in one embodiment and as shown, the upper linear straight surface 75a extends above the uppermost surface 88 of the top gate 30t adjacent to the upper linear straight surface 75a, and the lower linear straight surface 75b extends below the lowermost surface 89 of the bottom gate 30b adjacent to the lower linear straight surface 75b.

[0023] refer to Figure 17 Through trench 87, the remaining silicon-germanium material 19 (no longer shown) has been removed (e.g., by selective etching relative to silicon material 14) and replaced by insulating material 86 and insulating material 24.

[0024] refer to Figure 18 Through trench 87, silicon material 14 has been removed as shown (e.g., by etching with tetramethylammonium hydroxide) to leave a suitable portion of silicon material 14 extending beyond the capacitor side 80 of the top gate 30t and bottom gate 30b, as shown. This is followed by conductive doping of the silicon material 14 through trench 87 (e.g., by gas diffusion doping) to form the first source / drain region 23 on the capacitor side of the horizontal transistor being formed.

[0025] refer to Figure 19The conductive material (e.g., a conductive metal material) of the first capacitor electrode 33 (e.g., a storage node electrode) has been conformally deposited within the trench 87 and on its surface. This conductive material has then been removed (e.g., by anisotropic etching) to expose the ends (not shown) of the insulating material 24 and insulating material 86 exposed to the trench 87. This is followed by selective etching of the insulating material 24 and insulating material 86 (both not shown) to leave the first capacitor electrode 33, as illustrated.

[0026] refer to Figure 20 A capacitor C is formed in trench 87 by forming a capacitor insulator 36 (e.g., dielectric or ferroelectric) and a second capacitor electrode 34 (e.g., comprising a conductive metal material 70 and conductive doped polysilicon 71). In one example of multiple capacitors C, the second capacitor electrodes 34 are directly electrically coupled to each other. In another example, the first capacitor electrode 33 is directly coupled to the first source / drain region 23.

[0027] refer to Figures 21 to 25 The insulating material 24 has been removed from trench 74 (not shown), and the insulating material 86 has been etched back to expose the silicon material 14 on the digital line side 90. Following this, the silicon material 14 is conductively doped through trench 74 (e.g., by gas diffusion doping) to form a second source / drain region 26 on the digital line side, wherein channel regions 28, 14 are horizontally positioned between the first source / drain region 23 and the second source / drain region 26, thus forming a horizontal transistor T. In the common memory cell hierarchy 22*... Figure 21 Regions 23, 26 and 28, 14, located on or outside the plane of the page, adjacent to memory cells MC at different horizontal levels, can be isolated from each other by an insulating material (not shown). After forming the second source / drain region 26, digital lines DL are formed in the trench 74 to be directly electrically coupled to the individual second source / drain regions 26, thus forming a memory cell MC comprising one of the horizontal transistors T and one of the capacitors C. Subsequently, an example insulating material 62 (e.g., silicon dioxide and / or silicon nitride) is formed in the trench 74 and between the adjacent digital lines DL. The capacitors C and the digital lines DL can be formed relative to each other in any order.

[0028] Figure 26 and 27 The examples show the constructed 8c and 8d respectively, which may be derived from... Figure 8 and 9 The subsequent processing of structures 8c and 8d in the present invention, or in other ways and independently of the methods in the structural embodiments, may be used. Any other properties or aspects as shown and / or described herein with respect to other embodiments may be used.

[0029] Alternative embodiments may be constructed from the method embodiments described above or otherwise. In any case, embodiments of the invention cover circuit systems independent of manufacturing methods. However, such arrays of circuit systems may have any properties as described herein in the method embodiments. Similarly, the method embodiments described above may be incorporated into, formed, and / or have any properties described with respect to the device embodiments.

[0030] In one embodiment, the memory circuitry (e.g., 8, 8c, 8d) comprises vertically alternating insulating layers (e.g., 20) and memory cell layers (e.g., 22*). Memory cells (e.g., MC) are located within the memory cell layers and individually include a horizontal transistor (e.g., T), a capacitor (e.g., C) on the capacitor side (e.g., 80) of the horizontal transistor, and a portion of a digital line (e.g., DL) on the digital line side (e.g., 90) of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis (e.g., 35). The horizontal transistor has a gate (e.g., 30*) comprising a top gate (e.g., 30t; for example, a portion of one of a plurality of top horizontal conductive access lines [e.g., WLt]) and a bottom gate (e.g., 30b; for example, a portion of one of a plurality of bottom horizontal conductive access lines [e.g., WLb]), with a channel material (e.g., 28, 14) between the top and bottom gates. The vertically adjacent cells in a memory cell hierarchy include the upper memory cell hierarchy (e.g., Figures 25 to 27 22U in the middle) and the lower memory cell level (e.g., Figures 25 to 27 22L in the middle). An insulating material (e.g., 40) extends horizontally from beside the capacitor side of the top gate in the lower memory cell layer, through the insulating layer between the upper and lower memory cell layers, to beside the capacitor side of the bottom gate in the upper memory cell layer. The insulating material in the upper and lower memory cell layers has a vertical cross-section (e.g., ...) that extends horizontally through and along the axis. Figure 21 , 25 A transversely linear straight surface (e.g., a vertical cross-section of 26 or 27) has an outer linear surface in the transverse direction. Figures 25 to 27 (85*). The transverse outer linear straight surface is one of the following: vertical (e.g., construction 8), at an angle of no more than 40° to the vertical toward the capacitor side (e.g., construction 8c), or at an angle of no more than 30° to the vertical away from the capacitor side (e.g., construction 8d).

[0031] In one embodiment, the insulating layer between the upper memory cell layer and the lower memory cell layer primarily comprises an insulating material (e.g., 24; e.g., silicon dioxide), wherein the insulating material travels through the insulating material, and wherein the insulating material (e.g., silicon nitride) and the insulating material have different compositions relative to each other.

[0032] In one embodiment, the lengths of the lateral outer linear straight surfaces in the upper memory cell level (e.g., L1) and the lower memory cell level (e.g., L2) are individually greater than the vertical thicknesses of each of the top and bottom gates (e.g., T1 and T2, respectively). In one embodiment, the lateral outer linear straight surface (e.g., 85b) in the upper memory cell level extends above the uppermost surface (e.g., 92) of the bottom gate in the upper memory cell level, and the lateral outer linear straight surface (e.g., 85a) in the lower memory cell level extends below the lowermost surface (e.g., 93) of the top gate in the lower memory cell level.

[0033] In existing methods, by Figure 6 and 7 The example etching shown will form silicon material surfaces 75a and 75b that bend away from the capacitor side 80°. This will cause the corresponding silicon nitride surfaces 85a and 85b to also bend in the same way. This tends to be used in... Figure 18 The etch stop point of the silicon material 14 during processing can be determined or desired to be variable, for example, depending on the depth of a given memory cell level 22* in the fabrication. This will result in different lengths of the source / drain regions 23 on different capacitor sides at different depths in the fabrication, which is highly undesirable. The formation of silicon material surfaces 75a and 75b as described herein can reduce or eliminate such problems.

[0034] The above processing or construction can be considered relative to a single stack or single layer of such components formed above or as part of an underlying substrate, or an array of components therein (though a single stack / layer may have multiple levels). Control circuitry and / or other peripheral circuitry for operating or accessing such components in the array may also be formed anywhere as part of the finished construction, and in some embodiments, may be below the array (e.g., under-array CMOS). In any case, one or more additional such stacks / layers may be disposed or fabricated above and / or below the stacks / layers shown in the figures or described above. Furthermore, arrays of components may be identical or different relative to each other in different stacks / layers, and different stacks / layers may have the same or different thicknesses relative to each other. Intermediate structures (e.g., additional circuitry and / or dielectric layers) may be disposed between vertically adjacent stacks / layers. Furthermore, different stacks / layers may be electrically coupled relative to each other. Multiple stacks / layers may be fabricated individually and sequentially (e.g., one on top of another), or two or more stacks / layers may be fabricated substantially simultaneously. The assemblies and structures discussed above can be used in integrated circuits and incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and special-purpose modules, and can include multi-layered, multi-chip modules. Electronic systems can be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, mobile phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0035] In this document, unless otherwise indicated, “vertical,” “higher,” “up,” “down,” “top,” “at the top of,” “bottom,” “above,” “below,” “under,” “upward,” and “downward” generally refer to the vertical direction. “Horizontal” means along the general direction of the substrate surface (i.e., within 10 degrees) and relative to the direction in which the substrate is handled during manufacturing, and vertical is a direction generally orthogonal to the horizontal. “Completely horizontal” means along the direction of the substrate surface (i.e., without an angle to the substrate surface) and relative to the direction in which the substrate is handled during manufacturing, as shown in the figures (if present) herein. Furthermore, “vertical” and “horizontal” as used herein are directions that are generally perpendicular to each other during manufacturing and / or in the finished product construction and are independent of the substrate's orientation in three-dimensional space. Additionally, “vertically extending” and “vertically extending” refer to directions that are at least 45° angularly separated from “completely horizontal.” Furthermore, for field-effect transistors, "vertically extended," "vertically extended," "horizontally extended," "horizontally extended," and the like refer to the orientation of the channel length of the transistor along which the reference current flows between the source and drain regions during operation. For bipolar junction transistors, "vertically extended," "vertically extended," "horizontally extended," and "horizontally extended," and the like refer to the orientation of the base length along which the reference current flows between the emitter and collector during operation. In some embodiments, any vertically extended component, feature, and / or region extends vertically or within a vertical 10°.

[0036] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap between the two stated areas / materials / components relative to each other (i.e., horizontally). Additionally, using "above" without the preceding "direct" only requires that a portion of the stated area / material / component above another portion of the stated area / material / component is vertically located outside said other portion (i.e., independent of whether the two stated areas / materials / components have any lateral overlap). Similarly, using "below" without the preceding "direct" and "under" only requires that a portion of the stated area / material / component below / under another portion of the stated area / material / component is vertically inside said other portion (i.e., regardless of whether the two stated areas / materials / components have any lateral overlap).

[0037] Any of the materials, regions, and structures described herein may be homogeneous or heterogeneous, and in any event, may be continuous or discontinuous over any material on which any of the materials, regions, and structures are applied. Where one or more example components are provided for any material, the material may include, be substantially composed of, or be composed of such one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable existing or future-developed technique, among which atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation are examples.

[0038] Additionally, “thickness” itself (without a preceding directional adjective) is defined as the average straight-line distance through a given material or region perpendicular to the nearest surface of adjacent materials or regions with different compositions. Furthermore, the various materials or regions described herein may have substantially constant or variable thicknesses. If a variable thickness is present, then unless otherwise indicated, the thickness refers to the average thickness, and due to the variable thickness, this material or region will have a minimum thickness and a maximum thickness. As used herein, “different compositions” only requires that the portions of two stated materials or regions that may be in direct contact with each other are chemically and / or physically different (e.g., if such materials or regions are not homogeneous). If two stated materials or regions are not in direct contact with each other, then “different compositions” only requires that the portions of two stated materials or regions that are closest to each other are chemically and / or physically different (if this material or region is not homogeneous). In this document, a stated material, region, or structure is “in direct contact” with each other when there is at least some physical touch contact between them. In contrast, the words “above,” “on,” “adjacent,” “along,” and “against” without the prefix “directly” encompass “direct contact” and constructions in which the intermediate materials, areas, or structures result in no physical contact between the stated materials, areas, or structures relative to each other.

[0039] Here, if current can flow continuously from one zone-material-component to another during normal operation, and this flow is primarily achieved through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated, then the zone-material-components are “electrically coupled” relative to each other. Another electronic component can be electrically coupled between and to a zone-material-component. In contrast, when zone-material-components are referred to as “directly electrically coupled,” there are no intermediate electronic components (e.g., no diodes, transistors, resistors, transducers, switches, fuses, etc.) between the directly electrically coupled zone-material-components.

[0040] Any use of “row” and “column” in this document is for the convenience of distinguishing one series or orientation of features from another series or orientation of features and along which components have been or may be formed. “Row” and “column” are used synonymously with respect to any series of areas, components, and / or features unrelated to function. In any case, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, and columns may be as well. Furthermore, rows and columns may intersect each other at 90° or at one or more other angles (i.e., other than straight angles).

[0041] The composition of any of the conductive / conductor / conductive materials mentioned herein may be a conductive metallic material and / or a conductively doped semiconducting / semiconductor / semiconducting material. "Metallic material" means any elemental metal, any mixture or alloy of two or more elemental metals, and any one or more metallic compounds or combinations thereof.

[0042] In this document, any use of "selective" in relation to etching, removal, deposition, forming, and / or formation is an action in which a stated material is acted relative to another stated material at a rate of at least 2:1 by volume. Furthermore, any use of selective deposition, selective growth, or selective formation is for the first 75 angstroms of the deposition, growth, or formation of a material relative to another stated material at a rate of at least 2:1 by volume.

[0043] Unless otherwise stated, the use of "or" in this document covers either or both.

[0044] in conclusion

[0045] In some embodiments, a method for forming a memory circuit system includes forming a vertically alternating layer comprising silicon and silicon-germanium materials directly above a substrate. The silicon material layer includes portions of horizontal transistors in the finished configuration of the memory circuit system. Individual memory cells of the memory circuit system include one of the horizontal transistors, a capacitor on the capacitor side of the horizontal transistor, and portions of digital lines on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portions are horizontally spaced relative to each other along an axis. The horizontal transistor has a gate including a top gate and a bottom gate, and a channel material comprising silicon material is present between the top gate and the bottom gate. The horizontal portion of the layer comprising the silicon-germanium material is removed from the digital line side. After removal, the horizontal portion of the silicon material layer is vertically thinned from the digital line side to form a thinned portion of the silicon material in one of the individual silicon material layers. The thinned portion extends from the digital line side to the capacitor side. The vertical thinning forms a linear straight surface of the silicon material above and below the thinned portion on the capacitor side in a vertical cross-section that passes through and extends horizontally along the axis. The linear straight surface is one of the following: vertical, at an angle of no more than 40° away from the capacitor side, or at an angle of no more than 30° towards the capacitor side.

[0046] In some embodiments, the memory circuitry includes vertically alternating insulating layers and memory cell layers. Each memory cell in a memory cell layer individually includes a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis. The horizontal transistor has a gate, including a top gate and a bottom gate, with a channel material between the top and bottom gates. The vertically adjacent memory cell layers include an upper memory cell layer and a lower memory cell layer. An insulating material extends horizontally from beside the capacitor side of the top gate in the lower memory cell layer through the insulating layer between the upper and lower memory cell layers to beside the capacitor side of the bottom gate in the upper memory cell layer. The insulating material in the upper and lower memory cell layers has a laterally linear straight surface in a vertical cross-section extending horizontally along the axis. The transverse outer linear straight surface is one of the following: vertical, at an angle of no more than 40° to the vertical towards the capacitor side, or at an angle of no more than 30° to the vertical away from the capacitor side.

[0047] In some embodiments, the memory circuitry includes vertically alternating insulating layers and memory cell layers comprising silicon dioxide. Each memory cell in a memory cell layer includes a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis. Vertically adjacent layers in the memory cell hierarchy include an upper memory cell layer and a lower memory cell layer. The horizontal transistor has a gate including a top gate as a portion of one of a plurality of top horizontal conductive access lines and a bottom gate including a portion of one of a plurality of bottom horizontal conductive access lines. A top horizontal conductive access line and a bottom horizontal conductive access line together directly electrically couple multiple top and bottom gates of different horizontal transistors in the same memory cell layer. The silicon nitride extends horizontally from the capacitor side of the top gate in the lower memory cell layer through the silicon dioxide of the insulating layer between the upper and lower memory cell layers to the capacitor side of the bottom gate in the upper memory cell layer. The silicon nitride in both the upper and lower memory cell layers has a laterally outer linear straight surface in a vertical cross-section that passes through and extends horizontally along the axis. This laterally outer linear straight surface is one of the following: vertical, at an angle not exceeding 40° away from the capacitor side, or at an angle not exceeding 30° towards the capacitor side.

[0048] As per regulations, the subject matter disclosed herein has been described in language that is more or less specific regarding structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include exemplary embodiments. Therefore, the claims should be provided with full scope in accordance with their literal wording and should be appropriately interpreted in accordance with the principle of equivalence.

Claims

1. A method for forming a memory circuit system, comprising: A vertically alternating layer comprising silicon and silicon-germanium materials is formed directly above a substrate. The silicon material layer includes portions of horizontal transistors in the finished structure of the memory circuit system. Individual memory cells of the memory circuit system include one of the horizontal transistors, a capacitor on the capacitor side of the horizontal transistor, and portions of digital lines on the digital line side of the horizontal transistor. The capacitor, the horizontal transistor, and the digital line portions are horizontally spaced relative to each other along an axis. The horizontal transistor has a gate, which includes a top gate and a bottom gate, and a channel material comprising the silicon material is formed between the top gate and the bottom gate. Remove the horizontal portion of the layer comprising the silicon-germanium material from the digital line side; and After the removal, the horizontal portion of the silicon material layer is vertically thinned from the digital line side to form a thinned portion of the silicon material in one of the individual silicon material layers. The thinned portion extends from the digital line side to the capacitor side. The vertical thinning forms a linear straight surface of the silicon material above and below the thinned portion on the capacitor side in a vertical cross-section that passes through the axis and extends horizontally along the axis. The linear straight surface is one of the following: vertical, at an angle of no more than 40° away from the capacitor side, or at an angle of no more than 30° towards the capacitor side.

2. The method according to claim 1, wherein the linear straight surface is vertical.

3. The method according to claim 1, wherein the linear straight surface is at an angle of no more than 40° from the vertical to the capacitor side.

4. The method according to claim 1, wherein the linear straight surface is oriented toward the capacitor side at an angle of no more than 30° to the vertical.

5. The method of claim 1, wherein the vertical thinning comprises dry etching using an etching chemical comprising a fluorine-containing precursor.

6. The method of claim 1, further comprising lining the sides, top, and bottom of the space between the vertically adjacent members in the thinned portion with an insulating material, the insulating material being adjacent to the linear straight surface extending downward from the upper portion of the vertically adjacent member in the thinned portion and adjacent to the linear straight surface extending upward from the lower portion of the vertically adjacent member in the thinned portion.

7. The method of claim 6, further comprising forming the insulating material by directly abutting each of the linear straight surfaces.

8. The method of claim 6, wherein the finished structure of the memory circuit system comprises vertically alternating memory cell layers and insulating layers containing the silicon material, and further comprises an insulating material forming the insulating layers in the remainder of the space after the sides, top, and bottom of the space; the insulating material and the insulating material having different compositions relative to each other.

9. The method according to claim 1, wherein: The linear straight surface of the silicon material above the thinned portion is an upper linear straight surface, and the linear straight surface of the silicon material below the thinned portion is a lower linear straight surface; The top gate and the bottom gate are formed after the thinned portion is formed; and The lengths of the upper linear straight surface and the lower linear straight surface are individually greater than the vertical thickness of each of the top gate and the bottom gate.

10. The method according to claim 1, wherein: The linear straight surface of the silicon material above the thinned portion is an upper linear straight surface, and the linear straight surface of the silicon material below the thinned portion is a lower linear straight surface; The top gate and the bottom gate are formed after the thinned portion is formed; and The upper linear straight surface extends above the uppermost surface of the top gate adjacent to the upper linear straight surface; and The lower linear straight surface extends below the lowest surface of the bottom gate adjacent to the lower linear straight surface.

11. The method of claim 10, wherein the length of the upper linear straight surface and the length of the lower linear straight surface are individually greater than the vertical thickness of each of the top gate and the bottom gate.

12. A memory circuit system comprising: Vertically alternating insulation layers and memory cell layers; The memory cells in the memory cell hierarchy individually include a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor; the capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis; the horizontal transistor has a gate, the gate including a top gate and a bottom gate, and a channel material between the top gate and the bottom gate; the vertically adjacent cells in the memory cell hierarchy include an upper memory cell hierarchy and a lower memory cell hierarchy; and An insulating material extending horizontally from the capacitor side of the top gate in the lower memory cell layer through the insulating layer between the upper and lower memory cell layers to the capacitor side of the bottom gate in the upper memory cell layer, wherein the insulating material in the upper and lower memory cell layers has a transversely outer linear straight surface in a vertical cross-section passing through and horizontally extending along the axis; the transversely outer linear straight surface is one of the following: vertical, at an angle not exceeding 40° to the vertical towards the capacitor side, or at an angle not exceeding 30° to the vertical away from the capacitor side.

13. The memory circuit system of claim 12, wherein the lateral outer linear straight surface is vertical.

14. The memory circuit system of claim 12, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 40° to the vertical.

15. The memory circuit system of claim 14, wherein the lateral outer linear straight surface is angled toward the capacitor side at an angle not exceeding 25° to the vertical.

16. The memory circuit system of claim 14, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 10° to the vertical.

17. The memory circuit system of claim 14, wherein the lateral outer linear surface is at an angle of no more than 5° from the vertical to the capacitor side.

18. The memory circuit system of claim 12, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 30° to the vertical.

19. The memory circuit system of claim 18, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 20° to the vertical.

20. The memory circuit system of claim 18, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 10° to the vertical.

21. The memory circuit system of claim 18, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 5° to the vertical.

22. The memory circuit system of claim 12, wherein the insulating layer between the upper memory cell layer and the lower memory cell layer comprises at least primarily an insulating material, wherein the insulating material travels through the insulating material, and the insulating material and the insulating material have different compositions relative to each other.

23. The memory circuit system of claim 12, wherein the length of the lateral outer linear surface in the upper memory cell level and the length of the lateral outer linear surface in the lower memory cell level are individually greater than the vertical thickness of each of the top gate and the bottom gate.

24. The memory circuit system according to claim 12, wherein, The lateral outer linear surface in the upper memory cell hierarchy extends above the uppermost surface of the bottom gate in the upper memory cell hierarchy; and The lateral outer linear straight surface in the lower memory cell hierarchy extends below the lowest surface of the top gate in the lower memory cell hierarchy.

25. The memory circuit system of claim 24, wherein the length of the lateral outer linear surface in the upper memory cell level and the length of the lateral outer linear surface in the lower memory cell level are individually greater than the vertical thickness of each of the top gate and the bottom gate.

26. A memory circuit system comprising: The vertical alternation includes silicon dioxide insulating layers and memory cell layers; The memory cells in the memory cell hierarchy individually include a horizontal transistor, a capacitor on the capacitor side of the horizontal transistor, and a portion of a digital line on the digital line side of the horizontal transistor; the capacitor, the horizontal transistor, and the digital line portion are horizontally spaced relative to each other along an axis; the vertically adjacent cells in the memory cell hierarchy include the upper memory cell hierarchy and the lower memory cell hierarchy; The horizontal transistor has a gate that includes a top gate as part of one of a plurality of top horizontal conductive access lines and a bottom gate as part of one of a plurality of bottom horizontal conductive access lines, wherein the top horizontal conductive access line and the bottom horizontal conductive access line together directly electrically couple multiple top and bottom gates of different horizontal transistors in the same memory cell level. and Silicon nitride, extending horizontally from the capacitor side of the top gate in the lower memory cell layer through the silicon dioxide of the insulating layer between the upper and lower memory cell layers to the capacitor side of the bottom gate in the upper memory cell layer, the silicon nitride in the upper and lower memory cell layers having a laterally outer linear straight surface in a vertical cross-section passing through and horizontally extending along the axis; the laterally outer linear straight surface is one of the following: vertical, at an angle not exceeding 40° away from the capacitor side, or at an angle not exceeding 30° towards the capacitor side.

27. The memory circuit system of claim 26, wherein the lateral outer linear straight surface is vertical.

28. The memory circuit system of claim 26, wherein the lateral outer linear surface is at an angle of no more than 40° from the vertical to the capacitor side.

29. The memory circuit system of claim 26, wherein the lateral outer linear surface is oriented toward the capacitor side at an angle of no more than 30° to the vertical.

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