Semiconductor structure and preparation method thereof, memory, memory system and electronic equipment

Abstract

The invention provides a semiconductor structure and a preparation method thereof, a memory, a memory system and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the technical problem of high production cost of a three-dimensional memory in the prior art. The semiconductor structure includes a stacked structure, a conductive structure, and a conductive plug. The stacked structure includes a core region and a non-core region. The stacked structure comprises a plurality of gate layers which are stacked in the first direction. And the multiple gate layers are distributed at intervals. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion and a gate layer are arranged on the same layer and are in electrical contact. The second portion is in electrical contact with the first portion. The second portion upwardly passes through the stack structure and encloses a plug opening. A conductive plug is located within the plug opening and in electrical contact with the second portion. The semiconductor structure is applied to the three-dimensional memory so as to realize data reading and writing operation.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on March 8, 2022, with application number 202210220730.7 and title "Semiconductor structure and preparation method thereof, memory, storage system and electronic device". Technical Field

[0002] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, a method for fabricating a semiconductor structure, a three-dimensional memory, a storage system, and an electronic device. Background Technology

[0003] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0004] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0005] In the existing technology, it is difficult and the process is complicated to electrically connect the gate layer (i.e., word line) to the word line contacts, which increases the production cost of three-dimensional memory. Summary of the Invention

[0006] The embodiments of this disclosure provide a semiconductor structure, a method for fabricating the semiconductor structure, a three-dimensional memory, a storage system, and an electronic device, aiming to solve the problem of high production costs of three-dimensional memories in the prior art.

[0007] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a semiconductor structure is provided. The semiconductor structure includes a stacked structure, a conductive structure, and a conductive plug. The stacked structure includes a core region and a non-core region. The stacked structure includes multiple gate layers stacked along a first direction. The multiple gate layers are spaced apart. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion is disposed on the same layer as a gate layer and is in electrical contact with it. The second portion is in electrical contact with the first portion. The second portion extends upward through the stacked structure and encloses a plug opening. The conductive plug is located within the plug opening and is in electrical contact with the second portion.

[0008] In some embodiments of the semiconductor structure provided in this disclosure, by setting a first part of the conductive structure to be disposed on the same layer as and electrically contacting a gate layer, a second part to be electrically contacting the first part, and the second part extending upward through the stacked structure, the conductive structure can be embedded within the stacked structure and electrically contacting a gate layer.

[0009] In this way, electrical connections between the gate layer and other components (such as word line contacts formed later) can be achieved through conductive structures, eliminating the need for stepped structures and avoiding the problem of misalignment between word line contact holes and stepped structures. Electrical contact between the conductive structure and the gate layer is achieved through the SCT (Self-align Contact) architecture, which simplifies the manufacturing process and reduces the production cost of semiconductor structures.

[0010] Furthermore, the second part encloses a plug opening, and a conductive plug is disposed within the plug opening and electrically contacted with the second part. This allows the subsequently formed word line contacts to achieve electrical connection with the gate layer through at least one of the conductive plug and the conductive structure. That is, the word line contacts can be electrically contacted with the end face of the second part of the conductive structure away from the first part, or with the surface of the conductive plug away from the stacked structure, or both the end face of the second part of the conductive structure away from the first part and the surface of the conductive plug away from the stacked structure can be electrically contacted.

[0011] This design increases the contact area between the word line contacts and the gate layer during electrical connection, which means it increases the landing window for electrical connection between the word line contacts and the gate layer. This improves the ease of electrical connection between the word line contacts and the gate layer, simplifies the manufacturing process, reduces the production cost of semiconductor structures, and thus reduces the production cost of 3D memory.

[0012] On the other hand, increasing the contact area between the word line contacts and the conductive structure during electrical connection can also reduce the resistance between the word line contacts and the gate layer, thereby improving the reliability of electrical signal transmission.

[0013] On the other hand, word line contacts achieve electrical connection with the gate layer through conductive plugs and conductive structures, eliminating the need for additional conductive structures between the word line contacts and conductive plugs, thus simplifying the semiconductor structure and further reducing its cost.

[0014] On the other hand, by placing the conductive plug inside the plug opening, the conductive plug can be embedded in the conductive structure without the need for additional interlayer structures to accommodate the conductive plug. This allows the SCT architecture to be combined with the conductive plug, further simplifying the structure of the semiconductor structure and reducing its cost.

[0015] In some embodiments, the semiconductor structure further includes a first dielectric layer. The first dielectric layer is located on top of the stacked structure. The first dielectric layer has a first opening, and the end of the second portion away from the first portion and the conductive plug are located within the first opening.

[0016] In some embodiments, the first dielectric layer further includes a second opening. The semiconductor structure also includes a channel structure and a channel contact. The channel structure is located in the core region and extends through the stacked structure. The channel contact is located within the second opening and is in electrical contact with the end of the channel structure near the first dielectric layer.

[0017] In some embodiments, the conductive plug and the channel contact are in the same layer and made of the same material.

[0018] In some embodiments, the second portion includes an extension. A first end of the extension is in electrical contact with the first portion, and a second end of the extension encloses a plug opening.

[0019] In some embodiments, the second portion further includes a contact portion. The contact portion is located within an opening formed at the first end of the extension, and the contact portion is in electrical contact with the first portion and the extension.

[0020] In some embodiments, the area of ​​the plug opening is larger than the area of ​​the opening enclosed by the first end of the extension, and the area of ​​the first portion projected onto the reference plane is larger than the area of ​​the opening enclosed by the first end of the extension. The reference plane is parallel to the multilayer gate layer.

[0021] In some embodiments, the semiconductor structure further includes an electrical isolation layer. The electrical isolation layer is located between the second portion and the stacked structure.

[0022] In some embodiments, the conductive structure and the conductive plug surround a receiving cavity. The semiconductor structure also includes an insulating material. The insulating material fills the receiving cavity.

[0023] In some embodiments, the receiving cavity has an air gap.

[0024] In some embodiments, the stacked structure includes a memory stack structure. Multiple gate layers are located within the memory stack structure. The memory stack structure also includes multiple gate insulating layers, which are alternately stacked with the gate layers. The channel structure includes a memory channel structure. The memory channel structure extends through the memory stack structure. The memory channel structure includes at least a memory functional layer and a channel layer sequentially distal from the multiple gate layers.

[0025] In some embodiments, the stack structure further includes a selection stack structure. The selection stack structure is located above the storage stack structure. The selection stack structure includes an insulating dielectric layer, a first conductive layer, and a second dielectric layer disposed sequentially. The insulating dielectric layer extends from a core region to a non-core region, and the first conductive layer and the second dielectric layer are located in the core region. The channel structure further includes a selection channel structure. The selection channel structure penetrates the selection stack structure and is in electrical contact with an end of the storage channel structure along a first direction. The selection channel structure includes at least an insulating layer and a second conductive layer disposed sequentially away from the first conductive layer.

[0026] In some embodiments, the semiconductor structure further includes a semiconductor structure layer. The semiconductor structure layer is located on the side of the stacked structure away from the first dielectric layer.

[0027] In some embodiments, the semiconductor structure further includes multiple virtual channel structures. These virtual channel structures are located in a non-core region and extend throughout the stacked structure.

[0028] On the other hand, a method for fabricating a semiconductor structure is provided. The method includes forming an initial stacked structure on one side of a substrate. The initial stacked structure has a core region and a non-core region. The initial stacked structure includes multiple gate sacrificial layers stacked along a first direction. The multiple gate sacrificial layers are spaced apart. The first direction is perpendicular to the substrate. A conductive structure is formed. The conductive structure is located in the non-core region. The conductive structure includes a first portion and a second portion. The first portion is disposed on the same layer as and in contact with a gate sacrificial layer. The second portion is electrically contacted with the first portion. The second portion extends upward through the initial stacked structure and encloses a plug opening. A conductive plug is formed. The conductive plug is located within the plug opening and is electrically contacted with the second portion.

[0029] In some embodiments, prior to the step of forming the conductive structure, a first dielectric film is further formed. The first dielectric film is located on an initial stack. The step of forming the conductive structure includes forming a first contact hole in a non-core region, the first contact hole penetrating the first dielectric film and exposing a target gate sacrificial layer. The target gate sacrificial layer is one of a plurality of gate sacrificial layers. A portion of the target gate sacrificial layer is removed via the first contact hole to form an epitaxial contact hole. A first portion is formed within the epitaxial contact hole. A second portion is formed within the first contact hole, the second portion being in electrical contact with the first portion.

[0030] In some embodiments, the initial stacked structure further includes multiple gate insulating layers, with gate insulating layers and gate sacrificial layers alternately stacked. The step of forming a first contact hole in the non-core region includes forming an initial contact hole in the non-core region. The initial contact hole penetrates the first dielectric film and exposes the target gate insulating layer. The target gate insulating layer is one of a plurality of gate insulating layers. An electrical isolation film is formed within the initial contact hole. The bottom wall of the electrical isolation film and a portion of the target gate insulating layer are removed to form an electrical isolation layer, and a first contact hole exposing the target gate sacrificial layer is formed inside the electrical isolation layer.

[0031] In some embodiments, after the step of forming the second portion within the first contact hole, the second portion is further filled with insulating material.

[0032] In some embodiments, the steps of forming a second portion within a first contact hole and filling the second portion with an insulating material include forming a first conductive film. The first conductive film includes a first sub-film and a second sub-film, the first sub-film covering a first dielectric film, and the second sub-film covering the sidewalls of the first contact hole and the first portion. An insulating material is deposited. The insulating material fills the cavity defined by the second sub-film and covers the first sub-film. The insulating material is etched down to the first sub-film to remove a portion of the insulating material within the cavity defined by the second sub-film and the insulating material covering the first sub-film. The ends of the first sub-film and the second sub-film extending beyond the surface of the first dielectric film away from the substrate are removed to form the second portion.

[0033] In some embodiments, after the step of forming the first dielectric film and before the step of forming the first contact hole in the non-core region, a stop layer is further formed. The stop layer covers the first dielectric film. The step of forming the first contact hole in the non-core region includes forming a first contact hole in the non-core region that penetrates the stop layer and the first dielectric film and exposes the target gate sacrificial layer. The steps of forming a second portion within the first contact hole and filling the second portion with an insulating material include forming a second conductive film, the second conductive film including a third sub-film and a fourth sub-film. The third sub-film covers the stop layer, and the fourth sub-film covers the sidewalls of the first contact hole and the first portion. The third sub-film is removed to expose the stop layer. An insulating material is deposited that fills the cavity defined by the fourth sub-film and covers the stop layer. The insulating material is etched down to at least a portion of the stop layer to remove a portion of the insulating material within the cavity defined by the fourth sub-film and the insulating material covering the stop layer. The remaining portion of the stop layer is removed to expose the first dielectric film. The end of the fourth sub-film extending beyond the surface of the first dielectric film away from the substrate is removed to form the second portion.

[0034] In some embodiments, the step of forming a stop layer includes forming a first stop layer located on the side of the first dielectric film away from the initial stacked structure. The step of forming a first protective layer located on the side of the first stop layer away from the first dielectric film. The step of etching an insulating material to at least a portion of the stop layer includes etching the insulating material and the first protective layer to the first stop layer. The step of removing the remaining portion of the stop layer includes removing the first stop layer.

[0035] In some embodiments, the semiconductor structure further includes a channel structure. The channel structure is located in the core region and extends through the initial stacked structure. The method of fabricating the semiconductor structure further includes forming a second opening on the first dielectric film to fabricate a first dielectric layer. The second opening exposes the end of the channel structure away from the substrate. The step of forming a conductive plug also includes forming a channel contact that is electrically in contact with the end of the channel structure near the first dielectric layer.

[0036] In some embodiments, the step of forming a second opening on the first dielectric film includes forming a mask on the side of the first dielectric film away from the initial stacked structure, the mask having etching openings. The second opening is formed on the first dielectric film using the etching openings of the mask.

[0037] In some embodiments, the step of forming a mask on the side of the first dielectric film away from the initial stacked structure includes forming a hard mask that covers the first dielectric film; forming a photoresist film that covers the hard mask; and forming an etching opening through the photoresist film and the hard mask.

[0038] In some embodiments, after forming the conductive plug, a gate line slot is further formed throughout the initial stacked structure. A gate line slot divides the core of an initial stacked structure into two initial memory blocks. Through the gate line slot, a gate sacrificial layer is replaced with a gate layer to form the stacked structure and memory blocks. The gate layer is in electrical contact with the first portion.

[0039] In some embodiments, prior to the step of forming the conductive structure, a gate line slot is further formed throughout the initial stacked structure. A gate line slot divides the core of an initial stacked structure into two initial memory blocks. Through the gate line slot, the gate sacrificial layer located in the core region is replaced with a first gate layer. After the step of forming the conductive plug, through the gate line slot, a portion of the gate sacrificial layer disposed on the same layer as and in contact with the first portion is replaced with a second gate layer to form the stacked structure and the memory blocks. The second gate layer is electrically contacted with the first gate layer and the first portion.

[0040] In another aspect, a three-dimensional memory is provided. The three-dimensional memory includes a semiconductor structure as described in some of the embodiments above, and peripheral devices electrically connected to the semiconductor structure.

[0041] On the other hand, a storage system is provided, including the three-dimensional memory as described above, and a controller coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0042] On the other hand, an electronic device is provided, including the storage system described above.

[0043] It is understood that the beneficial effects that the semiconductor structure fabrication method, three-dimensional memory, storage system and electronic device provided in the above embodiments of this disclosure can achieve can be referred to the beneficial effects of the semiconductor structure above, and will not be repeated here. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0045] Figure 1 This is a three-dimensional structural diagram of a three-dimensional memory according to some embodiments; Figure 2 A cross-sectional view of a three-dimensional memory according to some embodiments; Figure 3 for Figure 1 A cross-sectional view of a storage cell string in a three-dimensional memory along section line AA'; Figure 4 The equivalent circuit diagram for a string of storage cells; Figure 5 This is a structural diagram of a semiconductor structure according to some embodiments; Figure 6 This is a structural diagram of a semiconductor structure according to some other embodiments; Figure 7 for Figure 5 A cross-sectional structural diagram along the AA direction; Figure 8 for Figure 5 A cross-sectional structural diagram along the BB direction; Figure 9 This is a structural diagram of a conductive structure according to some embodiments; Figure 10 This is a structural diagram of a conductive structure and a conductive plug according to some embodiments; Figure 11 This is a structural diagram of a stacked structure according to some embodiments; Figure 12 This is a structural diagram of a channel structure according to some embodiments; Figure 13 This is a structural diagram of a stacked structure according to some other embodiments; Figure 14 This is a flowchart of the steps for fabricating a semiconductor structure according to some embodiments; Figure 15 This is a structural diagram of an initial stacking structure according to some embodiments; Figure 16 This is a structural diagram of a semiconductor structure according to some other embodiments; Figure 17 This is a structural diagram of a first dielectric film according to some embodiments; Figure 18 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 19 This is a structural diagram of a first contact hole according to some embodiments; Figure 20 This is a structural diagram of the first contact hole according to some other embodiments; Figure 21 This is a structural diagram of the first contact hole according to some other embodiments; Figure 22 This is a structural diagram of the first part according to some embodiments; Figure 23 This is a structural diagram of a conductive structure according to some other embodiments; Figure 24 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 25 This is a structural diagram of the initial contact hole according to some embodiments; Figure 26 This is a structural diagram of an electrically insulating membrane according to some embodiments; Figure 27 This is a diagram showing the filling structure of an insulating material according to some embodiments; Figure 28 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 29 This is a structural diagram of the first conductive film according to some embodiments; Figure 30 This is a diagram showing the filling structure of the insulating material according to some other embodiments; Figure 31 This is a diagram showing the filling structure of an insulating material according to some other embodiments; Figure 32 This is a structural diagram of the stop layer according to some embodiments; Figure 33 This is a structural diagram of the initial contact hole according to some other embodiments; Figure 34 This is a structural diagram of the first contact hole according to some other embodiments; Figure 35 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 36 This is a structural diagram of the second conductive film according to some embodiments; Figure 37 This is a structural diagram of the fourth submembrane according to some embodiments; Figure 38 This is a diagram showing the filling structure of an insulating material according to some other embodiments; Figure 39This is a diagram showing the filling structure of an insulating material according to some other embodiments; Figure 40 This is a diagram showing the filling structure of an insulating material according to some other embodiments; Figure 41 This is a diagram showing the filling structure of an insulating material according to some other embodiments; Figure 42 This is a structural diagram of a channel structure according to some other embodiments; Figure 43 This is a structural diagram of an initial stacking structure according to some other embodiments; Figure 44 This is a structural diagram of the first dielectric layer according to some embodiments; Figure 45 This is a structural diagram of a semiconductor structure according to some other embodiments; Figure 46 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 47 This is a structural diagram of a photomask according to some embodiments; Figure 48 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 49 This is a structural diagram of a photomask according to some other embodiments; Figure 50 This is a structural diagram of a photomask according to some other embodiments; Figure 51 This is a structural diagram of a photomask according to some other embodiments; Figure 52 This is a structural diagram of the fourth sub-membrane according to some other embodiments; Figure 53 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments; Figure 54 This is a structural diagram of the first gate layer according to some embodiments; Figure 55 This is a structural diagram of the first gate layer and the second gate layer according to some embodiments; Figure 56 This is a block diagram of a storage system according to some embodiments; Figure 57 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0046] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0047] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0048] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0049] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0050] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0051] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0052] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0053] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0054] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0055] As used herein, “approximation” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0056] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0057] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0058] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0059] The term "three-dimensional memory" refers to a semiconductor device formed by arrays of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate or source layer and extending in a direction perpendicular to the substrate or source layer. As used herein, the term "vertical / perpendicularly" means nominally perpendicular to the main surface of the substrate or source layer (i.e., the lateral surface).

[0060] Figure 1 This is a three-dimensional structural diagram of a three-dimensional memory provided in some embodiments of this disclosure. Figure 2 This is a cross-sectional view of a three-dimensional memory. Figure 3 for Figure 1 A cross-sectional view of a string of storage cells in a three-dimensional memory along section line AA'. Figure 4 The equivalent circuit diagram for the storage cell string.

[0061] It should be noted that, in Figure 1 and Figure 2 In this design, the three-dimensional memory 10 extends in the XY plane. The first direction X and the second direction Y are, for example, two orthogonal directions in the plane containing the semiconductor structure 200 (e.g., the plane containing the source layer SL). The first direction X is, for example, the extension direction of the word line (WL), and the second direction Y is, for example, the extension direction of the bit line (BL). The third direction Z is perpendicular to the plane containing the semiconductor structure 200, that is, perpendicular to the XY plane.

[0062] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor device (e.g., a three-dimensional memory) is determined relative to the substrate or source layer of the semiconductor device in the third direction Z, when the substrate or source layer is located in the lowest plane of the semiconductor device in the third direction Z. The same concepts are applied throughout this disclosure to describe spatial relationships.

[0063] In order to show the structure of the device more clearly, in Figure 2The image shows a view of the array region CA and a view of the stepped region SS. The view of the array region CA is based on the left coordinate system, and the view of the stepped region SS is based on the left coordinate system. That is, the view of the array region CA shows the cross-sectional structure along the Y direction, and the view of the stepped region SS shows the cross-sectional structure along the X direction.

[0064] See Figure 1 and Figure 2 Some embodiments of this disclosure provide a three-dimensional memory 10. The three-dimensional memory 10 may include a semiconductor structure 200 and peripheral devices 100 coupled to the semiconductor structure 200. The semiconductor structure 200 includes a source layer SL, and the peripheral devices 100 may be disposed on the side away from the source layer SL.

[0065] The source layer SL may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer SL may also include undoped regions.

[0066] Semiconductor structure 200 may include arrayed strings of memory cell transistors (referred to herein as “memory cell strings”, such as NAND memory cell strings) 400. A source layer SL may be coupled to the source ends of multiple memory cell strings 400.

[0067] Specifically, see Figure 3 and Figure 4 The storage cell string 400 may include multiple transistors T, one transistor T (e.g., Figure 4 Transistors T1 to T6 can be configured as a memory cell, and these transistors T are connected together to form a memory cell string. A transistor T (e.g., each transistor T) can be formed by a semiconductor channel 241 and a gate line G surrounding the semiconductor channel 241. The gate line G is configured to control the conduction state of the transistor.

[0068] It should be noted that, Figures 1-4 The number of transistors is only illustrative. The storage cell string of the three-dimensional memory provided in the embodiments of this disclosure may also include other numbers of transistors, such as 4, 16, 32, and 64.

[0069] Furthermore, along the third direction Z, the lowermost gate line among the multiple gate lines G (e.g., the gate line closest to the source layer SL among the multiple gate lines G) is constructed as a source select gate SGS. The source select gate SGS is configured to control the conduction state of transistor T6, thereby controlling the conduction state of the source channel in the memory cell string 400. The uppermost gate line among the multiple gate lines G (e.g., the gate line furthest from the source layer SL among the multiple gate lines G) is constructed as a drain select gate SGD. The drain select gate SGD is configured to control the conduction state of transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string 400. The middle gate line among the multiple gate lines G can be constructed as multiple word lines WL, such as word lines WL0, WL1, WL2, and WL3. By writing different voltages on the word lines WL, data writing, reading, and erasing of each memory cell (e.g., transistor T) in the memory cell string 400 can be completed.

[0070] See also Figure 1 and Figure 2 In some embodiments, the semiconductor structure 200 may further include an array interconnect layer 290. The array interconnect layer 290 may be coupled to the memory cell string 400. The array interconnect layer 290 may include the drain (i.e., bit line BL) of the memory cell string 400, which may be coupled to the semiconductor channel of at least one transistor T in the memory cell string 400.

[0071] The array interconnect layer 290 may include one or more first interlayer insulating layers 292, and may also include a plurality of contacts insulated from each other by these first interlayer insulating layers 292. The contacts may include, for example, bit line contacts BL-CNT coupled to the bit line BL, and drain select gate contacts SGD-CNT coupled to the drain select gate SGD. The array interconnect layer 290 may also include one or more first interconnect conductor layers 291. The first interconnect conductor layer 291 may include a plurality of interconnect lines, such as the bit line BL, and word line interconnect lines WL-CL coupled to the word line WL. The materials of the first interconnect conductor layers 291 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and one or more combinations of metal silicides, or other suitable materials. The material of the first interlayer insulating layer 292 is an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, or other suitable materials.

[0072] Peripheral device 100 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0073] Specifically, in some embodiments, the peripheral device 100 may include a substrate 110, a transistor 120 disposed on the substrate 110, and a peripheral interconnect layer 130 disposed on the substrate 110. The peripheral circuitry may include the transistor 120.

[0074] The substrate 110 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0075] The peripheral interconnect layer 130 is coupled to the transistor 120 to transmit electrical signals between the transistor 120 and the peripheral interconnect layer 130. The peripheral interconnect layer 130 may include one or more second interlayer insulating layers 131, and may also include one or more second interconnect conductor layers 132. Different second interconnect conductor layers 132 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 132 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 131 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0076] The peripheral interconnect layer 130 can be coupled to the array interconnect layer 290, enabling coupling between the semiconductor structure 200 and the peripheral device 100. Specifically, since the peripheral interconnect layer 130 is coupled to the array interconnect layer 290, the peripheral circuits in the peripheral device 100 can be coupled to the memory cell string in the semiconductor structure 200 to achieve the transmission of electrical signals between the peripheral circuits and the memory cell string. In some possible implementations, an bonding interface 500 can be provided between the peripheral interconnect layer 130 and the array interconnect layer 290, through which the peripheral interconnect layer 130 and the array interconnect layer 290 can be bonded and coupled to each other.

[0077] See you again Figure 1 and Figure 2 In some implementations, word line contact holes are typically formed in the stepped region SS, and conductive structures are disposed within the word line contact holes and electrically contact the gate layer (i.e., the word line WL). The word line contacts are electrically contacted with the conductive structures, and the word line connector WL-CL is electrically contacted with the word line contacts, enabling electrical signals to be transmitted between the word line connector WL-CL and the gate layer.

[0078] However, it is not easy to achieve word line contact holes that fall precisely on the stepped structure during the manufacturing process. Underetching or punch-through are common defects that increase the difficulty of electrical contact between the conductive structure and the gate layer, thereby increasing the process complexity of the semiconductor structure 200 and leading to higher production costs for the three-dimensional memory 10.

[0079] In other implementations, a self-aligned contact (SCT) architecture is used to achieve electrical contact between the gate layer and the word line contacts. The SCT architecture does not form a stepped structure; instead, a conductive structure is embedded in the non-core region (i.e., the stepped region SS). This conductive structure leads out the gate layer (i.e., the word line WL) to achieve electrical connection between the gate layer and the word line contacts. The word line connector WL-CL makes electrical contact with the word line contacts, allowing electrical signals to be transmitted between the word line connector WL-CL and the gate layer.

[0080] In some examples, the conductive structure in the SCT architecture is formed from a thicker conductive material (e.g., tungsten). However, the inventors of this disclosure have found that using a single conductive material to form a thicker conductive structure can lead to large stress variations, severely deteriorating the stress state of the wafer (i.e., the substrate) and even causing defects such as wafer cracks.

[0081] In other examples, the conductive structure in the SCT architecture includes a conductive layer and an insulating layer to reduce the stress effects of a single conductive material forming a thicker conductive structure. For example, the insulating layer is located at the center of the conductive layer, which may form a ring surrounding the insulating layer. However, the inventors of this disclosure have found that because the insulating layer is non-conductive, when the conductive structure is electrically connected to the word line contacts, the word line contacts can only land on the ring-shaped conductive layer. The presence of the insulating layer encroaches on the landing window, increasing the difficulty of electrical connection between the word line contacts and the gate layer. Furthermore, with less conductive layer deposition, the conductive layer is thinner, and part of the word line contacts lands on the insulating layer, resulting in increased contact resistance between the word line contacts and the gate layer.

[0082] As can be seen from the above, it is difficult to make electrical contact between the conductive structure and the word line contacts, that is, it is difficult to make electrical connection between the gate layer and the word line contacts, which increases the process complexity of the semiconductor structure 200 and leads to an increase in the production cost of the three-dimensional memory 10.

[0083] To address the aforementioned problems, some embodiments of this disclosure provide a semiconductor structure 200, which is described below with reference to... Figures 5 to 13 Examples of semiconductor structures 200 provided in some embodiments of this disclosure will be given.

[0084] Figure 5 This is a structural diagram of a semiconductor structure according to some embodiments. Figure 6 This is a structural diagram of a semiconductor structure according to some other embodiments. Figure 7 for Figure 5 A cross-sectional view along the AA direction. Figure 8 for Figure 5 A cross-sectional structural diagram along the BB direction.

[0085] In some embodiments, such as Figure 5 As shown, the semiconductor structure 200 includes a stacked structure 210. (As illustrated...) Figure 6 As shown, the stacked structure 210 has a core area and a non-core area.

[0086] In some examples, such as Figure 7 As shown, the semiconductor structure 200 also includes a substrate 201, with the stacked structure 210 located on one side of the substrate 201. Understandably, the substrate 201 includes a source layer SL. Furthermore, by way of example, the substrate 201 may also include a substrate 260 located on the side of the source layer SL away from the stacked structure 210.

[0087] In some embodiments, the substrate 260 may include monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, or III. Group V compound semiconductor materials, II A group VI compound semiconductor material or at least one of other semiconductor materials known in the art.

[0088] In some embodiments, the substrate 260 may be a single-layer structure, while in other embodiments, the substrate 260 may be a multilayer composite structure. For example, when the substrate 260 is a multilayer composite structure, the substrate 260 may include alternating layers of silicon oxide and polysilicon.

[0089] For example, such as Figure 7 As shown, the stacked structure 210 includes at least two materials, which are alternately stacked along a first direction. In some embodiments, the number of stacked layers of the stacked structure 210 can be 4, 16, 32, 64, or 128 layers. The embodiments of this disclosure do not further limit the number of layers in the stacked structure 210.

[0090] In some embodiments, such as Figure 7 As shown, the stacked structure 210 includes multiple gate layers 2211 stacked along a first direction. The multiple gate layers 2211 are spaced apart, and it can be understood that each gate layer 2211 extends from the core region to the non-core region.

[0091] For example, such as Figure 7 As shown, the first direction is perpendicular to or approximately perpendicular to the base 201.

[0092] like Figure 7 As shown, the core area and the non-core area are arranged adjacent to each other. The core area is used to store data, and the non-core area is used to electrically connect the gate layer 2211 (that is, the word line WL) to the word line contact V0.

[0093] In some embodiments, there can be multiple core regions and non-core regions. A core region can be located between two non-core regions, or multiple core regions can be spaced apart from multiple non-core regions.

[0094] Understandably, the multiple gate layers 2211 are stacked and spaced apart along the first direction, with each gate layer 2211 extending from the core region to the non-core region, enabling electrical connection between the core region and the non-core region through the gate layers 2211. In this way, by electrically connecting the word line contact V0 to the gate layer 2211 located in the non-core region, operations such as writing, reading, and erasing data can be achieved.

[0095] In some embodiments, the material of the gate layer 2211 includes at least one selected from tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The material and thickness of each gate layer 2211 may be the same or different.

[0096] In order to electrically connect the gate layer 2211 located in the non-core region to the word line contact V0, in some embodiments, such as Figure 7 As shown, the semiconductor structure 200 also includes a conductive structure 230 and a conductive plug 240. The conductive structure 230 is located in the non-core region, and the conductive plug 240 is located within the plug opening 242 formed by the conductive structure 230.

[0097] In some embodiments, such as Figure 7 As shown, the conductive structure 230 includes a first portion 231 and a second portion 232. (As indicated...) Figure 8 As shown, the first part 231 is disposed on the same layer as a gate layer 2211 and is in electrical contact. That is, the first part 231 of the conductive structure 230 can be in electrical contact with a gate layer 2211 located in the non-core region, so that electrical signals can be transmitted between the gate layer 2211 and the first part 231.

[0098] In some embodiments, the thickness of the first portion 231 is the same as or approximately the same as the thickness of a gate layer 2211.

[0099] For example, the material of conductive structure 230 includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The material of conductive structure 230 and gate layer 2211 may be the same or different.

[0100] In some embodiments, the first portion 231 and the second portion 232 of the conductive structure 230 can be an integrally formed structure, which improves the reliability of the electrical contact between the first portion 231 and the second portion 232.

[0101] Figure 9 This is a structural diagram of a conductive structure according to some embodiments. Figure 10 This is a structural diagram of a conductive structure and a conductive plug according to some embodiments.

[0102] like Figure 9 As shown, the second part 232 of the conductive structure 230 is in electrical contact with the first part 231, as... Figure 8 As shown, the second part 232 extends upward through the stacked structure 210. (As...) Figure 9 As shown, the second part 232 encloses the plug opening 242.

[0103] Understandably, the second part 232 extends "upwards" through the stacked structure 210, that is, the second part 232 extends through the stacked structure 210 in a direction away from the base 201. For example, as... Figure 8 As shown, one end of the second part 232 is in contact with the first part 231, and the other end penetrates the stacked structure 210 in a direction away from the base 201, and forms a plug opening 242.

[0104] In some embodiments, the plug opening 242 can be a closed shape, such as a square, a circle, or an irregular polygon. In other embodiments, the plug opening 242 can also be a non-closed shape, such as a C-shape, a U-shape, or other non-closed irregular shapes.

[0105] like Figure 10 As shown, the conductive plug 240 is located within the plug opening 242 and is in electrical contact with the second portion 232. Understandably, because the first portion 231 of the conductive structure 230 is in electrical contact with a gate layer 2211, and the second portion 232 of the conductive structure 230 is in electrical contact with the first portion 231, the conductive plug 240 can be electrically connected to the gate layer 2211 through the first portion 231 and the second portion 232 of the conductive structure 230.

[0106] In this way, by making electrical contact between word line contact V0 and any one or more of conductive plugs 240 and the second part 232, an electrical connection between word line contact V0 and gate layer 2211 can be achieved, which increases the landing window for electrical connection between word line contact V0 and gate layer 2211 and reduces the difficulty of electrical connection between word line contact V0 and gate layer 2211.

[0107] For example, the conductive plug 240 may be made of at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and metal silicides. The conductive plug 240 may be made of the same material as or different from the conductive structure 230.

[0108] Understandably, such as Figure 10 As shown, the conductive plug 240 can close the plug opening 242. In some embodiments, the conductive plug 240 can form a closed structure with the conductive structure 230 (including the first portion 231 and the second portion 232). In other embodiments, the conductive plug 240 may also form a closed structure only with the second portion 232 of the conductive structure 230.

[0109] In some embodiments, such as Figure 7 As shown, the side of the conductive plug 240 away from the substrate 201 is flush or nearly flush with the side of the second part 232 away from the first part 231, thereby improving the structural regularity of the semiconductor structure 200 and facilitating electrical contact between the word line contact V0 and the conductive plug 240 and the conductive structure 230.

[0110] As described above, there are multiple gate layers 2211. In some embodiments, the number of conductive structures 230 is the same as the number of gate layers 2211. A first portion 231 of a conductive structure 230 is in electrical contact with a gate layer 2211. The number of conductive plugs 240 is the same as the number of conductive structures 230, and a conductive plug 240 is in electrical contact with a second portion 232 of a conductive structure 230.

[0111] This configuration allows multiple gate layers 2211 to be electrically connected to multiple conductive plugs 240 respectively, and electrical signals can be transmitted between word line contacts V0 and gate layers 2211 through different conductive plugs 240, thereby improving the reliability of the semiconductor structure 200.

[0112] In some embodiments, such as Figure 7 As shown, the semiconductor structure 200 also includes a third dielectric layer 258, which is located on one side of the stacked structure 210 along the first direction, that is, on the side of the stacked structure 210 away from the substrate 201. The word line contact V0 is embedded in the third dielectric layer 258 and is in electrical contact with the conductive plug 240. Understandably, the third dielectric layer 258 can protect the word line contact V0.

[0113] As can be seen from the above, in some embodiments of this disclosure, such as Figure 8 As shown, by setting the first part 231 of the conductive structure 230 to be disposed on the same layer as and electrically contacting a gate layer 2211, and the second part 232 to be electrically contacting the first part 231, and extending upward through the stacked structure 210, the conductive structure 230 can be embedded within the stacked structure 210 and electrically contacting the gate layer 2211. In this way, the conductive structure 230 can realize the electrical connection between the gate layer 2211 and other components (such as the subsequently formed word line contacts V0), thus eliminating the need for a stepped structure and avoiding the problem of misalignment between the word line contact holes and the stepped structure. The SCT architecture simplifies the manufacturing process and reduces the production cost of the semiconductor structure 200 by realizing the electrical contact between the conductive structure 230 and the gate layer 2211.

[0114] Furthermore, the second portion 232 encloses a plug opening 242, and a conductive plug 240 is disposed within the plug opening 242 and electrically contacted with the second portion 232. This allows the subsequently formed word line contact V0 to achieve electrical connection with the gate layer 2211 through at least one of the conductive plug 240 and the conductive structure 230. That is, the word line contact V0 can be electrically contacted with the end face of the second portion 232 of the conductive structure 230 away from the first portion 231, or the word line contact V0 can be electrically contacted with the surface of the conductive plug 240 away from the stacked structure 210, or both the end face of the second portion 232 of the conductive structure 230 away from the first portion 231 and the surface of the conductive plug 240 away from the stacked structure 210 can be electrically contacted.

[0115] This configuration increases the contact area between the word line contact V0 and the gate layer 2211 when they are electrically connected, which means it increases the landing window when the word line contact V0 and the gate layer 2211 are electrically connected. This improves the convenience of the electrical connection between the word line contact V0 and the gate layer 2211, simplifies the manufacturing process, reduces the production cost of the semiconductor structure 200, and thus reduces the production cost of the three-dimensional memory 10.

[0116] On the other hand, increasing the contact area between the word line contact V0 and the conductive structure 230 during electrical connection can also reduce the resistance between the word line contact V0 and the gate layer 2211, thereby improving the reliability of electrical signal transmission.

[0117] On the other hand, the word line contact V0 achieves electrical connection with the gate layer 2211 through the conductive plug 240 and the conductive structure 230, eliminating the need for other conductive structures between the word line contact V0 and the conductive plug 240, thus simplifying the structure of the semiconductor structure 200 and further reducing the cost of the semiconductor structure 200.

[0118] On the other hand, the conductive plug 240 is placed inside the plug opening 242, so that the conductive plug 240 can be embedded in the conductive structure 230 without the need for additional interlayer structures to accommodate the conductive plug 240. This allows the SCT architecture to be combined with the conductive plug 240, further simplifying the structure of the semiconductor structure 200 and reducing the cost of the semiconductor structure 200.

[0119] In some embodiments, such as Figure 5 As shown, the semiconductor structure 200 has a gate line slot 206, which penetrates the stacked structure 210 in a direction perpendicular to the substrate 201. Furthermore, the gate line slot 206 extends from the core region to the non-core region.

[0120] Understandably, a gate gap 206 can divide the core of a stacked structure 210 into two memory blocks 220.

[0121] In some embodiments, an insulating material may be disposed on the inner wall of the gate line slot 206, and a conductive material may be filled in the cavity formed by the insulating material. The insulating material on the inner wall provides electrical isolation to the conductive material. For example, the conductive material in the gate line slot 206 may be in electrical contact with the source layer SL, so that electrical signals on the source layer SL can be transmitted through the conductive material filled in the gate line slot 206.

[0122] For example, the insulating material on the inner wall of the gate gap 206 may include at least one of silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. The conductive material filling the gate gap 206 may include at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and metal silicides.

[0123] Figure 11 This is a structural diagram of a stacked structure according to some embodiments.

[0124] In some embodiments, such as Figure 11 As shown, the semiconductor structure 200 also includes a first dielectric layer 250. The first dielectric layer 250 is located on top of the stacked structure 210. For example, as... Figure 11 As shown, the first dielectric layer 250 is located on one side of the stacked structure 210 along the first direction, that is, the first dielectric layer 250 is located on the side of the stacked structure 210 away from the substrate 201.

[0125] Understandably, the first dielectric layer 250 can cover the side of the stacked structure 210 away from the substrate 201, thereby protecting the stacked structure 210. In some embodiments, the side of the first dielectric layer 250 away from the substrate 201 is a smooth planar structure.

[0126] For example, the material of the first dielectric layer 250 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0127] like Figure 11 As shown, the first dielectric layer 250 has a first opening 251, which can be understood to penetrate the first dielectric layer 250 in a direction perpendicular to the substrate 201.

[0128] like Figure 7 As shown, the end of the second portion 232 away from the first portion 231 and the conductive plug 240 are located within the first opening 251. It can be understood that the end of the second portion 232 away from the first portion 231 can penetrate not only the stacked structure 210 but also the first dielectric layer 250, allowing the end of the second portion 232 away from the first portion 231 to be located within the first opening 251. The conductive plug 240 is located within the plug opening 242 formed at the end of the second portion 232 away from the first portion 231, thus allowing the conductive plug 240 to also be located within the first opening 251 of the first dielectric layer 250.

[0129] In some embodiments, such as Figure 7As shown, the conductive plug 240 on the side away from the substrate 201, the second part 232 on the side away from the substrate 201, and the first dielectric layer 250 on the side away from the substrate 201 are flush or nearly flush, which improves the structural regularity of the semiconductor structure 200.

[0130] By providing a first dielectric layer 250 and placing the end of the second portion 232 away from the first portion 231 and the conductive plug 240 within the first opening 251, the first dielectric layer 250 can protect the end of the second portion 232 away from the first portion 231 and the conductive plug 240. Furthermore, the first dielectric layer 250 can also electrically isolate the second portion 232 and the conductive plug 240 from other structures (such as the channel contact 226), improving the reliability of the semiconductor structure 200.

[0131] In some examples, such as Figure 7 As shown, the third dielectric layer 258 is located on the side of the first dielectric layer 250 away from the stack structure 210, such that the word line contact V0 embedded in the third dielectric layer 258 can make electrical contact with at least one of the conductive plug 240 and the conductive structure 230.

[0132] In some embodiments, such as Figure 11 As shown, the semiconductor structure 200 also includes a channel structure 223. The channel structure 223 is located in the core region and extends through the stacked structure 210. Understandably, the channel structure 223 extends through the stacked structure 210 in a direction perpendicular to the substrate 201.

[0133] In some embodiments, at least a portion of the channel structure 223 is used to store data, enabling the core region to perform storage functions.

[0134] Understandably, the number of channel structures 223 can be multiple to increase the storage capacity of the stacked structure 210. The shape of the channel structure 223 can be cylindrical, frustum-shaped, or prism-shaped, etc., and the embodiments of this disclosure do not further limit the shape of the channel structure 223.

[0135] like Figure 11 As shown, the first dielectric layer 250 also has a second opening 252. Understandably, the position of the second opening 252 corresponds to the position of the channel structure 223, and the second opening 252 penetrates the first dielectric layer 250 in a direction perpendicular to the substrate 201, so that the end of the channel structure 223 away from the substrate 201 can be exposed.

[0136] like Figure 7As shown, the semiconductor structure 200 also includes a channel contact 226. The channel contact 226 is located within the second opening 252 and is in electrical contact with the end of the channel structure 223 near the first dielectric layer 250, that is, the channel contact 226 is in electrical contact with the end of the channel structure 223 away from the substrate 201. This arrangement allows the channel structure 223 to achieve electrical connection with the outside through the channel contact 226, thereby enabling the semiconductor structure 200 to perform data writing, storage, and erasure.

[0137] like Figure 7 As shown, the channel contact 226 is disposed within the second opening 252, so that the first dielectric layer 250 can protect the channel contact 226. In addition, the channel contact 226 and the conductive plug 240 are disposed in the same layer, which improves the structural regularity of the semiconductor structure 200, facilitates the fabrication of the semiconductor structure 200, further simplifies the fabrication steps of the semiconductor structure 200, and reduces the production cost of the semiconductor structure 200.

[0138] In some embodiments, the side of the channel contact 226 away from the substrate 201 is flush or approximately flush with the side of the first dielectric layer 250 away from the substrate 201.

[0139] In some embodiments, such as Figure 7 As shown, the conductive plug 240 and the channel contact 226 are made of the same layer and material.

[0140] Understandably, "same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0141] By making the conductive plug 240 and the channel contact 226 share the same layer and material, the structural regularity of the semiconductor structure 200 is improved, facilitating electrical contact between the conductive plug 240 and the channel contact 226 and other components. Furthermore, this facilitates the fabrication of the semiconductor structure 200, simplifies the fabrication steps, increases production efficiency, and reduces production costs.

[0142] As described above, the second part 232 is in electrical contact with the first part 231. In some embodiments, such as Figure 9 As shown, the second part 232 includes an extension 2321. The first end of the extension 2321 is in electrical contact with the first part 231, and the second end of the extension 2321 forms a plug opening 242.

[0143] In some embodiments, the extension 2321 may be a closed shape, such as a ring, a rectangular ring, or other irregularly shaped ring. In other embodiments, the extension 231 may also be a non-closed shape, such as a C-shape, a U-shape, or other non-closed shape.

[0144] like Figure 8 As shown, the first end of the extension 2321 is in electrical contact with the first portion 231, and the second end of the extension 2321 extends upward through the stacked structure 210 and the first dielectric layer 250. Furthermore, as... Figure 9 As shown, the second end of the extension 2321 can form a plug opening 242.

[0145] like Figure 10 As shown, the conductive plug 240 can be inserted into the plug opening 242 formed by the extension 2321 and make electrical contact with the extension 2321.

[0146] The second part 232 includes an extension 2321. The first end of the extension 2321 is in electrical contact with the first part 231, and the second end extends upward through the stacked structure 210 and the first dielectric layer 250, and forms a plug opening 242. This increases the area of ​​electrical contact between the second part 232 and the first part 231 and the conductive plug 240, reduces the resistance between the second part 232 and the first part 231 and the conductive plug 240, and improves the reliability of the electrical connection between the second part 232 and the first part 231 and the conductive plug 240.

[0147] In some embodiments, such as Figure 9 As shown, the first end of the extension 2321 can form an opening P. (As indicated...) Figure 10 As shown, the second part 232 also includes a contact portion 2322. The contact portion 2322 is located within the opening P enclosed by the first end of the extension 2321, and the contact portion 2322 is in electrical contact with the first part 231 and the extension 2321.

[0148] In some embodiments, the contact portion 2322 can close the opening P formed by the first end of the extension portion 2321.

[0149] Understandably, by providing the contact portion 2322, and having the contact portion 2322 in electrical contact with the first portion 231 and the extension portion 2321, the area of ​​electrical contact between the second portion 232 and the first portion 231 is further increased, the resistance between the second portion 232 and the first portion 231 is reduced, and the reliability of electrical contact between the first portion 231 and the second portion 232 is improved.

[0150] In some embodiments, the contact portion 2322 and the extension portion 2321 can be an integrally formed structure, which improves the reliability of the electrical contact between the contact portion 2322 and the extension portion 2321.

[0151] In some embodiments, such as Figure 9 As shown, the area of ​​the plug opening 242 is larger than the area of ​​the opening P enclosed by the first end of the extension 2321.

[0152] like Figure 10 As shown, the contact portion 2322 is located within the opening P formed by the first end of the extension portion 2321, and the conductive plug 240 is located within the plug opening 242 formed by the second end of the extension portion 2321. Therefore, by providing a plug opening 242 with a larger area than the opening P formed by the first end of the extension portion 2321, the area of ​​the conductive plug 240 can be further increased.

[0153] In some examples, when the extension 2321 is annular, the area of ​​the plug opening 242 is larger than the area of ​​the opening P enclosed at the first end of the extension 2321, so that the extension 2321, the contact portion 2322, and the conductive plug 240 can form a closed frustum structure. The conductive plug 240 is the lower base of the frustum structure, and the contact portion 2322 is the upper base of the frustum structure. Understandably, the upper and lower bases of the frustum structure are parallel, and the area of ​​the upper base is smaller than the area of ​​the lower base.

[0154] In other examples, when the extension 2321 is a rectangular ring, the area of ​​the plug opening 242 is larger than the area of ​​the opening P enclosed at the first end of the extension 2321, so that the extension 2321, the contact portion 2322, and the conductive plug 240 can form a closed frustum structure. The conductive plug 240 is the lower base of the frustum structure, and the contact portion 2322 is the upper base of the frustum structure. Understandably, the upper and lower bases of the frustum structure are parallel, and the area of ​​the upper base is smaller than the area of ​​the lower base.

[0155] The area of ​​the plug opening 242 is larger than the area of ​​the opening P enclosed at the first end of the extension 2321, which can further increase the area of ​​the conductive plug 240. This increases the landing window when the word line contact V0 is electrically connected to the gate layer 2211, improves the convenience of electrical contact between the word line contact V0 and the conductive plug 240, and thus improves the convenience of electrical connection between the word line contact V0 and the gate layer 2211. This simplifies the manufacturing process of the semiconductor structure 200 and reduces the cost of the semiconductor structure 200.

[0156] In some embodiments, such as Figure 10As shown, the area of ​​the first portion 231 projected onto the reference plane is larger than the area of ​​the opening P enclosed by the first end of the extension 2321. The reference plane is parallel to the multilayer gate layer 2211.

[0157] Understandably, the reference plane is a virtual plane parallel to the multilayer gate layer 2211. The projected area of ​​the first portion 231 on the reference plane is set to be larger than the area of ​​the opening P enclosed by the first end of the extension 2321, thereby increasing the area of ​​electrical contact between the first portion 231 and the gate layer 2211, reducing the resistance between the first portion 231 and the gate layer 2211, and improving the reliability of the conductive structure 230.

[0158] In some examples, the area of ​​the surface on the side where the first part 231 is in electrical contact with the extension 2321 is greater than the area of ​​the opening P enclosed by the first end of the extension 2321, which further increases the area of ​​electrical contact between the first part 231 and a gate layer 2211 and reduces the resistance between the first part 231 and the gate layer 2211.

[0159] In some embodiments, such as Figure 10 As shown, the semiconductor structure 200 also includes an electrically insulating layer 202. (As...) Figure 8 As shown, the electrical isolation layer 202 is located between the second part 232 and the stacked structure 210.

[0160] Understandably, the electrical isolation layer 202 includes insulating material and serves a function of electrical isolation. For example... Figure 8 As shown, the first portion 231 of the conductive structure 230 is in electrical contact with a gate layer 2211, and a portion of the second portion 232 is embedded in the stacked structure 210 and is in electrical contact with the first portion 231. Therefore, by providing an electrical isolation layer 202 between the second portion 232 and the stacked structure 210, electrical contact between the gate layer 2211 and the second portion 232 can be avoided. This ensures that the gate layer 2211 can only be in electrical contact with the first portion 231 and cannot directly contact the second portion 232 (including the extension 2321 and the contact portion 2322), thereby improving the reliability of the conductive structure 230.

[0161] For example, the material of the electrical isolation layer 202 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0162] In some embodiments, such as Figure 10 As shown, the electrical isolation layer 202 is located on the outer periphery of the extension 2321, so that the electrical isolation layer 202 can provide electrical isolation between the extension 2321 and the gate layer 2211, thereby further improving the reliability of the semiconductor structure 200.

[0163] In some embodiments, such as Figure 10 As shown, the conductive structure 230 and the conductive plug 240 surround and form a receiving cavity Q. Figure 7 As shown, the semiconductor structure 200 also includes an insulating material 203. The insulating material 203 fills the receiving cavity Q.

[0164] In some embodiments, the receiving cavity Q enclosed by the conductive structure 230 and the conductive plug 240 is a closed receiving cavity. The insulating material 203 is filled in the receiving cavity Q, thereby providing mechanical support for the conductive structure 230 and the conductive plug 240, improving the mechanical strength of the electrical contact between the conductive structure 230 and the conductive plug 240, and thus improving the reliability of the semiconductor structure 200.

[0165] For example, insulating material 203 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0166] In some embodiments, such as Figure 7 As shown, the cavity Q also has an air gap 204.

[0167] Understandably, the number of air gaps 204 can be one or more. In some embodiments, air gaps 204 can be formed when filling the insulating material 203 to reduce structural stress and improve the reliability of the semiconductor structure 200.

[0168] As can be seen from the above, if Figure 11 As shown, the semiconductor structure 200 includes a channel structure 223 located in the core region and extending through the stacked structure 210. At least a portion of the channel structure 223 is used for storing data.

[0169] Figure 12 This is a structural diagram of a channel structure according to some embodiments. Figure 13 This is a structural diagram of a stacked structure according to some other embodiments. Referring below... Figure 12 and Figure 13 Examples of stacked structure 210 and channel structure 223 are given below.

[0170] In some embodiments, such as Figure 12 As shown, the stacked structure 220 includes a memory stacked structure 221. A plurality of gate layers 2211 are located in the memory stacked structure 221. The memory stacked structure 221 also includes a plurality of gate insulating layers 2212, which are alternately stacked with the gate layers 2211.

[0171] like Figure 11As shown, each gate insulating layer 2212 extends from the core region to the non-core region. Understandably, the gate insulating layer 2212 can play an insulating role. The gate insulating layer 2212 and the gate layer 2211 are stacked alternately to avoid short circuits between two adjacent gate layers 2211, thereby improving the reliability of the semiconductor structure 200.

[0172] Understandably, the gate insulating layer 2212 and the gate layer 2211 may have the same or different thicknesses. For example, the material of the gate insulating layer 2212 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0173] In some embodiments, such as Figure 12 As shown, the channel structure 223 includes a storage channel structure 224 that extends through the storage stack structure 221. Understandably, the storage channel structure 224 is used to store data.

[0174] In some embodiments, the memory channel structure 224 may include a plurality of memory cells to perform memory functions. In some embodiments, the semiconductor structure 200 may include a plurality of memory channel structures 224 to increase the memory capacity of the semiconductor structure 200.

[0175] In some embodiments, such as Figure 12 As shown, the memory channel structure 224 includes at least a memory functional layer 2241 and a channel layer 2242 that are sequentially located away from a plurality of gate layers 2211. Understandably, the memory functional layer 2241 is used to store data.

[0176] In some embodiments, the storage layer 2241 may include a barrier layer, a charge trapping layer, and a tunneling layer. The charge trapping layer stores charge, the barrier layer blocks the charge stored in the charge trapping layer and provides electrical insulation between the charge trapping layer and the gate layer 2211. The tunneling layer generates charge (electrons or holes).

[0177] For example, the material of the barrier layer includes, but is not limited to, silicon oxide; the material of the charge trapping layer includes, but is not limited to, silicon nitride; and the material of the tunneling layer includes, but is not limited to, silicon oxide. In some embodiments, when the material of the barrier layer is silicon oxide, the material of the charge trapping layer is silicon nitride, and the material of the tunneling layer is silicon oxide, the storage functional layer 2241 can form an "ONO" structure.

[0178] The channel layer 2242 is used to transport the required charge. For example, the material of the channel layer 2242 includes, but is not limited to, doped polysilicon.

[0179] In some embodiments, such as Figure 12As shown, the storage channel structure 224 may also include a storage channel filling medium 2247, which fills the accommodating space formed by the channel layer 2242 and serves to support the storage channel structure 224.

[0180] For example, the material of the storage channel filling medium 2247 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0181] In some embodiments, the storage channel filling medium 2247 filling the storage channel structure 224 may include an air gap to reduce structural stress.

[0182] In some embodiments, such as Figure 12 As shown, the memory channel structure 224 may further include a memory channel plug 2246. The memory channel plug 2246 is disposed at the end of the memory channel structure 224 away from the substrate 201 and is embedded within the memory channel structure 224, making electrical contact with the channel layer 2242. Electrical signals are transmitted through the memory channel plug 2246. For example, the material of the memory channel plug 2246 may be monocrystalline silicon or polycrystalline silicon, etc.

[0183] In some embodiments, such as Figure 12 As shown, the substrate 201 includes a source layer SL. The channel layer 2242 and the storage channel filling medium 2247 of the storage channel structure 224 near the end of the substrate 201 are embedded in the source layer SL, so that the end of the storage channel structure 224 near the substrate 201 can be electrically contacted with the source layer SL, thereby enabling multiple storage cells on the storage channel structure 224 to achieve a common source.

[0184] In some embodiments, such as Figure 12 As shown, the storage stack structure 221 includes a first storage stack structure 2213 and a second storage stack structure 2214. The first storage stack structure 2213 is disposed on one side of the substrate 201, and the second storage stack structure 2214 is disposed on the side of the first storage stack structure 2213 away from the substrate 201.

[0185] Understandably, the number of stacks in the first storage stack 2213 and the number of stacks in the second storage stack 2214 can be the same or different.

[0186] like Figure 12As shown, the storage channel structure 224 includes a first storage channel structure 2244 and a second storage channel structure 2245. The first storage channel structure 2244 penetrates the first storage stack structure 2213, and the second storage channel structure 2245 penetrates the second storage stack structure 2214. Understandably, the second storage channel structure 2245 is in electrical contact with the end of the first storage channel structure 2244 away from the substrate 201. The source layer SL is in electrical contact with the end of the first storage channel structure 2244 away from the second storage channel structure 2245. A storage channel plug 2246 is disposed at the end of the second storage channel structure 2245 away from the first storage channel structure 2244 and is embedded within the second storage channel structure 2245.

[0187] By setting up the storage stack structure 221 and the storage channel structure 224, the semiconductor structure 200 can realize functions such as writing, reading and erasing data, thereby improving the performance of the semiconductor structure 200.

[0188] In some embodiments, such as Figure 12 As shown, the stacking structure 210 also includes a selection stacking structure 222. The selection stacking structure 222 is located above the storage stacking structure 221, for example, as... Figure 12 As shown, the selected stack structure 222 is located on one side of the storage stack structure 221 along the first direction, that is, the selected stack structure 222 is located on the side of the storage stack structure 221 away from the substrate 201.

[0189] Understandably, when the storage stack structure 221 includes a first storage stack structure 2213 and a second storage stack structure 2214, the selected stack structure 222 is located on the side of the second storage stack structure 2214 that is away from the substrate 201.

[0190] like Figure 12 As shown, the selected stacked structure 222 includes an insulating dielectric layer 2221, a first conductive layer 2222, and a second dielectric layer 2223 arranged sequentially. Figure 13 As shown, the insulating dielectric layer 2221 extends from the core region to the non-core region, and the first conductive layer 2222 and the second dielectric layer 2223 are located in the core region.

[0191] For example, the insulating dielectric layer 2221 is made of silicon oxide, the first conductive layer 2222 is made of polycrystalline silicon, and the second dielectric layer 2223 is made of silicon nitride.

[0192] like Figure 13As shown, since the first conductive layer 2222 and the second dielectric layer 2223 are located in the core region, the insulating dielectric layer 2221 extends into the non-core region. This results in a height difference between the surface of the core region away from the substrate 201 (that is, the surface of the second dielectric layer 2223 away from the substrate 201) and the surface of the non-core region away from the substrate 201 (that is, the surface of the insulating dielectric layer 2221 away from the substrate 201).

[0193] In some embodiments, such as Figure 13 As shown, the stack structure 210 also includes a fill layer 208, which is located on the side of the insulating dielectric layer 2221 away from the storage stack structure 221 and is located in the non-core area.

[0194] By setting the filling layer 208, the side of the filling layer 208 away from the insulating dielectric layer 2221 can be flush or nearly flush with the side of the second dielectric layer 2223 away from the insulating dielectric layer 2221. That is, the surface of the core region away from the substrate 201 can be flush or nearly flush with the surface of the non-core region away from the substrate 201, thereby improving the structural regularity of the semiconductor structure 200.

[0195] For example, the material of the filling layer 208 includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0196] In other embodiments, the filling layer 208 may be omitted, and instead, the first dielectric layer 250 may be used to fill the side of the insulating dielectric layer 2221 away from the substrate 201, so that the side of the first dielectric layer 250 away from the substrate 201 is a smooth planar structure.

[0197] like Figure 12 As shown, the channel structure 223 also includes a selection channel structure 225. The selection channel structure 225 penetrates the selection stack structure 222 and is electrically contacted at the end of the storage channel structure 224 along the first direction, that is, the selection channel structure 225 is electrically contacted at the end of the storage channel structure 224 away from the substrate 201. Understandably, the selection channel structure 225 is used to control the storage channel structure 224 to perform operations such as writing, reading, or erasing data.

[0198] In some embodiments, when the storage channel structure 224 includes a first storage channel structure 2244 and a second storage channel structure 2245, the channel structure 225 is selected to make electrical contact with the end of the second storage channel structure 2245 remote from the first storage channel structure 2244. For example, when the storage channel plug 2246 is located at the end of the second storage channel structure 2245, the channel structure 225 is selected to make electrical contact with the storage channel plug 2246.

[0199] like Figure 12 As shown, the selected channel structure 225 includes at least an insulating layer 2251 and a second conductive layer 2252, sequentially located away from the first conductive layer 2222. Understandably, the second conductive layer 2252 is used to transport charge, and the insulating layer 2251 is used to block charge on the second conductive layer 2252, preventing charge from being transported to structures other than the storage channel structure 224. For example, the insulating layer 2251 may be made of silicon oxide, and the second conductive layer 2252 may be made of polycrystalline silicon.

[0200] In some embodiments, such as Figure 12 As shown, the selective channel structure 225 may further include a selective channel filling medium 2254. The selective channel filling medium 2254 fills the accommodating space formed by the second conductive layer 2252, and serves to support the selective channel structure 225.

[0201] For example, the material of the selected channel filling medium 2254 may be at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. In some embodiments, the selected channel filling medium 2254 filling the selected channel structure 225 may include an air gap to reduce structural stress.

[0202] In some embodiments, such as Figure 12 As shown, the selection channel structure 225 may further include a selection channel plug 2253. The selection channel plug 2253 is disposed at the end of the selection channel structure 225 away from the storage channel structure 224 and embedded within the selection channel structure 225, making electrical contact with the second conductive layer 2252. Electrical signals are transmitted through the selection channel plug 2253. For example, the material of the selection channel plug 2253 may be monocrystalline silicon or polycrystalline silicon, etc.

[0203] By selecting the stacked structure 222 and the channel structure 225, the storage channel structure 224 can be controlled to perform operations such as writing, reading or erasing data, further improving the performance of the semiconductor structure 200.

[0204] In some embodiments, the channel structure 225 can be configured as a simple metal-oxide-semiconductor (MOS) transistor, simplifying the process and reducing manufacturing costs.

[0205] In some embodiments, when the channel structure 223 includes a selected channel structure 225, such as Figure 12As shown, the channel contact 226 is in electrical contact with the end of the selected channel structure 225 near the first dielectric layer 250.

[0206] In some embodiments, such as Figure 5 As shown, the semiconductor structure 200 also includes a selective stack cutout 207, which penetrates the selective stack structure 222 in a direction perpendicular to the substrate 201 to separate the multiple selective channel structures 225 from each other.

[0207] This configuration facilitates control of each selected channel structure 225, thereby effectively reducing the time required for data writing, reading, and erasing, and improving the performance of the semiconductor structure 200.

[0208] In some embodiments, the selected stack cutout 207 may be filled with silicon oxide or silicon nitride to improve the mechanical strength of the semiconductor structure 200 and to provide insulation.

[0209] In some embodiments, such as Figure 7 As shown, the semiconductor structure 200 also includes a semiconductor structure layer 205. The semiconductor structure layer 205 is located on the side of the stacked structure 210 away from the first dielectric layer 250. For example, as... Figure 7 As shown, the semiconductor structure layer 205 is located between the substrate 201 and the stacked structure 210.

[0210] Understandably, the material of the semiconductor structure layer 205 can be polycrystalline silicon. The semiconductor structure layer 205 extends from the core region to the non-core region and is located between the substrate 201 and the stacked structure 210 to increase the mechanical strength of the semiconductor structure 200 and improve the reliability of the semiconductor structure 200.

[0211] In some embodiments, such as Figure 5 As shown, the semiconductor structure 200 also includes multiple virtual channel structures 209. For example... Figure 8 As shown, multiple virtual channel structures 209 are located in the non-core area and penetrate the stacked structure 210.

[0212] Understandably, multiple virtual channels 209 penetrate the stacked structure 210 in a direction perpendicular to the substrate 201. The multiple virtual channel structures 209 are arranged at intervals in the non-core area and avoid the conductive structure 230, thus providing mechanical support for the semiconductor structure 200.

[0213] For example, the virtual channel structure 209 may be filled with at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0214] On the other hand, some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, which is described below with reference to... Figures 14 to 55 The following are examples illustrating the methods for preparing semiconductor structures provided in some embodiments of this disclosure.

[0215] Figure 14 This is a flowchart of the steps for fabricating a semiconductor structure according to some embodiments. Figure 15 This is a structural diagram of an initial stacked structure according to some embodiments. Figure 16 This is a structural diagram of a semiconductor structure according to some other embodiments.

[0216] In some embodiments, such as Figure 14 As shown, the method for fabricating a semiconductor structure includes: Step S101: An initial stacked structure is formed on one side of the substrate. The initial stacked structure has a core region and a non-core region. The initial stacked structure includes multiple gate sacrificial layers stacked along a first direction. The multiple gate sacrificial layers are spaced apart. The first direction is perpendicular to the substrate.

[0217] In some embodiments, the substrate 260 may be a single-layer substrate. In other embodiments, such as Figure 15 As shown, substrate 260 can also be a composite substrate. For example, when substrate 260 includes a composite substrate, the composite substrate may include alternating layers of polysilicon and silicon oxide. In some embodiments, the composite substrate may be formed using ion implantation.

[0218] like Figure 15 As shown, the initial stacked structure 210' includes at least two materials, which are stacked alternately along a first direction, that is, at least two materials are stacked alternately along a direction perpendicular to or approximately perpendicular to the substrate 260.

[0219] For example, an initial stacked structure 210' can be formed on one side of the substrate 260 using any of the following thin film deposition processes: chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0220] For example, such as Figure 15 As shown, the initial stacked structure 210' has a core region and a non-core region. The initial stacked structure 210' includes multiple gate sacrificial layers 2215 stacked along a first direction. The multiple gate sacrificial layers 2215 are spaced apart, and understandably, each gate sacrificial layer 2215 extends from the core region to the non-core region.

[0221] Understandably, the gate sacrificial layer 2215 in the core region can be replaced with the gate layer 2211 in subsequent fabrication steps, and at least a portion of the gate layer 2215 in the non-core region can be replaced with the gate layer 2211 in subsequent fabrication steps.

[0222] For example, the material of the gate sacrificial layer 2215 can be one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon.

[0223] Step S102: A conductive structure is formed, located in the non-core region. The conductive structure includes a first part and a second part. The first part is disposed on the same layer as and in contact with a gate sacrificial layer. The second part is in electrical contact with the first part. The second part extends upward through the initial stacked structure and forms a plug opening.

[0224] like Figure 10 As shown, the conductive structure 230 includes a first portion 231 and a second portion 232. (As indicated...) Figure 16 As shown, the first portion 231 is disposed on the same layer as and in contact with a gate sacrificial layer 2215. For example, during gate replacement (i.e., when the gate sacrificial layer 2215 is replaced with the gate layer 2212), the portion of the gate sacrificial layer 2215 located in the non-core region and in contact with the first portion 231 can be replaced with the gate layer 2211, allowing the first portion 231 to make electrical contact with the gate layer 2211. The portion of the gate sacrificial layer 2215 located in the non-core region and not in contact with the first portion 231 is retained, serving as electrical isolation.

[0225] like Figure 16 As shown, one end of the second portion 232 is in electrical contact with the first portion 231, and the second portion 232 extends upward through the initial stacked structure 210'. For example, the end of the second portion 232 away from the first portion 231 can extend through the initial stacked structure 210' in a direction away from the substrate 260, as shown. Figure 9 As shown, the end of the second part 232 away from the first part 231 forms a plug opening 242.

[0226] In some embodiments, the conductive structure 230 may be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0227] Step S103: A conductive plug is formed, which is located inside the plug opening and is in electrical contact with the second part.

[0228] like Figure 16 As shown, after forming the plug opening 242, a conductive plug 240 is formed, such that the conductive plug 240 can close the plug opening 242 and make electrical contact with the second part 232.

[0229] In some embodiments, the conductive plug 240 may be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0230] Understandably, the structure and materials of the conductive structure 230 and the conductive plug 240 have been illustrated in the above embodiments of this disclosure and will not be repeated here.

[0231] The following example illustrates the method of electrical contact between the word line contact V0 and the conductive plug 240.

[0232] In some embodiments, such as Figure 16 As shown, a third dielectric layer 258 can be formed on the side of the first dielectric layer 250 away from the initial stack structure 210'. A first mask is formed on the side of the third dielectric layer 258 away from the first dielectric layer 250. The first mask is patterned to form a first etching opening. The third dielectric layer 258 is etched through the first etching opening to form a receiving hole that penetrates the third dielectric layer 258 along the direction to the conductive plug 240 and exposes the conductive plug 240. A word line contact V0 is formed within the receiving hole, allowing the word line contact V0 to be embedded within the third dielectric layer 258.

[0233] Understandably, electrical contact between the word line contact V0 and at least one of the conductive plug 240 and the conductive structure 230 enables the transmission of electrical signals between the word line contact V0 and the gate layer 2211. That is, by providing the conductive plug 240, the landing window for the electrical connection between the word line contact V0 and the gate layer 2211 is increased, reducing the technological difficulty of the electrical connection between the word line contact V0 and the gate layer 2211. This reduces the precision requirements for the pattern on the first mask, eliminating the need for repeated correction of the pattern on the first mask, simplifying the fabrication process of the semiconductor structure 200, and reducing the cost of the semiconductor structure 200.

[0234] As can be seen from the above, in some embodiments of this disclosure, by setting the first portion 231 of the conductive structure 230 to be disposed in the same layer and in contact with a gate sacrificial layer 2215, after the gate sacrificial layer 2215 is replaced with the gate layer 2211, the first portion 231 can be disposed in the same layer and in electrical contact with a gate layer 2211.

[0235] The second part 232 is electrically connected to the first part 231. The second part 232 extends upward through the initial stacked structure 210' and surrounds the plug opening 242. That is, the end of the second part 232 away from the first part 231 can extend upward through the initial stacked structure 210' (stacked structure 210), so that the conductive structure 230 can be embedded in the initial stacked structure 210' (stacked structure 210) and electrically contact a gate layer 2211.

[0236] In this way, the electrical connection between the gate layer 2211 and other components (such as the word line contacts V0 formed later) can be achieved through the conductive structure 230, thereby eliminating the need for a stepped structure and avoiding the problem of misalignment between the word line contact holes and the stepped structure. The electrical contact between the conductive structure 230 and the gate layer 2211 is achieved through the SCT architecture, which simplifies the manufacturing process and reduces the production cost of the semiconductor structure 200.

[0237] Furthermore, the second portion 232 encloses a plug opening 242, and a conductive plug 240 is disposed within the plug opening 242 and electrically contacted with the second portion 232. This allows the subsequently formed word line contact V0 to achieve electrical connection with the gate layer 2211 through at least one of the conductive plug 240 and the conductive structure 230. That is, the word line contact V0 can be electrically contacted with the end face of the second portion 232 of the conductive structure 230 away from the first portion 231, or the word line contact V0 can be electrically contacted with the surface of the conductive plug 240 away from the stacked structure 210, or both the end face of the second portion 232 of the conductive structure 230 away from the first portion 231 and the surface of the conductive plug 240 away from the stacked structure 210 can be electrically contacted.

[0238] This configuration increases the contact area between the word line contact V0 and the gate layer 2211 when they are electrically connected, which means it increases the landing window when the word line contact V0 and the gate layer 2211 are electrically connected. This improves the convenience of the electrical connection between the word line contact V0 and the gate layer 2211, simplifies the manufacturing process, reduces the production cost of the semiconductor structure 200, and thus reduces the production cost of the three-dimensional memory 10.

[0239] On the other hand, increasing the contact area between the word line contact V0 and the conductive structure 230 during electrical connection can also reduce the resistance between the word line contact V0 and the gate layer 2211, thereby improving the reliability of electrical signal transmission.

[0240] On the other hand, the word line contact V0 achieves electrical connection with the gate layer 2211 through the conductive plug 240 and the conductive structure 230, eliminating the need for other conductive structures between the word line contact V0 and the conductive plug 240, thus simplifying the structure of the semiconductor structure 200 and further reducing the cost of the semiconductor structure 200.

[0241] On the other hand, the conductive plug 240 is placed inside the plug opening 242, so that the conductive plug 240 can be embedded in the conductive structure 230 without the need for additional interlayer structures to accommodate the conductive plug 240. This allows the SCT architecture to be combined with the conductive plug 240, further simplifying the structure of the semiconductor structure 200 and reducing the cost of the semiconductor structure 200.

[0242] Figure 17 This is a structural diagram of a first dielectric film according to some embodiments. Figure 18 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 19 This is a structural diagram of a first contact hole according to some embodiments. Figure 20 This is a structural diagram of the first contact hole according to some other embodiments. Figure 21 This is a structural diagram of the first contact hole according to some other embodiments. Figure 22 This is a structural diagram of the first part according to some embodiments. Figure 23 This is a structural diagram of a conductive structure according to some other embodiments.

[0243] In some embodiments, prior to the step of forming the conductive structure, i.e., prior to step S102, the method for preparing the semiconductor structure further includes: A first dielectric film is formed, which is located on the initial stacked structure.

[0244] like Figure 17 As shown, after forming an initial stacked structure 210' on one side of the substrate 260 and before forming the conductive structure 230, the method for fabricating the semiconductor structure 200 includes forming a first dielectric film 250', which is located above the initial stacked structure 210'. For example, as... Figure 17 As shown, a first dielectric film 250' can be formed on one side of the initial stacked structure 210' along the first direction, that is, on the side of the initial stacked structure 210' away from the substrate 260.

[0245] For example, the material of the first dielectric film 250' includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials.

[0246] For example, a first dielectric film 250' can be formed on the side of the initial stacked structure 210' away from the substrate 260 using any of the thin film deposition processes of CVD, PVD, and ALD.

[0247] In some embodiments, such as Figure 18 As shown, the step of forming the conductive structure (i.e., step S102) includes: Step S1021: A first contact hole is formed in the non-core area. The first contact hole penetrates the first dielectric film and exposes the target gate sacrificial layer. The target gate sacrificial layer is one of multiple gate sacrificial layers.

[0248] Understandably, the first contact hole 261 penetrates the first dielectric film 250', thereby enabling the formation of the first opening 251 on the first dielectric film 250'.

[0249] like Figure 16 As shown, the initial stacked structure 210' also includes multiple gate insulating layers 2212, with the gate insulating layers 2212 and gate sacrificial layers 2215 alternately stacked. When the gate sacrificial layer 2215 is replaced by a gate layer 2211, the gate insulating layer 2212 can insulate between the two gate layers 2211. The material and thickness of the gate insulating layer 2212 have been illustrated in the above embodiments of this disclosure and will not be repeated here.

[0250] In some embodiments, such as Figure 19 As shown, the first contact hole 261 can be directly opened to the target gate sacrificial layer 2215a, so that the target gate sacrificial layer 2215a can be exposed.

[0251] In other embodiments, such as Figure 20 As shown, the first contact hole 261 can be opened to the gate insulating layer 2212 located on the layer above the target gate sacrificial layer 2215a, and then part of the gate insulating layer 2212 on the layer above the target gate sacrificial layer 2215a can be removed to expose the target gate sacrificial layer 2215a.

[0252] For example, the first contact hole 261 can be formed by dry etching or wet etching to expose the target gate sacrificial layer 2215a.

[0253] Understandably, the embodiments of this disclosure do not impose further restrictions on the critical dimension (CD) of the first contact hole 261.

[0254] In step S1022, a portion of the target gate sacrificial layer is removed via the first contact hole to form an epitaxial contact hole.

[0255] like Figure 21As shown, after forming the first contact hole 261, a portion of the target gate sacrificial layer 2215a can be removed through the first contact hole 261 to form the epitaxial contact hole 262. For example, the area of ​​the epitaxial contact hole 262 projected onto the reference plane is larger than the area of ​​the bottom opening of the first contact hole 261. That is, the area of ​​the epitaxial contact hole 262 projected onto the substrate 260 is larger than the area of ​​the bottom opening of the first contact hole 261.

[0256] For example, dry etching or wet etching can be used to remove part of the target gate sacrificial layer 2215a to form an epitaxial contact hole 262.

[0257] Step S1023: A first portion is formed within the epitaxial contact hole.

[0258] like Figure 22 As shown, a first portion 231 is formed within the epitaxial contact hole 262, such that the first portion 231 can be disposed in the same layer as and in contact with the target gate sacrificial layer 2215a. As can be seen from the above, the gate sacrificial layer 2215 in contact with the first portion 231 can be replaced by the gate layer 2211, thereby enabling the first portion 231 to be disposed in the same layer as and in electrical contact with the gate layer 2211.

[0259] In step S1024, a second part is formed inside the first contact hole, and the second part is in electrical contact with the first part.

[0260] like Figure 23 As shown, the second portion 232 is formed on the sidewall of the first contact hole 261 and covers the side of the first portion 231 away from the substrate 260, so that one end of the second portion 232 can make electrical contact with the first portion 231, and the other end can penetrate upward through the stacked structure 210' and the first dielectric film 250'.

[0261] Understandably, since the area of ​​the epitaxial contact hole 262 projected onto the substrate 260 is larger than the area of ​​the bottom opening of the first contact hole 261, the area of ​​the first portion 231 formed in the epitaxial contact hole 262 projected onto the substrate 260 (that is, the area of ​​the first portion 231 projected onto the reference plane) can be larger than the area of ​​the opening P formed by the first end of the second portion 232.

[0262] For example, the first portion 231 and the second portion 232 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD. The above embodiments of this disclosure have illustrated the structure and materials of the first portion 231 and the second portion 232, and will not be repeated here.

[0263] As can be seen from the above, in some embodiments of this disclosure, after the initial stacked structure 210' is formed, a first dielectric film 250' covering the initial stacked structure 210' is first formed, and then a first contact hole 261 is opened, so that the first contact hole 261 can penetrate the first dielectric film 250', thereby forming a first opening 251 on the first dielectric film 250'.

[0264] An epitaxial contact hole 262 is formed through the first contact hole 261, and then a first portion 231 and a second portion 232 of the conductive structure 230 are formed. This allows the first portion 231 to be disposed in the same layer as and in contact with a gate sacrificial layer 2215, and allows the second portion 232 to penetrate upward through the initial stacked structure 210' and the first dielectric film 250'. By forming the conductive structure 230 through the above steps, a portion of the conductive structure 230 (including the first portion 231 and a portion of the second portion 232) can be embedded in the initial stacked structure 210' and in contact with a gate sacrificial layer 2215. This process is simple and reduces the production cost of the semiconductor structure 200.

[0265] Figure 24 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 25 This is a structural diagram of the initial contact hole according to some embodiments. Figure 26 This is a structural diagram of an electrical isolation membrane according to some embodiments.

[0266] As can be seen from the above, if Figure 23 As shown, the initial stacked structure 210' also includes a plurality of gate insulating layers 2212, which are alternately stacked with gate insulating layers 2212 and gate sacrificial layers 2215.

[0267] In some embodiments, such as Figure 24 As shown, the step of forming the first contact hole in the non-core area (step S1021) includes: Step S10211: An initial contact hole is formed in the non-core area. The initial contact hole penetrates the first dielectric film and exposes the target gate insulating layer, which is one of multiple gate insulating layers.

[0268] like Figure 25 As shown, the initial contact hole 263 penetrates the first dielectric film 250' and extends to the initial stacked structure 210', thereby exposing the target gate insulating layer 2212a. For example, the initial contact hole 263 can be formed using either dry etching or wet etching.

[0269] Step S10212: An electrical isolation film is formed inside the initial contact hole.

[0270] like Figure 26As shown, an electrical isolation film 202' is formed on the inner wall (including the sidewall and bottom wall) of the initial contact hole 263. For example, the electrical isolation film 202' can be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0271] For example, the material of the electrical isolation film 202' includes at least one of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxide (e.g., aluminum oxide, hafnium dioxide, etc.) and its silicates, and organic insulating materials, which serves as electrical isolation.

[0272] Step S10213: Remove the bottom wall of the electrical isolation film and part of the target gate insulating layer to form an electrical isolation layer, and form a first contact hole inside the electrical isolation layer to expose the target gate sacrificial layer.

[0273] The electrical isolation film 202' on the bottom wall of the initial contact hole 263 is removed to form an electrical isolation layer 202, thereby exposing the target gate insulating layer 2212a. A portion of the target gate insulating layer 2212a (i.e., the portion of the target gate insulating layer 2212a forming the bottom wall of the initial contact hole 263) is removed, thereby exposing the target gate sacrificial layer 2215a. Thus, as... Figure 19 As shown, a first contact hole 261 is formed on the inner side of the electrical isolation layer 202 to expose the target gate sacrificial layer 2215a.

[0274] In other embodiments, the initial contact hole 263 may be directly formed into the target gate sacrificial layer 2215a, so that the electrical isolation film 202' can cover the target gate sacrificial layer 2215a. By removing the electrical isolation film 202' from the bottom wall of the initial contact hole 263, the electrical isolation layer 202 and the first contact hole 261 exposing the target gate sacrificial layer 2215a can be formed.

[0275] Understandably, an electrical isolation layer 202 is formed on the inner wall of the initial contact hole 263, with the first contact hole 261 located inside the electrical isolation layer 202. This allows the electrical isolation layer 202 to provide electrical isolation for the second portion 232, preventing the second portion 232 from contacting the gate sacrificial layer 2215, and thus preventing direct electrical contact between the second portion 232 and the gate layer 2211. This ensures that electrical signals on the gate layer 2211 can only be transmitted to the second portion 232 through the first portion 231, improving the reliability of the conductive structure 230. Furthermore, the above-described fabrication method allows the electrical isolation layer 202 to be located between the second portion 232 and the gate sacrificial layer 2215, simplifying the process and reducing the production cost of the semiconductor structure 200.

[0276] Figure 27 This is a diagram of the filling structure of an insulating material according to some embodiments.

[0277] In some embodiments, after the step of forming the second portion within the first contact hole (i.e., after step S1024), the method for fabricating the semiconductor structure 200 further includes: The second part is filled with insulating material.

[0278] Understandably, the second portion 232 is formed on the sidewall of the first contact hole 261, so that the second portion 232 can enclose and form a cavity structure. For example... Figure 27 As shown, after the second part 232 is formed, an insulating material 203 is filled into the second part 232. The insulating material 203 supports the second part 232 and improves the mechanical strength of the second part 232.

[0279] Furthermore, since the conductive plug 240 is formed within the plug opening 242 enclosed by the second portion 232, filling the cavity formed in the second portion 232 with insulating material 203 can also improve the mechanical strength of the electrical contact between the conductive plug 240 and the second portion 232, thereby improving the reliability of the semiconductor structure 200.

[0280] The above embodiments of this disclosure have provided examples of the materials used for insulating material 203, which will not be repeated here. For instance, a high aspect ratio (HARP) process can be used to fill the cavity formed in the second part 232 with insulating material 203.

[0281] In some embodiments, such as Figure 27 As shown, during the process of filling the insulating material 203 in the second part 232, an air gap 204 can be formed by controlling the filling process to reduce structural stress.

[0282] Understandably, such as Figure 27 As shown, there is a preset distance between the surface of the insulating material 203 away from the substrate 260 and the surface of the second part 232 away from the first part 231, so that the conductive plug 240 can be disposed in the plug opening 242 and make electrical contact with the second part 232.

[0283] Figure 28 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 29 This is a structural diagram of a first conductive film according to some embodiments. Figure 30 This is a diagram of the filling structure of an insulating material according to some other embodiments. Figure 31 This is a diagram of the filling structure of an insulating material according to some other embodiments.

[0284] In some embodiments, such as Figure 28As shown, the steps of forming a second portion within the first contact hole and filling the second portion with insulating material include: Step S10241: Form a first conductive film. The first conductive film includes a first sub-film and a second sub-film. The first sub-film covers the first dielectric film, and the second sub-film covers the sidewall and the first portion of the first contact hole.

[0285] like Figure 29 As shown, the first conductive film 271 includes a first sub-film 2711 and a second sub-film 2712. The first sub-film 2711 covers the first dielectric film 250'. Figure 21 As shown, the non-core area has a first contact hole 261 and an extended contact hole 262, as... Figure 22 As shown, the first portion 231 is formed within the epitaxial contact hole 262. (As indicated...) Figure 29 As shown, the second sub-film 2712 covers the sidewall of the first contact hole 261 and the first portion 231 formed in the epitaxial contact hole 262.

[0286] Understandably, the second subfilm 2712 covers the side of the first portion 231 away from the substrate 260. The second subfilm 2712 is capable of forming the second portion 232 of the conductive structure 230.

[0287] For example, the first conductive film 271 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD. For example, the material of the first conductive film 271 includes at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and metal silicides.

[0288] Step S10242: Deposit insulating material, the insulating material fills the cavity defined by the second sub-film, and the insulating material covers the first sub-film.

[0289] like Figure 29 As shown, the second sub-film 2712 covers the sidewall of the first contact hole 261 and the first portion 231 formed in the epitaxial contact hole 262, such that the second sub-film 2712 can define the cavity 2713.

[0290] like Figure 30 As shown, an insulating material 203 is deposited, which can fill the cavity 2713 defined by the second sub-film 2712 and cover the first sub-film 2711. For example, the insulating material 203 can be deposited using a HARP process.

[0291] Step S10243: Etch insulating material to the first sub-film to remove part of the insulating material within the cavity defined by the second sub-film and the insulating material covering the first sub-film.

[0292] like Figure 31As shown, when etching the insulating material 203, the first sub-film 2711 is used as an etching stop layer, and the insulating material 203 covering the first sub-film 2711 is removed. It can be understood that since the first sub-film 2711 and the second sub-film 2712 are formed in the same step (step S10241), there is no need for an additional step to form an etching stop layer, simplifying the fabrication process of the semiconductor structure 200, reducing the production cost of the semiconductor structure 200, and improving production efficiency. For example, the insulating material 203 can be etched using either dry etching or wet etching.

[0293] As described above, the second sub-film 2712 can form the second portion 232 of the conductive structure 230. Therefore, in order to form a plug opening 242 at the end of the second sub-film 2712 away from the first portion 231, as follows... Figure 31 As shown, after removing the insulating material 203 covering the first sub-film 2711, the insulating material 203 in the cavity 2713 defined by the second sub-film 2712 can continue to be etched, such that the surface of the insulating material 203 in the cavity 2713 defined by the second sub-film 2712 away from the substrate 260 is lower than the surface of the first dielectric film 250' away from the substrate 260.

[0294] Understandably, since the conductive plug 240 can close the plug opening 242, that is, the insulating material 203 can be located in the closed cavity, the smoothness requirement of the surface of the insulating material 203 away from the substrate 260 is reduced, that is, the etching process requirement of the insulating material 203 is reduced, the manufacturing process of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

[0295] Furthermore, by providing a conductive plug 240 to close the plug opening 242, the height difference between the surface of the insulating material 203 away from the substrate 260 and the surface of the first dielectric film 250' away from the substrate 260 can be reduced. Figure 31 The requirements of H) are met, thereby further simplifying the manufacturing process of semiconductor structure 200 and reducing the production cost of semiconductor structure 200.

[0296] Understandably, since the first sub-film 2711 covers the first dielectric film 250', when etching the insulating material 203 in the cavity 2713 defined by the second sub-film 2712, the first sub-film 2711 can protect the first dielectric film 250', preventing the first dielectric film 250' from being damaged during the etching process, thereby improving the reliability of the semiconductor structure 200 fabrication method.

[0297] Step S10244: Remove the ends of the first sub-film and the second sub-film that extend beyond the surface of the first dielectric film away from the substrate to form the second portion.

[0298] like Figure 27 As shown, after removing the first sub-film 2711, the first dielectric film 250' is exposed. Furthermore, while removing the first sub-film 2711, the end of the second sub-film 2712 that is away from the substrate 260 and extends beyond the first dielectric film 250' can be removed, such that the side of the second sub-film 2712 away from the substrate 260 is flush with or approximately flush with the side of the first dielectric film 250' that is away from the substrate 260, thus forming the second portion 232.

[0299] Understandably, in the embodiments of this disclosure, "simultaneously" means in the same step, rather than being limited to the same moment.

[0300] For example, a chemical mechanical polishing (CMP) process can be used to remove the first sub-film 2711 and the end of the second sub-film 2712 extending beyond the surface of the first dielectric film 250' away from the substrate 260, thereby enabling planarization of the first dielectric film 250' during removal.

[0301] Figure 32 This is a structural diagram of a stop layer according to some embodiments. Figure 33 This is a structural diagram of the initial contact hole according to some other embodiments. Figure 34 This is a structural diagram of the first contact hole according to some other embodiments.

[0302] As can be seen from the above, in some embodiments of this disclosure, the first sub-film 2711 of the first conductive film 271 can be used as the etching stop layer of the insulating material 203. In other embodiments of this disclosure, after the step of forming the first dielectric film and before the step of forming the first contact hole in the non-core region, the following steps are further included: A stop layer is formed, which covers the first dielectric film.

[0303] like Figure 32 As shown, after the first dielectric film 250' is formed and before the first contact hole 261 is opened, a stop layer 273 can be formed on the side of the first dielectric film 250' away from the substrate 260, and the stop layer 273 covers the first dielectric film 250'.

[0304] For example, such as Figure 32 As shown, the stop layer 273 includes a first stop layer 2731 and a first protective layer 2732.

[0305] In some examples, the steps for forming stop layer 273 include: A first stop layer is formed, which is located on the side of the first dielectric film away from the initial stacked structure.

[0306] A first protective layer is formed, which is located on the side of the first stop layer away from the first dielectric film.

[0307] Understandably, when forming the stop layer 273, a first stop layer 2731 is first formed on the side of the initial stacked structure 210' away from the substrate 260, and then a first protective layer 2732 is formed on the side of the first stop layer 2731 away from the initial stacked structure 210'.

[0308] For example, the first stop layer 2731 and the first protective layer 2732 can be formed using any of the thin film deposition processes of CVD, PVD and ALD.

[0309] In some embodiments, the material of the first stop layer 2731 includes silicon nitride, and the material of the first protective layer 2732 includes silicon oxide. When the material of the first dielectric film 250' is silicon oxide, the first dielectric film 250', the first stop layer 2731, and the first protective layer 2732 can form an "ONO" structure.

[0310] Understandably, the first stop layer 2731 serves to stop the etching process, and the first protective layer 2732 serves to protect the first stop layer 2731. In some embodiments, after forming the stop layer 273 and before filling the insulating material 203, the fabrication method of the semiconductor structure 200 may include other steps, such as etching other contact holes. Therefore, by providing the first protective layer 2732 to cover the first stop layer 2731, the first protective layer 2732 can protect the first stop layer 2731, preventing the first stop layer 2731 from being damaged before etching the insulating material 203, thus improving the reliability of the fabrication method of the semiconductor structure 200.

[0311] In other embodiments, when the semiconductor structure 200 is fabricated after the stop layer 273 is formed and before the insulating material 203 is filled, and the step of etching other contact holes is not included, that is, when there is no step that may damage the first stop layer 2731, the first protective layer 2731 may not be provided, further simplifying the fabrication process of the semiconductor structure 200.

[0312] Understandably, the stop layer 273 can be removed in a subsequent fabrication process to expose the first dielectric film 250'. For example, after the stop layer 273 is removed, the first dielectric film 250' can be fabricated as a first dielectric layer 250, and a third dielectric layer 258 and word line contacts V0 can be formed on the side of the first dielectric layer 250 away from the substrate 260.

[0313] The steps of forming the first contact hole in the non-core area include: A first contact hole is formed in the non-core region, penetrating the stop layer and the first dielectric film, and exposing the target gate sacrificial layer.

[0314] Understandably, since the stop layer 273 covers the first dielectric film 250', as Figure 33 As shown, when forming the initial contact hole 263, the initial contact hole 263 is made to penetrate not only the first dielectric film 250', but also the stop layer 273.

[0315] Therefore, when the initial contact hole 263 is fabricated as the first contact hole 261, as follows: Figure 34 As shown, this allows the first contact hole 261 to also penetrate the stop layer 273 and the first dielectric film 250', and expose the target gate sacrificial layer 2215a.

[0316] Understandably, using a non-metallic material as the stop layer 273 reduces the structural stress generated by the stop layer 273, lowers the risk of the wafer bending under stress, and further improves the reliability of the semiconductor structure 200 fabrication method.

[0317] Figure 35 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 36 This is a structural diagram of the second conductive film according to some embodiments. Figure 37 This is a structural diagram of the fourth submembrane according to some embodiments. Figure 38 This is a diagram of the filling structure of an insulating material according to some other embodiments. Figure 39 This is a diagram of the filling structure of an insulating material according to some other embodiments. Figure 40 This is a diagram of the filling structure of an insulating material according to some other embodiments. Figure 41 This is a diagram of the filling structure of an insulating material according to some other embodiments.

[0318] like Figure 35 As shown, in some other embodiments, after the stop layer 273 is formed, the steps of forming a second portion within the first contact hole and filling the second portion with insulating material include: Step S10241': A second conductive film is formed, which includes a third sub-film and a fourth sub-film. The third sub-film covers the stop layer, and the fourth sub-film covers the sidewall and the first portion of the first contact hole.

[0319] like Figure 36 As shown, the second conductive film 272 includes a third sub-film 2722 and a fourth sub-film 2723. The third sub-film 2722 covers the stop layer 273, and understandably, the third sub-film 2722 is located on the side of the initial stacked structure 210' away from the substrate 260.

[0320] like Figure 21 As shown, the non-core area has a first contact hole 261 and an extended contact hole 262, as... Figure 22As shown, the first portion 231 is formed within the epitaxial contact hole 262. (As indicated...) Figure 36 As shown, the fourth sub-film 2723 covers the sidewall of the first contact hole 261 and the first portion 231 formed within the epitaxial contact hole 262. Understandably, the fourth sub-film 2723 can form the second portion 232 of the conductive structure 230.

[0321] For example, the third sub-film 2722 and the fourth sub-film 2723 can be formed using any of the thin film deposition processes of CVD, PVD and ALD.

[0322] For example, the materials of the third sub-film 2722 and the fourth sub-film 2723 include at least one of tungsten, cobalt, copper, aluminum, doped polycrystalline silicon, and metal silicides.

[0323] Step S10242': Remove the third submembrane to expose the stop layer.

[0324] like Figure 37 As shown, removing the third sub-film 2722 exposes the stop layer 273. For example, a CMP process can be used to remove the third sub-film 2722 covering the stop layer 273 to expose the stop layer 273.

[0325] Step S10243': Deposit insulating material, the insulating material fills the cavity defined by the fourth sub-film, and the insulating material covers the stop layer.

[0326] Understandably, such as Figure 37 As shown, since the fourth sub-film 2723 covers the sidewall of the first contact hole 261 and the first portion 231 formed in the extended contact hole 262, the fourth sub-film 2723 is able to define the cavity 2721.

[0327] like Figure 38 As shown, after removing the third sub-film 2722, an insulating material 203 is deposited such that the insulating material 203 can fill the cavity 2721 defined by the fourth sub-film 2723 and cover the stop layer 273. For example, the insulating material 203 can be deposited using a HARP process.

[0328] Step S10244': Etch insulating material down to at least part of the stop layer to remove part of the insulating material within the cavity defined by the fourth sub-film and the insulating material covering the stop layer.

[0329] like Figure 39 As shown, the insulating material 203 is etched to at least a portion of the stop layer 273 to remove the insulating material 203 covering the stop layer 273 and a portion of the insulating material 203 within the cavity 2721 defined by the fourth sub-film 2723.

[0330] As described above, the fourth sub-film 2723 can form the second portion 232 of the conductive structure 230. Therefore, in order to form a plug opening 242 at the end of the fourth sub-film 2723 away from the first portion 231, as follows... Figure 39 As shown, after removing the insulating material 203 covering the stop layer 273, the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 can continue to be etched, such that the surface of the insulating material 203 in the cavity 2721 defined by the fourth sub-film 2723 away from the substrate 260 can be lower than the surface of the first dielectric film 250' away from the substrate 260.

[0331] Understandably, since the conductive plug 240 can close the plug opening 242, that is, the insulating material 203 can be located in the closed cavity, the smoothness requirement of the surface of the insulating material 203 away from the substrate 260 is reduced, that is, the etching process requirement of the insulating material 203 is reduced, the manufacturing process of the semiconductor structure 200 is simplified, and the production cost of the semiconductor structure 200 is reduced.

[0332] Furthermore, by providing a conductive plug 240 to close the plug opening 242, the height difference between the surface of the insulating material 203 away from the substrate 260 and the surface of the first dielectric film 250' away from the substrate 260 can be reduced. Figure 39 This simplifies the manufacturing process of the semiconductor structure 200 and reduces its production cost, in accordance with the requirements of L).

[0333] For example, dry etching or wet etching can be used to remove the insulating material 203 and at least part of the stop layer.

[0334] Understandably, when etching the insulating material 203 within the cavity 2721 defined by the fourth sub-film 2723, at least a portion of the stop layer 273 can cover the first dielectric film 250', thereby protecting the first dielectric film 250' and preventing it from being damaged during the etching process, thus improving the reliability of the semiconductor structure 200 fabrication method.

[0335] Step S10245': Remove the remaining portion of the stop layer to expose the first dielectric film.

[0336] like Figure 40 As shown, the remaining portion of the stop layer 273 is removed, allowing the first dielectric film 250' to be exposed. For example, a CMP process or an etching process can be used to remove the remaining portion of the stop layer 273.

[0337] Step S10246': Remove the end of the fourth sub-film that extends beyond the surface of the first dielectric film away from the substrate to form the second portion.

[0338] like Figure 41 As shown, the end of the fourth sub-film 2723 that extends beyond the first dielectric film 250' away from the substrate 260 is removed, so that the end of the fourth sub-film 2723 away from the substrate 260 is flush or nearly flush with the side of the first dielectric film 250' away from the substrate 260, to form the second portion 232.

[0339] For example, a CMP process can be used to remove the end of the fourth sub-film 2723 that extends beyond the first dielectric film 250' on the side away from the substrate 260.

[0340] As described above, the stop layer 273 includes a first stop layer 2731 and a first protective layer 2732. In some embodiments, the step of etching the insulating material to at least a portion of the stop layer (i.e., step S10244') includes: Etch the insulating material and the first protective layer to the first stop layer.

[0341] like Figure 39 As shown, when etching the insulating material 203 covering the stop layer 273, the first stop layer 2731 is used as the etching stop layer, and the first protective layer 2732 and the insulating material 203 covering the first protective layer 2732 are etched and removed together. In this way, there is no need for an additional step to remove the first protective layer 2732, which further simplifies the manufacturing process of the semiconductor structure 200 and reduces the production cost of the semiconductor structure 200.

[0342] Understandably, when etching the insulating material 203 within the cavity 2721 defined by the fourth sub-film 2723, the first etching stop layer 2731 can cover the first dielectric film 250', thereby protecting the first dielectric film 250' and preventing it from being damaged.

[0343] In some embodiments, the step of removing the remaining stop layer (i.e., step S10245') includes: Remove the first stopping layer.

[0344] For example, such as Figure 40 As shown, the first stop layer 2731 can be removed by etching or CMP process, so that the first dielectric film 250' can be exposed.

[0345] Figure 42 This is a structural diagram of a channel structure according to some other embodiments.

[0346] In some embodiments, such as Figure 42 As shown, the semiconductor structure 200 also includes a channel structure 223, which is located in the core region and extends through the initial stacked structure 210'.

[0347] The above embodiments of this disclosure have illustrated the structure and function of the channel structure 223, and will not be repeated here. The method for forming the channel structure 223 will now be illustrated.

[0348] Figure 43 This is a structural diagram of an initial stacking structure according to some other embodiments.

[0349] In some embodiments, such as Figure 43 As shown, the initial stack structure 210' includes an initial memory stack structure 221'. The initial memory stack structure 221' includes a plurality of gate sacrificial layers 2215 and gate insulating layers 2212, with the gate insulating layers 2212 and the gate sacrificial layers 2215 stacked alternately.

[0350] For example, the initial memory stack structure 221' can be formed using any of the thin film deposition processes of CVD, PVD, and ALD. The materials and thicknesses of the gate insulating layer 2212 and the gate sacrificial layer 2215 have been illustrated in the above embodiments of this disclosure, and will not be repeated here.

[0351] like Figure 12 As shown, the channel structure 223 includes a storage channel structure 224, which penetrates the initial storage stack structure 221'. The method for forming the storage channel structure 224 is illustrated below.

[0352] In some embodiments, a memory channel via can be formed in a direction perpendicular to the substrate 260, and the memory channel via penetrates the initial memory stack structure 221'. A memory functional layer 2241 and a channel layer 2242 are sequentially formed in the memory channel via, and a memory channel filling medium 2247 is filled in the accommodating space enclosed by the channel layer 2242 to form a memory channel structure 224.

[0353] For example, the storage channel can be formed using either a dry etching process or a wet etching process, and the storage functional layer 2241 and the channel layer 2242 can be formed using any of the thin film deposition processes of CVD, PVD and ALD.

[0354] like Figure 12 As shown, in some embodiments, the storage channel structure 224 includes a first storage channel structure 2244 and a second storage channel structure 2245, which can be formed by the following method.

[0355] For example, such as Figure 43As shown, a first initial memory stack structure 2213' can be formed on one side of the substrate 260, and a first memory channel via can be formed on the first initial memory stack structure 2213'. The first memory channel via is filled with a channel sacrificial dielectric to support the first memory channel via. In some embodiments, the channel sacrificial dielectric can be silicon oxide or silicon nitride, etc.

[0356] A second initial memory stack 2214' is formed on the side of the first initial memory stack 2213' away from the substrate 260. A second memory channel via is formed on the second initial memory stack 2214', and the second memory channel via is connected to the first memory channel via. The channel sacrificial dielectric in the first memory channel via is removed, and a memory functional layer 2241, a channel layer 2242, and a memory channel filling dielectric 2247 are sequentially formed in the first memory channel via and the second memory channel via to form a first memory channel structure 2244 and a second memory channel structure 2245.

[0357] In some embodiments, the storage channel plug 2246 may be formed using the following method.

[0358] The storage channel filling medium 2247 of the second storage channel structure 2245, away from the end of the first storage channel structure 2244, is etched to form a storage channel window. A storage channel plug 2246 is formed within the storage channel window, enabling the storage channel plug 2246 to make electrical contact with the channel layer 2242. In some embodiments, such as Figure 43 As shown, the initial stacked structure 210' further includes a selection stacked structure 222. The selection stacked structure 222 is located on the side of the initial storage stacked structure 221' away from the substrate 260. The structure and materials of the selection stacked structure 222 have been illustrated in the above embodiments of this disclosure and will not be repeated here. The method of forming the selection stacked structure 222 will be described below.

[0359] In some embodiments, an insulating dielectric layer 2221, a first conductive layer 2222, and a second dielectric layer 2223 may be sequentially formed on the side of the initial storage stack 221' away from the substrate 260. For example... Figure 42 As shown, the insulating dielectric layer 2221, the first conductive layer 2222, and the second dielectric layer 2223 extend from the core region to the non-core region.

[0360] Using the insulating dielectric layer 2221 as the etching stop layer, the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region are removed. For example, dry etching or wet etching can be used to remove the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region.

[0361] Understandably, after the first conductive layer 2222 and the second dielectric layer 2223 in the non-core region are removed, a height difference exists between the surface of the core region away from the substrate 260 (that is, the surface of the second dielectric layer 2223 away from the substrate 260) and the surface of the non-core region away from the substrate 260 (that is, the surface of the insulating dielectric layer 2221 away from the substrate 260).

[0362] In some implementations, such as Figure 42 As shown, a filling layer 208 can be formed on the side of the insulating dielectric layer 2221 away from the initial storage stack structure 221'. The side of the filling layer 208 away from the insulating dielectric layer 2221 is flush or nearly flush with the side of the second dielectric layer 2223 away from the insulating dielectric layer 2221. That is, the surface of the core region away from the substrate 260 is flush or nearly flush with the surface of the non-core region away from the substrate 260, thereby improving the structural regularity of the semiconductor structure 200.

[0363] For example, a filler layer 208 is formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0364] In other embodiments, the filling layer 208 may be omitted, and instead, the first dielectric layer 250 may be used to fill the side of the insulating dielectric layer 2221 away from the substrate 260, so that the side of the first dielectric layer 250 away from the substrate 260 is a smooth planar structure.

[0365] The following example illustrates the manufacturing method of selecting channel structure 225.

[0366] For example, a selection channel via can be formed in the selection stack structure 222, penetrating the selection stack structure 222 in a direction perpendicular to the substrate 260, so that the storage channel plug 2246 can be exposed. An insulating layer 2251, a second conductive layer 2252, and a selection channel filling dielectric 2254 are sequentially formed in the selection channel via to form the selection channel structure 225.

[0367] In some embodiments, selective channel vias can be formed using either dry etching or wet etching processes. The insulating layer 2251 and the second conductive layer 2252 can be formed using any of the following thin film deposition processes: CVD, PVD, and ALD.

[0368] In some embodiments, etching can be used to remove a portion of the select channel filling medium 2254 away from the end of the select channel structure 225 away from the storage channel structure 224 to form a select channel window. A select channel plug 2253 is formed within the select channel window, such that the select channel plug 2253 can make electrical contact with the second conductive layer 2252.

[0369] The method for forming substrate 201 is illustrated below with an example.

[0370] As can be seen from the above, the substrate 260 can be a composite substrate. In some embodiments, such as Figure 43 As shown, the semiconductor structure 200 also includes a first etch barrier layer 265 and a second etch barrier layer 205'. The first etch barrier layer 265 and the second etch barrier layer 205' are located between the substrate 260 and the initial memory stack structure 221'. The first etch barrier layer 265 is disposed on one side of the composite substrate, and the second etch barrier layer 205' is disposed on the side of the first etch barrier layer 265 away from the composite substrate.

[0371] For example, the first etch barrier layer 265 and the second etch barrier layer 205' can be formed using any of the thin film deposition processes of CVD, PVD, and ALD. For example, the material of the first etch barrier layer 265 can be silicon oxide, and the material of the second etch barrier layer 205' can be polysilicon.

[0372] In some embodiments, the first etch stop layer 265 can be used as an etch stop layer to remove the composite substrate, thereby exposing the first etch stop layer 265. The second etch stop layer 205' can be used as an etch stop layer to remove the first etch stop layer 265 and the memory functional layer 2241 of the memory channel structure 224 away from the end of the select channel structure 225, thereby exposing the channel layer 2242 of the memory channel structure 224 away from the end of the select channel structure 225.

[0373] A source layer SL is formed, such that the channel layer 2242 of the memory channel structure 224 away from the end of the select channel structure 225, and the memory channel filling medium 2247 filled in the channel layer 2242 can be embedded in the source layer SL. The source layer SL is electrically contacted with the end of the memory channel structure 224 away from the select channel structure 225, so that the substrate 260 can form the substrate 201, and the second etch barrier layer 205' can form the semiconductor structure layer 205.

[0374] For example, a dry etching process or a wet etching process can be used to remove the composite substrate and the first etch barrier layer 265.

[0375] Figure 44 This is a structural diagram of the first dielectric layer according to some embodiments. Figure 45 This is a structural diagram of a semiconductor structure according to some other embodiments.

[0376] As described above, the semiconductor structure 200 also includes a channel structure 223. The channel structure 223 is located in the core region and extends through the initial stacked structure 210'.

[0377] In some embodiments, the method for fabricating the semiconductor structure 200 further includes: A second opening is formed on the first dielectric film to fabricate the first dielectric layer. The second opening exposes the end of the channel structure away from the substrate.

[0378] like Figure 44 As shown, a second opening 252 is formed on the first dielectric film 250' to fabricate the first dielectric layer 250. Furthermore, the second opening 252 exposes the end of the channel structure 223 away from the substrate 260. It is understood that when the channel structure 223 includes a storage channel structure 224 and a select channel structure 225, the second opening 252 can expose the end of the select channel structure 225 away from the storage channel structure 224.

[0379] In some embodiments, the second opening 252 can be formed using either dry etching or wet etching. It is understood that when the second opening 252 is formed using either dry etching or wet etching, some impurities will form within the second opening 252. Therefore, in some embodiments, after the second opening 252 is formed, it can be cleaned using methods such as wet etching or acid etching to remove the impurities within the second opening 252.

[0380] In the embodiments of this disclosure, a first opening 251 and a second opening 252 are formed on the first dielectric film 250' to prepare the first dielectric layer 250. That is, the first dielectric layer 250 does not include any other film layer structures besides the first dielectric film 250'. In this way, it is not necessary to perform repeated deposition or planarization processes on the first dielectric film 250', which simplifies the fabrication process of the semiconductor structure 200 and reduces the production cost of the semiconductor structure 200.

[0381] Furthermore, since no other film layer structure needs to be formed on the first dielectric film 250', the thickness of the first dielectric film 250' is reduced, which facilitates the formation of the second opening 252 on the first dielectric film 250', that is, facilitates the preparation of the first dielectric layer 250, and further improves the convenience of the preparation method of the semiconductor structure 200.

[0382] The step of forming the conductive plug also includes: A channel contact is formed, and the channel contact makes electrical contact with the end of the channel structure near the first dielectric layer.

[0383] like Figure 45 As shown, while forming the conductive plug 240, a channel contact 226 is formed in the second opening 252, so that the channel contact 226 can make electrical contact with the end of the channel structure 223 near the first dielectric layer 250, that is, the channel contact 226 can make electrical contact with the end of the channel structure 223 away from the substrate 260.

[0384] Understandably, when the channel structure 223 includes a storage channel structure 224 and a selection channel structure 225, the channel contact 226 can make electrical contact with the end of the selection channel structure 225 that is away from the storage channel structure 224.

[0385] It should be noted that in the embodiments of this disclosure, the conductive plug 240 and the channel contact 226 are formed simultaneously, which is understood to mean that the conductive plug 240 and the channel contact 226 are formed in the same step, rather than being limited to the two needing to be formed at the same "moment".

[0386] In the embodiments of this disclosure, the channel contact 226 is formed simultaneously with the conductive plug 240, further simplifying the fabrication process of the semiconductor structure 200 and reducing its production cost. Furthermore, since both the conductive plug 240 and the channel contact 226 are embedded within the first dielectric layer 250, it is not necessary to deposit other film structures on the side of the first dielectric layer 250 away from the substrate 260 to achieve electrical connection between the gate layer 2211 and the channel structure 223 and the outside, further simplifying the structure of the semiconductor structure 200, thereby simplifying the manufacturing process of the semiconductor structure 200 and reducing its production cost.

[0387] In some embodiments, after forming the conductive plug 240 and the channel contact 226, a CMP process can be used to planarize the side of the conductive plug 240 away from the substrate 260, the side of the channel contact 226 away from the substrate 260, and the side of the first dielectric layer 250 away from the substrate 260, so that the three sides of the conductive plug 240 away from the substrate 260, the side of the channel contact 226 away from the substrate 260, and the side of the first dielectric layer 250 away from the substrate 260 can be flush or nearly flush, thereby improving the structural regularity of the semiconductor structure 200.

[0388] In some embodiments, the conductive plug 240 and the channel contact 226 are of the same layer and material.

[0389] Figure 46 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 47 This is a structural diagram of a photomask according to some embodiments.

[0390] In some implementations, such as Figure 46 As shown, the step of forming the second opening on the first dielectric film includes: Step S301: A mask is formed on the side of the first dielectric film away from the initial stacked structure, and the mask has etching openings.

[0391] like Figure 47As shown, before forming the second opening 252, a mask 274 can be formed on the side of the first dielectric film 250' away from the initial stacked structure 210', so that the mask 274 can cover the first dielectric film 250', the second portion 232 and the insulating material 203 filled in the second portion 232.

[0392] Step S302: A second opening is formed on the first dielectric film using the etching opening of the mask.

[0393] like Figure 47 As shown, the photomask 274 has an etching opening 2743. The first dielectric film 250' is etched through the etching opening 2743 to create a second opening 252 in the first dielectric film 250', thus fabricating the first dielectric layer 250. For example, the second opening 252 can be formed by dry etching or wet etching.

[0394] Understandably, by setting the mask 274, the parts of the first dielectric film 250' that do not need to be etched (that is, the parts other than the second opening 252), the second part 232, and the insulating material 203 filled in the second part 232 can be protected, so as to avoid damage to the first dielectric film 250', the second part 232, and the insulating material 203 filled in the second part 232 during the etching process, thereby improving the reliability of the semiconductor structure 200 fabrication method.

[0395] In some embodiments, after the second opening 252 is formed, the mask 274 can be removed to prevent the mask 274 from affecting the formation of the channel contact 226. For example, a CMP process can be used to remove the mask 274.

[0396] Figure 48 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments. Figure 49 This is a structural diagram of a mask according to some other embodiments.

[0397] In some implementations, such as Figure 48 As shown, the step of forming a mask on the side of the first dielectric film away from the initial stacked structure (i.e., step S301) includes: Step S3011: A hard mask is formed, which covers the first dielectric film.

[0398] Understandably, such as Figure 49 As shown, a hard mask 2741 is formed on the side of the first dielectric film 250' away from the initial stacked structure 210', so that the hard mask 2741 can cover the first dielectric film 250'.

[0399] Understandably, the hard mask 2741 has high rigidity. For example, the material of the hard mask 2741 can be polycrystalline silicon, alumina, or other metals. In some embodiments, the hard mask 2741 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0400] Step S3012: A photoresist film is formed, which covers the hard mask.

[0401] like Figure 49 As shown, a photoresist film 2742 (PR) is formed on the side of the hard mask 2741 away from the initial stacked structure 210', so that the photoresist film 2742 can cover the hard mask 2741. For example, the photoresist film 2742 can be formed using any of the thin film deposition processes of CVD, PVD, and ALD.

[0402] Understandably, because the hard mask 2741 has high rigidity, it can support the photoresist film 2742.

[0403] Step S3013: Form an etching opening that penetrates the photoresist film and the hard mask.

[0404] In some embodiments, the photoresist film 2742 may be exposed, and the exposed photoresist film 2742 may be developed to remove the unexposed photoresist film 2742 in order to pattern the photoresist film 2742, that is, to form an opening through the photoresist film 2742.

[0405] Using the patterned photoresist film 2742 as a mask, the hard mask 2741 is etched to form the patterned hard mask 2741, such as... Figure 47 As shown, an etching opening 2743 is formed that penetrates the hard mask 2741 and the photoresist film 2742.

[0406] Understandably, since the first contact hole 263 penetrates the first dielectric film 250', the first opening 251 is formed when the first contact hole 263 is formed. In this way, only the etching opening 2743 needs to be formed on the mask 274 in the core area, without needing to form etching openings 2743 on the mask 274 in the non-core area. This reduces the number of etching openings 2743 on the mask 274, facilitating the patterning of the photoresist film 2742 and the hard mask 2741, thereby further simplifying the fabrication process of the semiconductor structure 200 and reducing its production cost.

[0407] As can be seen from the above, in some embodiments, when the first sub-film 2711 is used as the etching stop layer of the insulating material 203, after removing the first sub-film 2711 covering the first dielectric film 250', the end of the second sub-film 2712 that is away from the substrate 260 and extends beyond the first dielectric film 250' can be removed using a CMP process. When the stop layer 273 is used as the etching stop layer of the insulating material 203, after removing the first stop layer 2731 covering the first dielectric film 250', the end of the fourth sub-film 2723 that is away from the substrate 260 and extends beyond the first dielectric film 250' can also be removed using a CMP process.

[0408] Therefore, in some embodiments of this disclosure, after removing the etching stop layer (e.g., the first sub-film 2711 or the first stop layer 2731) of the insulating material 203, a planarization process can be performed using CMP, so that the end of the second portion 232 away from the substrate 260 can be flush or approximately flush with the side of the first dielectric film 250' away from the substrate 260.

[0409] In other embodiments of this disclosure, planarization may not be performed after removing the etching stop layer (e.g., the first sub-film 2711 or the first stop layer 2731) of the insulating material 203. In this way, as... Figure 39 As shown (taking the first stop layer 2731 as an etching stop layer as an example), the end of the fourth sub-film 2723 on the side away from the substrate 260 protrudes from the surface of the first dielectric film 250' on the side away from the substrate 260.

[0410] Figure 50 This is a structural diagram of a mask according to some other embodiments. Figure 51 This is a structural diagram of a mask according to some other embodiments. Figure 52 This is a structural diagram of the fourth submembrane according to some other embodiments.

[0411] like Figure 50 As shown, in some other embodiments of this disclosure, no planarization process is performed after the first stop layer 2731 is removed, so that when the mask 274 is formed on the side of the first dielectric film 250' away from the initial stacked structure 210', the end of the fourth sub-film 2723 on the side away from the substrate 260 can extend into the mask 274.

[0412] like Figure 51 As shown, an etching opening 2743 is formed that penetrates the hard mask 2741 and the photoresist film 2742, and a second opening 252 is formed through the etching opening 2743 to prepare the first dielectric layer 250.

[0413] like Figure 52As shown, in some embodiments, after removing the hard mask 2741 and the photoresist film 2742, a CMP process can be used to planarize the end of the fourth sub-film 2723 on the side away from the substrate 260 to form the second portion 232.

[0414] In other embodiments, after forming the channel contact 226, the end of the fourth sub-film 2723 on the side away from the substrate 260 may be planarized to form the second portion 232.

[0415] Figure 53 This is a flowchart of the steps for fabricating a semiconductor structure according to some other embodiments.

[0416] In some implementations, such as Figure 53 As shown, after the step of forming the conductive plug, the process further includes: Step S401: A gate line slot is formed that runs through the initial stack structure. One gate line slot divides the core of an initial stack structure into two initial memory blocks.

[0417] Understandably, such as Figure 5 As shown, the gate line slot 206 extends through the initial stack structure 210' in a direction perpendicular to the substrate 260, separating the two initial memory blocks 220' with the core region of the initial stack structure 210'. For example, the gate line slot 206 extends from the core region to the non-core region.

[0418] In step S402, the gate sacrificial layer is replaced with a gate layer through the gate line gap to form a stacked structure and a memory block. The gate layer is in electrical contact with the first portion.

[0419] In some embodiments, dry etching or wet etching can be used to remove the gate sacrificial layer 2215 through the gate line gaps 206 to form spaced cavities. Then, the gate layer 2211 is formed in the cavities again through the gate line gaps 206 to form the stacked structure 210 and the memory block 220.

[0420] Understandably, the first portion 231 of the conductive structure 230 is disposed in the same layer as and in contact with a gate sacrificial layer 2215, so that after the gate sacrificial layer 2215 is replaced with the gate layer 2211, the gate layer 2211 can make electrical contact with the first portion 231.

[0421] Figure 54 This is a structural diagram of the first gate layer according to some embodiments. Figure 55 This is a structural diagram of the first gate layer and the second gate layer according to some embodiments.

[0422] As can be seen from the above, in some embodiments, the gate wire gaps 206 can be formed after the conductive plug 240 is formed. In other embodiments, the process further includes: A gate line slot is formed that runs through the initial stack structure, and a gate line slot divides the core of an initial stack structure into two initial memory blocks.

[0423] By using the gate line gaps, the gate sacrificial layer located in the core region is replaced with the first gate layer.

[0424] Understandably, before forming the conductive structure 230, a gate line gap 206 is formed that penetrates the initial stacked structure 210', such as... Figure 54 As shown, the gate sacrificial layer 2215 in the core region of the initial stacked structure 210' is replaced with the first gate layer 2211c through the gate line gap 206, while the gate sacrificial layer 2215 in the non-core region is retained.

[0425] Following the step of forming the conductive plug, the following is also included: By using the gate line gaps, a portion of the gate sacrificial layer that is co-layered with and in contact with the first portion is replaced with a second gate layer to form a stacked structure and a memory block. The second gate layer is in electrical contact with both the first gate layer and the first portion.

[0426] After forming the conductive plug 240, the portion of the gate sacrificial layer 2215 located in the non-core region and in contact with the first portion 231 is replaced with the second gate layer 2211d, as follows. Figure 55 As shown, the gate sacrificial layer 2215, which is not in contact with the first part 231, is retained.

[0427] Understandably, after replacing the portion of the gate sacrificial layer 2215 located in the non-core region and in contact with the first portion 231 with the first gate layer 2211d, as follows: Figure 5 As shown, a stacked structure 210 and a storage block 220 can be formed.

[0428] Understandably, the second gate layer 2211d is electrically contacted with the first gate layer 2211c and the first portion 231, so that electrical signals can be transmitted between the second gate layer 2211d, the first gate layer 2211c and the first portion 231.

[0429] It should be noted that in the embodiments of this disclosure, the first gate layer 2211c and the second gate layer 2211d are only used to distinguish the gate layer 2211 located in the core region and the non-core region, and do not further limit the structure and material of the gate layer 2211.

[0430] Understandably, after forming the conductive plug 240, only the portion of the gate sacrificial layer 2215 located in the non-core region and in contact with the first portion 231 is replaced with the gate layer 2211, while the portion of the gate sacrificial layer 2215 that is not in contact with the first portion is retained. This arrangement enables the gate sacrificial layer 2215 to play an electrical isolation role, preventing the remaining positions of the conductive structure 230 (excluding the first portion 231) from making electrical contact with the gate layer 2211. This ensures that the gate layer 2211 can only be electrically connected to the conductive plug 240 through the first portion 231, thereby improving the reliability of the semiconductor structure 200.

[0431] Figure 56 This is a block diagram of a storage system according to some embodiments. Figure 57 This is a block diagram of a storage system according to some other embodiments.

[0432] Please see Figure 56 Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 20 and a three-dimensional memory 10 as described in some of the embodiments above, the controller 20 being coupled to the three-dimensional memory 10 to control the three-dimensional memory 10 to store data.

[0433] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0434] In some embodiments, see Figure 56 The storage system 1000 includes a controller 20 and a three-dimensional memory 10, and the storage system 1000 can be integrated into a memory card.

[0435] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0436] In other embodiments, see Figure 57 The storage system 1000 includes a controller 20 and multiple three-dimensional storage devices 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0437] In some embodiments of the storage system 1000, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0438] In other embodiments, controller 20 is configured to operate in a high duty cycle environment in an SSD or eMMC, which is used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0439] In some embodiments, controller 20 may be configured to manage data stored in 3D memory 10 and communicate with external devices (e.g., a host). In some embodiments, controller 20 may also be configured to control operations of 3D memory 10, such as read, erase, and program operations. In some embodiments, controller 20 may also be configured to manage various functions relating to data stored or to be stored in 3D memory 10, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, controller 20 is also configured to process error correction codes relating to data read from or written to 3D memory 10.

[0440] Of course, controller 20 can also perform any other suitable functions, such as formatting the three-dimensional memory 10; for example, controller 20 can communicate with external devices (e.g., hosts) through at least one of various interface protocols.

[0441] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0442] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0443] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0444] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized in that, include: The first stack structure includes a first sub-stack structure and a second sub-stack structure. The first sub-stack structure includes a first portion of a plurality of gate insulating layers and a gate sacrificial layer that are alternately stacked along a first direction. The second sub-stack structure includes a second portion of the gate insulating layers and a gate layer that are alternately stacked along the first direction. The first sub-stack structure and the second sub-stack structure are arranged in a direction perpendicular to the first direction. The gate sacrificial layer and the gate layer are disposed in the same layer. A first channel structure extends through the second sub-stack structure along the first direction and includes a first channel plug and a channel layer extending along the first direction. The second stacked structure is located on one side of the first stacked structure along the first direction and includes a first conductive layer; The second channel structure extends through the second stack structure along the first direction and includes a second conductive layer extending along the first direction, wherein the first channel plug contacts the channel layer and the second conductive layer; A conductive structure is located in the first sub-stack structure and includes a first conductive portion extending along the first direction and a second conductive portion extending along the second direction and contacting a gate layer, wherein the first conductive portion is in contact with the second conductive portion, and the second direction is perpendicular to the first direction; A conductive plug, in contact with the first conductive portion, wherein the conductive plug and the conductive structure enclose a receiving cavity; and Insulating material is filled into the cavity.

2. The semiconductor structure according to claim 1, characterized in that, The receiving cavity includes an air gap, and the insulating material surrounds the air gap.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: The first dielectric layer is located on the side of the second stacked structure away from the first stacked structure along the first direction; as well as The channel contact penetrates the first dielectric layer along the first direction and contacts the second channel structure.

4. The semiconductor structure according to claim 3, characterized in that, The conductive plug and the channel contact are made of the same material. The conductive plug includes a first end portion, which is located away from the second conductive portion relative to the insulating material. The channel contact includes a second end that contacts the second channel structure and a third end that is disposed opposite to the second end along the first direction. The first end of the conductive plug and the third end of the channel contact are approximately flush.

5. The semiconductor structure according to claim 1, characterized in that, The second stacked structure further includes a first insulating layer and a second dielectric layer. The first conductive layer is located between the first insulating layer and the second dielectric layer. The insulating dielectric layer is in contact with one of the gate insulating layers in the first stacked structure, and The second dielectric layer is in contact with the first dielectric layer.

6. The semiconductor structure according to claim 5, characterized in that, The first conductive layer is in contact with the first insulating layer and the first dielectric layer.

7. The semiconductor structure according to claim 5, characterized in that, The material of the first insulating layer includes silicon oxide. The material of the first conductive layer includes polycrystalline silicon, and The material of the second dielectric layer includes silicon nitride.

8. The semiconductor structure according to claim 1, characterized in that, The second channel structure further includes a second insulating layer, which is located between the second stack structure and the second conductive layer in the second direction.

9. The semiconductor structure according to claim 1 or 8, characterized in that, The second channel structure further includes a second channel plug and a filling medium, wherein the filling medium is located within the accommodating space formed by the second channel plug and the second conductive layer.

10. The semiconductor structure according to claim 1, characterized in that, The channel layer, the second conductive layer, and the first channel plug all comprise polycrystalline silicon.

11. The semiconductor structure according to claim 1, characterized in that, Also includes: A source layer is located on the side of the first stack structure away from the second stack structure along the first direction, wherein the channel layer is in contact with the source layer.

12. The semiconductor structure according to claim 11, characterized in that, Also includes: The channel layer includes two ends disposed opposite to each other along the first direction, one of the ends being in contact with the first channel plug, and the other end being located in the source layer and in contact with the source layer.

13. The semiconductor structure according to claim 1 or 11, characterized in that, Also includes: The peripheral circuit is located on the side of the second stacked structure away from the first stacked structure along the first direction.

14. The semiconductor structure according to claim 1, characterized in that, Also includes The first channel structure includes a first storage channel structure and a second storage channel structure, with the second storage channel structure located between the first storage channel structure and the second channel structure.

15. The semiconductor structure according to claim 14, characterized in that, The first storage channel structure includes a first end and a second end disposed along the first direction. The second storage channel structure includes a third end and a fourth end disposed along the first direction. The second end of the first storage channel structure contacts the third end of the second storage channel structure. The dimension of the second end of the first storage channel structure along the second direction is greater than the dimension of the third end of the second storage channel structure along the second direction.

16. The semiconductor structure according to claim 1, characterized in that, The material of the gate layer includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The gate insulating layer is made of at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides and their silicates, and organic insulating materials. The material of the gate sacrificial layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. The material of the gate insulating layer is different from the material of the gate sacrificial layer.

17. A semiconductor structure, characterized in that, include: A first stacked structure, the first stacked structure comprising a plurality of gate insulating layers and gate layers alternately stacked along a first direction; A first channel structure extends through the first stack structure along the first direction and includes a first channel plug and a channel layer extending along the first direction. The second stacked structure is located on one side of the first stacked structure along the first direction and includes a first conductive layer; The second channel structure extends through the second stack structure along the first direction and includes a second conductive layer extending along the first direction, wherein the first channel plug contacts the channel layer and the second conductive layer; A conductive structure is located in the first stacked structure and includes a first conductive portion extending along the first direction and a second conductive portion extending along the second direction and contacting a gate layer, wherein the first conductive portion is in contact with the second conductive portion, and the second direction is perpendicular to the first direction; A conductive plug, in contact with the first conductive portion, the conductive plug and the conductive structure forming a receiving cavity; and Insulating material is filled into the cavity.

18. The semiconductor structure according to claim 17, characterized in that, Also includes: An electrical isolation layer is located between the first conductive portion and the first stacked structure.

19. The semiconductor structure according to claim 17, characterized in that, The receiving cavity includes an air gap, and the insulating material surrounds the air gap.

20. The semiconductor structure according to claim 17, characterized in that, Also includes: The first dielectric layer is located on the side of the second stacked structure away from the first stacked structure along the first direction; as well as The channel contact penetrates the first dielectric layer along the first direction and contacts the second channel structure.

21. The semiconductor structure according to claim 20, characterized in that, The conductive plug and the channel contact are made of the same material. The conductive plug includes a first end portion, which is located away from the second conductive portion relative to the insulating material. The channel contact includes a second end that contacts the second channel structure and a third end that is disposed opposite to the second end along the first direction. The first end of the conductive plug and the third end of the channel contact are approximately flush.

22. The semiconductor structure according to claim 17, characterized in that, The second stacked structure further includes a first insulating layer and a second dielectric layer. The first conductive layer is located between the first insulating layer and the second dielectric layer. The insulating dielectric layer is in contact with one of the gate insulating layers in the first stacked structure, and The second dielectric layer is in contact with the first dielectric layer.

23. The semiconductor structure according to claim 22, characterized in that, The first conductive layer is in contact with the first insulating layer and the first dielectric layer.

24. The semiconductor structure according to claim 22, characterized in that, The material of the first insulating layer includes silicon oxide. The material of the first conductive layer includes polycrystalline silicon, and The material of the second dielectric layer includes silicon nitride.

25. The semiconductor structure according to claim 17, characterized in that, The second channel structure further includes a second insulating layer, which is located between the second stack structure and the second conductive layer in the second direction.

26. The semiconductor structure according to claim 17 or 25, characterized in that, The second channel structure further includes a second channel plug and a filling medium, wherein the filling medium is located within the accommodating space formed by the second channel plug and the second conductive layer.

27. The semiconductor structure according to claim 17, characterized in that, The channel layer, the second conductive layer, and the first channel plug all comprise polycrystalline silicon.

28. The semiconductor structure according to claim 17, characterized in that, Also includes: A source layer is located on the side of the first stack structure away from the second stack structure along the first direction, wherein the channel layer is in contact with the source layer.

29. The semiconductor structure according to claim 27, characterized in that, Also includes: The channel layer includes two ends disposed opposite to each other along the first direction, one of the ends being in contact with the first channel plug, and the other end being located in the source layer and in contact with the source layer.

30. The semiconductor structure according to claim 1 or 27, characterized in that, Also includes: The peripheral circuit is located on the side of the second stacked structure away from the first stacked structure along the first direction.

31. The semiconductor structure according to claim 17, characterized in that, Also includes The first channel structure includes a first storage channel structure and a second storage channel structure, with the second storage channel structure located between the first storage channel structure and the second channel structure.

32. The semiconductor structure according to claim 30, characterized in that, The first storage channel structure includes a first end and a second end disposed along the first direction. The second storage channel structure includes a third end and a fourth end disposed along the first direction. The second end of the first storage channel structure contacts the third end of the second storage channel structure. The dimension of the second end of the first storage channel structure along the second direction is greater than the dimension of the third end of the second storage channel structure along the second direction.

33. The semiconductor structure according to claim 17, characterized in that, The material of the gate layer includes at least one of tungsten, cobalt, copper, aluminum, doped polysilicon, and metal silicides. The gate insulating layer is made of at least one of the following materials: silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides and their silicates, and organic insulating materials. The material of the gate sacrificial layer includes one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, amorphous silicon, amorphous carbon, and polycrystalline silicon. The material of the gate insulating layer is different from the material of the gate sacrificial layer.

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