Semiconductor device

Abstract

Embodiments of the invention generally relate to semiconductor devices. According to one embodiment, a semiconductor device includes an element region and a terminal region surrounding the element region. The element region includes a silicon carbide region of a first conductivity type, a silicon carbide layer having a plurality of silicon carbide regions of a second conductivity type, and a gate electrode. The terminal region includes a silicon carbide layer having a silicon carbide region of the first conductivity type, a first silicon carbide region of the second conductivity type located outside the plurality of silicon carbide regions of the second conductivity type, and a second silicon carbide region of the second conductivity type spaced apart from the first silicon carbide region and surrounding the first silicon carbide region. In the terminal region, one contact portion of the wiring layer is connected to the first silicon carbide region, and the other contact portion of the wiring layer is connected to the second silicon carbide region. The second conductivity type impurity concentration of a portion where one contact portion is connected to the first silicon carbide region is lower than the second conductivity type impurity concentration of a portion where the other contact portion is connected to the second silicon carbide region.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority from Japanese Patent Application No. 2024-164903 (Filing Date: September 24, 2024). This application incorporates the entire contents of the base application by reference thereto. TECHNICAL FIELD

[0003] Embodiments of the present application generally relate to semiconductor devices. BACKGROUND

[0004] A longitudinal type metal oxide semiconductor field effect transistor (MOSFET) using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, even if the MOSFET is in an off state, by using the pn junction diode, a backflow current can flow.

[0005] However, if the backflow current flows using the pn junction diode that performs a bipolar operation, a stacking defect grows in the silicon carbide layer by recombination energy of carriers. If the stacking defect grows in the silicon carbide layer, there is a problem that an on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET causes a decrease in reliability of the MOSFET. For example, a Schottky barrier diode (SBD) that performs a unipolar operation is provided as a built-in diode in the MOSFET, whereby growth of the stacking defect in the silicon carbide layer can be suppressed. SUMMARY

[0006] A semiconductor device of an embodiment has an element region and an end region surrounding the element region. The element region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer provided between the first electrode and the second electrode, having a first surface on the first electrode side and a second surface on the second electrode side, a first silicide layer provided between an eighth silicon carbide region and the first electrode, and a gate insulating layer provided between the gate electrode and a fifth silicon carbide region and between the gate electrode and a first portion. The silicon carbide layer of the element region includes a first silicon carbide region of a first conductivity type, having the first portion in contact with the first surface and facing the gate electrode, and a second portion in contact with the first surface and in contact with the first electrode, a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface, a third silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, provided on the end region side than the second silicon carbide region, and electrically connected to the first electrode, a fourth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, provided between the second silicon carbide region and the third silicon carbide region, facing the gate electrode, and electrically connected to the first electrode, the fifth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, provided between the second silicon carbide region and the fourth silicon carbide region, facing the gate electrode, and electrically connected to the first electrode, a sixth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, provided between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and shallower in depth than the third silicon carbide region and the fourth silicon carbide region, a seventh silicon carbide region of the first conductivity type provided between the fifth silicon carbide region and the first surface, and electrically connected to the first electrode, and the eighth silicon carbide region of the second conductivity type provided between the sixth silicon carbide region and the first surface, having a higher second conductivity type impurity concentration than the sixth silicon carbide region. The end region includes a wiring layer electrically connected to the first electrode, the second electrode, the silicon carbide layer, and a second silicide layer provided between an eleventh silicon carbide region and the wiring layer. The silicon carbide layer includes the first silicon carbide region having a third portion in contact with the first surface and in contact with the wiring layer, a ninth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, surrounding the element region, and in contact with the third silicon carbide region, and a tenth silicon carbide region of the second conductivity type provided between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separated from the ninth silicon carbide region, and electrically connected to the wiring layer.The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The end region further includes a third silicide layer, which is disposed between the ninth silicon carbide region and the first surface and contacts the ninth silicon carbide region. The wiring layer further includes a fifth contact portion that contacts the third silicide layer.

[0007] According to this embodiment, a semiconductor device capable of suppressing the growth of stacking defects can be provided. Attached Figure Description

[0008] Figure 1 of (a), Figure 1 (b) is a schematic top view of the semiconductor device according to the first embodiment.

[0009] Figure 2 of (a), Figure 2 (b) is a schematic top view of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0011] Figure 4 This is an equivalent circuit diagram of the semiconductor device according to the first embodiment.

[0012] Figure 5 This is a schematic cross-sectional view of a comparative example semiconductor device.

[0013] Figure 6 This is an explanatory diagram of a comparative example semiconductor device.

[0014] Figure 7 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0015] Figure 8 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment.

[0016] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0017] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to a variation of the second embodiment.

[0018] Figure 11This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0019] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0020] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment. Detailed Implementation

[0021] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Furthermore, in the following description, the same or similar components will be labeled with the same reference numerals, and descriptions of components that have already been described once will sometimes be appropriately omitted.

[0022] Additionally, in the following explanation, when there exists n + n, n － and p + p, p － In the case of markings, these markings indicate the relative levels of impurity concentration in each conductivity type. That is, n + This indicates that the concentration of n-type impurities is relatively high compared to n. － This indicates that the concentration of n-type impurities is relatively low compared to n. Additionally, p... + This indicates that the concentration of p-type impurities is relatively high compared to p-type impurities. － This indicates that the concentration of p-type impurities is relatively low compared to p-type impurities. Additionally, sometimes n-type impurities are used... + type, n － The type is abbreviated as n-type, and p + Type, p － The type is abbreviated as p-type.

[0023] Furthermore, in this specification, unless otherwise stated, "impurity concentration" refers to the concentration after compensating for the concentration of impurities of the opposite conductivity type. That is, the n-type impurity concentration of an n-type silicon carbide region is the concentration obtained by subtracting the p-type impurity concentration from the n-type impurity concentration. Similarly, the p-type impurity concentration of a p-type silicon carbide region is the concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. Additionally, in this specification, unless otherwise stated, "impurity concentration of a silicon carbide region" refers to the maximum impurity concentration of the corresponding silicon carbide region.

[0024] Impurity concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). Furthermore, the relative levels of impurity concentration can be determined, for example, by the carrier concentration obtained through scanning capacitance microscopy (SCM). Additionally, the depth, thickness, and spacing of impurity regions can be determined, for example, by SIMS or scanning electron microscopy (SEM). Furthermore, the depth, thickness, width, and spacing of impurity regions can be determined, for example, by using a composite image of an SCM image and an atomic force microscope (AFM) image.

[0025] (First Implementation)

[0026] The semiconductor device of the first embodiment has a device region and an end region surrounding the device region. The device region includes a first electrode, a second electrode, a gate electrode, a silicon carbide layer, a first silicide layer, and a gate insulating layer. The silicon carbide layer is disposed between the first electrode and the second electrode, and has a first surface on the first electrode side and a second surface on the second electrode side. The silicon carbide layer includes: a first silicon carbide region of a first conductivity type, having a first portion contacting the first surface and opposite the gate electrode, and a second portion contacting the first surface and contacting the first electrode; a second silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface; a third silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, disposed on the end region side of the second silicon carbide region, and electrically connected to the first electrode; a fourth silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, disposed between the second silicon carbide region and the third silicon carbide region, opposite the gate electrode, and electrically connected to the first electrode; and a fourth silicon carbide region of a second conductivity type. A fifth silicon carbide region is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode and electrically connected to the first electrode; a sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the fourth silicon carbide region; a seventh silicon carbide region of the first conductivity type is disposed between the fifth silicon carbide region and the first surface, and electrically connected to the first electrode; and an eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, the second conductivity type having a higher impurity concentration than the sixth silicon carbide region; a first silicide layer is disposed between the eighth silicon carbide region and the first electrode; and a gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The terminal region includes a wiring layer electrically connected to the first electrode, a second electrode, a silicon carbide layer, and a second silicide layer. The silicon carbide layer includes: a first silicon carbide region having a third portion that contacts the first surface and the wiring layer; a ninth silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, surrounding the component region, and contacting the third silicon carbide region; a tenth silicon carbide region of a second conductivity type, disposed between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separated from the ninth silicon carbide region, and electrically connected to the wiring layer; and an eleventh silicon carbide region of a second conductivity type, disposed between the tenth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer.The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The end region also includes a third silicide layer disposed between the ninth silicon carbide region and the first surface and in contact with the ninth silicon carbide region. The wiring layer also includes a fifth contact portion that contacts the third silicide layer.

[0027] Figure 1 of (a), Figure 1 (b) is a schematic top view of the semiconductor device according to the first embodiment. Figure 1 (a) represents the layout pattern of the component area and the end area. Figure 1 (b) represents the layout pattern of the source electrode, source electrode wiring layer, gate pad electrode and gate electrode wiring layer.

[0028] Figure 2 of (a), Figure 2 (b) is a schematic top view of the semiconductor device according to the first embodiment. Figure 2 (a) represents the layout pattern of the component area and the end area. Figure 2 (b) represents the layout pattern of the gate electrode, gate interconnect layer and gate pad layer.

[0029] Figure 3 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 3 yes Figure 1 , Figure 2 The AA' section shown.

[0030] The semiconductor device of the first embodiment is a planar gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 is, for example, a dual-injection MOSFET (DIMOSFET) in which the substrate region and source region are formed by ion implantation. Furthermore, the semiconductor device of the first embodiment has an SBD as a built-in diode.

[0031] The following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. MOSFET 100 is a vertical n-channel MOSFET that uses electrons as charge carriers.

[0032] The MOSFET 100 has a silicon carbide layer 10, a source electrode 12 (first electrode), a source electrode wiring layer 13 (wiring layer), a first silicide layer 14a, a second silicide layer 14b, a third silicide layer 14c, a drain electrode 15 (second electrode), a gate insulating layer 16, a gate electrode 18, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26.

[0033] The source electrode 12 includes a first contact portion 12x and a second contact portion 12y. The source electrode wiring layer 13 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0034] Hereinafter, the first silicide layer 14a, the second silicide layer 14b, and the third silicide layer 14c are sometimes referred to individually or collectively as silicide layer 14.

[0035] The silicon carbide layer 10 contains n + The n-type drain region 30, the n-type drift region 31 (first silicon carbide region), the p-type peripheral p-region 32 (third silicon carbide region), the p-type first substrate region 33a (fourth silicon carbide region), the p-type second substrate region 33b (fifth silicon carbide region), the p-type third substrate region 33c (second silicon carbide region), the p-type first p-region 34 (sixth silicon carbide region), and the n-type... + Type 35 source region (seventh silicon carbide region), p + The first high-concentration p-region 36 (eighth silicon carbide region) of the p-type, the second p-region 37 (ninth silicon carbide region) of the p-type, the third p-region 38 (tenth silicon carbide region) of the p-type, p + The second high-concentration p-region 39 (eleventh silicon carbide region) of the p-type and the fourth p-region 40 (twelfth silicon carbide region) of the p-type. The drift region 31 (first silicon carbide region) of the n-type has n － The n-type drift region 31a (low concentration region) has a low concentration region and the n-type drift region 31b (high concentration region). The n-type drift region 31 has a first part 31x, a second part 31y, and a third part 31z.

[0036] Hereinafter, the first substrate region 33a (fourth silicon carbide region), the second substrate region 33b (fifth silicon carbide region), and the third substrate region 33c (second silicon carbide region) are sometimes referred to individually or collectively as substrate region 33.

[0037] The MOSFET 100 has a device region 101 and an end region 102. The end region 102 surrounds the device region 101.

[0038] Component region 101 contains multiple MOSFETs and multiple SBDs. End region 102 contains SBDs.

[0039] When the MOSFET 100 is in the off state, the end region 102 mitigates the intensity of the electric field applied to the end of the pn junction of the element region 101. The end region 102 also has the function of increasing the insulation breakdown voltage of the MOSFET 100.

[0040] The device region 101 includes a silicon carbide layer 10, a source electrode 12, a first silicide layer 14a, a drain electrode 15, a gate insulating layer 16, a gate electrode 18, a field insulating layer 24, and an interlayer insulating layer 26. The source electrode 12 of the device region 101 includes a first contact portion 12x and a second contact portion 12y.

[0041] The silicon carbide layer 10 of the component region 101 contains n + The n-type drain region 30, the n-type drift region 31 (first silicon carbide region), the p-type peripheral p-region 32 (third silicon carbide region), the p-type first substrate region 33a (fourth silicon carbide region), the p-type second substrate region 33b (fifth silicon carbide region), the p-type third substrate region 33c (second silicon carbide region), the p-type first p-region 34 (sixth silicon carbide region), and the n-type... + Type 35 source region (seventh silicon carbide region), p + The first high-concentration p-region 36 (eighth silicon carbide region) of the type. The drift region 31 of the element region 101 has n － The low-concentration region 31a of type n and the high-concentration region 31b of type n. The drift region 31 of element region 101 has a first part 31x and a second part 31y.

[0042] The terminal region 102 includes a silicon carbide layer 10, a source electrode wiring layer 13, a second silicide layer 14b, a third silicide layer 14c, a drain electrode 15, a gate connection layer 20, a gate pad layer 21, a gate electrode pad 22, a gate electrode wiring layer 23, a field insulating layer 24, and an interlayer insulating layer 26. The source electrode wiring layer 13 of the terminal region 102 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0043] The silicon carbide layer 10 of the end region 102 contains n + The drain region 30 of the n-type, the drift region 31 of the n-type (first silicon carbide region), the second p-type region 37 of the p-type (ninth silicon carbide region), the third p-type region 38 of the p-type (tenth silicon carbide region), and the p-type... + The second high-concentration p-region 39 (eleventh silicon carbide region) of the p-type and the fourth p-region 40 (twelfth silicon carbide region) of the p-type. The drift region 31 of the terminal region 102 has a third part 31z.

[0044] A silicon carbide layer 10 is disposed between the source electrode 12 and the drain electrode 15. The silicon carbide layer 10 is a single crystal SiC. For example, the silicon carbide layer 10 is 4H-SiC.

[0045] The silicon carbide layer 10 has a first surface ( Figure 3 (F1) and the second side ( Figure 3(F2). The first surface F1 is the surface of the silicon carbide layer. The second surface F2 is the back surface of the silicon carbide layer. Hereinafter, the first surface F1 is sometimes referred to as the surface, and the second surface F2 as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 15 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 are opposite each other. Furthermore, below, "depth" refers to the depth in the direction towards the second surface, with the first surface as a reference. Additionally, the "surface" of the first surface F1 and the second surface F2, for example, refers to the interface between the silicon carbide layer and the insulating film, or between the silicon carbide layer and a metal.

[0046] The first surface is parallel to both the first and second directions. The second direction is perpendicular to the first direction.

[0047] The first surface F1 is, for example, a surface tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (0001) surface. The second surface F2 is, for example, a surface tilted at an angle of 0 degrees or more but less than 8 degrees relative to the (000-1) surface. The (0001) surface is called the silicon surface. The (000-1) surface is called the carbon surface.

[0048] The thickness of the silicon carbide layer 10 is, for example, 5 μm or more and 350 μm or less.

[0049] n + A drain region 30 is disposed on the back side of the silicon carbide layer 10. The drain region 30 may contain nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 30 may be, for example, 1 × 10⁻⁶. 18 cm －3 Above and 1×10 21 cm －3 the following.

[0050] The n-type drift region 31 is disposed between the drain region 30 and the first surface F1. The n-type drift region 31 is disposed between the source electrode 12 and the drain electrode 15. The n-type drift region 31 is disposed between the gate electrode 18 and the drain electrode 15. The n-type drift region 31 is disposed above the drain region 30.

[0051] Drift region 31, for example, contains nitrogen (N) as an n-type impurity. The n-type impurity concentration in drift region 31 is lower than that in drain region 30. The n-type impurity concentration in drift region 31 is, for example, 4 × 10⁻⁶. 14 cm －3 Above and 5×10 17 cm －3 The thickness of the drift region 31 is, for example, 3 μm or more and 100 μm or less.

[0052] Drift region 31 is located in component region 101 and has n －The low-concentration region 31a is of type n, and the high-concentration region 31b is of type n. The high-concentration region 31b is located between the low-concentration region 31a and the first surface F1.

[0053] Through having n － The low-concentration region 31a of the n-type leads to an increase in the insulation breakdown voltage of, for example, MOSFET 100. Additionally, the high-concentration region 31b of the n-type leads to an increase in the on-state current of, for example, MOSFET 100.

[0054] The drift region 31 is located in the element region 101 and includes a first portion 31x and a second portion 31y. The first portion 31x and the second portion 31y are contained within the high concentration region 31b.

[0055] The first portion 31x is in contact with the first surface F1 and is opposed to the gate electrode 18 through the gate insulating layer 16. The first portion 31x functions, for example, as a current path for the MOSFET in the element region 101.

[0056] The second portion 31y is in contact with the first surface F1 and with the source electrode 12. The second portion 31y functions, for example, as a current path for the SBD of the element region 101. A silicide layer (not shown) is provided in a second direction of the second portion 31y.

[0057] The p-type substrate region 33 is disposed between the drift region 31 and the first surface F1. The substrate region 33 is disposed between the high concentration region 31b and the first surface F1.

[0058] The base region 33 extends, for example, in the second direction. For example, multiple base regions 33 are repeatedly configured in the first direction.

[0059] The base region 33 includes, for example, a first base region 33a, a second base region 33b, and a p-shaped third base region 33c. The first base region 33a is disposed between the third base region 33c and the peripheral p-region 32. The second base region 33b is disposed between the third base region 33c and the first base region 33a.

[0060] The substrate region 33 functions, for example, as the channel region of the MOSFET 100.

[0061] The width of the substrate region 33 is, for example, 0.5 μm or more and 2.0 μm or less. The width of the first substrate region 33a in the first direction is, for example, 0.5 μm or more and 2.0 μm or less.

[0062] The distance between two adjacent substrate regions 33 in the first direction is, for example, more than 0.5 μm and less than 2.0 μm. The distance between the first substrate region 33a and the second substrate region 33b in the first direction is, for example, more than 0.5 μm and less than 2.0 μm.

[0063] The depth of the substrate region 33 is, for example, more than 1.0 μm and less than 2.0 μm. By deepening the substrate region 33, the amount of current flowing in the MOSFET 100 when a short-circuit current flows is suppressed, thereby improving the short-circuit withstand capability of the MOSFET 100.

[0064] The substrate region 33 is electrically connected to the source electrode 12. The substrate region 33 is fixed at the potential of the source electrode 12.

[0065] A portion of the substrate region 33 is in contact with the first surface F1. A portion of the substrate region 33 is opposite to the gate electrode 18. For example, a portion of the first substrate region 33a is opposite to the gate electrode 18. For example, a portion of the second substrate region 33b is opposite to the gate electrode 18. A gate insulating layer 16 is sandwiched between a portion of the substrate region 33 and the gate electrode 18.

[0066] The substrate region 33, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the substrate region 33 is, for example, 5 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 the following.

[0067] The outer p-region 32 of the p-type is disposed between the drift region 31 and the first surface F1. The outer p-region 32 is disposed between the high concentration region 31b and the first surface F1.

[0068] The peripheral p-region 32 is disposed on the outer periphery of the base region 33. The peripheral p-region 32 is located on the end region 102 side of the base region 33. The peripheral p-region 32 is disposed on the end region 102 side of the third base region 33c. For example, in the first surface F1, the peripheral p-region 32 surrounds the base region 33.

[0069] The width of the peripheral p-region 32 in the first direction is, for example, more than 0.5 μm and less than 2.0 μm. The width of the peripheral p-region 32 in the first direction is substantially the same as the width of the substrate region 33 in the first direction.

[0070] The distance in the first direction between the peripheral p-region 32 and the first substrate region 33a is, for example, more than 0.5 μm and less than 2.0 μm. For example, the distance in the first direction between the peripheral p-region 32 and the first substrate region 33a is substantially equal to the distance in the first direction between two adjacent substrate regions 33.

[0071] The depth of the peripheral p-region 32 is, for example, more than 1.0 μm and less than 2.0 μm. The depth of the peripheral p-region 32 is, for example, substantially the same as the depth of the substrate region 33.

[0072] The peripheral p-region 32 is electrically connected to the source electrode 12. The peripheral p-region 32 is fixed at the potential of the source electrode 12.

[0073] The outer p-region 32 contains, for example, aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the outer p-region 32 is, for example, 5 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 The p-type impurity concentration in the peripheral p-region 32 is substantially the same as that in the substrate region 33.

[0074] The outer p-region 32 is formed, for example, by using the same manufacturing process with the same mask pattern as the base region 33.

[0075] The first p-region 34 of the p-type is disposed between the drift region 31 and the first surface F1. The first p-region 34 is disposed between the high concentration region 31b and the first surface F1.

[0076] The first p-region 34 is, for example, disposed between two adjacent base regions 33 in the first direction. The first p-region 34 is disposed between the outer peripheral p-region 32 and the first base region 33a. The first p-region 34 is in contact with the outer peripheral p-region 32 and the first base region 33a.

[0077] The first p-region 34 is disposed between the first high-concentration p-region 36 and the high-concentration region 31b. The first p-region 34 is disposed between the silicide layer 14 and the high-concentration region 31b.

[0078] The depth of the first p-region 34 is shallower than the depth of the outer p-region 32 and the depth of the base region 33. The depth of the first p-region 34 is, for example, shallower than the depth of the first base region 33a. The depth of the first p-region 34 is, for example, 0.5 μm or more and 1 μm or less.

[0079] By setting a first p-region 34 that is shallower than the depth of the base region 33, current winding into the bottom of the base region 33 is facilitated when a forward current flows in the SBD of the element region 101. Therefore, the operating start voltage of the pn junction diode with the base region 33 as the anode can be increased.

[0080] The first p-region 34 is electrically connected to the source electrode 12. The first p-region 34 is fixed at the potential of the source electrode 12.

[0081] The first p-region 34, for example, contains aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the first p-region 34 is, for example, 5 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 the following.

[0082] The drift region 31, located in the end region 102, includes a third portion 31z. The third portion 31z is in contact with the first surface F1 and with the source electrode wiring layer 13. The third portion 31z functions, for example, as a current path for the SBD in the end region 102.

[0083] The second p-region 37 of the p-type is disposed between the drift region 31 and the first surface F1. The second p-region 37 is disposed between the low concentration region 31a and the first surface F1.

[0084] The second p-region 37 surrounds the component region 101. The second p-region 37 is in contact with the outer p-region 32.

[0085] The depth of the second p-region 37 is shallower than the depth of the peripheral p-region 32 and the depth of the base region 33. The depth of the second p-region 37 is, for example, shallower than the depth of the first base region 33a. The depth of the second p-region 37 is, for example, 0.5 μm or more and 1 μm or less.

[0086] The depth of the second p region 37 is substantially the same as the depth of the first p region 34.

[0087] The second p-region 37 is electrically connected to the source electrode wiring layer 13. The second p-region 37 is fixed at the potential of the source electrode wiring layer 13. The second p-region 37 is fixed at the potential of the source electrode 12.

[0088] The second p-region 37, for example, contains aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the second p-region 37 is, for example, 5 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 The p-type impurity concentration in the second p-region 37 is, for example, substantially the same as the p-type impurity concentration in the first p-region 34.

[0089] The second p region 37 is formed, for example, by using the same manufacturing process with the same mask pattern as the first p region 34.

[0090] The third p-region 38 of the p-type is located between the drift region 31 and the first surface F1. The third p-region 38 is located between the low concentration region 31a and the first surface F1.

[0091] The third p region 38 surrounds the second p region 37. The third p region 38 and the second p region 37 are separated in the first direction.

[0092] A drift region 31 is set between the third p region 38 and the second p region 37. A third part 31z of the drift region 31 is set between the third p region 38 and the second p region 37.

[0093] The depth of the third p-region 38 is shallower than the depth of the outer p-region 32 and the depth of the base region 33. The depth of the third p-region 38 is, for example, shallower than the depth of the first base region 33a. The depth of the third p-region 38 is, for example, more than 0.5 μm and less than 1 μm.

[0094] The depth of the third p region 38 is substantially the same as the depth of the first p region 34 and the depth of the second p region 37.

[0095] The third p-region 38 is electrically connected to the source electrode 12. The third p-region 38 is fixed at the potential of the source electrode 12.

[0096] The third p-region 38, for example, contains aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the third p-region 38 is, for example, 5 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 The p-type impurity concentration in the third p region 38 is substantially the same as that in the first p region 34 and the second p region 37.

[0097] The third p region 38 is formed, for example, by using the same manufacturing process with the same mask pattern as the first p region 34 and the second p region 37.

[0098] The fourth p-region 40 of the p-type is located between the drift region 31 and the first surface F1. The fourth p-region 40 is located between the drift region 31 and the second p-region 37.

[0099] The fourth p region 40 is, for example, located between the low concentration region 31a and the first surface F1. The fourth p region 40 is, for example, located between the low concentration region 31a and the second p region 37. The fourth p region 40 is, for example, in contact with the low concentration region 31a.

[0100] The fourth p-region 40 is disposed on the outer periphery of the outer p-region 32. The fourth p-region 40 is disposed on the end region 102 side of the outer p-region 32. The fourth p-region 40 is separated from the outer p-region 32 in a first direction. For example, in the first surface F1, the fourth p-region 40 surrounds the outer p-region 32.

[0101] The width of the fourth p-region 40 in the first direction is, for example, more than 0.5 times and less than 3 times the width of the substrate region 33 in the first direction. The width of the fourth p-region 40 in the first direction is, for example, more than 0.5 times and less than 3 times the width of the first substrate region 33a in the first direction. The width of the fourth p-region 40 in the first direction is, for example, more than 0.5 μm and less than 10 μm. The width of the fourth p-region 40 in the first direction is, for example, substantially the same as the width of the substrate region 33 in the first direction.

[0102] The distance in the first direction between the fourth p-region 40 and the outer p-region 32 is more than 0.5 times and less than 3 times the distance in the first direction between the first base region 33a and the second base region 33b. The distance in the first direction between the fourth p-region 40 and the outer p-region 32 is, for example, more than 0.5 μm and less than 2.0 μm.

[0103] The fourth p region 40 is provided, for example, at the end of the field insulating layer 24 on the element region 101 side of the end region 102, near the element region 101 side.

[0104] The depth of the fourth p region 40 is greater than the depth of the second p region 37. The depth of the fourth p region 40 is, for example, more than 1.0 μm and less than 2.0 μm. The depth of the fourth p region 40 is, for example, more than 1.5 times and less than 5 times the depth of the second p region 37.

[0105] The depth of the fourth p region 40 is, for example, more than 0.5 times and less than 2 times the depth of the base region 33. The depth of the fourth p region 40 is, for example, greater than the depth of the base region 33. The first depth of the fourth p region 40 is, for example, deeper than the depth of the base region 33.

[0106] The depth of the fourth p region 40 is, for example, more than 0.5 times and less than 2 times the depth of the outer p region 32. The depth d1 of the fourth p region 40 is, for example, greater than the depth of the outer p region 32. The depth of the fourth p region 40 is, for example, deeper than the depth d2 of the outer p region 32.

[0107] The fourth p-region 40 is electrically connected to the source electrode 12. The fourth p-region 40 is fixed at the potential of the source electrode 12.

[0108] The fourth p-region 40, for example, contains aluminum (Al) as a p-type impurity. The concentration of the p-type impurity in the fourth p-region 40 is, for example, 1 × 10⁻⁶. 17 cm －3 Above and 1×10 20 cm －3 the following.

[0109] The p-type impurity concentration in the fourth p-region 40 is, for example, more than 0.1 times and less than 2 times the p-type impurity concentration in the substrate region 33. The p-type impurity concentration in the fourth p-region 40 is, for example, substantially the same as the p-type impurity concentration in the substrate region 33.

[0110] The p-type impurity concentration in the fourth p-region 40 is, for example, more than 0.1 times and less than 2 times the p-type impurity concentration in the peripheral p-region 32. The p-type impurity concentration in the fourth p-region 40 is, for example, substantially the same as the p-type impurity concentration in the peripheral p-region 32.

[0111] The fourth p region 40 is formed, for example, by using the same manufacturing process with the same mask pattern as the base region 33 and the outer p region 32.

[0112] By providing the fourth p-region 40, the intensity of the electric field applied to the end of the pn junction of the element region 101 is further mitigated. Therefore, by providing the fourth p-region 40, the insulation breakdown voltage of the MOSFET 100 is further improved.

[0113] n + The source region 35 is disposed between the substrate region 33 and the first surface F1. The source region 35 may also be disposed between the second substrate region 33b and the first surface F1. The source region 35 may extend in a first direction.

[0114] Source region 35 may contain phosphorus (P) or nitrogen (N) as an n-type impurity, for example. The concentration of n-type impurities in source region 35 is higher than that in drift region 31.

[0115] The n-type impurity concentration in source region 35 is, for example, 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The depth of the source region 35 is shallower than the depth of the first p-region 34. The depth of the source region 35 is, for example, 0.05 μm or more and 0.2 μm or less.

[0116] Source region 35 is electrically connected to source electrode 12. Source region 35 is in contact with silicide layer 14. The contact between source region 35 and source electrode 12 is, for example, an ohmic contact. Source region 35 is fixed at the potential of source electrode 12.

[0117] p + A first high-concentration p-region 36 is disposed between the first p-region 34 and the first surface F1. The first high-concentration p-region 36 is disposed between the first p-region 34 and the first silicide layer 14a.

[0118] The first high-concentration p-region 36, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration of the first high-concentration p-region 36 is higher than that of the first p-region 34. The p-type impurity concentration of the first high-concentration p-region 36 is, for example, more than 10 times and less than 1000 times that of the p-type impurity concentration of the first p-region 34.

[0119] The concentration of p-type impurities in the first high-concentration p region 36 is, for example, 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The depth of the first high-concentration p region 36 is, for example, 0.1 μm or more and 0.2 μm or less.

[0120] The first high-concentration p-region 36 is electrically connected to the source electrode 12. The first high-concentration p-region 36 is in contact with the first silicide layer 14a.

[0121] p + The second high-concentration p-region 39 is disposed between the third p-region 38 and the first surface F1. The second high-concentration p-region 39 is disposed between the third p-region 38 and the second silicide layer 14b.

[0122] The second high-concentration p-region 39, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration of the second high-concentration p-region 39 is higher than that of the second p-region 37 and the third p-region 38. The p-type impurity concentration of the second high-concentration p-region 39 is, for example, more than 10 times and less than 1000 times that of the p-type impurity concentration of the third p-region 38.

[0123] The concentration of p-type impurities in the second highest concentration p region 39 is, for example, 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The depth of the second high-concentration p region 39 is, for example, 0.1 μm or more and 0.2 μm or less.

[0124] The second high-concentration p-region 39 is electrically connected to the source electrode wiring layer 13. The second high-concentration p-region 39 is in contact with the second silicide layer 14b.

[0125] The second high-concentration p region 39 is formed, for example, by using the same manufacturing process with the same mask pattern as the first high-concentration p region 36.

[0126] A first silicide layer 14a is disposed between a first high-concentration p-region 36 and a source electrode 12. The first silicide layer 14a is in contact with the first high-concentration p-region 36 and the source electrode region 35.

[0127] The second silicide layer 14b is disposed between the second high-concentration p-region 39 and the source electrode wiring layer 13. The second silicide layer 14b is in contact with the second high-concentration p-region 39.

[0128] The third silicide layer 14c is disposed between the second p-region 37 and the source electrode wiring layer 13. The third silicide layer 14c is in contact with the second p-region 37.

[0129] The silicide layer 14 contains silicide. The silicide layer 14 may contain, for example, nickel (Ni) or titanium (Ti). The silicide layer 14 may be, for example, nickel silicide or titanium silicide.

[0130] A gate electrode 18 is disposed on the first surface F1 side of the silicon carbide layer 10. The gate electrode 18 extends, for example, in a second direction. A plurality of gate electrodes 18 are arranged in parallel with each other, for example, in the first direction. The gate electrode 18 has, for example, a strip shape.

[0131] The gate electrode 18 is a conductive layer. The gate electrode 18 is, for example, polysilicon containing p-type or n-type impurities.

[0132] Gate electrode 18 is opposite to substrate region 33. Gate electrode 18 is opposite to first portion 31x.

[0133] The gate interconnect layer 20 is disposed on the first surface F1 side of the silicon carbide layer 10. The gate interconnect layer 20 is disposed on the gate insulating layer 16 or the field insulating layer 24.

[0134] A portion of the gate interconnect layer 20 extends, for example, in a direction perpendicular to the gate electrode 18. The gate interconnect layer 20 has the function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0135] The gate connection layer 20 is formed, for example, by the same material as the gate electrode 18.

[0136] The gate pad layer 21 is disposed on the first surface F1 side of the silicon carbide layer 10. The gate pad layer 21 is disposed on the field insulating layer 24.

[0137] The gate pad layer 21 is physically and electrically connected to the gate interconnect layer 20. The gate pad layer 21 has the function of electrically connecting the gate electrode 18 and the gate electrode pad 22.

[0138] The gate pad layer 21 is formed, for example, by the same material as the gate electrode 18 and the gate connection layer 20.

[0139] A gate insulating layer 16 is disposed between the gate electrode 18 and the substrate region 33. A gate insulating layer 16 is disposed between the gate electrode 18 and the first portion 31x. A gate insulating layer 16 is disposed between the gate electrode 18 and the source region 35.

[0140] The gate insulating layer 16 is, for example, silicon oxide. A high-k insulating material (high dielectric constant insulating material) can be applied to the gate insulating layer 16, for example.

[0141] A field insulating layer 24 is disposed on the silicon carbide layer 10 of the end region 102. The field insulating layer 24 is, for example, silicon oxide.

[0142] An interlayer insulating layer 26 is disposed above the gate electrode 18 and the silicon carbide layer 10. The interlayer insulating layer 26 is, for example, silicon oxide.

[0143] The source electrode 12 is disposed on the first surface F1 side of the silicon carbide layer 10 in the element region 101. The source electrode 12 is disposed on the interlayer insulating layer 26.

[0144] The source electrode 12 comprises metal. For example, the source electrode 12 is a laminated structure comprising a first film containing titanium (Ti) and a second film containing aluminum (Al). Alternatively, the source electrode 12 may be a laminated film of titanium and aluminum films. For example, the source electrode 12 does not contain silicide.

[0145] The source electrode 12 includes a first contact portion 12x and a second contact portion 12y.

[0146] The first contact portion 12x contacts the second portion 31y of the drift region 31. No silicide layer is disposed between the first contact portion 12x and the second portion 31y. The contact between the first contact portion 12x and the second portion 31y is called a Schottky contact.

[0147] A portion of the first contact portion 12x, for example, contacts the base region 33.

[0148] The first contact portion 12x functions as the anode electrode of the SBD in the element region 101.

[0149] The second contact portion 12y is in contact with the first silicide layer 14a. The first silicide layer 14a is in contact with the first high-concentration p-region 36 and the source region 35.

[0150] The contact resistance between the second contact portion 12y and the first high-concentration p-region 36 is reduced by sandwiching the first silicide layer 14a in between. The contact between the second contact portion 12y and the first high-concentration p-region 36 is, for example, an ohmic contact.

[0151] The contact resistance between the second contact portion 12y and the source region 35 is reduced by sandwiching the first silicide layer 14a in between. The contact between the second contact portion 12y and the source region 35 is, for example, an ohmic contact.

[0152] The second contact portion 12y, for example, has the function of fixing the potentials of the base region 33, the first p region 34 and the second p region 37 to the potential of the source electrode 12.

[0153] The source electrode wiring layer 13 is disposed on the first surface F1 side of the silicon carbide layer 10 in the end region 102. The source electrode wiring layer 13 is disposed on the interlayer insulating layer 26.

[0154] The source electrode wiring layer 13 is physically and electrically connected to the source electrode 12. For example, the source electrode 12 is surrounded by the source electrode 13.

[0155] The source electrode wiring layer 13 contains metal. For example, the source electrode wiring layer 13 is a stacked structure comprising a first film containing titanium (Ti) and a second film containing aluminum (Al). Alternatively, the source electrode wiring layer 13 is a stacked film of titanium and aluminum films. For example, the source electrode wiring layer 13 does not contain silicide.

[0156] The source electrode wiring layer 13 is formed, for example, by the same material as the source electrode 12.

[0157] The source electrode wiring layer 13 includes a third contact portion 13x, a fourth contact portion 13y, and a fifth contact portion 13z.

[0158] The fourth contact portion 13y is provided, for example, at the end of the third p region 38 on the side of the second p region 37. The fifth contact portion 13z is provided, for example, at the end of the second p region 37 on the side of the third p region 38.

[0159] The third contact portion 13x is disposed between the fourth contact portion 13y and the fifth contact portion 13z. An interlayer insulating layer 26 is disposed, for example, between the third contact portion 13x and the fourth contact portion 13y. An interlayer insulating layer 26 is disposed, for example, between the third contact portion 13x and the fifth contact portion 13z.

[0160] The distance in the first direction between the third contact portion 13x and the fourth contact portion 13y is substantially the same as the distance in the first direction between the third contact portion 13x and the fifth contact portion 13z. The distance in the first direction between the third contact portion 13x and the fourth contact portion 13y is, for example, more than 0.5 times and less than 2 times the distance in the first direction between the third contact portion 13x and the fifth contact portion 13z.

[0161] The third contact portion 13x contacts the third portion 31z of the drift region 31. No silicide layer is disposed between the third contact portion 13x and the third portion 31z. The contact between the third contact portion 13x and the third portion 31z is called a Schottky contact.

[0162] A portion of the third contact portion 13x contacts, for example, the second p region 37. Another portion of the third contact portion 13x contacts, for example, the third p region 38.

[0163] The third contact portion 13x functions as the anode electrode of the SBD in the end region 102.

[0164] The fourth contact portion 13y is in contact with the second silicide layer 14b. The second silicide layer 14b is in contact with the second high-concentration p-region 39 and the third p-region 38.

[0165] The contact resistance between the fourth contact portion 13y and the second high-concentration p-region 39 is reduced by sandwiching a second silicide layer 14b in between. The contact between the fourth contact portion 13y and the second high-concentration p-region 39 is, for example, an ohmic contact.

[0166] The fourth contact portion 13y has, for example, the function of fixing the potential of the third p region 38 to the potential of the source electrode 12 and the source electrode wiring layer 13.

[0167] The fifth contact portion 13z is in contact with the third silicide layer 14c. The third silicide layer 14c is in contact with the second p-region 37.

[0168] The contact resistance between the fifth contact portion 13z and the second p region 37 is reduced by sandwiching a third silicide layer 14c in between.

[0169] The fifth contact portion 13z has, for example, the function of fixing the potential of the second p region 37 to the potential of the source electrode 12 and the source electrode wiring layer 13.

[0170] The resistance between the fifth contact 13z and the second p-region 37 of the MOSFET 100 is higher than the resistance between the fourth contact 13y and the third p-region 38. There is no region with high p-type impurity concentration between the fifth contact 13z and the second p-region 37, hence the higher resistance.

[0171] The third silicide layer 14c is in contact with the second p-region 37. The p-type impurity concentration of the second p-region 37 is lower than that of the second high-concentration p-region 39. For example, the p-type impurity concentration of the portion of the second p-region 37 in contact with the third silicide layer 14c is more than one-thousandth and less than one-tenth of the p-type impurity concentration of the portion of the second high-concentration p-region 39 in contact with the second silicide layer 14b.

[0172] The gate electrode pad 22 is disposed on the first surface F1 side of the silicon carbide layer 10 in the end region 102. The gate electrode pad 22 is disposed on the interlayer insulating layer 26.

[0173] The gate electrode pad 22 contains metal. The gate electrode pad 22 is formed, for example, of the same material as the source electrode 12 and the source electrode wiring layer 13.

[0174] The gate electrode wiring layer 23 is disposed on the first surface F1 side of the silicon carbide layer 10 in the end region 102. The gate electrode wiring layer 23 is disposed on the interlayer insulating layer 26.

[0175] The gate electrode wiring layer 23 is physically and electrically connected to the gate electrode pad 22. The gate electrode wiring layer 23 is physically and electrically connected to the gate connection layer 20.

[0176] The gate electrode wiring layer 23 contains metal. The gate electrode wiring layer 23 is formed, for example, of the same material as the source electrode 12, the source electrode wiring layer 13, and the gate electrode pad 22.

[0177] The drain electrode 15 is disposed on the back side of the silicon carbide layer 10. The drain electrode 15 is in contact with the drain region 30.

[0178] The drain electrode 15 is, for example, a metal or a metal semiconductor compound. The drain electrode 15 may contain, for example, at least one material selected from the group consisting of nickel silicide, titanium (Ti), nickel (Ni), silver (Ag), and gold (Au).

[0179] In device region 101, a MOSFET is formed by a gate electrode 18, a gate insulating layer 16, a substrate region 33, a source region 35, a first portion 31x of a drift region 31, a drain region 30, a second contact portion 12y of the source electrode 12, and a drain electrode 15. When the MOSFET 100 is in the on state, current flows from the drain electrode 15 to the source electrode 12 through the MOSFET in device region 101.

[0180] In the element region 101, the first contact portion 12x of the source electrode 12, the second portion 31y of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in the off state, and a voltage that is positive relative to the drain electrode 15 is applied to the source electrode 12, current flows from the source electrode 12 to the drain electrode 15 through the SBD of the element region 101.

[0181] In the terminal region 102, the third contact 13x of the source electrode wiring layer 13, the third portion 31z of the drift region 31, the drain region 30, and the drain electrode 15 form an SBD. When the MOSFET 100 is in the off state, and a voltage that is positive relative to the drain electrode 15 is applied to the source electrode 12, current flows from the source electrode wiring layer 13 to the drain electrode 15 through the SBD in the terminal region 102.

[0182] Next, the function and effect of the MOSFET 100 in the first embodiment will be explained.

[0183] Figure 4This is an equivalent circuit diagram of the semiconductor device according to the first embodiment. In the MOSFET 100, a pn junction diode and an SBD are connected in parallel with the transistor as built-in diodes between the source electrode 12 and the drain electrode 15 in the element region 101. The substrate region 33 is located on the anode side of the pn junction diode, and the drift region 31 is located on the cathode side of the pn junction diode. In addition, the source electrode 12 is the anode of the SBD, and the drain electrode 15 is the cathode of the SBD.

[0184] For example, consider the case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, due to the induced current caused by the inductive load, a voltage that is positive relative to the drain electrode 15 is sometimes applied to the source electrode 12. In this case, forward current flows in the built-in diode. This state is also known as the reverse conduction state.

[0185] Assuming the MOSFET does not have a SBD (Special Diode), forward current flows through the pn junction diode. The pn junction diode operates bipolarly. If a bipolar-operating pn junction diode is used and return current flows, stacking defects will grow in the silicon carbide layer due to the recombination energy of the charge carriers. The growth of stacking defects in the silicon carbide layer leads to an increase in the MOSFET's on-resistance. This increased on-resistance results in a decrease in the MOSFET's reliability.

[0186] The MOSFET 100 has a SBD (Short Buffer Diode). The forward voltage (Vf) at which forward current begins to flow in the SBD is lower than the forward voltage (Vf) of the pn junction diode. Therefore, forward current flows in the SBD before the pn junction diode.

[0187] The forward voltage (Vf) of an SBD is, for example, above 1.0V and below 2.0V. The forward voltage (Vf) of a pn junction diode is, for example, above 2.0V and below 3.0V.

[0188] The SBD operates as a single-pole circuit. Therefore, even with forward current flowing, stacking defects will not grow in the silicon carbide layer 10 due to carrier recombination energy. This suppresses the increase in the on-resistance of the MOSFET 100, thereby improving the reliability of the MOSFET 100.

[0189] Furthermore, the forward current flowing in the SBD causes the voltage on the N-side of the pn junction diode to rise, effectively reducing the voltage applied to the pn junction near the SBD. Therefore, by setting the SBD, the forward voltage (Vf) of the pn junction diode near the SBD can be effectively increased. This suppresses the flow of forward current in the pn junction diode. In other words, the operating start voltage of the pn junction diode can be increased. Consequently, the reliability of the MOSFET 100 is improved.

[0190] Figure 5 This is a schematic cross-sectional view of a comparative example semiconductor device. The comparative example semiconductor device is a MOSFET 900. Figure 5 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0191] The MOSFET 900 in the comparative example differs from the MOSFET 100 in the first embodiment in that a p-type region 37 is provided between the third silicide layer 14c and the p-type second p-region 37. + The third highest concentration p region 41 (thirteenth silicon carbide region) of the type.

[0192] p + The third high-concentration p-region 41 is disposed between the second p-region 37 and the first surface F1. The third high-concentration p-region 41 is disposed between the second p-region 37 and the third silicide layer 14c.

[0193] The third high-concentration p-region 41, for example, contains aluminum (Al) as a p-type impurity. The p-type impurity concentration in the third high-concentration p-region 41 is higher than that in the second p-region 37 and the third p-region 38. The p-type impurity concentration in the third high-concentration p-region 41 is, for example, more than 10 times and less than 1000 times that in the second p-region 37.

[0194] The concentration of p-type impurities in the third highest concentration p region 41 is, for example, 1 × 10⁻⁶. 19 cm －3 Above and 1×10 21 cm －3 The depth of the third high-concentration p region 41 is, for example, 0.1 μm or more and 0.2 μm or less.

[0195] The third high-concentration p-region 41 is electrically connected to the source electrode wiring layer 13. The third high-concentration p-region 41 is in contact with the second silicide layer 14b.

[0196] The third high-concentration p region 41 is formed, for example, by using the same manufacturing process with the same mask pattern as the first high-concentration p region 36 and the second high-concentration p region 39.

[0197] Figure 6 This is an explanatory diagram illustrating the function and effect of a comparative example semiconductor device. Figure 6 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 6 Is with Figure 5 The corresponding diagram.

[0198] Figure 6 The pn junction diode and SBD inherent in the MOSFET 900 are represented using circuit notation. Additionally,Figure 6 The current flowing in the drift region 31 of the MOSFET 900 when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 of the MOSFET 900 is indicated by the arrow.

[0199] like Figure 6 As shown, in the element region 101, a forward current flows in the SBD, which includes the first contact portion 12x of the source electrode 12 and the second portion 31y of the drift region 31. The forward current flows through the base regions 33 and winds into the bottom of the base regions 33. Due to the forward current winding into the bottom of the base regions 33, the voltage on the N-side of the pn junction diode formed by the base regions 33 and the drift regions 31 increases, and the voltage applied to the pn junction near the SBD is effectively reduced. Therefore, the forward voltage (Vf) of the pn junction diode in the element region 101 can be effectively increased. As a result, the flow of forward current in the pn junction diode in the element region 101 is suppressed.

[0200] like Figure 6 As shown, in the end region 102, a forward current flows in the SBD, which includes the third contact 13x of the source electrode wiring layer 13 and the third portion 31z of the drift region 31. The forward current passes between the second p region 37 and the third p region 38, and winds into the bottom of the second p region 37, the third p region 38, and the fourth p region 40. However, since there is a distance from the SBD of the end region 102 to the second p region 37 or the fourth p region 40 that is close to the component region 101, the winding of the current into the bottom of the second p region 37 or the fourth p region 40 that is close to the component region 101 is suppressed.

[0201] Therefore, in the portion close to component region 101, the voltage rise on the N-side of the pn junction diode formed by the second p-region 37 and drift region 31, or by the fourth p-region 40 and drift region 31, is less likely to occur. That is, the voltage drop applied to the pn junction due to forward current is suppressed. Therefore, when the pn junction diode in the end region 102 close to component region 101 operates, bipolar current easily flows in the drift region 31. Consequently, the reliability of the MOSFET 900 may decrease due to an increase in on-resistance.

[0202] Figure 7 This is an explanatory diagram of a comparative example semiconductor device. Figure 7 This is a schematic cross-sectional view of a comparative example semiconductor device. Figure 7 Is with Figure 5 The corresponding diagram.

[0203] Figure 7 The pn junction diode and SBD integrated into the MOSFET 900 are represented using circuit notation. Additionally,Figure 7 The current flowing into the second p-region 37 of the p-type MOSFET 900 when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 and the source electrode wiring layer 13 of the MOSFET 900 is indicated by the arrow.

[0204] In the comparative example MOSFET 900, the fifth contact 13z is in contact with the third silicide layer 14c. The third silicide layer 14c is in contact with the third high-concentration p-region 41 and the second p-region 37.

[0205] The contact resistance between the fifth contact portion 13z and the third high-concentration p-region 41 is reduced by sandwiching the third silicide layer 14c in between. The contact between the fifth contact portion 13z and the third high-concentration p-region 41 is, for example, an ohmic contact. Furthermore, the resistance between the fifth contact portion 13z and the second p-region 37 is also reduced by sandwiching the third silicide layer 14c and the third high-concentration p-region 41 in between. Therefore, the contact between the fifth contact portion 13z and the second p-region 37 is, for example, an ohmic contact.

[0206] As indicated by the arrow, current flows from the source electrode 12 into the second p-region 37 via the second contact portion 12y. In other words, holes are supplied from the source electrode 12 into the second p-region 37 via the second contact portion 12y.

[0207] Additionally, as indicated by the arrow, current flows from the source electrode wiring layer 13 to the second p region 37 via the fifth contact portion 13z. In other words, holes are supplied from the source electrode wiring layer 13 to the second p region 37 via the fifth contact portion 13z.

[0208] If the amount of holes supplied to the second p-region 37 increases, it promotes the start of operation of the pn junction diode in the end region 102, which is close to the element region 101. Furthermore, the bipolar current flowing in the drift region 31 increases when the pn junction diode operates. This may lead to a decrease in the reliability of the MOSFET 900 due to the increased on-resistance.

[0209] In the MOSFET 100 of the first embodiment, similarly to the MOSFET 900, the pn junction diode in the end region 102, which is close to the element region 101, operates, and bipolar current easily flows in the drift region 31. As a result, the reliability of the MOSFET 100 may be reduced due to the increase in on-resistance.

[0210] Figure 8 This is an explanatory diagram illustrating the function and effects of the semiconductor device according to the first embodiment. Figure 8 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment. Figure 8 Is with Figure 3The corresponding diagram. Additionally... Figure 8 It is compared with the example Figure 7 The corresponding diagram.

[0211] Figure 8 The pn junction diode and SBD inherent in the MOSFET 100 are represented using circuit notation. Additionally, Figure 8 The current flowing into the second p-region 37 of the p-type MOSFET 100 when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 of the MOSFET 100 is indicated by the arrow.

[0212] In the MOSFET 100 of the first embodiment, unlike the MOSFET 900 of the comparative example, there is no high-concentration region of p-type below the third silicide layer 14c. In the MOSFET 100, the third silicide layer 14c only contacts the second p-region 37.

[0213] Compared to MOSFET 900, the concentration of p-type impurities in the p-region that contacts the third silicide layer 14c is lower, thus the resistance between the fifth contact 13z and the second p-region 37 becomes higher.

[0214] Therefore, the current flowing from the source electrode wiring layer 13 through the fifth contact portion 13z to the second p-region 37, as indicated by the dashed arrow, is smaller compared to that of the MOSFET 900. The amount of holes supplied from the source electrode wiring layer 13 to the second p-region 37 through the fifth contact portion 13z is also reduced.

[0215] Therefore, the start of operation of the pn junction diode in the end region 102, which is close to the element region 101, is suppressed. Furthermore, the bipolar current flowing in the drift region 31 when the pn junction diode operates is reduced. This suppresses the growth of stack-up defects and the increase in on-resistance, thereby improving the reliability of the MOSFET 100.

[0216] From the viewpoint of increasing the contact resistance between the fifth contact portion 13z and the second p region 37, the p-type impurity concentration of the portion of the second p region 37 that contacts the third silicide layer 14c is preferably less than one-tenth of the p-type impurity concentration of the portion of the second high-concentration p region 39 that contacts the second silicide layer 14b, and more preferably less than one-hundredth.

[0217] The above describes a MOSFET with improved reliability achieved by suppressing the forward current flowing in the pn junction diode according to the first embodiment.

[0218] (Second Implementation)

[0219] The semiconductor device of the second embodiment differs from that of the semiconductor device of the first embodiment in that the wiring layer, except for the third contact portion, does not include any portion that directly contacts or contacts the ninth silicon carbide region through a silicide layer. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0220] The semiconductor device in the second embodiment is a planar gate type vertical MOSFET 200 using silicon carbide.

[0221] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment. Figure 9 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0222] like Figure 9 As shown, the source electrode wiring layer 13 of the MOSFET 200 does not include any portion that directly contacts or contacts the second p region 37 through the silicide layer, except for the third contact portion 13x.

[0223] The source electrode wiring layer 13 of MOSFET 200 does not have Figure 5 The comparative example MOSFET 900 shown has a fifth contact portion 13z. Therefore, when a voltage that is positive relative to the drain electrode 15 is applied to the source electrode 12 and the source electrode wiring layer 13, current flows only from the source electrode 12 to the second p region 37 via the second contact portion 12y.

[0224] Therefore, compared to MOSFET 900, the current flowing into the second p-region 37 is smaller. This suppresses the growth of stack-up defects and the increase in on-resistance, thereby improving the reliability of MOSFET 200.

[0225] (Modified Example)

[0226] The semiconductor device of the modified example of the second embodiment differs from the semiconductor device of the second embodiment in that the silicon carbide layer in the end region further includes a thirteenth silicon carbide region of the second conductivity type, which is disposed between the ninth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region, and the third contact portion is in contact with the thirteenth silicon carbide region.

[0227] The semiconductor device in the modified example of the second embodiment is a planar gate type vertical MOSFET 201 using silicon carbide.

[0228] Figure 10 This is a schematic cross-sectional view of a semiconductor device according to a variation of the second embodiment. Figure 10 It is the same as the second embodiment. Figure 9 The corresponding diagram.

[0229] like Figure 10 As shown, similar to the MOSFET 200 of the second embodiment, the source electrode wiring layer 13, except for the third contact portion 13x, does not include any portion that directly contacts or contacts the second p region 37 through the silicide layer. Therefore, the reliability of the MOSFET 201 is improved.

[0230] like Figure 10 As shown, MOSFET 201 is positioned between the second p-region 37 and the first surface F1, where the p-type impurity concentration is higher than that of the second p-region 37 and the third p-region 38. + The third highest concentration p region 41 (thirteenth silicon carbide region) of the type.

[0231] A portion of the third contact 13x contacts the third high-concentration p-region 41. Because the third contact 13x contacts the third high-concentration p-region 41, the contact resistance between the source electrode wiring layer 13 and the second p-region 37 is reduced compared to the MOSFET 200.

[0232] The resistance between the third contact 13x and the second p region 37 of MOSFET 201 is higher than the resistance between the fourth contact 13y and the third p region 38.

[0233] In MOSFET 201, compared to MOSFET 200, the fixation of the potential of the second p-region 37 to the potential of the source electrode wiring layer 13 is enhanced. Therefore, compared to MOSFET 200, MOSFET 201 exhibits more stable insulation breakdown voltage.

[0234] Based on the second embodiment and its variations, a MOSFET with improved reliability is achieved by suppressing the forward current flowing in the pn junction diode.

[0235] (Third Implementation)

[0236] The semiconductor device of the third embodiment differs from that of the semiconductor device of the first embodiment in that the wiring layer further includes a fifth contact portion that contacts the ninth silicon carbide region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0237] The semiconductor device in the third embodiment is a planar gate type vertical MOSFET 300 using silicon carbide.

[0238] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment. Figure 11 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0239] likeFigure 11 As shown, the fifth contact 13z of the MOSFET 300 is in direct contact with the second p-region 37. The fifth contact 13z is not in contact with the drift region 31.

[0240] Compared to the MOSFET 900 in the comparative example, the third silicide layer 14c and p are not disposed between the fifth contact 13z and the second p region 37 of the MOSFET 300. + The third high-concentration p-region 41 (thirteenth silicon carbide region) of the type. Therefore, the resistance between the fifth contact 13z of MOSFET 300 and the second p-region 37 is higher than the resistance between the fifth contact 13z of MOSFET 900 and the second p-region 37.

[0241] For example, the resistance between the fifth contact 13z and the second p region 37 of the MOSFET 300 is higher than the resistance between the fourth contact 13y and the third p region 38.

[0242] In MOSFET 300, compared to MOSFET 900, when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 and the source electrode wiring layer 13, the current flowing into the second p-region 37 is reduced. This suppresses the growth of stack-up defects and the increase in on-resistance, thereby improving the reliability of MOSFET 300.

[0243] According to the third embodiment, the forward current flowing in the pn junction diode is suppressed, thereby improving the reliability of the MOSFET.

[0244] (Fourth Implementation)

[0245] The semiconductor device of the fourth embodiment differs from that of the semiconductor device of the first embodiment in that the silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type, which is disposed between the ninth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The wiring layer further includes a fifth contact portion that contacts the thirteenth silicon carbide region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0246] The semiconductor device in the fourth embodiment is a planar gate type vertical MOSFET 400 using silicon carbide.

[0247] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment. Figure 12 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0248] like Figure 12As shown, a p-type second p-region 37 is disposed between the third silicide layer 14c and the p-type layer 14c. + The third high-concentration p-region 41 (thirteenth silicon carbide region) has a higher p-type impurity concentration than the second p-region 37 and the third p-region 38. The fifth contact 13z of the MOSFET 400 is in direct contact with the third high-concentration p-region 41.

[0249] Compared to the MOSFET 900 in the comparative example, the third silicide layer 14c is not provided between the fifth contact 13z and the second p-region 37 of the MOSFET 400. Therefore, the resistance between the fifth contact 13z and the second p-region 37 of the MOSFET 400 is higher than that between the fifth contact 13z and the second p-region 37 of the MOSFET 900.

[0250] For example, the resistance between the fifth contact 13z and the second p region 37 of the MOSFET 400 is higher than the resistance between the fourth contact 13y and the third p region 38.

[0251] In MOSFET 400, compared to MOSFET 900, when a positive voltage relative to the drain electrode 15 is applied to the source electrode 12 and the source electrode wiring layer 13, the current flowing into the second p-region 37 is reduced. This suppresses the growth of stack-up defects and the increase in on-resistance, thereby improving the reliability of MOSFET 400.

[0252] According to the fourth embodiment, the forward current flowing in the pn junction diode is suppressed, thereby improving the reliability of the MOSFET.

[0253] (Fifth Implementation)

[0254] The semiconductor device of the fifth embodiment differs from that of the semiconductor device of the first embodiment in that the silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type, which is disposed between the ninth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The ninth silicon carbide region includes a first region that contacts the third silicon carbide region, and a second region that surrounds the first region, is separated from the first region, and contacts the thirteenth silicon carbide region. Hereinafter, some descriptions that are repeated in the first embodiment will be omitted.

[0255] The semiconductor device in the fifth embodiment is a planar gate type vertical MOSFET 500 using silicon carbide.

[0256] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to the fifth embodiment.Figure 13 It is the same as the first embodiment. Figure 3 The corresponding diagram.

[0257] like Figure 13 As shown, in MOSFET 500, a p-type second p-region 37 is formed between the third silicide layer 14c and the p-type layer 14c. + The third high-concentration p-region 41 (the thirteenth silicon carbide region) has a higher p-type impurity concentration than the second p-region 37 and the third p-region 38.

[0258] For example, the resistance between the fifth contact 13z and the second p region 37 of the MOSFET 500 is essentially the same as the resistance between the fourth contact 13y and the third p region 38.

[0259] Additionally, in the MOSFET 500, the second p-region 37 of the p-type has an inner region 37a (first region) and an outer region 37b (second region). The second p-region 37 is divided into an inner region 37a and an outer region 37b.

[0260] The inner region 37a surrounds the component region 101. The inner region 37a is in contact with the outer peripheral p region 32.

[0261] The outer region 37b surrounds the inner region 37a. The outer region 37b is separated from the inner region 37a. A drift region 31 is provided between the inner region 37a and the outer region 37b. The outer region 37b is in contact with the third high-concentration p region 41.

[0262] The end of the inner region 37a on the outer region 37b side is, for example, located on the element region 101 side of the field insulating layer 24 in the end region 102, adjacent to the opposite side of the element region 101. In other words, the end of the inner region 37a on the outer region 37b side is, for example, located on the element region 101 side of the field insulating layer 24 in the end region 102, adjacent to the third p region 38 side.

[0263] The first distance between the inner region 37a and the outer region 37b in a first direction parallel to the first surface is, for example, more than 0.5 times and less than 3 times the second distance in the first direction between adjacent base regions 33 in the first direction. The first distance is, for example, more than 0.5 times and less than 3 times the second distance in the first direction between the first base region 33a and the second base region 33b.

[0264] The fourth p-region 40 of the p-type is located between the drift region 31 and the inner region 37a. The fourth p-region 40 is in contact with the inner region 37a.

[0265] Compared to the comparative example MOSFET 900, the difference in MOSFET 500 is that the second p-region 37 is divided into an inner region 37a and an outer region 37b. Therefore, in the source electrode 12 and source electrode wiring layer 13, for example, current flowing from the second contact 12y of MOSFET 500 to the outer region 37b is interrupted. Additionally, in the source electrode 12 and source electrode wiring layer 13, for example, current flowing from the fifth contact 13z of MOSFET 500 to the inner region 37a is interrupted.

[0266] Therefore, compared to MOSFET 900, the current flowing into the second p-region 37 in the source electrode 12 and source electrode wiring layer 13 is reduced. This suppresses the growth of stack-up defects and the increase in on-resistance, thereby improving the reliability of MOSFET 500.

[0267] From the viewpoint of reducing the current flowing into the second p region 37, the first distance is preferably 0.5 times or more than the second distance, and more preferably 1 times or more.

[0268] Furthermore, from the viewpoint of suppressing damage during the dynamic operation of the MOSFET 500, the end of the inner region 37a on the outer region 37b side is preferably located on the element region 101 side of the field insulating layer 24 in the end region 102, which is opposite to the element region 101.

[0269] According to the fifth embodiment, the forward current flowing in the pn junction diode is suppressed, thereby improving the reliability of the MOSFET.

[0270] In the first to fifth embodiments, the crystal structure of SiC was described using 4H-SiC as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H-SiC and 3C-SiC. In addition, surfaces other than the (0001) surface can also be applied to the surface of the silicon carbide layer 10.

[0271] In the first to fifth embodiments, the case where the first conductivity type is n-type and the second conductivity type is p-type was described as an example, but it is also possible to set the first conductivity type to p-type and the second conductivity type to n-type.

[0272] In the first to fifth embodiments, aluminum (Al) is exemplified as a p-type impurity, but boron (B) can also be used. Additionally, nitrogen (N) and phosphorus (P) are exemplified as n-type impurities, but arsenic (As), antimony (Sb), and the like can also be used.

[0273] In the first to fifth embodiments, the case in which the gate electrode 18 has a strip shape in the element region 101 is described as an example, but it is also possible to construct the gate electrode 18 with a grid shape.

[0274] Several embodiments of the present invention have been described, but these embodiments are given by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, have: Component area; as well as The end region surrounds the component region. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode; A first silicide layer is disposed between the eighth silicon carbide region and the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The silicon carbide layer in the element region comprises: A first silicon carbide region of a first conductivity type has a first portion that is in contact with the first surface and opposite the gate electrode, and a second portion that is in contact with the first surface and in contact with the first electrode. A second silicon carbide region of a second conductivity type is disposed between the first silicon carbide region and the first surface; The third silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and is disposed on the side closer to the end region than the second silicon carbide region, and is electrically connected to the first electrode; The fourth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The fifth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of a first conductivity type is disposed between the fifth silicon carbide region and the first surface, and is electrically connected to the first electrode; and The eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the sixth silicon carbide region. The terminal region includes: A wiring layer, electrically connected to the first electrode; The second electrode; The silicon carbide layer; and A second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer. The silicon carbide layer in the terminal region comprises: The first silicon carbide region has a third portion that contacts the first surface and the wiring layer; The ninth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the element region, and is in contact with the third silicon carbide region; A tenth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separating it from the ninth silicon carbide region, and electrically connected to the wiring layer; and The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The terminal region further includes a third silicide layer, which is disposed between the ninth silicon carbide region and the first surface, and in contact with the ninth silicon carbide region. The wiring layer also includes a fifth contact portion that contacts the third silicide layer.

2. The semiconductor device of claim 1, wherein, The impurity concentration of the second conductivity type in the portion of the ninth silicon carbide region that contacts the third silicide layer is less than one-tenth of the impurity concentration of the second conductivity type in the portion of the eleventh silicon carbide region that contacts the second silicide layer.

3. The semiconductor device as claimed in claim 1, wherein, The resistance between the fifth contact and the ninth silicon carbide region is higher than the resistance between the fourth contact and the tenth silicon carbide region.

4. The semiconductor device of claim 1, wherein, The first silicon carbide region of the element region has a low-concentration region and a high-concentration region. The high-concentration region is disposed between the low-concentration region and the first surface. The concentration of a first conductivity type impurity in the high-concentration region is higher than that in the low-concentration region. The second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are disposed between the high-concentration region and the first surface.

5. The semiconductor device of claim 1, wherein, The silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of a second conductivity type, which is disposed between the first silicon carbide region and the ninth silicon carbide region and is separated from the third silicon carbide region in a first direction parallel to the first surface.

6. A semiconductor device, wherein, have: Component area; as well as The end region surrounds the component region. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode; A first silicide layer is disposed between the eighth silicon carbide region and the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The silicon carbide layer in the element region comprises: A first silicon carbide region of a first conductivity type has a first portion that is in contact with the first surface and opposite the gate electrode, and a second portion that is in contact with the first surface and in contact with the first electrode. A second silicon carbide region of a second conductivity type is disposed between the first silicon carbide region and the first surface; The third silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and is disposed on the end region side of the second silicon carbide region, and is electrically connected to the first electrode; The fourth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The fifth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of a first conductivity type is disposed between the fifth silicon carbide region and the first surface, and is electrically connected to the first electrode; and The eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the sixth silicon carbide region. The terminal region includes: A wiring layer, electrically connected to the first electrode; The second electrode; The silicon carbide layer; and A second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer. The silicon carbide layer in the terminal region comprises: The first silicon carbide region has a third portion that contacts the first surface and the wiring layer; The ninth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the element region, and is in contact with the third silicon carbide region; A tenth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separating it from the ninth silicon carbide region, and electrically connected to the wiring layer; and The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The wiring layer, except for the third contact portion, does not include any portion that directly contacts or contacts the ninth silicon carbide region through the silicide layer.

7. The semiconductor device of claim 6, wherein, The silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type, which is disposed between the ninth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region. The third contact portion comes into contact with the thirteenth silicon carbide region.

8. The semiconductor device of claim 7, wherein, The resistance between the third contact and the ninth silicon carbide region is higher than the resistance between the fourth contact and the tenth silicon carbide region.

9. The semiconductor device of claim 6, wherein, The first silicon carbide region of the element region has a low-concentration region and a high-concentration region. The high-concentration region is disposed between the low-concentration region and the first surface. The concentration of a first conductivity type impurity in the high-concentration region is higher than that in the low-concentration region. The second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are disposed between the high-concentration region and the first surface.

10. The semiconductor device of claim 6, wherein, The silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of a second conductivity type, which is disposed between the first silicon carbide region and the ninth silicon carbide region and is separated from the third silicon carbide region in a first direction parallel to the first surface.

11. A semiconductor device, wherein, have: Component area; as well as The end region surrounds the component region. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode; A first silicide layer is disposed between the eighth silicon carbide region and the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The silicon carbide layer in the element region comprises: A first silicon carbide region of a first conductivity type has a first portion that is in contact with the first surface and opposite the gate electrode, and a second portion that is in contact with the first surface and in contact with the first electrode. A second silicon carbide region of a second conductivity type is disposed between the first silicon carbide region and the first surface; The third silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and is disposed on the end region side of the second silicon carbide region, and is electrically connected to the first electrode; The fourth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The fifth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of a first conductivity type is disposed between the fifth silicon carbide region and the first surface, and is electrically connected to the first electrode; and The eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the sixth silicon carbide region. The terminal region includes: A wiring layer, electrically connected to the first electrode; The second electrode; The silicon carbide layer; and A second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer. The silicon carbide layer in the terminal region comprises: The first silicon carbide region has a third portion that contacts the first surface and the wiring layer; The ninth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the element region, and is in contact with the third silicon carbide region; A tenth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separating it from the ninth silicon carbide region, and electrically connected to the wiring layer; and The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The wiring layer also includes a fifth contact portion that contacts the ninth silicon carbide region.

12. The semiconductor device of claim 11, wherein, The fifth contact portion does not contact the first silicon carbide region.

13. The semiconductor device of claim 11, wherein, The resistance between the fifth contact and the ninth silicon carbide region is higher than the resistance between the fourth contact and the tenth silicon carbide region.

14. The semiconductor device of claim 11, wherein, The first silicon carbide region of the element region has a low-concentration region and a high-concentration region. The high-concentration region is disposed between the low-concentration region and the first surface. The concentration of a first conductivity type impurity in the high-concentration region is higher than that in the low-concentration region. The second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are disposed between the high-concentration region and the first surface.

15. The semiconductor device of claim 11, wherein, The silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of a second conductivity type, which is disposed between the first silicon carbide region and the ninth silicon carbide region and is separated from the third silicon carbide region in a first direction parallel to the first surface.

16. A semiconductor device, wherein, have: Component area; as well as The end region surrounds the component region. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode; A first silicide layer is disposed between the eighth silicon carbide region and the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The silicon carbide layer in the element region comprises: A first silicon carbide region of a first conductivity type has a first portion that is in contact with the first surface and opposite the gate electrode, and a second portion that is in contact with the first surface and in contact with the first electrode. A second silicon carbide region of a second conductivity type is disposed between the first silicon carbide region and the first surface; The third silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and is disposed on the end region side of the second silicon carbide region, and is electrically connected to the first electrode; The fourth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The fifth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of a first conductivity type is disposed between the fifth silicon carbide region and the first surface, and is electrically connected to the first electrode; and The eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the sixth silicon carbide region. The terminal region includes: A wiring layer, electrically connected to the first electrode; The second electrode; The silicon carbide layer; and A second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer. The silicon carbide layer in the terminal region comprises: The first silicon carbide region has a third portion that contacts the first surface and the wiring layer; The ninth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the element region, and is in contact with the third silicon carbide region; A tenth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounding the ninth silicon carbide region, separating it from the ninth silicon carbide region, and electrically connected to the wiring layer; and The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth and tenth silicon carbide regions. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion and a fourth contact portion that contacts the second silicide layer. The silicon carbide layer in the terminal region further includes a thirteenth silicon carbide region of a second conductivity type, which is disposed between the ninth silicon carbide region and the first surface. The impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region. The wiring layer also includes a fifth contact portion that contacts the thirteenth silicon carbide region.

17. The semiconductor device of claim 16, wherein, No silicide layer is provided between the fifth contact portion and the ninth silicon carbide region.

18. The semiconductor device of claim 16, wherein, The resistance between the fifth contact and the ninth silicon carbide region is higher than the resistance between the fourth contact and the tenth silicon carbide region.

19. The semiconductor device of claim 16, wherein, The first silicon carbide region of the element region has a low-concentration region and a high-concentration region. The high-concentration region is disposed between the low-concentration region and the first surface. The concentration of a first conductivity type impurity in the high-concentration region is higher than that in the low-concentration region. The second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are disposed between the high-concentration region and the first surface.

20. The semiconductor device of claim 16, wherein, The silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of a second conductivity type, which is disposed between the first silicon carbide region and the ninth silicon carbide region and is separated from the third silicon carbide region in a first direction parallel to the first surface.

21. A semiconductor device, wherein, have: Component area; as well as The end region surrounds the component region. The component region includes: First electrode; Second electrode; Gate electrode; A silicon carbide layer is disposed between the first electrode and the second electrode, having a first surface on the side of the first electrode and a second surface on the side of the second electrode; A first silicide layer is disposed between the eighth silicon carbide region and the first electrode; as well as A gate insulating layer is disposed between the gate electrode and the fifth silicon carbide region, and between the gate electrode and the first portion. The silicon carbide layer in the element region comprises: A first silicon carbide region of a first conductivity type has a first portion that is in contact with the first surface and opposite the gate electrode, and a second portion that is in contact with the first surface and in contact with the first electrode. A second silicon carbide region of a second conductivity type is disposed between the first silicon carbide region and the first surface; The third silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and is disposed on the end region side of the second silicon carbide region, and is electrically connected to the first electrode; The fourth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the third silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The fifth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the second silicon carbide region and the fourth silicon carbide region, opposite to the gate electrode, and electrically connected to the first electrode; The sixth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, and between the third silicon carbide region and the fourth silicon carbide region, and is in contact with the third silicon carbide region and the fourth silicon carbide region, and its depth is shallower than the depth of the third silicon carbide region and the depth of the fourth silicon carbide region. A seventh silicon carbide region of a first conductivity type is disposed between the fifth silicon carbide region and the first surface, and is electrically connected to the first electrode; and The eighth silicon carbide region of the second conductivity type is disposed between the sixth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the sixth silicon carbide region. The terminal region includes: A wiring layer, electrically connected to the first electrode; The second electrode; The silicon carbide layer; A second silicide layer is disposed between the eleventh silicon carbide region and the wiring layer; and A third silicide layer is disposed between the thirteenth silicon carbide region and the wiring layer. The silicon carbide layer in the terminal region comprises: The first silicon carbide region has a third portion that contacts the first surface and the wiring layer; The ninth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the element region, and is in contact with the third silicon carbide region; The tenth silicon carbide region of the second conductivity type is disposed between the first silicon carbide region and the first surface, surrounds the ninth silicon carbide region, is separated from the ninth silicon carbide region, and is electrically connected to the wiring layer. The eleventh silicon carbide region of the second conductivity type is disposed between the tenth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region; and The thirteenth silicon carbide region of the second conductivity type is disposed between the ninth silicon carbide region and the first surface, and the impurity concentration of the second conductivity type is higher than that of the ninth silicon carbide region and the tenth silicon carbide region. The first electrode includes a first contact portion that contacts the second portion and a second contact portion that contacts the first silicide layer. The wiring layer includes a third contact portion that contacts the third portion, a fourth contact portion that contacts the second silicide layer, and a fifth contact portion that contacts the third silicide layer. The ninth silicon carbide region includes: a first region in contact with the third silicon carbide region, and a second region surrounding the first region, separated from the first region, and in contact with the thirteenth silicon carbide region.

22. The semiconductor device of claim 21, wherein, The first silicon carbide region is disposed between the first region and the second region.

23. The semiconductor device of claim 21, wherein, The first distance between the first region and the second region in a first direction parallel to the first surface is more than 0.5 times and less than 3 times the second distance in the first direction between the fourth silicon carbide region and the fifth silicon carbide region.

24. The semiconductor device of claim 21, wherein, The first silicon carbide region of the element region has a low-concentration region and a high-concentration region. The high-concentration region is disposed between the low-concentration region and the first surface. The concentration of a first conductivity type impurity in the high-concentration region is higher than that in the low-concentration region. The second silicon carbide region, the third silicon carbide region, the fourth silicon carbide region, and the fifth silicon carbide region are disposed between the high-concentration region and the first surface.

25. The semiconductor device of claim 21, wherein, The silicon carbide layer in the terminal region further includes a twelfth silicon carbide region of a second conductivity type, which is disposed between the first silicon carbide region and the ninth silicon carbide region, in contact with the first region, and separated from the third silicon carbide region in a first direction parallel to the first surface.

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