Display panel and display device

Abstract

The invention provides a display panel and a display device. The problem of how to improve PPI in the prior art is solved. The display panel comprises: a substrate; the functional circuit comprises a plurality of transistor sets, each transistor set comprises at least one transistor arranged on the same layer, the transistor sets are located on one side of the substrate and are sequentially arranged in the direction away from the substrate, and orthographic projections of at least part of the transistor sets on the substrate are overlapped; and the transistors in the plurality of transistor groups are electrically connected, and the transistors which are directly and electrically connected are positioned on the same layer or adjacent layers.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and a display device. Background Technology

[0002] As consumer electronics devices move towards higher resolutions and higher screen-to-body ratios, the pixel density (PPI) of display panels continues to increase. This has led to a dramatic reduction in the physical space (pixel pitch) that each pixel can occupy.

[0003] The industry has already experimented with vertically arranged transistors to reduce layout space. Building on this, how to rationally arrange multiple transistors to further reduce the footprint and improve PPI has become one of the important research topics for those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of this application provide a display panel and a display device that solve the problem of how to improve PPI in the prior art.

[0005] The first aspect of this application provides a display panel, including: a substrate; and a functional circuit including a plurality of transistor groups, each transistor group including at least one transistor disposed on the same layer, the plurality of transistor groups being located on one side of the substrate and arranged sequentially in a direction away from the substrate, at least some of the transistor groups having overlapping orthographic projections on the substrate; the transistors in the plurality of transistor groups being electrically connected, and the directly electrically connected transistors being on the same layer or located on adjacent layers.

[0006] In conjunction with the first aspect, in some possible implementations, the difference in the number of transistors in adjacent transistor groups is less than or equal to 1.

[0007] In conjunction with the first aspect, in some possible implementations, the functional circuit further includes at least one capacitor located between adjacent transistor groups; preferably, the at least one capacitor includes multiple capacitors arranged in different layers.

[0008] In conjunction with the first aspect, in some possible implementations, the functional circuit includes a pixel circuit, and the display panel also includes a light-emitting device located on the side of the pixel circuit away from the substrate and electrically connected to the pixel circuit; preferably, the plurality of transistor groups include a first transistor group, a second transistor group, a third transistor group and a fourth transistor group arranged sequentially along the direction away from the substrate; preferably, the pixel circuit includes an 8T2C pixel circuit.

[0009] In conjunction with the first aspect, in some possible implementations, the plurality of transistor groups include a third transistor group, the third transistor group including a first transistor, the first transistor serving as a driving transistor, the first transistor including a top-gate transistor; preferably, the display panel further includes a fifth gate insulating layer, the fifth gate insulating layer being located between the gate and the channel of the first transistor, the thickness of the fifth gate insulating layer being in the range of 800-1400 Å; preferably, the third transistor group further includes a fourth transistor, the side projections of the first transistor and the fourth transistor coinciding on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor; preferably, the first electrode of the fourth transistor is connected to the first electrode of the first transistor, the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is connected to the first scan signal line.

[0010] In conjunction with the first aspect, in some possible implementations, the plurality of transistor groups further includes a fourth transistor group located on the side of the third transistor group away from the substrate; the functional circuit further includes a first capacitor, the first plate of which is located between the third transistor group and the fourth transistor group, and the gate of the first transistor is multiplexed as the second plate of the first capacitor; preferably, the fourth transistor group includes a sixth transistor, a seventh transistor, and an eighth transistor, and the sixth and seventh transistors are symmetrically arranged on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor, with the side projections of the seventh transistor and the eighth transistor coinciding; preferably, the first electrode of the sixth transistor is connected to the second electrode of the first transistor, the second electrode of the sixth transistor is connected to a light-emitting device, and the gate of the sixth transistor is connected to a second light-emitting control signal line; the first electrodes of the seventh transistor and the eighth transistor are respectively connected to the first plate of the first capacitor, the second electrodes of the seventh transistor and the eighth transistor are respectively connected to a first initialization signal line, the gate of the seventh transistor is connected to a first scan signal line, and the gate of the eighth transistor is connected to a second scan signal line.

[0011] In conjunction with the first aspect, in some possible implementations, the plurality of transistor groups further includes a second transistor group located on the side of the third transistor group closer to the substrate. The second transistor group includes a fifth transistor, the first terminal of which is connected to the first terminal of the first transistor, the second terminal of which is connected to a power signal line, and the gate of which is connected to a first light emission control signal line. Preferably, the plurality of transistors further includes a first transistor group located on the side of the second transistor group closer to the substrate. The first transistor group includes a second transistor and a third transistor, which are symmetrically arranged in a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor. Preferably, the pixel circuit further includes a second capacitor located between the second transistor group and the first transistor group. Preferably, the first plate of the second capacitor is connected to the first terminal of the first transistor, the second plate of the second capacitor is connected to the first terminal of the third transistor, the second terminal of the third transistor is connected to a second initialization signal line, the gate of the third transistor is connected to a second light emission control signal line, the first terminal of the second transistor is connected to the second plate of the second capacitor, the second terminal of the second transistor is connected to a data signal line, and the gate of the second transistor is connected to a second scan signal line.

[0012] In conjunction with the first aspect, in some possible implementations, the plurality of transistor groups include a third transistor group, the third transistor group including a first transistor, the first transistor being used as a driving transistor, the first transistor including a bottom gate transistor; preferably, the display panel further includes a fourth gate insulating layer, the fourth gate insulating layer being located between the gate and the channel of the first transistor, the thickness of the fourth gate insulating layer being in the range of 2000-5000 Å; preferably, the third transistor group further includes a fourth transistor, the side projection of the first transistor and the side projection of the fourth transistor coinciding in a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor; preferably, the first electrode of the fourth transistor is connected to the first electrode of the first transistor, the second electrode of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is connected to the first scan signal line.

[0013] In conjunction with the first aspect, in some possible implementations, the plurality of transistor groups further includes a second transistor group located on the side of the third transistor group closer to the substrate; the functional circuit further includes a first capacitor, the first plate of which is located between the second transistor group and the third transistor group, and the gate of the first transistor is multiplexed as the second plate of the first capacitor; preferably, the second transistor group includes a fifth transistor, the first electrode of which is connected to the first electrode of the first transistor, the second electrode of which is connected to a power signal line, and the gate of which is connected to a first light emission control signal line; on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor, the fifth transistor and the first transistor are staggered in a direction perpendicular to the substrate; preferably, the plurality of transistor groups further includes a first transistor group and a fourth transistor group, the first transistor group located between the second transistor group and the substrate, and the fourth transistor group located on the side of the third transistor group away from the substrate.

[0014] A second aspect of this application provides a display device, including the display panel provided in any of the above embodiments.

[0015] According to the display panel and display device provided in the embodiments of this application, by dividing multiple transistors in the functional circuit into multiple transistor groups, and stacking these multiple transistor groups along a direction perpendicular to the substrate, the occupation of horizontal layout space is reduced. Simultaneously, by setting directly electrically connected transistors T to be located in the same or adjacent layers, without cross-layer connections, the number of conductive vias is minimized, thereby further reducing the occupation of horizontal layout space. Combining these two aspects, the resolution of the display panel is improved. Attached Figure Description

[0016] Figure 1 This is a top view of the display panel provided in one embodiment of this application.

[0017] Figure 2 Provided for an embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel.

[0018] Figure 3 Provided for the second embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel.

[0019] Figure 4 Provided for the third embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel.

[0020] Figure 5 Provided for an embodiment of this application Figure 4 The circuit diagram corresponding to the cross-sectional structure shown.

[0021] Figure 6Provided for the fourth embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel.

[0022] Figure 7 The driving timing diagram provided for the fifth embodiment of this application.

[0023] Figure 8 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0024] AMOLED display technology has become the mainstream technology for displays in watches, mobile phones, and other devices. With its increasing market share and superior display performance, it is gradually penetrating the fields of virtual reality (VR) and augmented reality (AR). However, based on the existing film structure, it is difficult to meet the high PPI requirements, becoming a major obstacle for AMOLED technology to penetrate into small-sized AR and VR display products, which urgently needs to be addressed.

[0025] In view of this, embodiments of this application provide a display panel and a display device. By dividing multiple transistors in the functional circuit into multiple groups, and stacking these groups along a direction perpendicular to the substrate, the horizontal layout space occupied is reduced. Simultaneously, by arranging directly electrically connected transistors in the same or adjacent layers without cross-layer connections, the number of conductive vias is minimized, further reducing the horizontal layout space occupied. Combining these two aspects, the resolution of the display panel is improved.

[0026] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0027] In the accompanying drawings, the dimensions of layers and regions may be exaggerated for clarity. It is understood that when a structure is referred to as being "on" or "below" another structure, the structure may be directly on or below the other structure, or there may be intermediate structures. The same reference numerals always indicate the same structure. Structures referred to herein include any of the following: membrane, element, device, component, assembly.

[0028] When a structure is referred to as being “connected” to another structure, it can be directly connected to the other structure or indirectly connected to the other structure by means of one or more intermediate structures placed between them.

[0029] Figure 1This is a top view of the display panel provided in one embodiment of this application. Figure 2 Provided for an embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel. Figure 1 As shown, the display panel includes a display area AA and a non-display area NA surrounding the display area AA. Figure 2 The cross-sectional structure shown can correspond to Figure 1 The cross-sectional line A1A2 located in the display area AA can also correspond to Figure 1 The cross-sectional line B1B2 is located in the non-display area NA.

[0030] Combination Figure 1 and Figure 2 As shown, the display panel includes a substrate 10 and a functional circuit 20. The functional circuit 20 includes a plurality of transistor groups S, each transistor group including at least one transistor T disposed on the same layer. The plurality of transistor groups S are located on one side of the substrate 10 and are arranged sequentially in a direction away from the substrate 10. At least some of the transistor groups S have overlapping orthographic projections on the substrate 10. The transistors T in the plurality of transistor groups S are electrically connected, and the directly electrically connected transistors T are on the same layer or located on adjacent layers.

[0031] In this embodiment, the functional circuit 20 can be any circuit module in the display panel capable of performing a specific function. For example, the functional circuit 20 includes a pixel circuit and a gate driving circuit. The pixel circuit, such as a 7T1C pixel circuit, an 8T1C pixel circuit, an 8T2C pixel circuit, etc., can be located in the display area AA. The gate driving circuit can be located in the non-display area NA.

[0032] The functional circuit 20 includes a plurality of transistors T which are electrically connected. The term "electrical connection" here can refer to a direct electrical connection (i.e., there are no other components between them, and they are directly connected by wires) or an indirect electrical connection through other components.

[0033] All or some of the transistors in the functional circuit 20 are divided into multiple transistor groups S. The multiple transistor groups S are stacked along a third direction Z perpendicular to the substrate 10. Each transistor group is located within a composite structure layer, and the multiple transistor groups S are respectively located within multiple sequentially stacked composite structure layers. Within a composite structure layer, the active layers, gate layers, source and drain layers of multiple transistors T in the same transistor group S are on the same layer. A transistor group S includes at least one transistor T, and multiple transistors T in the same transistor group S are located in the same composite structure layer. The number of transistors T in different transistor groups S may be equal or unequal.

[0034] Directly electrically connected transistors T in the same or adjacent layers means that the directly electrically connected transistors T are located in the same composite structure layer or in adjacent composite structure layers. In other words, directly electrically connected transistors T belong to the same transistor group S, or belong to adjacent transistor groups S.

[0035] According to the display panel provided in this embodiment, by dividing the multiple transistors T in the functional circuit 20 into multiple transistor groups S, and stacking these multiple transistor groups S along a direction perpendicular to the substrate 10, the occupation of horizontal layout space is reduced. Simultaneously, by setting the directly electrically connected transistors T to be located in the same or adjacent layers, without cross-layer connections, the number of conductive vias is minimized, thereby further reducing the occupation of horizontal layout space. Combining these two aspects, the resolution of the display panel is improved.

[0036] In one embodiment, see Figure 2 The difference in the number of transistors T in adjacent transistor groups S is less than or equal to 1. In this way, the difference in the number of transistors T in multiple transistor groups S can be minimized as much as possible, so that multiple transistors T are distributed as evenly as possible in multiple transistor groups S, thereby making the horizontal layout space occupied by different transistor groups S roughly the same, thus achieving a higher PPI in the case of vertical stacking.

[0037] Figure 3 Provided for the second embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel. Figure 3 The display panel shown and Figure 2 The difference in the display panels shown is that, as Figure 3 As shown, in this embodiment, the functional circuit further includes at least one capacitor C, which is located between adjacent transistor groups S. In this case, the orthographic projection of either of the two transistor groups S adjacent to the capacitor C on the substrate 10 overlaps with the orthographic projection of the capacitor C on the substrate 10. This has the advantage of reducing the horizontal layout space occupied by the capacitor C, further improving the PPI.

[0038] In one embodiment, see Figure 3 At least one capacitor C includes multiple capacitors C, which are arranged in different layers. The advantages are twofold: firstly, it facilitates the electrical connection between different devices in the functional circuit 20, reducing or avoiding connection methods such as drilling and wire wrapping; secondly, it ensures that the capacitor C is large enough to meet functional requirements.

[0039] Figure 4 Provided for the third embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel. Figure 4The difference between the display panel shown and the display panel provided in any of the above embodiments is that, in this embodiment, the functional circuit 20 includes a pixel circuit. The display panel also includes a light-emitting device 30, which is located on the side of the pixel circuit away from the substrate 10 and is electrically connected to the pixel circuit. For example, the anode 31 of the light-emitting device 30 is electrically connected to the pixel circuit.

[0040] In one embodiment, the plurality of transistor groups S includes a first transistor group S1, a second transistor group S2, a third transistor group S3, and a fourth transistor group S4 arranged sequentially along a direction away from the substrate 10. In this embodiment, the plurality of transistors T in the pixel circuit are divided into at least four transistor groups S.

[0041] In one embodiment, the pixel circuit includes an 8T2C pixel circuit.

[0042] Specifically, such as Figure 4 As shown, the third transistor group S3 includes a first transistor T1, which serves as a driving transistor and includes a top-gate transistor. The use of a top-gate transistor in the first transistor T1 is a targeted optimization for "high brightness" display performance. It allows for a thin gate insulating layer physical design, achieving excellent driving capability and is one of the key technologies to meet the needs of high-end displays (especially VR / AR scenarios that may require high brightness). In this case, the display panel also includes a fifth gate insulating layer GI5, located between the gate G1 and channel A1 of the first transistor T1. The thickness D1 of the fifth gate insulating layer GI5 ranges from 800 to 1400 Å. For example, the thickness D1 is 1000 Å. This range allows for a thinner fifth gate insulating layer GI5, ensuring injection conductivity, which facilitates a smaller subthreshold swing in the first transistor T1, achieving a larger on-state current and enabling the display panel to achieve high brightness.

[0043] Figure 5 Provided for an embodiment of this application Figure 4 The circuit diagram corresponding to the cross-sectional structure shown. Combined with... Figure 4 and Figure 5 As shown, in this embodiment, the third transistor group S3 further includes a fourth transistor T4, with a cross-section Q (i.e., perpendicular to the substrate 10 and parallel to the channel A1 direction of the first transistor T1) on the cross-section 10. Figure 4On the cross section shown, the side projection of the first transistor T1 and the side projection of the fourth transistor T4 coincide, that is, the side projection of the first transistor T1 on cross section Q and the side projection of the fourth transistor T4 on cross section Q coincide. Specifically, the side projection of the gate G1 of the first transistor T1 coincides with the side projection of the gate G4 of the fourth transistor T4, and the side projection of the channel A1 of the first transistor T1 coincides with the side projection of the channel A4 of the fourth transistor T4. The advantages are twofold: firstly, simplified process and improved uniformity. Specifically, the coincidence of the side projections of the first transistor T1 and the fourth transistor T4 means that they can achieve a high degree of uniformity in manufacturing process steps, the thickness and pattern of the material layers used (such as gate, active layer, insulating layer, source and drain electrodes). This greatly simplifies the design and manufacturing process of the photomask. Secondly, stable and adaptable performance. Specifically, the first transistor T1 is the driving transistor, and its performance (such as threshold voltage and mobility) directly affects the uniformity and brightness of the display. The fourth transistor T4 is a key switch directly connected to the gate G1 of the first transistor T1, used for compensation and data writing. The overlapping cross-sectional structure of the two transistors means that their electrical characteristics (such as channel formation quality and interface states) are easier to keep consistent in the process, which helps to improve the accuracy and stability of the pixel circuit compensation effect and reduce performance mismatch caused by process fluctuations.

[0044] In one embodiment, combined Figure 4 and Figure 5 As shown, the first terminal of the fourth transistor T4 is connected to the first terminal of the first transistor T1, the second terminal of the fourth transistor T4 is connected to the gate G1 of the first transistor T1, and the gate G4 of the fourth transistor T4 is connected to the first scan signal line Scan1. The advantage is that the connection between the fourth transistor T4 and the first transistor T1 forms the core path for the "threshold voltage compensation" function in the pixel circuit. Its core function is to short-circuit the gate G1 and source of the first transistor T1 at a specific stage, making them connected in the form of a diode. This allows the threshold voltage (Vth) data of the first transistor T1 to be written and stored in the capacitor, compensating for the adverse effect of Vth drift of the first transistor T1 on brightness.

[0045] In one embodiment, combined Figure 4 and Figure 5 As shown, the functional circuit 20 also includes a first capacitor C1. The first plate of the first capacitor C1 is located between the third transistor group S3 and the fourth transistor group S4. The gate G1 of the first transistor T1 is multiplexed as the second plate of the first capacitor C1. A first dielectric layer CI1 is disposed between the two plates of the first capacitor C1. The first dielectric layer CI1 can be made of materials with higher dielectric constants than SiO, such as ZrO, HfO, and AlO, in order to reduce the area of ​​the capacitor without reducing the capacitance value.

[0046] In one embodiment, combined Figure 4 and Figure 5 As shown, the fourth transistor group S4 includes a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8. On a cross-section perpendicular to the substrate 10 and parallel to the channel A1 direction of the first transistor T1, the sixth transistor T6 and the seventh transistor T7 are symmetrically arranged, and the side projections of the seventh transistor T7 and the eighth transistor T8 coincide. Specifically, the gate G6 of the sixth transistor T6 is symmetrical to the gate G7 of the seventh transistor T7, and the channel A6 of the sixth transistor T6 is symmetrical to the channel A7 of the seventh transistor T7. The side projections of the gate G7 of the seventh transistor T7 and the gate G8 of the eighth transistor T8 coincide, and the side projections of the channel A7 of the seventh transistor T7 and the channel A8 of the eighth transistor T8 coincide.

[0047] In one embodiment, combined Figure 4 and Figure 5 As shown, the first terminal of the sixth transistor T6 is connected to the second terminal of the first transistor T1, and the second terminal of the sixth transistor T6 is connected to the light-emitting device 30. The gate G6 of the sixth transistor T6 is connected to the second light-emitting control signal line EM2. The first terminals of the seventh transistor T7 and the eighth transistor T8 are respectively connected to the first plate of the first capacitor C1, and the second terminals of the seventh transistor T7 and the eighth transistor T8 are respectively connected to the first initialization signal line Vref. The gate G7 of the seventh transistor T7 is connected to the first scan signal line Scan1, and the gate G8 of the eighth transistor T8 is connected to the second scan signal line Scan2.

[0048] In one embodiment, combined Figure 4 and Figure 5 As shown, the second transistor group S2 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the first terminal of the first transistor T1, the second terminal of the fifth transistor T5 is connected to the power supply signal line Vdd, and the gate G5 of the fifth transistor T5 is connected to the first light emission control signal line EM1.

[0049] In one embodiment, combined Figure 4 and Figure 5 As shown, the first transistor group T1 includes a second transistor T2 and a third transistor T3. On a cross-section perpendicular to the substrate 10 and parallel to the channel A1 of the first transistor T1, the second transistor T2 and the third transistor T3 are symmetrically arranged about an axis perpendicular to the channel A1 of the first transistor T1. Specifically, the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 are symmetrically arranged, and the channels A2 of the second transistor T2 and the channel A3 of the third transistor T3 are symmetrically arranged.

[0050] In one embodiment, combined Figure 4and Figure 5 As shown, the pixel circuit also includes a second capacitor C2, which is located between the second transistor group S2 and the first transistor group S1. A second dielectric layer CI2 is disposed between the two plates of the second capacitor C2. The second dielectric layer CI2 can be made of materials with higher dielectric constants than SiO, such as ZrO, HfO, and AlO, in order to reduce the area of ​​the capacitor without reducing the capacitance value.

[0051] In one embodiment, combined Figure 4 and Figure 5 As shown, the first plate of the second capacitor C2 is connected to the first terminal of the first transistor T1, the second plate of the second capacitor C2 is connected to the first terminal of the third transistor T3, the second terminal of the third transistor T3 is connected to the second initialization signal line Vini, the gate G3 of the third transistor T3 is connected to the second light emission control signal line EM2, the first terminal of the second transistor T2 is connected to the second plate of the second capacitor C2, the second terminal of the second transistor T2 is connected to the data signal line Vdata, and the gate G2 of the second transistor T2 is connected to the second scan signal line Scan2.

[0052] In this embodiment, all transistors T except for the first transistor T1 are switching transistors.

[0053] In one embodiment, the active layers of multiple transistors T are all oxide layers. Depending on the product requirements, the material of the oxide layer can be chosen differently. The oxide layer material includes metal oxide semiconductors, and the metal oxide includes binary compounds (ABx), ternary compounds (ABxCy), or quaternary compounds (ABxCyDz) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). For example, metal oxides include indium oxide (In Oxide), indium zinc oxide (In-Zn Oxide), indium tin oxide (In-Sn Oxide), indium titanium oxide (In-Ti Oxide), indium gallium oxide (In-Ga Oxide), indium aluminum gallium oxide (In-Ga-Al Oxide), indium gallium tin oxide (In-Ga-SnOxide, also written as IGTO), gallium zinc oxide (Ga-Zn Oxide, also written as GZO), aluminum zinc oxide (Al-Zn Oxide, also written as AZO), indium aluminum zinc oxide (In-Al-Zn Oxide, also written as IAZO), indium tin zinc oxide (In-Sn-ZnOxide, also written as ITZO), indium titanium zinc oxide (In-Ti-Zn Oxide), indium gallium zinc oxide (In-Ga-Zn Oxide, also written as IGZO), and indium gallium tin zinc oxide (In-Ga-Sn-Zn). Oxide, also written as IGZTO, indium gallium aluminum zinc oxide (In-Ga-Al-ZnOxide, also written as IGAZO, IGZAO, or IAGZO), gallium tin oxide (Ga-Sn Oxide), and aluminum tin oxide (Al-SnOxide). For example, the oxide layer material can be a low-mobility oxide material such as IGZO to meet product stability and high subthreshold oscillation requirements; or it can be a high-mobility oxide material such as IZO, IGO, InO, or ITZO to meet high brightness requirements.

[0054] In one embodiment, multiple transistors T can be configured as four-terminal devices, or connected with the source via the top gate or bottom gate, or configured as three-terminal devices without a bottom gate or top gate.

[0055] In one embodiment, the display panel further includes a light-shielding layer 51 located between the substrate 10 and the pixel circuitry. The orthographic projection of the active layers of transistors T in the first transistor group S1 (e.g., second transistor T2 and third transistor T3) onto the substrate 10 lies within the orthographic projection range of the light-shielding layer 51 onto the substrate 10. The light-shielding layer 51 can also be reused as the gate of transistor T in the first transistor group S1. For example, as... Figure 4As shown, the light-shielding layer 51 includes a first light-shielding part and a second light-shielding part. The first light-shielding part serves as the second gate G20 of the second transistor T2, and the second light-shielding part serves as the second gate G30 of the third transistor T3. That is, both the second transistor T2 and the third transistor T3 are dual-gate transistors.

[0056] In one embodiment, the display panel further includes the following layers stacked sequentially along the direction away from the substrate 10: a first gate insulating layer GI1, a second gate insulating layer GI2, a second buffer layer BL2, a third buffer layer BL3, a first dielectric layer CI1, a fourth buffer layer BL4, a third gate insulating layer GI3, a fourth gate insulating layer GI4, a fifth buffer layer BL5, a fifth gate insulating layer GI5, a second dielectric layer CI2, a sixth buffer layer BL6, a sixth gate insulating layer GI6, a seventh buffer layer BL7, and a planarization layer PLN.

[0057] The first gate insulating layer GI1 is located between the light-shielding layer 51 and the first transistor group S1.

[0058] The second gate insulating layer GI2 is located between the gate G2 and the channel A2 of the second transistor T2, and between the gate G3 and the channel A3 of the third transistor T3.

[0059] The second buffer layer BL2 is located between the gate of the transistor in the first transistor group S1 and the first conductive layer SD1.

[0060] The display panel has a first via H1, which penetrates the second buffer layer BL2 and the second gate insulating layer GI2. The first conductive layer SD1 includes the first electrode of the second transistor T2, which is multiplexed as the first electrode of the third transistor T3. The first electrode of the second transistor T2 is connected to the conductor between the second transistor T2 and the third transistor T3 through the first via H1.

[0061] The third buffer layer BL3 is located between the first transistor group S1 and the second capacitor C2.

[0062] The display panel has a second via H2, which penetrates the third buffer layer BL3. The second plate of the second capacitor C2 is connected to the first electrode of the second transistor T2 through the second via H2.

[0063] The first dielectric layer CI1 is located between the first and second plates of the second capacitor C2.

[0064] The fourth buffer layer BL4 is located between the second capacitor C2 and the fifth transistor T5.

[0065] The display panel has a third via H3, which penetrates the fourth buffer layer BL4. The conductor portion on the channel A5 side of the fifth transistor T5 is connected to the first plate of the second capacitor C2 through the third via H3.

[0066] The third gate insulating layer GI3 is located between the channel A5 and the gate G5 of the fifth transistor T5.

[0067] The fourth gate insulating layer GI4 is located between the gate G5 of the fifth transistor T5 and the second conductive layer SD2. The second conductive layer SD2 includes the first electrode of the fifth transistor T5, the second electrode of the fifth transistor T5, and the first transition portion 41, which is located between the first electrode and the second electrode of the fifth transistor T5.

[0068] The display panel has two fourth vias H4, which penetrate the fourth gate insulating layer GI4 and the third gate insulating layer GI3. The first electrode of the fifth transistor T5 is connected to the conductor portion on one side of the channel A5 of the fifth transistor T5 through one fourth via H4, and the second electrode of the fifth transistor T5 is connected to the conductor portion on the other side of the channel A5 of the fifth transistor T5 through another fourth via H4.

[0069] The fifth buffer layer BL5 is located between the second conductive layer SD2 and the third transistor group S3.

[0070] The display panel has a fifth via H5, which penetrates the fifth buffer layer BL5. The conductor portion on the channel A1 side of the first transistor T1 is connected to the first electrode of the fifth transistor T5 through the fifth via H5.

[0071] The fifth gate insulating layer GI5 is located between the gate G1 and the channel A1 of the first transistor T1.

[0072] The second dielectric layer CI2 is located between the first and second plates of the first capacitor C1.

[0073] The display panel has a sixth via H6, which penetrates the second dielectric layer CI2 and the fifth gate insulating layer GI5. The second transition portion 42 is connected to the conductor portion on the other side of the channel A1 of the first transistor T1 through the sixth via H6. The second transition portion 42 and the second electrode of the first capacitor C1 are on the same layer, both located on the third conductive layer SD3.

[0074] The sixth buffer layer BL6 is located between the third conductive layer SD3 and the fourth transistor group S4.

[0075] The display panel has a seventh via H7, and the conductor between the sixth transistor T6 and the seventh transistor T7 is connected to the second plate of the first capacitor C1 through the seventh via H7.

[0076] The sixth gate insulating layer GI6 is located between the channel A6 and gate G6 of the sixth transistor T6, between the channel A7 and gate G7 of the seventh transistor T7, and between the channel A8 and gate G8 of the eighth transistor T8.

[0077] The seventh buffer layer BL7 is located between the gate of transistor T in the fourth transistor group S4 and the fourth conductive layer SD4.

[0078] The display panel has an eighth via H8 and multiple ninth vias H9. The first and second terminals of the sixth transistor T6 are connected to the conductor portions on both sides of the channel A6 of the sixth transistor T6 through a ninth via H9. The first and second terminals of the seventh transistor T7 are connected to the conductor portions on both sides of the channel A7 of the seventh transistor T7 through a ninth via H9. The first and second terminals of the eighth transistor T8 are connected to the conductor portions on both sides of the channel A8 of the eighth transistor T8 through a ninth via H9. The first terminal of the sixth transistor T6 is further connected to the second transition section 42 through the eighth via H8.

[0079] The planarization layer PLN is located between the fourth conductive layer SD4 and the anode 31.

[0080] The display panel has a tenth via H10, which penetrates the planarization layer PLN. The anode 31 is connected to the second electrode of the sixth transistor T6 through the tenth via H10.

[0081] According to the display panel provided in this embodiment, the transistors T in the 8T2C pixel circuit are stacked vertically on the substrate 10 in groups. On the one hand, since there are more transistors in 8T2C, the circuit compensation effect is better. On the other hand, vertical stacking can reduce the horizontal layout space occupied by a single pixel circuit, which is conducive to achieving high PPI requirements and makes it possible to apply 8T2C in the VR and AR fields.

[0082] Figure 6 Provided for the fourth embodiment of this application Figure 1 The diagram shows a cross-sectional view of the display panel. Figure 6 For the corresponding Figure 5 Another cross-sectional structure of the circuit schematic shown. (See diagram below.) Figure 6 The display panel shown is Figure 4 The difference in the display panel shown is that, in this embodiment, it combines... Figure 6 and Figure 5 As shown, the third transistor group S3 includes a first transistor T1, which is used as a driving transistor and includes a bottom gate transistor.

[0083] In one embodiment, combined Figure 6 and Figure 5As shown, the display panel also includes a fourth gate insulating layer GI4, which is located between the gate G and the channel A1 of the first transistor T1. The thickness D2 of the fourth gate insulating layer GI4 ranges from 2000 to 5000 Å. For example, the thickness D2 is 3500 Å. The relatively large thickness of the fourth gate insulating layer GI4 within this range is beneficial for achieving a larger subthreshold swing, which is beneficial for grayscale expansion of the display panel and improves the unevenness of low grayscale display.

[0084] In one embodiment, combined Figure 6 and Figure 5 As shown, the third transistor group S3 also includes a fourth transistor T4. On a cross section perpendicular to the substrate 10 and parallel to the channel A1 direction of the first transistor T1, the side projection of the first transistor T1 and the side projection of the fourth transistor T4 coincide.

[0085] In one embodiment, combined Figure 6 and Figure 5 As shown, the first terminal of the fourth transistor T4 is connected to the first terminal of the first transistor T1, the second terminal of the fourth transistor T4 is connected to the gate G1 of the first transistor T1, and the gate G4 of the fourth transistor T4 is connected to the first scan signal line Scan1.

[0086] In one embodiment, combined Figure 6 and Figure 5 As shown, the functional circuit also includes a first capacitor C1, the first plate of the first capacitor C1 is located between the second transistor group S2 and the third transistor group S3, and the gate G1 of the first transistor T1 is multiplexed as the second plate of the first capacitor C1.

[0087] In one embodiment, combined Figure 6 and Figure 4As shown, the second transistor group S2 includes a fifth transistor T5. The first terminal of the fifth transistor T5 is connected to the first terminal of the first transistor T1, the second terminal of the fifth transistor T5 is connected to the power signal line Vdd, and the gate G5 of the fifth transistor T5 is connected to the first light-emitting control signal line EM1. On a cross-section perpendicular to the substrate 10 and parallel to the channel A1 direction of the first transistor T1, the fifth transistor T5 and the first transistor T1 are staggered in a direction perpendicular to the substrate 10. This staggered arrangement means that on this cross-section, along the first direction X, the first transistor T1 and the fifth transistor T5 are arranged sequentially, and in the third direction Z, the first transistor T1 and the fifth transistor T5 do not overlap, or only partially overlap. The advantage of this staggered arrangement is that it optimizes the path layout of the power signal line Vdd, reducing voltage drop and signal interference. Specifically, staggering the fifth transistor T5 and the first transistor T1 on the horizontal plane provides a more direct and wider routing path for the power signal line Vdd. The power signal line Vdd can be directly connected to the area where the fifth transistor T5 is located via a bypass, without having to force its way through or be close to the complex structure layer below the first transistor T1. This reduces wiring resistance and parasitic coupling with other signal lines (such as data lines and scan lines), helps stabilize the power supply voltage, and reduces brightness unevenness.

[0088] In one embodiment, see Figure 4 The first transistor T1 can also be a dual-gate transistor. In this case, the first transistor T1 further includes a second gate G10, which is located on the side of the channel A1 of the first transistor T1 away from the substrate 10. Correspondingly, the fourth transistor T4 further includes a second gate G40, which is located on the side of the channel A4 of the fourth transistor T4 away from the substrate 10.

[0089] In one embodiment, the display panel further includes, sequentially stacked along a direction away from the substrate 10, the following layers: a first buffer layer BL1, a first gate insulating layer GI1, a second gate insulating layer GI2, a second buffer layer BL2, a third buffer layer BL3, a first dielectric layer CI1, a fourth buffer layer BL4, a third gate insulating layer GI3, an eighth buffer layer BL8, a second dielectric layer CI2, a seventh gate insulating layer GI7, a fifth gate insulating layer GI5, a ninth buffer layer BL9, a sixth buffer layer BL6, a sixth gate insulating layer GI6, a seventh buffer layer BL7, and a planarization layer PLN. The film structure between the fourth buffer layer BL4 and the substrate 10 is... Figure 6 The embodiment shown is the same, and the film structure between the sixth buffer layer BL6 and the anode 31 is the same. Figure 4 The embodiments shown are the same, and will not be described again here.

[0090] Figure 4 The display panel shown and Figure 4The difference in the display panel shown lies in the film structure between the third gate insulating layer GI3 and the ninth buffer layer BL9.

[0091] Specifically, the third gate insulating layer GI3 is located between the channel A5 and the gate G5 of the fifth transistor T5.

[0092] The eighth buffer layer BL8 is located between the gate of the fifth transistor T5 and the second conductive layer SD2.

[0093] The display panel has multiple eleventh vias H11, which penetrate the eighth buffer layer BL8 and the third gate insulating layer GI3. The first and second terminals of the fifth transistor T5 are respectively connected to the conductor portions on both sides of the channel A5 of the fifth transistor T5 through an eleventh via H11.

[0094] The second dielectric layer CI2 is located between the first and second plates of the first capacitor C1. The first plate is located on the second conductive layer SD2, which also includes a third transition portion 43.

[0095] The display panel has a twelfth via H12, which penetrates the second dielectric layer CI2. The third adapter 43 is connected to the first electrode of the fifth transistor T5 through the twelfth via H12.

[0096] The seventh gate insulating layer GI7 is located between the gate G1 and the channel A1 of the first transistor T1, and between the gate G4 and the channel A4 of the fourth transistor T4.

[0097] The display panel has a thirteenth via H13, which penetrates the seventh gate insulating layer GI7. The conductor portion on the channel A1 side of the first transistor T1 is connected to the third transition portion 43 through the thirteenth via H13.

[0098] The fifth gate insulating layer GI5 is located between the channel A1 and the second gate G10 of the first transistor T1, and between the channel A4 and the second gate G40 of the fourth transistor T4.

[0099] The ninth buffer layer BL9 is located between the second gate G10 of the first transistor T1 and the third conductive layer SD3.

[0100] The display panel has a fourteenth via H14, which penetrates the ninth buffer layer BL9, the fifth gate insulating layer GI5, the seventh gate insulating layer GI7, and the second dielectric layer CI2. The conductor portion between the channel A6 of the sixth transistor T6 and the channel A7 of the seventh transistor T7 is connected to the second plate of the first capacitor C1 through the fourteenth via H14.

[0101] The display panel and provided in this embodiment Figure 7The structural details of the same display panel shown are not described in detail in this embodiment; please refer to [link to relevant documentation]. Figure 5 The illustrated embodiment.

[0102] Figure 7 This is a driving timing diagram provided in the fifth embodiment of this application. This driving timing diagram is applicable to… Figure 8 The pixel circuit shown. (See attached image.) Figure 8 The driving process of the pixel circuit includes initialization stage t1, compensation stage t2, data writing stage t3, and light emission stage t4. The following section combines... Figure 8 The driving process of the pixel circuit is explained.

[0103] Initialization phase t1: The first light-emitting control signal line EM1 is set to a high level, and the fifth transistor T5 is turned on. The first scan signal line Scan1 is set to a high level, and the fourth transistor T4 and the seventh transistor T7 are turned on. The second scan signal line Scan2 is set to a high level, and the second transistor T2 and the fifth transistor T5 are turned on. In this case, the high-voltage power supply signal in the power supply signal line Vdd is provided to the gate G1 of the first transistor T1 through the fifth transistor T5 and the fourth transistor T4, thereby initializing the gate G1 of the first transistor T1. The first initialization signal in the first initialization signal line Vref is provided to the anode of the light-emitting device 30 through the seventh transistor T7 and the eighth transistor T8, thereby initializing the anode of the light-emitting device 30. The data signal in the data signal line Vdata is provided to the second plate of the second capacitor C2 through the second transistor T2, thereby initializing the second capacitor C2.

[0104] Compensation phase t2: The second light-emitting control signal line EM2 is set to a high level, and the third transistor T3 and the sixth transistor T6 are turned on. The first scan signal line Scan1 remains high, and the fourth transistor T4 and the seventh transistor T7 remain on. The first terminal and gate G1 of the first transistor T1 are shorted to achieve diode compensation. At the same time, the second initialization signal in the second initialization signal line Vini is provided to the second plate of the second capacitor C2 through the third transistor T3. During this process, when the potential of the gate G1 of the first transistor T1 drops to a constant value, compensation for the threshold voltage of the first transistor T1 is achieved.

[0105] Data writing phase t3: The first scan signal in the first scan signal line Scan1 remains high, and the fourth transistor T4 and the seventh transistor T7 remain on. The second scan signal in the second scan signal line Scan2 is set to high, and the second transistor T2 and the eighth transistor T8 are on. The data signal in the data signal line Vdata is written to the gate G1 of the first transistor T1 through the second transistor T2, the second capacitor C2, and the fourth transistor T4.

[0106] Emission stage t4: The first light-emitting control signal line EM1 is set to a high level, and the fifth transistor T5 is turned on. The second light-emitting control signal line EM2 is set to a high level, and the third transistor T3 and the sixth transistor T6 are turned on, causing the light-emitting device 30 to emit light.

[0107] ​ This is a schematic diagram of the structure of a display device provided in an embodiment of this application. ​ As shown, the display device includes the display panel provided in any of the above embodiments.

[0108] Display device 700 is a product with image display capabilities. For example, display device 700 can be used to display static images, such as pictures or photographs. Display device 700 can also be used to display moving images, such as videos.

[0109] Display device 700 can be a laptop, mobile phone, handheld or portable computer, camera, camcorder, in-vehicle smart central control screen, calculator, smartwatch, GPS navigator, electronic photo, electronic billboard or sign, projector, etc.

[0110] In addition, the display device 700 can also perform functions such as taking photos, recording videos, fingerprint recognition, and facial recognition. Accordingly, the display device 700 also includes at least one functional module for implementing the above functions, such as an under-display camera or an under-display fingerprint recognition sensor.

[0111] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0112] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A display panel, characterized in that, include: substrate; and A functional circuit includes multiple transistor groups, each transistor group including at least one transistor disposed on the same layer. The multiple transistor groups are located on one side of the substrate and are arranged sequentially in a direction away from the substrate. At least some of the transistor groups have overlapping orthographic projections on the substrate. The transistors in the multiple transistor groups are electrically connected, and the directly electrically connected transistors are on the same layer or located on adjacent layers.

2. The display panel according to claim 1, characterized in that, The difference in the number of transistors in adjacent transistor groups is less than or equal to 1.

3. The display panel according to claim 1, characterized in that, The functional circuit also includes at least one capacitor located between adjacent transistor groups; Preferably, at least one of the capacitors comprises a plurality of capacitors, which are arranged in different layers.

4. The display panel according to claim 1, characterized in that, The functional circuit includes a pixel circuit, and the display panel further includes a light-emitting device. The light-emitting device is located on the side of the pixel circuit away from the substrate and is electrically connected to the pixel circuit. Preferably, the plurality of transistor groups include a first transistor group, a second transistor group, a third transistor group, and a fourth transistor group arranged sequentially along a direction away from the substrate; Preferably, the pixel circuit includes an 8T2C pixel circuit.

5. The display panel according to claim 1, characterized in that, The plurality of transistor groups include a third transistor group, the third transistor group including a first transistor, the first transistor being used as a driving transistor, the first transistor including a top-gate transistor; Preferably, the display panel further includes a fifth gate insulating layer, which is located between the gate and the channel of the first transistor, and the thickness of the fifth gate insulating layer is in the range of 800-1400 Å; Preferably, the third transistor group further includes a fourth transistor, wherein the side projection of the first transistor and the side projection of the fourth transistor coincide on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor. Preferably, the first terminal of the fourth transistor is connected to the first terminal of the first transistor, the second terminal of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is connected to the first scan signal line.

6. The display panel according to claim 5, characterized in that, The plurality of transistor groups further includes a fourth transistor group, which is located on the side of the third transistor group away from the substrate; the functional circuit further includes a first capacitor, the first plate of which is located between the third transistor group and the fourth transistor group, and the gate of the first transistor is multiplexed as the second plate of the first capacitor. Preferably, the fourth transistor group includes a sixth transistor, a seventh transistor, and an eighth transistor. On a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor, the sixth transistor and the seventh transistor are symmetrically arranged, and the side projections of the seventh transistor and the eighth transistor coincide. Preferably, the first terminal of the sixth transistor is connected to the second terminal of the first transistor, the second terminal of the sixth transistor is connected to the light-emitting device, and the gate of the sixth transistor is connected to the second light-emitting control signal line; the first terminals of the seventh transistor and the eighth transistor are respectively connected to the first plate of the first capacitor, the second terminals of the seventh transistor and the eighth transistor are respectively connected to the first initialization signal line, the gate of the seventh transistor is connected to the first scan signal line, and the gate of the eighth transistor is connected to the second scan signal line.

7. The display panel according to claim 5 or 6, characterized in that, The plurality of transistor groups further includes a second transistor group located on the side of the third transistor group closer to the substrate. The second transistor group includes a fifth transistor, the first terminal of which is connected to the first terminal of the first transistor, the second terminal of which is connected to a power signal line, and the gate of which is connected to a first light emission control signal line. Preferably, the plurality of transistors further includes a first transistor group located on the side of the second transistor group closer to the substrate; the first transistor group includes a second transistor and a third transistor, and the second transistor and the third transistor are symmetrically arranged in a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor; Preferably, the functional circuit further includes a second capacitor, which is located between the second transistor group and the first transistor group; Preferably, the first plate of the second capacitor is connected to the first electrode of the first transistor, the second plate of the second capacitor is connected to the first electrode of the third transistor, the second electrode of the third transistor is connected to the second initialization signal line, the gate of the third transistor is connected to the second light emission control signal line, the first electrode of the second transistor is connected to the second plate of the second capacitor, the second electrode of the second transistor is connected to the data signal line, and the gate of the second transistor is connected to the second scan signal line.

8. The display panel according to claim 5, characterized in that, The plurality of transistor groups include a third transistor group, the third transistor group including a first transistor, the first transistor being used as a driving transistor, the first transistor including a bottom gate transistor; Preferably, the display panel further includes a fourth gate insulating layer, which is located between the gate and the channel of the first transistor, and the thickness of the fourth gate insulating layer is in the range of 2000-5000 Å. Preferably, the third transistor group further includes a fourth transistor, wherein the side projection of the first transistor and the side projection of the fourth transistor coincide on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor. Preferably, the first terminal of the fourth transistor is connected to the first terminal of the first transistor, the second terminal of the fourth transistor is connected to the gate of the first transistor, and the gate of the fourth transistor is connected to the first scan signal line.

9. The display panel according to claim 8, characterized in that, The plurality of transistor groups further includes a second transistor group located on the side of the third transistor group closer to the substrate; the functional circuit further includes a first capacitor, the first plate of the first capacitor being located between the second transistor group and the third transistor group, and the gate of the first transistor being multiplexed as the second plate of the first capacitor; Preferably, the second transistor group includes a fifth transistor, the first terminal of the fifth transistor is connected to the first terminal of the first transistor, the second terminal of the fifth transistor is connected to a power signal line, and the gate of the fifth transistor is connected to a first light emission control signal line; on a cross section perpendicular to the substrate and parallel to the channel direction of the first transistor, the fifth transistor and the first transistor are staggered in a direction perpendicular to the substrate. Preferably, the plurality of transistor groups further includes a first transistor group and a fourth transistor group, wherein the first transistor group is located between the second transistor group and the substrate, and the fourth transistor group is located on the side of the third transistor group away from the substrate.

10. A display device, characterized in that, The display panel includes any one of claims 1-9.

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