Display panel, manufacturing method thereof and display device

Abstract

The invention provides a display panel, a manufacturing method thereof and a display device. In the display panel, a connection electrode is located on an insulating layer and electrically connected with a pixel circuit; a first electrode of the light-emitting element is located on the insulating layer; the separation structure comprises a first separation part; the pixel defining layer includes a first opening configured to expose at least a portion of the connection electrode; the second electrode of the light-emitting element is arranged on the pixel defining layer and is connected with the connecting electrode through the first opening of the pixel defining layer, and the pixel defining layer further comprises a second opening which is configured to expose at least one part of the first electrode of the light-emitting element to define a light-emitting area of the light-emitting element; the display panel comprises a display area and gate driving areas on the array, the gate driving areas on the array are located on one side of the display area, the boundary of the display area and the boundary of the gate driving areas on the array extend in the first direction, and the connecting electrodes extend in the first direction. The space can be saved as much as possible while the effective contact area is increased, and the aperture ratio is improved.

Description

Technical Field

[0001] At least one embodiment of this disclosure relates to a display panel and a method for manufacturing the same, as well as a display device. Background Technology

[0002] Inverted organic light-emitting diodes (OLEDs) can solve the temperature rise problem caused by the floating source in all N-type pixel circuits. However, if the cathode-common layer-light-emitting layer (e.g., R / G / B)-common layer-anode of an OLED device are completely reversed, not only will most of the device materials need to be replaced, but the reversed evaporation sequence may also require production line modifications, which would be very costly.

[0003] Recently, the uses and applications of display devices have diversified. As customers demand thinner and lighter displays, their applications have expanded. With OLED technology gradually entering the mid-size display panel market, N-type metal-oxide-semiconductor (NMOS) interpolated pixel circuits using all-oxide channels, such as indium gallium zinc oxide (IGZO) thin-film transistors (TFTs), are an ideal choice for mid-to-large-size display panels. Summary of the Invention

[0004] At least one embodiment of this disclosure relates to a display panel and a method for manufacturing the same, as well as a display device, which can improve the connection stability between the connecting electrode and the second electrode, increase the effective contact area while saving space as much as possible, and improve the aperture ratio.

[0005] Embodiments of this disclosure provide a display panel, comprising: a substrate; a pixel circuit located on the substrate; an insulating layer located on the pixel circuit; a connection electrode located on the insulating layer and electrically connected to the pixel circuit; a first electrode of a light-emitting element located on the insulating layer; a separation structure including a first separation portion; a pixel defining layer including a first opening configured to expose at least a portion of the connection electrode; and a second electrode of the light-emitting element disposed on the pixel defining layer and connected to the connection electrode through the first opening of the pixel defining layer, wherein the pixel defining layer further includes a second opening configured to expose at least a portion of the first electrode of the light-emitting element to define a light-emitting area of ​​the light-emitting element, wherein the display panel includes a display area and a gate driving region on an array, the gate driving region on the array being located on one side of the display area, the boundary between the display area and the gate driving region on the array extending along a first direction, and the connection electrode extending along the first direction.

[0006] For example, in the display panel provided in the embodiments of this disclosure, the connecting electrode extends along a straight line and is strip-shaped, arc-shaped, curved, or includes multiple portions extending along different straight lines and respectively strip-shaped.

[0007] For example, in the display panel provided in the embodiments of this disclosure, the length of the connecting electrode in its extension direction is greater than or equal to the length of the light-emitting area adjacent to the connecting electrode in the extension direction.

[0008] For example, in the display panel provided in the embodiments of this disclosure, each light-emitting area corresponds to a connection electrode, and the connection electrodes corresponding to the light-emitting areas in the same column are arranged alternately or randomly.

[0009] For example, in the display panel provided in the embodiments of this disclosure, the connecting electrodes corresponding to two adjacent light-emitting areas are located on different sides of their respective light-emitting areas.

[0010] For example, in the display panel provided in the embodiments of this disclosure, the connecting electrode includes two connecting electrode portions spaced apart from each other, the two connecting electrode portions being respectively disposed on opposite sides of the light-emitting area.

[0011] For example, in the display panel provided in the embodiments of this disclosure, the display panel further includes a power cord connected to the first electrode of the light-emitting element.

[0012] For example, in the display panel provided in the embodiments of this disclosure, the power line includes a power signal line extending along a second direction and a power connection line extending along a first direction, the second direction intersecting the first direction, and two adjacent columns of light-emitting elements sharing the same power connection line.

[0013] For example, in the display panel provided in the embodiments of this disclosure, the power cord is in the form of a mesh.

[0014] For example, in the display panel provided in the embodiments of this disclosure, the power signal line includes a first widened portion, and the first widened portions of two adjacent power signal lines are staggered.

[0015] For example, in the display panel provided in the embodiments of this disclosure, a plurality of first widened portions are arranged to correspond to light-emitting elements that emit the same color of light.

[0016] For example, in the display panel provided in the embodiments of this disclosure, multiple light-emitting elements are provided, including a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is configured to emit a first color light, the second light-emitting element is configured to emit a second color light, and the third light-emitting element is configured to emit a third color light. The first light-emitting element and the second light-emitting element are located on the same side of the third light-emitting element and are arranged along the first direction. The first widened portion is provided corresponding to the third light-emitting element.

[0017] For example, in the display panel provided in the embodiments of this disclosure, the power line further includes a connection bus, and one connection bus corresponds to at least two columns of power connection lines.

[0018] For example, in the display panel provided in the embodiments of this disclosure, the connection bus has a second widening portion, the extension direction of the second widening portion intersecting the extension direction of the first widening portion.

[0019] For example, in the display panel provided in the embodiments of this disclosure, the separation structure further includes a second separation portion, which is configured to disconnect the second electrodes of different sub-pixels.

[0020] For example, in the display panel provided in the embodiments of this disclosure, the second separation portion is in contact with the insulating layer, in contact with the pixel defining layer, or is an integral structure with the pixel defining layer.

[0021] For example, in the display panel provided in the embodiments of this disclosure, the connecting electrode is configured to extend in a direction perpendicular to the direction of movement of the vapor deposition source when the connecting electrode is formed in the vapor deposition process.

[0022] For example, in the display panel provided in the embodiments of this disclosure, no connecting electrode is provided in the direction parallel to the direction of movement of the vapor deposition source.

[0023] For example, in the display panel provided in the embodiments of this disclosure, the display area and the gate driving area on the array are arranged along a second direction, and the first direction intersects the second direction.

[0024] For example, the pixel circuits of different sub-pixels are connected to different second electrodes to independently control the voltage on the second electrode of each sub-pixel, while the first electrodes of multiple sub-pixels have the same voltage.

[0025] For example, the light-emitting elements are provided in multiple forms to form a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color sub-pixel being configured to emit a first color light, the second color sub-pixel being configured to emit a second color light, and the third color sub-pixel being configured to emit a third color light, wherein at least two of the connecting electrodes of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel have different lengths in the first direction.

[0026] For example, the length of the connection electrode of the first color sub-pixel in the first direction is different from the length of the connection electrode of the second color sub-pixel in the first direction.

[0027] For example, the length of the connection electrode of the second color sub-pixel in the first direction is different from the length of the connection electrode of the third color sub-pixel in the first direction.

[0028] For example, for the same sub-pixel, the ratio of the length of the connecting electrode in the first direction to the maximum length of the second opening in the first direction ranges from 0.6 to 1.5.

[0029] For example, for the same sub-pixel, the ratio of the maximum length of the second opening in the first direction to the maximum length of the first opening in the first direction ranges from 0.6 to 1.5.

[0030] Embodiments of this disclosure also provide a method for manufacturing a display panel, comprising: forming a pixel circuit on a substrate; forming an insulating layer on the pixel circuit; forming a connection electrode electrically connected to the pixel circuit on the insulating layer; forming a first electrode of a light-emitting element on the insulating layer; forming a separation structure including a first separation portion; forming a pixel defining layer including a first opening and a second opening, the first opening being configured to expose at least a portion of the connection electrode, and the second opening being configured to expose at least a portion of the first electrode of the light-emitting element to define a light-emitting area of ​​the light-emitting element; and forming a second electrode of the light-emitting element on the pixel defining layer, the second electrode being connected to the connection electrode through the first opening of the pixel defining layer, wherein the display panel includes a display area and a gate driving region on an array, the gate driving region on the array being located on one side of the display area, the boundary between the display area and the gate driving region on the array extending along a first direction, and the connection electrode extending along the first direction.

[0031] For example, in the method for manufacturing a display panel provided in the embodiments of this disclosure, forming the connecting electrode includes: the connecting electrode is configured to extend in a direction perpendicular to the moving direction of the vapor deposition source when the connecting electrode is formed in the vapor deposition process.

[0032] For example, in the method for manufacturing a display panel provided in the embodiments of this disclosure, no connecting electrodes are provided in the direction parallel to the direction of movement of the vapor deposition source.

[0033] Embodiments of this disclosure also provide a display device, including any of the above-described display panels. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0035] Figure 1 This is a circuit diagram of a display panel containing P-type pixel circuitry.

[0036] Figure 2 This is a circuit diagram of a display panel containing all N-type pixel circuits.

[0037] Figure 3 This is a schematic diagram of a portion of the structure of a display panel provided in an embodiment of this disclosure.

[0038] Figure 4 This is a cross-sectional view of a display panel provided in one embodiment of the present disclosure.

[0039] Figure 5A cross-sectional view of a display panel provided for another embodiment of this disclosure.

[0040] Figure 6 This is a plan view of a display panel provided for an embodiment of the present disclosure.

[0041] Figure 7 The evaporation process of the evaporation source at different times is shown.

[0042] Figure 8 This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0043] Figure 9 This is a plan view of a display panel provided for another embodiment of the present disclosure.

[0044] Figure 10 This is a plan view of a display panel provided in one embodiment of the present disclosure.

[0045] Figure 11 A schematic diagram of the light-emitting area connecting the electrode and the sub-pixel in a display panel provided for an embodiment of this disclosure.

[0046] Figure 12 This is a schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0047] Figure 13 This is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure.

[0048] Figure 14 This is a cross-sectional schematic diagram of a display panel provided in one embodiment of the present disclosure.

[0049] Figures 15 to 17 This is a plan view of a display panel provided in an embodiment of the present disclosure. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0051] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0052] Figure 1 This is a circuit diagram of a display panel containing P-type pixel circuitry. Figure 2 This is a circuit diagram of a display panel containing all N-type pixel circuits.

[0053] like Figure 1 and Figure 2 As shown, the pixel circuit includes transistors T1 to T5, capacitors C1 and C2. The pixel circuit drives the light-emitting element M0 to emit light.

[0054] like Figure 1 and Figure 2 As shown, transistor T1 is the driving transistor, transistor T2 is the data writing transistor, transistor T3 is the threshold compensation transistor, transistor T4 is the reset transistor, transistor T5 is the light-emitting control transistor, and transistor T6 is the reset transistor.

[0055] Figure 1 and Figure 2The diagram illustrates power lines PL1 and PL2, an illumination control signal line EM, an initialization signal line INT, a gate line GT, a data line DT, a reference voltage line REF, and reset control signal lines RST1, RST2, and RST3. Power line PL1 is configured to provide the power supply voltage VDD, power line PL2 is configured to provide the power supply voltage VSS, the illumination control signal line EM is configured to provide an illumination control signal, the initialization signal line INT is configured to provide an initialization voltage Vint, the gate line GT is configured to provide a scan signal, the data line DT is configured to provide a data voltage Vdt, the reference voltage line REF is configured to provide a reference voltage Vref, and the reset control signal lines RST1, RST2, and RST3 are configured to provide reset control signals. The reset control signals on different reset control signal lines can be the same or different. The power supply voltage VDD is greater than the power supply voltage VSS. The initialization voltage Vint can be between the power supply voltages VDD and VSS. The reference voltage Vref can be a fixed voltage.

[0056] Figure 1 and Figure 2 Nodes N1 to N4 are shown. For example, node N2 is the drain terminal of driving transistor T1, and node N4 is the source terminal of driving transistor T1.

[0057] like Figure 1 and Figure 2 As shown, for the N-type TFT backplane technology using oxide in the channel, theoretical analysis reveals that the source of its driving transistor is driven by a high-potential power supply voltage VDD (such as...). Figure 1 (As shown) Change to a low-potential power supply voltage VSS (e.g.) Figure 2 (As shown). However, in existing OLED devices, the power supply voltage VSS terminal is the cathode trace, which results in a large resistance of the cathode trace and a large voltage drop, causing extreme instability of the source and thus affecting brightness uniformity.

[0058] Figure 2 The transistor T1 may include a bottom gate and a top gate. The bottom gate may be connected to the second node N2 to improve the performance of the switching transistor, for example, to improve the data range of the switching transistor. Of course, embodiments of this disclosure include, but are not limited to, this.

[0059] It should be noted that the embodiments of this disclosure are based on... Figure 2 The pixel circuit shown is used as an example for illustration. However, the embodiments of this disclosure do not limit the structure of the pixel circuit. For example, the structure of the pixel circuit includes the number of transistors, the number of storage capacitors, the connection relationship of the transistors, etc. That is, those skilled in the art can adjust the structure of the pixel circuit as needed.

[0060] Figure 3 This is a schematic diagram of a portion of the structure of a display panel provided in an embodiment of this disclosure. Figure 4 This is a cross-sectional view of a display panel provided in one embodiment of the present disclosure. Figure 5 A cross-sectional view of a display panel provided for another embodiment of this disclosure.

[0061] Figure 4 and Figure 5 The light-emitting elements in the display panel shown are of an inverted structure. Compared to conventional light-emitting elements, inverted light-emitting elements do not require adjustment during vapor deposition. The transistors in the pixel circuits are connected to the second electrode E2 (cathode), independently controlling the voltage on the second electrode (cathode) of each sub-pixel for image display. That is, the pixel circuits of different sub-pixels are connected to different second electrodes to independently control the voltage on the second electrode E2 of each sub-pixel. The first electrodes E1 (anodes) of multiple sub-pixels have the same voltage. For example, the first electrodes E1 (anodes) employ a patterned mesh design. For example, for large-sized display panels, the pattern of the first electrodes E1 (anodes) can be arranged to surround the sub-pixels; for small and medium-sized display panels, the first electrodes E1 (anodes) are at least located on the top and bottom sides of the sub-pixels. The first electrodes E1 (anodes) are connected to a bus, and then to an integrated circuit.

[0062] FMM-free technology refers to the manufacturing process of the light-emitting elements in a display panel that does not use a fine metal mask (FMM), such as the ELEAP technology mentioned later. Of course, FMM technology can also be used to form the display panel, such as... Figure 4 and Figure 5 The display panel shown can be formed using FMM technology.

[0063] Figure 2 This is an embodiment of a pixel circuit where all channels of the TFT are all N-type oxide. (Reference) Figure 1 and Figure 2 From a principle perspective, the discrete N-type pixel circuit (such as...) Figure 2 As shown) compare the P-type pixel circuit (e.g.) Figure 1 As shown), Figure 1 The source (node ​​N4) of the driving transistor (DTFT) in the pixel circuit shown is positioned closer to the VDD terminal. Figure 2 In the N-type pixel circuit shown, the source (node ​​N2) of the driving transistor (DTFT) is close to the VSS terminal. Because the resistance drop at the VSS terminal and the parasitic capacitance of the light-emitting element (OLED device) itself will affect the gate-source potential of the driving transistor, the threshold voltage of the N-type pixel circuit will drift, affecting the display effect.

[0064] Figure 6 This is a plan view of a display panel provided for an embodiment of the present disclosure. (See diagram below.) Figure 6 As shown, the display panel includes a display area 201 and a gate driver on array (GOA) area 202, which is located on one side of the display area 201. Figure 6 The surrounding area 203 is shown. (For example...) Figure 6 As shown, the surrounding area 203 includes the GOA area 202.

[0065] like Figures 2 to 6 As shown, an embodiment of this disclosure provides a display panel including: a substrate BS, a pixel circuit PXC, an insulating layer LL, a connection electrode CE, a first electrode E1 of a light-emitting element M0, a separation structure P0, and a pixel defining layer PDL. The pixel circuit PXC is located on the substrate BS. The insulating layer LL is located on the pixel circuit PXC. The connection electrode CE is located on the insulating layer LL and electrically connected to the pixel circuit PXC. The first electrode E1 of the light-emitting element M0 is located on the insulating layer LL. The separation structure P0 includes a first separation portion P1. For example, the separation structure P0 includes a first separation portion P1 located on the connection electrode CE. For example, the pixel defining layer PDL is disposed on the insulating layer LL and the first separation portion P1. For example, the pixel defining layer PDL includes a first opening OPN1, which is configured to expose at least a portion of the connection electrode CE. The second electrode E2 of the light-emitting element M0 is disposed on the pixel defining layer PDL and connected to the connection electrode CE through the first opening OPN1 of the pixel defining layer PDL. The pixel defining layer PDL also includes a second opening OPN2, which is configured to expose at least a portion of the first electrode E1 of the light-emitting element to define the light-emitting area 66 of the light-emitting element.

[0066] like Figure 3 and Figure 6 As shown, the boundary 301 between the display area 201 and the gate driving region 202 on the array extends along the first direction Y, and the connecting electrode CE extends along the first direction Y. Figure 6 As shown, the boundary 301 between the display area 201 and the gate driving area 202 on the array can be a vertical dashed line on the left.

[0067] In conventional technologies, connecting electrodes are joined at points, resulting in very high contact resistance and the possibility of incomplete connection, preventing pixels from lighting up. The display panel provided in this disclosure features a connecting electrode CE extending along the first direction Y, changing the conventional point-like connecting electrode to a non-point-like structure. This improves the connection stability between the connecting electrode CE and the second electrode E2, increasing the effective contact area while saving space and improving the aperture ratio. The display panel provided in this disclosure increases the effective overlap area while maintaining the aperture ratio. Furthermore, the display panel provided in this disclosure reduces overlap resistance and voltage drop.

[0068] like Figure 4 and Figure 5 As shown, the pixel defining layer PDL forms an undercut structure at the first separation part P1 to facilitate the connection of the second electrode E2 with the connecting electrode CE.

[0069] like Figure 6 As shown, multiple gate driving units 401 are provided in the GOA region 202 of the display panel. Gate lines GT are connected to the gate driving units 401. The gate driving units 401 provide scan signals to the gate lines GT. Figure 6 As shown, multiple gate driving units 401 are arranged along the first direction Y. For example, multiple gate driving units 401 can be cascaded.

[0070] Figure 6 The following description uses the left portion of the peripheral area 203 as an example of the GOA region 202. However, embodiments of this disclosure include, but are not limited to, this. In some embodiments, the right portion of the peripheral area 203 can be the GOA region 202. In this case, the boundary 301 between the display area 201 and the gate driving region 202 on the array can be a vertical dashed line on the right. In some other embodiments, both the left and right portions of the peripheral area 203 can be GOA regions 202. In this case, the vertical dashed line on the left and the vertical dashed line on the right can be considered as the boundary 301 between the display area 201 and the gate driving region 202 on the array, respectively.

[0071] like Figure 6 As shown, the gate line GT extends along the second direction X, and multiple gate lines GT are arranged along the first direction Y.

[0072] In embodiments of this disclosure, if a component extends in a certain direction, then the dimension of the component in that direction is greater than the dimension of the component in other directions. Extending a component in a certain direction does not require that every part of the component extends in that direction; it may refer to the general direction in which the component extends.

[0073] In embodiments of this disclosure, the first direction Y is parallel to the substrate BS. For example... Figure 3 andFigure 6 As shown, the first direction Y is vertical.

[0074] In embodiments of this disclosure, the second direction X is parallel to the substrate BS, and the second direction X intersects the first direction Y. For example, the second direction X is perpendicular to the first direction Y. Figure 3 and Figure 6 As shown, the second direction X is horizontal.

[0075] In embodiments of this disclosure, the third direction Z is perpendicular to the substrate BS. That is, the third direction Z is perpendicular to the first direction Y and the second direction X.

[0076] like Figures 3 to 6 As shown, different sub-pixels 100 are separated so that the second electrodes E2 (VSS terminals) of different sub-pixels are independent of each other. Thus, each sub-pixel 100 can have a different cathode voltage.

[0077] For example, such as Figure 4 As shown, the separation structure P0 further includes a second separation section P2, which is configured to disconnect the second electrodes E2 of different sub-pixels. The second electrodes E2 of different sub-pixels are disconnected at the second separation section P2.

[0078] like Figure 4 As shown, the pixel defining layer PDL also includes a third opening OPN3, and the second electrode E2 is disconnected at the third opening OPN3.

[0079] like Figure 4 As shown, the second electrode E2 of different sub-pixels is disconnected at the second separation part P2 and the third opening OPN3.

[0080] In some display panels, the second electrode E2 of different sub-pixels can be disconnected by setting a second separation part P2 and a third opening OPN3, or the second electrode E2 of different sub-pixels can be disconnected by other means.

[0081] like Figure 4 As shown, the pixel delimiting layer PDL forms an undercut structure at the second separation part P2 to facilitate the separation of the second electrodes E2 of different sub-pixels.

[0082] For example, such as Figure 4 As shown, the second separation part P2 is in contact with the insulating layer LL and the pixel defining layer PDL. The second separation part P2 can also be integrated with the pixel defining layer PDL.

[0083] In the embodiments of this disclosure, the first separation part P1 can be made of a conductive material or an insulating material, and the second separation part P2 can be made of a conductive material or an insulating material. The materials of the first separation part P1 and the second separation part P2 can be the same or different. For example, conductive materials include metals, and insulating materials include organic insulating materials and inorganic insulating materials. Organic insulating materials include resins, but are not limited to these. Inorganic insulating materials include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] Figure 5 The display panel shown disconnects the second electrodes E2 of different sub-pixels by setting an inverted trapezoidal third separation section P3.

[0085] For example, such as Figure 3 As shown, the connecting electrode CE is configured to extend in a direction perpendicular to the direction of movement of the vapor deposition source during the vapor deposition process. Figure 3 As shown, the direction of movement of the vapor deposition source is the second direction X.

[0086] For example, the display area 201 and the gate driving area 202 on the array are arranged along the second direction X, and the first direction Y intersects the second direction X.

[0087] For example, such as Figure 3 As shown, no connecting electrode CE is provided in the direction parallel to the moving direction of the vapor deposition source. The periphery of the light-emitting region 66 is divided into a direction parallel to the moving direction of the vapor deposition source and a direction perpendicular to the moving direction of the vapor deposition source. For example, the first direction Y is perpendicular to the moving direction of the vapor deposition source, and the second direction X is parallel to the moving direction of the vapor deposition source. The connecting electrode CE is provided outside the light-emitting region 66 and in the direction perpendicular to the moving direction of the vapor deposition source, while no connecting electrode CE is provided in the direction parallel to the moving direction of the vapor deposition source.

[0088] Figure 4 and Figure 5 The light-emitting functional layer FL is shown. The light-emitting functional layer FL is located between the first electrode E1 and the second electrode E2. The light-emitting functional layer FL includes a first light-emitting functional part FL1 and a second light-emitting functional part FL2. It should be noted that the arrangement of the light-emitting functional layer FL is not limited to that shown in the figure and can be adjusted as needed. For example, the second light-emitting functional part FL2 can be fabricated using an open-face mask. The second light-emitting functional part FL2 can be referred to as the common layer.

[0089] like Figure 4 and Figure 5 As shown, the display panel includes insulating layers L0 to L5. Insulating layers L0 to L3 can be made of inorganic insulating materials. Insulating layers L4 to L5 can be made of organic insulating materials.

[0090] like Figure 4 and Figure 5 As shown, the pixel boundary layer (PDL) can be made of organic insulating materials, or a combination of organic and inorganic insulating materials. For example, the PDL may include multiple sublayers. These sublayers can be made of suitable materials as needed. For instance, some sublayers may be made of organic insulating materials, while others may be made of inorganic insulating materials.

[0091] like Figure 4 As shown, the third separation part P3 can be made of organic insulating material. The pixel defining layer PDL and the third separation part P3 can be an integral structure or separate structures.

[0092] like Figure 4 and Figure 5 As shown, the display panel includes an encapsulation layer (ECS). The ECS is used to encapsulate the light-emitting elements to prevent water intrusion.

[0093] like Figure 4 and Figure 5 As shown, the display panel includes a conductive structure A0, a conductive structure G0, and a connector S0. For example, conductive structures A0 and G0 constitute a capacitor. The connector S0 is used for connection with other components.

[0094] like Figure 4 and Figure 5 As shown, the pixel circuit is an NMOS circuit, and the light-emitting element (OLED device) is inverted.

[0095] Because the connecting electrode and cathode in the usual technology are connected in a point shape, a common layer needs to be deposited before the cathode is formed. Trying to cover the very thin cathode with the common layer and connect it with the connecting electrode will test the process factors such as the deposition angle. Even if it is successfully connected, the connection area will be very small, which will inevitably lead to a large contact resistance. When the current is large, it is easy to heat up, which is not conducive to obtaining high brightness and other display quality.

[0096] Figure 7 The evaporation process of the evaporation source at different times is shown. When the evaporation source moves, the evaporation material (cathode) at a large angle of movement can well extend beyond the second light-emitting functional part FL2 and connect with the connecting electrode CE. At time t1, the material at evaporation lines La and Lb has an overhanging eaves (such as...) due to the undercut structure. Figure 7 As shown, the shielding prevents the cathode material from being deposited onto the connecting electrode CE. At time t2, the movement of the deposition source allows the cathode material deposited at deposition line Lb to connect with the connecting electrode CE.

[0097] For example, such as Figure 3As shown, the length of the connecting electrode CE in its extension direction is greater than or equal to the length of the light-emitting area adjacent to the connecting electrode CE in its extension direction. The length of the connecting electrode CE in its extension direction is the same as or slightly longer than the length of the sub-pixel, so as to maximize the contact area.

[0098] If the extension direction of the connecting electrode CE is parallel to the evaporation direction, the aforementioned effect will not occur as the evaporation source moves. On the one hand, this could lead to some sub-pixels' evaporated cathode material not properly overlapping with the connecting electrode CE; on the other hand, at the edges, because they are farther from the evaporation source, material can be deposited at a large angle, but at the center, there may not be enough material at a sufficiently large angle, resulting in poor overlap. This uneven overlap resistance between the center and edge areas of the display panel can cause display inconsistencies. Therefore, the parallel connecting electrode CE can be omitted, which also saves space and increases the overall aperture ratio of the pixels.

[0099] Compared to the dot-matrix connection method of inverted OLEDs in conventional technologies, the design of the connecting electrode CE in the display panel provided in the embodiments of this disclosure can increase the effective contact area while saving space as much as possible and improving the aperture ratio.

[0100] Figure 8 This is a plan view of a display panel provided in one embodiment of the present disclosure. Figure 9 This is a plan view of a display panel provided for another embodiment of the present disclosure.

[0101] like Figure 3 and Figure 8 As shown, the plurality of sub-pixels 100 include a first color sub-pixel 101, a second color sub-pixel 102, and a third color sub-pixel 103. For example, the first color sub-pixel 101 is a red sub-pixel, the second color sub-pixel 102 is a green sub-pixel, and the third color sub-pixel 103 is a blue sub-pixel, but is not limited thereto.

[0102] For example, such as Figure 8 As shown, among the connecting electrodes CE corresponding to the light-emitting areas 66 in the same column, the connecting electrodes CE corresponding to two adjacent light-emitting areas 66 are located on different sides of their respective light-emitting areas 66. That is, each light-emitting area 66 corresponds to one connecting electrode CE, and for the same column of light-emitting areas 66, the connecting electrodes CE corresponding to two adjacent rows of light-emitting areas 66 are located on different sides of their respective light-emitting areas 66. For the connecting electrodes CE corresponding to the same column of light-emitting areas 66, the connecting electrodes CE are arranged alternately on opposite sides of the light-emitting areas 66. Figure 8 Multiple columns of subpixels 100 are shown. The multiple subpixels 100 include a first color subpixel 101, a second color subpixel 102, and a third color subpixel 103.

[0103] For example, such as Figure 8 As shown, for the first column of sub-pixels (first color sub-pixel 101), the connecting electrodes CE corresponding to two adjacent light-emitting areas 66 are located on different sides of their respective light-emitting areas 66, i.e., the left and right sides. For example, for the second column of sub-pixels (second color sub-pixel 102), the connecting electrodes CE corresponding to two adjacent light-emitting areas 66 are located on different sides of their respective light-emitting areas 66, i.e., the left and right sides. For example, for the third column of sub-pixels (third color sub-pixel 103), the connecting electrodes CE corresponding to two adjacent light-emitting areas 66 are located on different sides of their respective light-emitting areas 66, i.e., the left and right sides. Figure 8 Let's take the example of sub-pixels in the same column having the same emission color. Of course, in other embodiments, the emission colors of sub-pixels in the same column can also be different.

[0104] Of course, for the same column of light-emitting areas 66, the connecting electrodes CE can also be arranged alternately in multiple rows of light-emitting areas 66.

[0105] For example, such as Figure 9 As shown, the connecting electrode CE includes two connecting electrode portions CEc and CEd spaced apart from each other, and the two connecting electrode portions CEc and CEd are respectively disposed on opposite sides of the light-emitting area 66. Figure 9 Two connecting electrode portions, CEc and CEd, are shown, respectively disposed on the left and right sides of the light-emitting area 66. That is, connecting electrode portions CEc and CEd are respectively disposed on opposite sides of the same light-emitting area 66.

[0106] Figure 10 This is a plan view of a display panel provided according to an embodiment of the present disclosure. For example, as shown... Figure 10 As shown, each light-emitting area 66 corresponds to a connecting electrode CE. Among the connecting electrodes CE corresponding to the light-emitting areas 66 in the same column, the connecting electrodes CE are arranged randomly. In the embodiments of this disclosure, random arrangement means that they are not arranged in an alternating manner.

[0107] Because the connecting electrodes CE are made of metal, they can reflect external light. If all the connecting electrodes CE are arranged on one side of the sub-pixel, they may visually form a line, which can be recognized by the human eye when reflecting light.

[0108] In embodiments of this disclosure, the connecting electrodes CE can be arranged on one side of the sub-pixel, or they can be arranged alternately or randomly on both sides, or connecting electrodes CE can be arranged on both sides of the sub-pixel. If they are arranged alternately or randomly, the probability of being recognized by the human eye can be reduced. If the connecting electrodes CE are arranged on both sides of the sub-pixel, the contact area can be increased, further reducing the resistance.

[0109] Figure 11A schematic diagram of the light-emitting area connecting the electrode and the sub-pixel in a display panel provided for an embodiment of this disclosure.

[0110] like Figure 11 As shown in (a), the light-emitting area 66 is elliptical and the connecting electrode CE is arc-shaped.

[0111] like Figure 11 As shown in (b), the light-emitting area 66 is elliptical, and the connecting electrode CE is zigzag-shaped. The connecting electrode CE comprises multiple parts that extend along different straight lines and are each strip-shaped.

[0112] like Figure 11 As shown in (c), the light-emitting area 66 is hexagonal, and the connecting electrode CE is linear, which can also be called strip.

[0113] like Figure 11 As shown in (d), the light-emitting area 66 is hexagonal, and the connecting electrode CE is zigzag-shaped. The connecting electrode CE comprises multiple parts extending along different straight lines and each being strip-shaped.

[0114] For example, such as Figure 11 As shown, the connecting electrode CE can extend along a straight line and be strip-shaped, arc-shaped, curved, or include multiple parts extending along different straight lines and each being strip-shaped.

[0115] In the embodiments of this disclosure, the connecting electrode CE can take various shapes. The embodiments of this disclosure do not limit the shape of the connecting electrode CE, as long as it facilitates the connection between the connecting electrode CE and the second electrode E2.

[0116] It should be noted that the shape of the light-emitting area 66 is not limited in the embodiments of this disclosure and can be adjusted as needed. For example, the light-emitting area 66 can be circular, elliptical, polygonal, etc. For example, polygons include rectangles, pentagons, hexagons, and octagons.

[0117] Figure 12 This is a schematic diagram of a display panel provided according to an embodiment of the present disclosure. Figure 12 As shown, the pixel arrangement adopts a diamond shape, the sub-pixels 100 are polygonal in shape, and the connecting electrodes CE are arranged in an alternating manner. Each light-emitting area 66 corresponds to one connecting electrode CE. For the same column of sub-pixels 100, two adjacent connecting electrodes CE are located on the upper left and lower right sides of their corresponding light-emitting areas 66, respectively. For example, as... Figure 12 As shown, the emission colors of sub-pixels in the same column are different.

[0118] It should be noted that the embodiments disclosed herein do not limit the pixel arrangement.

[0119] As described above, in order to improve the reliability of cathode overlap in the undercut structure while maximizing the aperture ratio of the light-emitting area, the embodiments of this disclosure have designed the shape and position of the overlap portion.

[0120] like Figure 3 , Figures 8 to 10 ,as well as Figure 12 As shown, the plurality of sub-pixels 100 include a first color sub-pixel 101, a second color sub-pixel 102, and a third color sub-pixel 103; at least two of the connection electrodes CE of the first color sub-pixel 101, the second color sub-pixel 102, and the third color sub-pixel 103 have different lengths in the first direction Y.

[0121] like Figure 3 ,as well as Figures 8 to 12 As shown, the length of the connecting electrode CE of the first color sub-pixel 101 in the first direction Y is different from the length of the connecting electrode CE of the second color sub-pixel 102 in the first direction Y. For example, the length of the connecting electrode CE of the first color sub-pixel 101 in the first direction Y is greater than the length of the connecting electrode CE of the second color sub-pixel 102 in the first direction Y.

[0122] like Figure 3 ,as well as Figures 8 to 12 As shown, the length of the connecting electrode CE of the second color sub-pixel 102 in the first direction Y is different from the length of the connecting electrode CE of the third color sub-pixel 103 in the first direction Y. For example, the length of the connecting electrode CE of the second color sub-pixel 102 in the first direction Y is less than the length of the connecting electrode CE of the third color sub-pixel 103 in the first direction Y.

[0123] like Figure 3 ,as well as Figures 8 to 10 As shown, the length of the connecting electrode CE of the first color sub-pixel 101 in the first direction Y and the length of the connecting electrode CE of the third color sub-pixel 103 in the first direction Y can be equal or unequal.

[0124] like Figure 3 ,as well as Figures 8 to 12 As shown, the length of the first color sub-pixel 101 in the first direction Y and the length of the second color sub-pixel 102 in the first direction Y are different. For example, the length of the first color sub-pixel 101 in the first direction Y is greater than the length of the second color sub-pixel 102 in the first direction Y.

[0125] like Figure 3 ,as well as Figures 8 to 12As shown, the length of the second color sub-pixel 102 in the first direction Y is different from the length of the third color sub-pixel 103 in the first direction Y. For example, the length of the second color sub-pixel 102 in the first direction Y is less than the length of the third color sub-pixel 103 in the first direction Y.

[0126] like Figure 3 ,as well as Figures 8 to 12 As shown, the length of the first color sub-pixel 101 in the first direction Y and the length of the third color sub-pixel 103 in the first direction Y can be equal or unequal.

[0127] The length of the connecting electrode CE of the sub-pixel in the first direction Y can be associated with the length of the sub-pixel in the first direction Y.

[0128] The length of sub-pixel 100 in the first direction Y refers to the length of the light-emitting area 66 (second opening OPN2) of the sub-pixel in the first direction Y.

[0129] For example, such as Figure 3 , Figures 8 to 12 As shown, for the same sub-pixel, the ratio of the length of the connecting electrode CE in the first direction Y to the maximum length of the second opening (pixel opening) OPN2 in the first direction Y ranges from 0.6 to 1.5. Further, for example, this ratio ranges from 0.8 to 1.2.

[0130] For example, such as Figure 3 , Figures 8 to 12 As shown, for the same sub-pixel, the ratio of the maximum length of the second opening (pixel opening) OPN2 in the first direction Y to the maximum length of the first opening OPN1 in the first direction Y ranges from 0.6 to 1.5. Further, for example, this ratio ranges from 0.8 to 1.2. The maximum length of the first opening OPN1 in the first direction Y can be considered as the maximum length of the connecting electrode CE at the corresponding position in the figure in the first direction Y.

[0131] Figure 13 This is a plan view of a partial structure of a display panel provided in an embodiment of the present disclosure. Figure 14 This is a cross-sectional schematic diagram of a display panel provided in one embodiment of the present disclosure. Figures 15 to 17 This is a plan view of a display panel provided in an embodiment of the present disclosure.

[0132] For example, such as Figure 2 , Figure 13 and Figure 14 As shown, the display panel also includes a power line PL1, which is connected to the first electrode E1 of the light-emitting element.

[0133] like Figure 4 and Figure 5As shown, the power line PL1 and the first electrode E1 of the light-emitting element can be an integral structure. That is, the power line PL1 and the first electrode E1 of the light-emitting element are located on the same layer and are formed integrally.

[0134] like Figure 14 As shown, the power line PL1 and the first electrode E1 of the light-emitting element are located on different layers, and they are connected through a via V0. Figure 14 As shown, via V0 penetrates both planarization layer PLN1 and planarization layer PLN2.

[0135] like Figure 4 , Figure 5 and Figure 14 As shown, the connecting electrode CE is connected to the connecting line CC, and the connecting line CC is connected to the pixel circuit PXC.

[0136] Figure 14 Electrodes SDa, SDb, SDc, and SDd are shown. Electrodes SDa and SDb are connected to the active layer AT, respectively. Figure 14 Gates GE1 and GE2 are shown. Gates GE1 and GE2 can be the bottom gate and the top gate, respectively. Gates GE1 and GE2 can be connected to each other or not.

[0137] Figure 14 The diagram shows a gate insulating layer GI1, an interlayer insulating layer ILD1, a gate insulating layer GI2, an interlayer insulating layer ILD2, a passivation layer PVX, a planarization layer PLN1, a planarization layer PLN2, a pixel defining layer PDL, and a substrate BS. Figure 14 The following description takes a substrate BS comprising a buffer layer BF1, a barrier layer BR1, a barrier layer BR2, a first substrate PI1, and a second substrate PI2 as an example. However, it is not limited to this and the structure of the substrate BS can be adjusted as needed.

[0138] like Figure 4 and Figure 5 As shown, the display panel also includes conductive structure G11, conductive structure G21, and conductive structure SD0. For example, conductive structure G11 and conductive structure SD0 are connected, and conductive structure G21 and conductive structure G11 form a capacitor.

[0139] For example, Figures 15 to 17 As shown, the power line PL1 includes a power signal line PL11 extending along the second direction X and a power connection line PL12 extending along the first direction Y. The power signal line PL11 and the power connection line PL12 are connected to each other. For example, the power signal line PL11 and the power connection line PL12 are a single unit.

[0140] For example, such as Figures 15 to 17As shown, adjacent columns of light-emitting elements share the same power connection line PL12. Compared to setting a separate power connection line PL12 for each column of light-emitting elements, this reduces the resistance of the power line PL1, facilitates connection to the first electrode E1 (anode), and reduces the wasted light-emitting area of ​​the first electrode E1 (anode) due to the connection of the power line PL1, thereby reducing metal line reflection. For example, the layout of adjacent sub-pixel columns can be mirrored.

[0141] For example, such as Figures 15 to 17 As shown, the power signal line PL11 and the power connection line PL12 are integrated into one structure. To reduce resistance and differences between areas, the power line PL1 is meshed. The mesh design of the power line PL1 also improves layout flexibility, reduces routing pressure in the lower pad area, and increases the space for routing in the lower pad area.

[0142] For example, such as Figures 15 to 17 As shown, the power signal line PL11 includes a first widened portion W1. To facilitate layout design, the first widened portions W1 of adjacent power signal lines PL11 are staggered. Figures 15 to 17 As shown, the first widened portion W1 of two adjacent power signal lines PL11 is offset in the second direction X, that is, offset laterally. The widened area (first widened portion W1) of the power signal line PL11 is designed to be offset between adjacent rows, which improves the flexibility of the layout space.

[0143] like Figures 15 to 17 As shown, the first widened portions W1 corresponding to the same column of light-emitting areas 66 are not aligned. For example, the first widened portion W11 located in the even-numbered rows of the same column of light-emitting areas 66 is positioned to the right, while the first widened portion W12 located in the odd-numbered rows of the same column of light-emitting areas 66 is positioned to the left. For example, the left and right ends of the first widened portions W1 corresponding to the same column of light-emitting areas 66 are not aligned. For example, the dimensions of the first widened portions W1 corresponding to the same column of light-emitting areas 66 are the same. The first widened portion W1 includes the first widened portion W11 and the first widened portion W12.

[0144] For example, such as Figures 15 to 17 As shown, multiple first widened portions W1 are arranged to correspond to light-emitting elements that emit light of the same color. Figures 15 to 17 Multiple first widened portions W1 are set to correspond to light-emitting elements (third color sub-pixels 103) that emit third color light.

[0145] For example, such as Figures 15 to 17 As shown, multiple first widened portions W1 are arranged corresponding to the largest light-emitting area emitting the same color light. The light-emitting area 66 of the third color sub-pixel 103 has the largest size, and multiple first widened portions W1 are arranged corresponding to the light-emitting area of ​​the third color sub-pixel 103.

[0146] For example, such asFigure 17 As shown, multiple light-emitting elements are provided, including a first light-emitting element M1, a second light-emitting element M2, and a third light-emitting element M3. The first light-emitting element M1 is configured to emit a first color light, the second light-emitting element M2 is configured to emit a second color light, and the third light-emitting element M3 is configured to emit a third color light. The first light-emitting element M1 and the second light-emitting element M2 are located on the same side of the third light-emitting element M3 and are arranged along the first direction Y. The first widened portion W1 is provided corresponding to the third light-emitting element M3.

[0147] For example, such as Figure 17 As shown, the power line PL1 also includes a connection bus BL, and one connection bus BL corresponds to at least two columns of power connection lines PL12.

[0148] For example, such as Figure 17 As shown, the connecting bus BL has a second widened portion W2. (As indicated...) Figure 17 As shown, the second widened portion W2 extends along the first direction Y, and the first widened portion W1 extends along the second direction X. The extension directions of the first widened portion W1 and the second widened portion W2 are different. The extension directions of the first widened portion W1 and the second widened portion W2 intersect. The dimensions of the first widened portion W1 and the second widened portion W2 can be the same or different.

[0149] For example, such as Figure 14 As shown, the power line PL1 in the lower bezel area is designed to drive two or four wires simultaneously, reducing the number of traces in the lower bezel edge area and the number of traces in the rounded corner area, thus achieving a narrow bezel and effectively reducing the number of traces in the lower bezel area.

[0150] like Figure 14 As shown, the display panel includes a separation structure, which includes a separation part P4. The separation part P4 includes a main body P41 and a roof P42. The roof P42 extends out of the main body P41 to form an eave, that is, the roof P42 protrudes from the main body P41 to facilitate the isolation of the light-emitting functional layer FL and the second electrode E2.

[0151] like Figure 14 As shown, in the ELEAP technique, the second electrode E2 is connected to the connecting electrode CC via the body P41. The body P41 is conductive. For example, the body P41 can be made of a metallic material.

[0152] The roof P42 can be made of either conductive or insulating materials. The conductive and insulating materials can be those described previously and will not be repeated here.

[0153] For example, the main body P41 and the roof P42 can be made of different materials or the same material.

[0154] like Figure 14As shown, the second electrode E2 (cathode) is connected to the pixel circuit PXC. The second electrode E2 (cathode) is connected to the pixel circuit PXC through the main body P41, the connecting structure CC0, and the connecting line CC.

[0155] like Figure 14 As shown, the second electrode E2 (cathode) is connected to the connecting structure CC0 through the main body P41. The connecting structure CC0 is connected to the connecting line CC, and the connecting line CC is connected to the pixel circuit PXC, which can achieve the effect of reducing the resistance of the cathode.

[0156] For example, such as Figure 4 As shown, the encapsulation layer ECS includes an inorganic encapsulation film ECS1, an organic encapsulation film ECS2, and an inorganic encapsulation film ECS3. Inorganic encapsulation films ECS1 and ECS3 are made of inorganic insulating materials, while organic encapsulation film ECS2 is made of organic insulating materials.

[0157] Furthermore, the display panel structure provided in the embodiments of this disclosure is applicable to inverted OLEDs with all-N-type pixel circuits. Its light-emitting device structure is consistent with the conventional structure, eliminating the need for the development of new materials and effectively reducing development costs.

[0158] Embodiments of this disclosure also provide a method for manufacturing a display panel, such as... Figure 5 , Figure 14 , Figure 3 As shown, the method includes: forming a pixel circuit PXC on a substrate BS; forming an insulating layer LL on the pixel circuit PXC; forming a connection electrode CE electrically connected to the pixel circuit PXC on the insulating layer LL; forming a first electrode E1 of a light-emitting element on the insulating layer LL; forming a separation structure P0, the separation structure P0 including a first separation portion P1; forming a pixel defining layer PDL, the pixel defining layer PDL including a first opening OPN1 and a second opening OPN2, the first opening OPN1 being configured to expose at least a portion of the connection electrode CE, and the second opening OPN2 being configured to expose at least a portion of the first electrode E1 of the light-emitting element to define the light-emitting area of ​​the light-emitting element; and forming a second electrode E2 of the light-emitting element on the pixel defining layer PDL, the second electrode E2 being connected to the connection electrode CE through the first opening OPN1 of the pixel defining layer PDL. Figure 6 , Figure 7 as well as Figure 14 As shown, the display panel includes a display area 201 and a gate driving region 202 on the array. The gate driving region 202 on the array is located on one side of the display area 201. The boundary between the display area 201 and the gate driving region 202 on the array extends along a first direction Y. The connecting electrode CE extends along the first direction Y.

[0159] Figure 14The main body P41 is the connecting electrode CE.

[0160] exist Figure 14 In the middle, the first opening OPN1 and the second opening OPN2 are the same opening.

[0161] Figure 4 The separation part P4 in the middle corresponds to Figure 5 and Figure 3 The separation structure P0 (first separation part P1) in the middle.

[0162] For example, such as Figures 8 to 12 As shown, in the method of manufacturing a display panel, forming a connecting electrode CE includes: the connecting electrode CE is configured to extend in a direction perpendicular to the moving direction of the vapor deposition source when forming the connecting electrode CE in the vapor deposition process.

[0163] For example, such as Figure 14 As shown, in the method of manufacturing the display panel, no connecting electrode CE is provided in the direction parallel to the moving direction of the vapor deposition source.

[0164] The effects described in the manufacturing method of the display panel can be referenced in the technical effects described in the display panel, and will not be repeated here.

[0165] Figure 14 This is a display panel formed using ELEAP (E: environment positive, L: lithography with maskless deposition, E: extreme long life, low power, and high luminance, AP: any shape patterning) technology.

[0166] For example, in ELEAP technology, a display panel is formed by forming the material of the light-emitting element (including the light-emitting functional layer FL and the second electrode E2) on the entire surface, and then removing the material of the unwanted areas by etching.

[0167] like ​As shown, a material (including a light-emitting functional layer FL and a second electrode E2) for a light-emitting element emitting a first color of light is formed on the entire substrate. This material is retained in the region of the first color sub-pixel, removed in the regions of the second and third color sub-pixels, and retained in the non-display area to facilitate the isolation of the light-emitting functional layer and the second electrode at the isolation structure. Similarly, a material (including a light-emitting functional layer FL and a second electrode E2) for a light-emitting element emitting a second color of light is formed on the entire substrate. This material is retained in the region of the second color sub-pixel, removed in the regions of the first and third color sub-pixels, and retained in the non-display area to facilitate the isolation of the light-emitting functional layer and the second electrode at the isolation structure. Likewise, a material (including a light-emitting functional layer FL and a second electrode E2) for a light-emitting element emitting a third color of light is formed on the entire substrate. This material is retained in the region of the third color sub-pixel, removed in the regions of the first and second color sub-pixels, and retained in the non-display area to facilitate the isolation of the light-emitting functional layer and the second electrode at the isolation structure. The partition structure in the non-display area of ​​the adjacent display area can be made of the material of light-emitting elements (including the light-emitting functional layer FL and the second electrode E2) that emit two different colors of light.

[0168] By forming the light-emitting element and the isolation structure at the same time, there is no need to make a separate cathode isolation part (isolation column), which realizes cathode patterning and improves the image quality display of the full N-type pixel circuit.

[0169] The same ELEAP technology also suffers from cathode overlap issues. Of course, this isn't unique to ELEAP; display panels formed using fine metal masks also exhibit cathode overlap problems. The solutions provided in the embodiments of this disclosure can be used to resolve cathode overlap issues in all undercut structures.

[0170] In ELEAP technology, the cathode overlap can adopt a structure that surrounds the entire sub-pixel. However, in the portion parallel to the movement of the evaporation source, the overlap between the central and edge pixels will be inconsistent, resulting in unevenness across the entire display screen. Therefore, the design provided in the embodiments of this disclosure can also be used to optimize ELEAP technology.

[0171] The embodiments of this disclosure are illustrated by taking as an example that multiple sub-pixels 100 include a first color sub-pixel 101, a second color sub-pixel 102, and a third color sub-pixel 103, and that the first color sub-pixel 101, the second color sub-pixel 102, and the third color sub-pixel 103 constitute a single pixel. For example, the first color sub-pixel 101 may be a red sub-pixel, the second color sub-pixel 102 a green sub-pixel, and the third color sub-pixel 103 a blue sub-pixel. However, the embodiments of this disclosure include, but are not limited to, this. The number of sub-pixels included in a single pixel can be determined as needed, and the emission color of the sub-pixels is not limited to red, green, or blue, but can be determined as needed.

[0172] Embodiments of this disclosure also provide a display device, including any of the above-described display panels.

[0173] For example, a display device can be any product or component with a display function, such as a television, digital camera, mobile phone, watch, tablet computer, laptop computer, or navigator, which includes an organic light-emitting diode display device.

[0174] The following points need to be explained:

[0175] (1) Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning as understood by a person of ordinary skill in the art to which this disclosure pertains.

[0176] (2) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0177] (3) For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0178] (4) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other.

[0179] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: Substrate; Pixel circuitry is located on the substrate. An insulating layer is located on the pixel circuit; A connecting electrode is located on the insulating layer and electrically connected to the pixel circuit. The first electrode of the light-emitting element is located on the insulating layer; The separation structure includes a first separation section; A pixel defining layer includes a first opening configured to expose at least a portion of the connection electrode; as well as The second electrode of the light-emitting element is disposed on the pixel defining layer and connected to the connecting electrode through the first opening in the pixel defining layer. The pixel defining layer further includes a second opening configured to expose at least a portion of the first electrode of the light-emitting element to define the light-emitting area of ​​the light-emitting element. The display panel includes a display area and a gate driving area on an array. The gate driving area on the array is located on one side of the display area. The boundary between the display area and the gate driving area on the array extends along a first direction. The connecting electrode extends along the first direction.

2. The display panel according to claim 1, wherein, The connecting electrode extends along a straight line and is strip-shaped, arc-shaped, curved, or includes multiple parts extending along different straight lines and each being strip-shaped.

3. The display panel according to claim 1, wherein, The length of the connecting electrode in its extension direction is greater than or equal to the length of the light-emitting area adjacent to the connecting electrode in its extension direction.

4. The display panel according to claim 1, wherein, Each light-emitting area corresponds to a connecting electrode. Among the connecting electrodes corresponding to the light-emitting areas in the same column, the connecting electrodes are arranged alternately or randomly.

5. The display panel according to claim 4, wherein, The connecting electrodes corresponding to two adjacent light-emitting regions are located on different sides of their respective light-emitting regions.

6. The display panel according to claim 1, wherein, The connecting electrode includes two connecting electrode portions spaced apart from each other, and the two connecting electrode portions are respectively disposed on opposite sides of the light-emitting area.

7. The display panel according to any one of claims 1-6, further comprising a power cord, wherein, The power line is connected to the first electrode of the light-emitting element.

8. The display panel according to claim 7, wherein, The power line includes a power signal line extending along a second direction and a power connection line extending along the first direction. The second direction intersects the first direction, and adjacent columns of light-emitting elements share the same power connection line.

9. The display panel according to claim 8, wherein, The power cord is mesh-like.

10. The display panel according to claim 9, wherein, The power signal line includes a first widened portion, and the first widened portions of two adjacent power signal lines are staggered.

11. The display panel according to claim 10, wherein, Multiple first widened portions are arranged to correspond to light-emitting elements that emit the same color of light.

12. The display panel according to claim 10, wherein, The light-emitting elements are provided in multiple forms, including a first light-emitting element, a second light-emitting element, and a third light-emitting element. The first light-emitting element is configured to emit a first color of light, the second light-emitting element is configured to emit a second color of light, and the third light-emitting element is configured to emit a third color of light. The first light-emitting element and the second light-emitting element are located on the same side of the third light-emitting element and are arranged along the first direction. The first widened portion is provided corresponding to the third light-emitting element.

13. The display panel according to any one of claims 10-12, wherein, The power line also includes a connection bus, with one connection bus corresponding to at least two power connection lines.

14. The display panel according to claim 13, wherein, The connection bus has a second widened portion, the extension direction of which intersects the extension direction of the first widened portion.

15. The display panel according to any one of claims 1-6, wherein, The separation structure further includes a second separation section, which is configured to disconnect the second electrodes of different sub-pixels.

16. The display panel according to claim 15, wherein, The second separation portion is in contact with the insulating layer, in contact with the pixel defining layer, or is an integral structure with the pixel defining layer.

17. The display panel according to any one of claims 1-6, wherein, The connecting electrode is configured to extend in a direction perpendicular to the direction of movement of the vapor deposition source during the vapor deposition process.

18. The display panel according to claim 17, wherein, No connecting electrode is provided in the direction parallel to the direction of movement of the vapor deposition source.

19. The display panel according to any one of claims 1-6, wherein, The display area and the gate driving area on the array are arranged along a second direction, and the first direction intersects the second direction.

20. The display panel according to any one of claims 1-6, wherein, The pixel circuits of different sub-pixels are connected to different second electrodes to independently control the voltage on the second electrode of each sub-pixel, while the first electrodes of multiple sub-pixels have the same voltage.

21. The display panel according to any one of claims 1-6, wherein, The light-emitting elements are provided in multiple forms to form a plurality of sub-pixels, the plurality of sub-pixels including a first color sub-pixel, a second color sub-pixel, and a third color sub-pixel, the first color sub-pixel being configured to emit a first color light, the second color sub-pixel being configured to emit a second color light, and the third color sub-pixel being configured to emit a third color light. At least two of the connection electrodes of the first color sub-pixel, the second color sub-pixel, and the third color sub-pixel have different lengths in the first direction.

22. The display panel according to claim 21, wherein, The length of the connecting electrode of the first color sub-pixel in the first direction is different from the length of the connecting electrode of the second color sub-pixel in the first direction.

23. The display panel according to claim 21, wherein, The length of the connecting electrode of the second color sub-pixel in the first direction is different from the length of the connecting electrode of the third color sub-pixel in the first direction.

24. The display panel according to claim 21, wherein, For the same sub-pixel, the ratio of the length of the connecting electrode in the first direction to the maximum length of the second opening in the first direction ranges from 0.6 to 1.

5.

25. The display panel according to claim 21, wherein, For the same sub-pixel, the ratio of the maximum length of the second opening in the first direction to the maximum length of the first opening in the first direction ranges from 0.6 to 1.

5.

26. A method for manufacturing a display panel, comprising: Pixel circuits are formed on a substrate. An insulating layer is formed on the pixel circuit; A connection electrode electrically connected to the pixel circuit is formed on the insulating layer; A first electrode of a light-emitting element is formed on the insulating layer; A separation structure is formed, the separation structure including a first separation section; A pixel defining layer is formed, the pixel defining layer including a first opening and a second opening, the first opening being configured to expose at least a portion of the connecting electrode, and the second opening being configured to expose at least a portion of the first electrode of the light-emitting element to define the light-emitting area of ​​the light-emitting element; as well as A second electrode of the light-emitting element is formed on the pixel defining layer, and the second electrode is connected to the connection electrode through the first opening in the pixel defining layer. The display panel includes a display area and a gate driving area on an array. The gate driving area on the array is located on one side of the display area. The boundary between the display area and the gate driving area on the array extends along a first direction. The connecting electrode extends along the first direction.

27. The method for manufacturing a display panel according to claim 26, wherein, Forming the connection electrode includes: The connecting electrode is configured to extend in a direction perpendicular to the direction of movement of the vapor deposition source when the connecting electrode is formed in the vapor deposition process.

28. The method for manufacturing a display panel according to claim 26 or 27, wherein, No connecting electrode is provided in the direction parallel to the direction of movement of the vapor deposition source.

29. A display device comprising a display panel according to any one of claims 1-25.

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