Chip packaging structure based on large-size plastic packaging adapter plate and preparation method thereof

Abstract

The invention provides a chip packaging structure based on a large-size plastic packaging adapter plate and a preparation method of the chip packaging structure based on the large-size plastic packaging adapter plate. In combination with a preparation process of filling a first conductive column in a through hole, patterning upper and lower surface metal layers to form corresponding bonding pads, and coating a chip and a gap between an adapter plate and a printed circuit board by double filling layers respectively, high-density integration of a plurality of chips is realized, and the stability of structural connection and the electric heat conduction efficiency are guaranteed; therefore, the area limitation and the integration level bottleneck of the traditional packaging technology are broken through, the packaging technological process is simplified, the dependence of special equipment and a photoetching mask is reduced, the substrate utilization rate and the mass production adaptability are improved, and finally the chip packaging effect with larger packaging area, higher I / O density, better reliability and lower unit cost is achieved. Wide industrial application prospects are realized.

Description

Technical Field

[0001] This invention relates to the field of semiconductor chip packaging, and in particular to a chip packaging structure based on a large-size plastic-encapsulated adapter board and its fabrication method. Background Technology

[0002] TSMC, a leader in semiconductor manufacturing technology, has long relied on silicon interposers to achieve high bandwidth and high I / O density integration through its flagship advanced packaging technology, CoWoS (Chipon Wafer on Substrate), which has become a core solution for high-performance chip packaging. However, with the continuous increase in the size of artificial intelligence (AI) GPU chips and the increasing number of high-bandwidth memory (HBM) stacks, CoWoS technology is gradually facing a key bottleneck—the size limitation of the photolithography mask directly restricts the maximum package area of ​​a single module, making it difficult to meet the needs of next-generation chips for larger integration scales.

[0003] Fan-out panel level package (FOPLP) technology, as a novel packaging solution, offers a potential path to overcome the aforementioned limitations. Compared to traditional fan-out wafer level package (FOWLP), the core difference of FOPLP lies in using a larger rectangular panel instead of a circular wafer, forming a unique technological system in key parameters such as material selection, production equipment, and linewidth / spacing. By extending I / O wiring outside the chip boundary, it can significantly improve I / O density, reduce package size, and optimize electrical performance, while also possessing advantages such as larger overall packaging capacity, higher production efficiency, and lower unit cost. Currently, FOPLP sample sizes have evolved from the initial 300×300mm to 500×500mm, 600×600mm, and even larger specifications. With its low cost, flexible design, excellent electrothermal performance, diverse business models, and wide range of applications, it demonstrates strong technological competitiveness and development prospects.

[0004] Given the inherent limitations of CoWoS technology and the significant advantages of FOPLP technology, TSMC proposed the CoPoS (Chipon Panel on Substrate) solution. While architecturally consistent with CoWoS, CoPoS's core innovation lies in replacing the silicon interposer in traditional CoWoS with a panel-sized substrate. This "circular to square" design innovation reduces waste of incomplete chips at the edges of circular wafers, achieving higher substrate utilization, greater packaging density, better yield efficiency, and lower unit area cost. This technology supports multiple panel-level packaging sizes, including 600mm×600mm, 700mm×700mm, and 310mm×310mm, providing more ample packaging space, higher I / O integration, and a more efficient production process, and is considered a natural evolution of the CoWoS platform.

[0005] However, how to effectively integrate the core technological advantages of FOPLP and CoWoS, overcome the challenges of compatibility, reliability, and process adaptability in the integration process, and develop a new CoPoS chip packaging technology with stable performance and feasible mass production has become a key issue that urgently needs to be addressed in the current semiconductor packaging field. Summary of the Invention

[0006] The purpose of this invention is to provide a chip packaging structure based on a large-size plastic-encapsulated adapter board and its preparation method, in order to solve the technical problems of excessively high cost and low packaging efficiency of existing chip packaging technologies.

[0007] To address the aforementioned technical problems, this invention provides a method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board, the method comprising: S10 features multiple spaced through holes on a large-size plastic-encapsulated adapter plate; S20, multiple first conductive pillars are completely filled in multiple through holes, and a first metal layer and a second metal layer are formed on the upper and lower surfaces of the large-size plastic-encapsulated adapter plate, respectively, with both the first metal layer and the second metal layer completely covering the first conductive pillars. S30, the first metal layer is patterned to obtain multiple spaced first pads; simultaneously, the second metal layer is patterned to obtain multiple spaced second pads. S40, multiple chips are fixed at intervals on the first pad, and then a first filler layer is formed on the upper surface of the large-size plastic-encapsulated adapter board; the first filler layer completely covers the multiple chips and covers the gap between the large-size plastic-encapsulated adapter board and the chips; S50, a large-size plastic-encapsulated adapter board is fixed on a printed circuit board, so that the second pad is electrically connected to the third pad on the surface of the printed circuit board; then a second filling layer is formed in the gap between the large-size plastic-encapsulated adapter board and the printed circuit board, thus obtaining a chip packaging structure based on the large-size plastic-encapsulated adapter board.

[0008] Preferably, step S10 specifically includes: S101, A large-size plastic-encapsulated adapter plate is formed on a plate-level carrier plate using a plastic-encapsulation process; S102, after the large-size plastic-encapsulated adapter board is separated from the board-level carrier board, multiple first blind holes are formed on its upper surface by laser engraving process; the depth of each first blind hole is less than the thickness of the large-size plastic-encapsulated adapter board; S103, multiple second blind holes are formed on the lower surface of a large-size plastic-encapsulated adapter board by laser engraving process. Each second blind hole corresponds to a first blind hole, and the two holes pass through each other to form a through hole. The diameter of the second blind hole is the same as that of the corresponding first blind hole.

[0009] Preferably, in step S101, the overall dimensions of the large-size plastic-encapsulated adapter plate are (310~700) mm × (310~700) mm, the thickness is 10~25 mm, the material is epoxy resin or polyimide, and the volume resistivity is >10. 16 Ω·cm.

[0010] Preferably, in step S20, the first conductive pillar, the first metal layer, and the second metal layer each include at least one of aluminum, copper, gold, platinum, nickel, and tin.

[0011] Preferably, in step S30, the patterning process is performed sequentially using photolithography, wet etching, and resist removal.

[0012] Preferably, the first pad includes a plurality of spaced-apart first pads, and the second pad includes a plurality of spaced-apart second pads; each first pad is electrically connected to a corresponding second pad through a corresponding first conductive post, and the first pad and the corresponding second pad overlap in their orthogonal projection portions on the large-size plastic-encapsulated adapter board.

[0013] Preferably, in step S40, the pins of multiple chips are electrically connected to the corresponding first pads one by one through the second conductive pillars; in step S50, the second pads are soldered to the third pads through metal conductive balls.

[0014] Preferably, both the second conductive post and the metal conductive ball comprise at least one of aluminum, copper, gold, platinum, nickel, and tin.

[0015] Preferably, in steps S40 and S50, both the first filler layer and the second filler layer are epoxy resin or silicon oxide.

[0016] Accordingly, the present invention also provides a chip packaging structure, which is prepared by any of the above preparation methods.

[0017] The beneficial effects of this invention are as follows: Unlike existing technologies, this invention provides a chip packaging structure based on a large-size plastic-encapsulated adapter board and its fabrication method. The fabrication method uses a large-size plastic-encapsulated adapter board as an intermediary layer, combined with a process of filling through-holes with first conductive pillars, patterning upper and lower surface metal layers to form corresponding pads, and using double filling layers to cover the chip and the gap between the adapter board and the printed circuit board. This enables high-density integration of multiple chips and ensures the stability of the structural connection and the efficiency of electrothermal conduction. This breaks through the area limitations and integration bottlenecks of traditional packaging technologies, thereby simplifying the packaging process, reducing reliance on special equipment and photomasks, improving substrate utilization and mass production adaptability, and ultimately achieving a chip packaging effect with larger packaging area, higher I / O density, better reliability, and lower unit cost, which has broad prospects for industrial applications. Attached Figure Description

[0018] Figure 1 This is a flowchart of the fabrication method of the chip packaging structure based on a large-size plastic-encapsulated adapter board provided in Example 1; Figures 2a to 2j This is a schematic diagram of each step in the fabrication method of the chip packaging structure based on a large-size plastic-encapsulated adapter board provided in Example 1; In the attached diagram: 10—Board-level carrier board; 11—Large-size plastic-encapsulated adapter board; 12—First metal layer; 121—First pad; 13—Second metal layer; 131—Second pad; 14—Second conductive post; 15—Pin; 16—Chip; 17—First filler layer; 18—Metal conductive ball; 19—Printed circuit board; 20—Second filler layer; 201—First blind via; 202—Through hole; 203—First conductive post. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] To address the shortcomings of existing technologies, this invention provides a chip packaging structure based on a large-size plastic-encapsulated interposer and its fabrication method. This chip packaging structure and its fabrication method use a large-size plastic-encapsulated interposer as an interposer to fabricate a highly integrated chip packaging structure, which can greatly improve chip packaging efficiency and significantly reduce chip packaging costs.

[0021] The technical solution of the present invention will now be further described with reference to specific embodiments.

[0022] Example 1: Please see Figure 1 And Figure 2, Figure 1 Figure 1 is a flowchart of the fabrication method of the chip packaging structure based on the large-size plastic-encapsulated adapter board 11 provided in Example 1; Figure 2 is a schematic diagram of each step in the fabrication method of the chip packaging structure based on the large-size plastic-encapsulated adapter board 11 provided in Example 1; wherein, the fabrication method of the above-mentioned chip packaging structure specifically includes the following steps: S10, multiple spaced through holes 202 are opened on the large-size plastic-encapsulated adapter plate 11.

[0023] Specifically, step S10 also includes: First, a large-size plastic-encapsulated adapter plate 11 is fabricated on the plate-level carrier plate 10 using a plastic-encapsulation process, resulting in the following: Figure 2a The structure is shown. The specific dimensions and thickness of the large-size plastic-encapsulated adapter plate 11 are determined according to specific requirements, and theoretically can be any size.

[0024] Next, the large-size plastic-encapsulated adapter board 11 is separated from the board-level carrier board 10, and multiple first blind holes 201 are formed on the upper surface of the large-size plastic-encapsulated adapter board 11 using a laser engraving process, resulting in... Figure 2b The structure shown is as follows. The depth of the first blind hole 201 is determined based on the specific thickness of the large-size plastic-encapsulated adapter plate 11. Theoretically, the depth of the first blind hole 201 is less than the thickness of the large-size plastic-encapsulated adapter plate 11.

[0025] Finally, multiple second blind holes are formed on the lower surface of the large-size plastic-encapsulated adapter board 11 using a laser engraving process, resulting in... Figure 2c The structure is shown. It should be noted that the positions of each second blind hole and the first blind hole 201 are one-to-one, and the two pass through each other to form a through hole 202, as shown in c.

[0026] In this embodiment 1, the overall dimensions of the large-size plastic-encapsulated adapter plate 11 are (310~700) mm × (310~700) mm, the thickness is 10~25 mm, the material is epoxy resin or polyimide, and the volume resistivity is >10. 16 Ω·cm.

[0027] Specifically, in step S10, an epoxy resin or polyimide plastic-encapsulated adapter board is first prepared based on the board-level carrier board 10 using a plastic encapsulation process. Then, after the carrier board is separated, a first blind hole 201 and a second blind hole are respectively prepared on the upper and lower surfaces of the adapter board using a laser engraving process, and through holes 202 are formed. This not only realizes the flexible preparation of large-size adapter boards to adapt to the needs of large-area high-density packaging, but also ensures the accurate correspondence and penetration effect of the through hole 202 position through the high-precision processing of laser engraving. At the same time, the insulation reliability of the adapter board is ensured by the use of specific insulating materials and high volume resistivity parameters.

[0028] S20, multiple first conductive pillars 203 are completely filled in multiple through holes 202, and a first metal layer 12 and a second metal layer 13 are formed on the upper and lower surfaces of the large-size plastic-encapsulated adapter plate 11, respectively, with the first metal layer 12 and the second metal layer 13 completely covering the first conductive pillars 203.

[0029] Specifically, step S20 also includes: Using Physical Vapor Deposition (PVD) coating technology combined with electroplating, in such... Figure 2c The structure shown forms multiple first conductive pillars 203, and a first metal layer 12 and a second metal layer 13 are formed on the upper and lower surfaces of the large-size plastic-encapsulated adapter plate 11, respectively, to obtain the following... Figure 2d The structure shown is such that the first conductive pillar 203, the first metal layer 12, and the second metal layer 13 each include at least one of aluminum, copper, gold, platinum, nickel, and tin.

[0030] Furthermore, step S20 not only ensures high adhesion, high purity, and uniform coverage between the first metal layer 12 and the second metal layer 13 and the surface of the large-size plastic-encapsulated adapter board 11 through the PVD process, but also achieves dense filling and precise molding of the first conductive pillar 203 in the through hole 202 through the electroplating process. At the same time, the optional configuration of various high-conductivity metals can flexibly adapt to the electrical performance requirements of different packaging scenarios, effectively constructing a stable and reliable vertical conductive path between the chip 16 and the printed circuit board 19.

[0031] S30, the first metal layer 12 is patterned to obtain a plurality of spaced first pads 121; simultaneously, the second metal layer 13 is patterned to obtain a plurality of spaced second pads 131.

[0032] Specifically, step S30 also includes: Patterned first pads 121 and second pads 131 are formed on the upper and lower surfaces of a large-size plastic-encapsulated adapter board 11 using photolithography, wet etching, and resist removal processes, resulting in... Figure 2eThe structure shown is such that each first pad 121 is electrically connected to the corresponding second pad 131 through the corresponding first conductive post 203, and the first pad 121 and the corresponding second pad 131 overlap on the orthographic projection portion of the large-size plastic-encapsulated adapter board 11.

[0033] Furthermore, step S30 not only ensures the consistency and molding accuracy of pad size and spacing through high-precision patterning technology, but also reduces contact resistance and improves the stability and efficiency of electrical signal transmission through precise correspondence of conductive paths and projection layout design. At the same time, the spaced structure avoids signal interference between pads, providing a precisely matched interface for the reliable electrical connection of pin 15 of chip 16 with the first pad 121, and the second pad 131 with the third pad of printed circuit board 19. This further enhances the high-density integration capability and excellent electrical performance of the large-size package structure, laying a key foundation for the reliability of the overall package structure.

[0034] S40, multiple chips 16 are fixed at intervals on the first pad 121, and then a first filler layer 17 is formed on the upper surface of the large-size plastic-encapsulated adapter board 11; the first filler layer 17 completely covers the multiple chips 16 and covers the gap formed between the large-size plastic-encapsulated adapter board 11 and the chips 16.

[0035] Specifically, step S40 also includes: First, two chips 16 (Chip1, Chip2) are fixed onto the patterned first pad 121 on the upper surface of a large-size plastic-encapsulated adapter board 11 using flip-chip technology, resulting in the following... Figure 2f The structure is shown. In this structure, each pin 15 of chip 16 is electrically connected to a corresponding first pad 121 via a second conductive post 14. The second conductive post 14 is at least one of aluminum, copper, gold, platinum, nickel, and tin. The two chips 16 can be the same type of chip 16 or different types of chips 16.

[0036] Subsequently, the gap between the two chips 16 and the large-size plastic-encapsulated adapter board 11 is filled using a bottom filling process, and a first filling layer 17 is formed around the two chips 16, resulting in the following... Figure 2g In the structure shown, the first filling layer 17 is an insulating material such as epoxy resin or silicon dioxide.

[0037] Furthermore, step S40, through the flip-chip technology of chip 16 combined with the second conductive post 14 of multiple selectable materials, achieves precise electrical connection between different types of chips 16 and the first pad 121, balancing the flexibility of chip 16 integration with the reliability of electrical connection; at the same time, the bottom filling process is used to form the first filler layer 17 of insulating material, which not only fully fills the gap between chip 16 and large-size plastic-encapsulated adapter board 11, enhancing the mechanical stability of the package structure, but also provides insulation protection for chip 16 and connection parts, effectively avoiding external contamination or short circuit risks, adapting to the high integration requirements of large-size packaging, and comprehensively improving the stability and safety of the package structure.

[0038] S50, the large-size plastic-encapsulated adapter board 11 is fixed on the printed circuit board 19, so that the second pad 131 is electrically connected to the third pad on the surface of the printed circuit board 19; then, a second filling layer 20 is formed in the gap between the large-size plastic-encapsulated adapter board 11 and the printed circuit board 19 (PCB), and a chip packaging structure based on the large-size plastic-encapsulated adapter board 11 is obtained.

[0039] Specifically, step S50 also includes: First, metal conductive balls 18 are formed on the patterned second pads 131 on the lower surface of the large-size plastic-encapsulated adapter board 11 using a ball-planting process (each metal conductive ball 18 corresponds one-to-one with each second pad 131), resulting in the following... Figure 2h The structure shown is then followed by fixing the large-size plastic-encapsulated adapter board 11 onto the printed circuit board 19, so that the second pad 131 is electrically connected to the third pad on the surface of the printed circuit board 19 through the corresponding metal conductive ball 18, resulting in the structure shown. Figure 2i The structure is shown; finally, the gap between the large-size plastic-encapsulated adapter board 11 and the printed circuit board 19 (PCB) is filled by a bottom filling process to form a second filling layer 20, ultimately obtaining a chip packaging structure based on the large-size plastic-encapsulated adapter board 11, as shown. Figure 2j As shown.

[0040] In Example 1, the second conductive post 14 and the metal conductive ball 18 each include at least one of aluminum, copper, gold, platinum, nickel and tin, preferably copper; the second filler layer 20 is epoxy resin, silicon oxide or other insulating material.

[0041] Furthermore, in step S50, a ball-planting process is used to form metal conductive balls 18 that correspond one-to-one with the second pad 131, achieving precise alignment and stable electrical connection between the large-size plastic-encapsulated adapter board 11 and the third pad on the surface of the printed circuit board 19, ensuring the reliability of the package structure and external circuit signal transmission. Subsequently, a second filler layer 20 is formed through a bottom filling process, which not only fully fills the gap between the two and significantly enhances the mechanical stability and impact resistance of the overall package structure, but also avoids the risk of short circuits or external contamination at the connection points through the protective effect of the insulating material, adapting to the connection requirements of large-size packages and comprehensively improving the overall reliability and long-term stability of the package structure.

[0042] Please see Figure 2j Example 1 also provides a chip packaging structure, which is prepared by the above-mentioned preparation method based on molding process, photolithography process, wet etching process, resist removal process, chip flip-chip process and underfill process.

[0043] The chip packaging structure and its fabrication method based on a large-size plastic-encapsulated adapter board 11 provided by the present invention use the large-size plastic-encapsulated adapter board 11 as an interposer, and adopt the flip chip technology to achieve high integration of multiple types and quantities of chips 16. The other side of the large-size plastic-encapsulated adapter board 11 is connected to the PCB board (or substrate) to finally obtain a highly integrated chip packaging structure.

[0044] In summary, compared with the prior art, the chip packaging structure and its fabrication method based on the large-size plastic-encapsulated adapter board 11 provided by the present invention have the following technical advantages: (1) This technical solution proposes for the first time to use laser technology to form blind hole structures on both sides of a large-size plastic-encapsulated adapter board 11, and finally to interconnect the blind holes on both sides to form a through hole 202 structure. This process can effectively control the consistency of the size of the waist of the through hole 202 and the surface during the formation of the through hole 202 structure on the large-size plastic-encapsulated adapter board 11 by laser technology, and avoid the formation of a "funnel-shaped" hole structure; and this process is particularly suitable for forming through holes 202 or blind hole structures on large-size plastic-encapsulated adapter boards 11 with a large thickness.

[0045] (2) This technical solution uses a large-size plastic encapsulation plate as an interposer to prepare a CoWoS-like chip packaging structure. Relying on the unparalleled large size advantage of the large-size plastic encapsulation plate (specifically, 310mm×310mm, 600mm×600mm, 700mm×700mm or larger sizes can be used), the chip 16 packaging efficiency can be greatly improved and the chip 16 packaging cost can be significantly reduced.

[0046] (3) This technical solution uses a large-size plastic-encapsulated adapter plate 11 as an interposer. The plastic-encapsulated material (such as epoxy resin, polyimide, etc.) itself has excellent insulation properties with high impedance and low leakage current, and the volume resistivity is usually >10. 16 Ω cm can effectively block current leakage; compared with traditional silicon interposers, although the latter can improve insulation by depositing an insulating layer (such as SiO2), the silicon substrate itself is a semiconductor material, which requires additional processing and has the risk of insulation failure.

[0047] It should be noted that all the above embodiments belong to the same inventive concept, and the descriptions of each embodiment have different focuses. Where the description in a particular embodiment is not detailed, please refer to the description in other embodiments.

[0048] The above embodiments merely illustrate implementation methods of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. A method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board, characterized in that, The method includes: S10 features multiple spaced through holes on a large-size plastic-encapsulated adapter plate; S20, the plurality of first conductive pillars are completely filled in the plurality of through holes, and a first metal layer and a second metal layer are formed on the upper and lower surfaces of the large-size plastic-encapsulated adapter plate, respectively, wherein the first metal layer and the second metal layer completely cover the first conductive pillars. S30, the first metal layer is patterned to obtain a plurality of spaced first pads; simultaneously, the second metal layer is patterned to obtain a plurality of spaced second pads. S40, multiple chips are fixed at intervals on the first pad, and then a first filler layer is formed on the upper surface of the large-size plastic-encapsulated adapter board; the first filler layer completely covers the multiple chips and covers the gap formed between the large-size plastic-encapsulated adapter board and the chips; S50, the large-size plastic-encapsulated adapter board is fixed on the printed circuit board, so that the second pad is electrically connected to the third pad on the surface of the printed circuit board; then a second filling layer is formed in the gap between the large-size plastic-encapsulated adapter board and the printed circuit board, thereby obtaining a chip packaging structure based on the large-size plastic-encapsulated adapter board.

2. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 1, characterized in that, The S10 step specifically includes: S101, The large-size plastic-encapsulated adapter plate is formed on the plate-level carrier plate using a plastic-encapsulation process; S102, after the large-size plastic-encapsulated adapter board is peeled from the board-level carrier board, a plurality of first blind holes are formed on its upper surface by laser engraving process; the depth of each first blind hole is less than the thickness of the large-size plastic-encapsulated adapter board; S103, a plurality of second blind holes are formed on the lower surface of the large-size plastic-encapsulated adapter plate by laser engraving process. Each second blind hole corresponds to a first blind hole, and the two holes pass through each other to form the through hole.

3. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 2, characterized in that, In step S101, the overall dimensions of the large-size plastic-encapsulated adapter plate are (310~700) mm × (310~700) mm, the thickness is 10~25 mm, the material is epoxy resin or polyimide, and the volume resistivity is >10. 16 Ω·cm.

4. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 1, characterized in that, In step S20, the first conductive pillar, the first metal layer, and the second metal layer each include at least one of aluminum, copper, gold, platinum, nickel, and tin.

5. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 1, characterized in that, In step S30, the patterning process is performed sequentially using photolithography, wet etching, and resist removal.

6. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 5, characterized in that, Each of the first pads is electrically connected to the corresponding second pad through the corresponding first conductive post, and the first pads and the corresponding second pads overlap in their orthogonal projections on the large-size plastic-encapsulated adapter board.

7. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 6, characterized in that, In step S40, the pins of the multiple chips are electrically connected to the corresponding first pads one by one through the second conductive pillars; in step S50, the second pads are soldered to the third pads through metal conductive balls.

8. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 7, characterized in that, The second conductive post and the metal conductive ball each include at least one of aluminum, copper, gold, platinum, nickel and tin.

9. The method for fabricating a chip packaging structure based on a large-size plastic-encapsulated adapter board according to claim 1, characterized in that, In steps S40 and S50, both the first filler layer and the second filler layer are epoxy resin or silicon oxide.

10. A chip packaging structure, characterized in that, The chip packaging structure is prepared by the preparation method according to any one of claims 1 to 9.

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