Chip fan-out packaging structure and manufacturing method thereof

Abstract

The invention discloses a chip fan-out packaging structure and a manufacturing method thereof.The chip fan-out packaging structure comprises a substrate, a passivation layer, a chip, a substrate bonding pad, a chip bonding pad and a plastic packaging layer, the passivation layer is arranged on the surface of the substrate, a chip mounting area is reserved in the passivation layer, the chip is mounted on the surface of the substrate, the chip bonding pad is arranged on the surface of the substrate bonding pad, and the plastic packaging layer is arranged between the substrate bonding pad and the chip bonding pad. The passivation layer is arranged on the surface of the substrate, the chip bonding pad is arranged on the surface, far away from the substrate, of the chip, the substrate bonding pad is arranged between the passivation layer and the substrate, the substrate bonding pad and the chip bonding pad are connected through metal wires, and the plastic packaging layer is arranged on the surface of the substrate and wraps the passivation layer, the chip and the metal wires; the passivation layer is made of photoetching polyimide or a dry film; and the plastic package layer is made of one of non-photolithographic resin, non-photosensitive polyimide and glass fiber prepreg. The chip fan-out packaging processing cost can be reduced, and large-scale mass production is facilitated.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor packaging, and particularly relates to a chip fan-out packaging structure and a manufacturing method thereof. BACKGROUND

[0002] Fan-out packaging technology is a key technical solution for realizing device miniaturization and high-density integration due to the fan-out expansion capability of I / O ports. However, in the prior art, packaging relies on expensive special materials, and the complicated process leads to high equipment investment, low production efficiency, superimposed yield fluctuation, and significantly increased manufacturing cost, which is difficult to balance the demand for packaging performance, thinness and low cost. In the face of various chips and higher density and finer line packaging requirements, fan-out packaging still needs to develop new structures and process methods to adapt to various needs while ensuring quality and reducing cost. SUMMARY

[0003] In order to solve the above problems existing in the prior art, the application provides a chip fan-out packaging structure and a manufacturing method thereof, which has lower manufacturing cost, simpler processing method and structure of the overall packaging process, to overcome the deficiencies of the prior art.

[0004] In order to achieve the above purpose, the application adopts the following technical solutions:

[0005] According to a first aspect of the application, a chip fan-out packaging structure is provided, characterized in that it comprises a substrate, a passivation layer, a chip, a substrate pad, a chip pad and a plastic packaging layer. The passivation layer is arranged on the surface of the substrate and has a reserved area for mounting the chip. The chip is mounted on the surface of the substrate. The chip pad is arranged on the side of the chip away from the substrate. The substrate pad is arranged between the passivation layer and the substrate. The substrate pad and the chip pad are connected by a metal wiring. The plastic packaging layer is arranged on the surface of the substrate and covers the passivation layer, the chip and the metal wiring. The material of the passivation layer is photoetchable polyimide or dry film. The material of the plastic packaging layer is one of non-photoetchable resin, non-photosensitive polyimide and glass fiber prepreg. The use of photoetchable passivation layer facilitates precise patterning. The use of low-cost non-photosensitive material as the main plastic packaging layer significantly reduces the overall manufacturing cost while ensuring structure protection and support. The processing method and structure of the overall packaging process are also simpler.

[0006] Preferably, the metal wiring comprises a vertically arranged metal via hole, the aperture of the metal via hole gradually increases from the bottom to the top, and the bottom of the metal via hole is connected to the chip pad or the substrate pad. This is conducive to subsequent metal filling and covering, improves the reliability and yield of interconnection, and the structure of widening from top to bottom also enhances the stability of the wiring.

[0007] Preferably, the thickness of the passivation layer is less than the chip. Ensuring that the encapsulation layer material can flow and coat the chip sidewall to form a stable support, effectively preventing the chip from shifting or being damaged, improving the overall firmness and reliability of the packaging structure.

[0008] Preferably, a chip fan-out packaging structure further comprises a solder joint connecting the chip pad and the substrate pad through the metal wire, and the solder joint is exposed to the encapsulation layer.

[0009] Preferably, the material of the substrate is silicon or glass.

[0010] According to the second aspect of the present application, a manufacturing method of a chip fan-out packaging structure is provided, which is used to manufacture the above-mentioned chip fan-out packaging structure, and comprises the following steps:

[0011] S1: providing a substrate, preparing a substrate pad and a passivation layer on the surface of the substrate, the passivation layer covering the substrate pad, removing the passivation layer of the chip mounting area and opening a window at the position of the substrate pad, mounting the chip on the surface of the substrate, and the chip being provided with a chip pad away from the surface of the substrate; the material of the passivation layer is photo-etchable polyimide or dry film;

[0012] S2: preparing an encapsulation layer, the encapsulation layer covering the chip, the substrate pad, the chip pad and the passivation layer, opening a window at the positions of the substrate pad and the chip pad by laser, and filling metal to connect the chip pad and the substrate pad through a metal wire; the material of the encapsulation layer is one of non-photo-etchable resin, non-photo-sensitive polyimide and glass fiber prepreg.

[0013] The use of photo-etchable passivation layer facilitates precise patterning, and the use of non-photo-etchable encapsulation layer material increases the thickness of the encapsulation body, which improves the flexibility of the mounting and processing of chips with different thicknesses. The use of laser for pad exposure rapid processing eliminates the complex process of traditional photo-etching and other pad windowing processes. This process simplifies the traditional complex process, significantly reduces the cost, and is suitable for large-scale production.

[0014] Preferably, it further comprises step S3: manufacturing a solder joint, which is exposed to the encapsulation layer and connects the metal wire.

[0015] Further preferably, it further comprises step S4: thinning the substrate. This facilitates the ultra-thin miniaturization of the device.

[0016] Preferably, the material of the substrate is silicon or glass; and the thickness of the passivation layer is less than the chip.

[0017] Preferably, the metal wiring comprises a metal via arranged vertically, a hole diameter of the metal via gradually increases from a bottom to a top, and the bottom of the metal via is connected to the chip pad or the substrate pad.

[0018] Compared with the prior art, the beneficial results of the present application are that:

[0019] The present application provides a chip fan-out packaging structure and a manufacturing method thereof. In the structure, a combination of a patternable passivation layer and a low-cost non-photosensitive encapsulation layer is creatively adopted. The former is used to realize high-precision substrate wiring, while the latter greatly reduces the cost of the main encapsulation material and enhances the structural flexibility and compatibility with chips of different thicknesses. In the process, the complex and expensive photolithography process is abandoned, and the chip pad and the substrate pad are exposed by laser at one time. The self-top-down taper via formed is more conducive to metal filling, improves the interconnection reliability, and greatly simplifies the process steps. This scheme not only realizes the ultra-thin miniaturization of packaging by thinning the substrate, but also significantly reduces the packaging processing cost due to its simplified process and low-cost materials, while having excellent yield and potential for mass production, realizing the unification of high performance, ultra-thin and low cost. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings provide further explanation of embodiments, which are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain the principles of the present application. Other embodiments and many of the intended advantages of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. Other features, objects, and advantages of the present application will become more apparent from the following detailed description when read in connection with the accompanying drawings, in which:

[0021] Figure 1 is a structural schematic diagram of a chip fan-out packaging structure according to one specific embodiment of the present application;

[0022] Figure 2 is a flow chart of a manufacturing method of a chip fan-out packaging structure according to one specific embodiment of the present application;

[0023] Figures 3-6 is a step diagram of a manufacturing method of a chip fan-out packaging structure according to one specific embodiment of the present application.

[0024] The meanings of the numbers in the figures are as follows: 1-substrate, 2-passivation layer, 3-chip, 4-substrate pad, 5-chip pad, 6-encapsulation layer, 7-metal wiring, 71-metal via, 8-solder joint, 9-mounting layer. DETAILED DESCRIPTION

[0025] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0026] In the description of this invention, it should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0027] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installed", "equipped", "sleeved / connected", "connected", etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0028] To facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0029] Figure 1This application illustrates a specific embodiment of a chip fan-out package structure, comprising: a substrate 1, a passivation layer 2, a chip 3, substrate pads 4, chip pads 5, and a molding compound 6. The passivation layer 2 is disposed on the surface of the substrate 1 and has a reserved area for mounting the chip 3. The chip 3 is mounted on the surface of the substrate 1. At least one chip pad 5 is provided on the side of the chip 3 away from the substrate 1. The substrate pads 4 are disposed between the passivation layer 2 and the substrate 1. The substrate pads 4 and the chip pads 5 are connected by metal wiring 7. The molding compound 6 is disposed on the surface of the substrate 1 and encapsulates... The passivation layer 2, the chip 3, and the metal wiring 7 are covered. The material of the passivation layer 2 is photolithographically identifiable polyimide or dry film. The material of the molding layer 6 is one of non-photolithographic resin, non-photosensitive polyimide, and glass fiber prepreg. Specifically, the non-photolithographic resin can be a resin-based composite material, which is a composite material of resin and inorganic materials. The resin includes, but is not limited to, one of epoxy resin, phenolic resin, and polyimide resin. The inorganic materials include, but are not limited to, one of silicon dioxide, silicon nitride, and alumina powder. The mixing ratio is 15-45% resin and 55-85% inorganic materials by weight. The polyimide resin is non-photosensitive polyimide, which has high temperature resistance and is suitable for high-temperature process environments. The glass fiber prepreg is glass fiber prepreg of resin, which can provide mechanical support strength. The inorganic filler can adjust the coefficient of thermal expansion. Preferably, the inorganic filler is silicon dioxide or alumina powder with a particle size controlled in the range of 1-8 μm. The use of a photolithographic passivation layer 2 facilitates precise patterning, and the combination of a low-cost non-photosensitive material as the main molding layer 6 significantly reduces the overall manufacturing cost while ensuring structural protection and support.

[0030] In a specific embodiment, the metal wiring 7 has a multi-layer structure. The metal wiring 7 can be stacked in multiple layers according to actual needs. The molding layer 6 covers the metal wiring 7, eliminating the need for photolithography and further reducing processing costs.

[0031] Optionally, the chip 3 is attached to the surface of the substrate 1 via a mounting layer 8, the material of which can be conductive adhesive, metal paste, or DAF (Die Attach Film).

[0032] In a specific embodiment, the metal wiring 7 includes a vertically arranged metal via 71, the diameter of which gradually increases from bottom to top, and the bottom of the metal via 71 is connected to the chip pad 5 or the substrate pad 4.

[0033] In a specific embodiment, the thickness of the passivation layer 2 is less than that of the chip 3; and there is a gap between the chip 3 and the passivation layer 2.

[0034] In a specific embodiment, a chip fan-out package structure further includes solder joints 8, which connect the chip pads 5 and the substrate pads 4 through the metal wiring 7. The solder joints 8 are located where the metal wiring 7 is exposed outside the molding compound 6.

[0035] Optionally, the substrate 1 is made of silicon or glass.

[0036] Figure 2 This application illustrates a method for fabricating a chip fan-out package structure according to a specific embodiment, which includes the following steps:

[0037] S1: A substrate 1 is provided. Substrate pads 4 and a passivation layer 2 are prepared on the surface of the substrate 1. The passivation layer 2 covers the substrate pads 4. The passivation layer 2 in the mounting area of ​​the chip 3 is removed, and a window is made at the position of the substrate pads 4. The chip 3 is mounted on the surface of the substrate 1. Chip pads 5 are provided on the surface of the chip 3 away from the substrate 1. The material of the passivation layer 2 is photolithographic polyimide or dry film.

[0038] S2: Prepare molding layer 6, which covers chip 3, substrate pad 4, chip pad 5 and passivation layer 2. Use laser to create windows at the positions of substrate pad 4 and chip pad 5, and fill with metal so that chip pad 5 and substrate pad 4 are connected by metal wiring 7. The material of molding layer 6 is one of non-photolithographic resin, non-photosensitive polyimide and glass fiber prepreg.

[0039] By employing a non-photolithographic molding layer 6 material, the thickness of the molding compound is increased, enhancing the flexibility of mounting chips 3 of varying thicknesses. Laser-assisted rapid exposure of the solder pads eliminates the need for complex traditional photolithography processes for pad opening. Combined with laser processing, metal vias 71 with gradually increasing openings from bottom to top are obtained, facilitating metal interconnection and further reducing processing costs. This process simplifies traditional complex processes, significantly reduces costs, and is suitable for mass production.

[0040] In a specific embodiment, the following steps are also included:

[0041] S3: Fabricate solder joint 8, which is exposed outside the plastic encapsulation layer 6 and connected to the metal wiring 7;

[0042] S4: Thin the substrate 1. This facilitates the ultra-thin miniaturization of the device.

[0043] In a specific embodiment, the non-photolithographic resin can be a resin-based composite material, which is a composite material of resin and inorganic materials. The resin includes, but is not limited to, epoxy resin, phenolic resin, or polyimide resin, and the inorganic materials include, but are not limited to, silicon dioxide, silicon nitride, or alumina powder. The mixing ratio, by weight, is 15-45% resin and 55-85% inorganic materials. The polyimide resin is selected as a non-photosensitive polyimide, which has high-temperature resistance and is suitable for high-temperature process environments. The glass fiber prepreg is glass fiber prepreg of resin, which provides mechanical support strength, and the inorganic filler can adjust the coefficient of thermal expansion. Preferably, the inorganic filler is silicon dioxide or alumina powder with a particle size controlled within the range of 1-8 μm.

[0044] Optionally, the substrate 1 is made of silicon or glass.

[0045] In a specific embodiment, the thickness of the passivation layer 2 is less than that of the chip 3.

[0046] In a specific embodiment, the metal wiring 7 includes a vertically arranged metal via 71, the diameter of which gradually increases from bottom to top, and the bottom of the metal via 71 is connected to the chip pad 5 or the substrate pad 4.

[0047] In a specific embodiment, there is a gap between the chip 3 and the passivation layer 2.

[0048] In a specific embodiment, multiple layers of metal wiring 7 can be constructed. The method involves preparing and covering a non-photolithographic molding layer 6 on the previous layer of metal wiring 7, followed by laser processing to create windows, thereby forming a new layer of metal wiring 7 and metal vias 71 with gradually increasing openings from bottom to top. This process facilitates metal interconnection and further reduces processing costs by eliminating the need for photolithography.

[0049] Optionally, depending on the actual needs of the product, the metal via 71 may not be made, that is, the substrate pad 4 is not connected to the solder joint 8 and the chip pad 5 through the metal wiring 7, and the substrate pad 4 does not need to be led out for metal interconnect wiring.

[0050] Figures 3-6 The diagram illustrates the steps of a method for fabricating a chip fan-out package structure according to a specific embodiment of this application, as shown below. Figure 3 As shown, a substrate 1 is provided, a passivation layer 2 is formed on the surface of the substrate 1, and a window is made in the passivation layer 2 in advance for the area to be reserved for chip 3 mounting. Then the chip 3 is mounted on the substrate 1, and the chip 3 has at least one chip pad 5.

[0051] Optionally, the chip 3 is mounted on the surface of the substrate 1 via a mounting layer 8, the material of which can be conductive adhesive, metal paste, or DAF film.

[0052] Optionally, the openings in the passivation layer 2 above the pads have the same aperture at the bottom and top, and the thickness of the chip 3 is greater than that of the passivation layer 2.

[0053] In a specific embodiment, the passivation layer 2 is made of photolithographic polyimide or a dry film.

[0054] like Figure 4 As shown, a molding compound 6 is applied to the surface of chip 3, passivation layer 2, substrate pad 4 and substrate 1. The openings of chip pad 5 and substrate pad 4 are opened by laser processing. The hole structure obtained by laser processing has an increasing aperture from bottom to top, reaching its maximum at the surface. Then, the first metal wiring 7 is performed to electrically connect substrate pad 4 and chip pad 5 through metal wiring 7.

[0055] like Figure 5 As shown, the metal wiring 7 is further covered with a plastic encapsulation layer 6, and then a laser is used to open a window in the area where the metal wiring 7 needs to be connected, and a second metal wiring 7 is made to create solder joints 8, which are then connected to the metal wiring 7.

[0056] like Figure 6 As shown, the side of substrate 1 away from chip 3 is thinned and then cut to form a single package.

[0057] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described inventive concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A chip fan-out packaging structure, characterized in that, include: The invention comprises a substrate, a passivation layer, a chip, substrate pads, chip pads, and a molding compound. The passivation layer is disposed on the surface of the substrate and has a reserved area for chip mounting. The chip is mounted on the surface of the substrate. Chip pads are provided on the side of the chip away from the substrate. The substrate pads are disposed between the passivation layer and the substrate. The substrate pads and the chip pads are connected by metal wiring. The molding compound is disposed on the surface of the substrate and covers the passivation layer, the chip, and the metal wiring. The passivation layer is made of photolithographic polyimide or dry film. The molding compound is made of one of the following: non-photolithographic resin, non-photosensitive polyimide, and glass fiber prepreg.

2. The chip fan-out packaging structure according to claim 1, characterized in that, The metal wiring includes vertically arranged metal vias, the diameter of which gradually increases from bottom to top, and the bottom of the metal vias is connected to the chip pads or the substrate pads.

3. The chip fan-out packaging structure according to claim 1, characterized in that, The passivation layer is thinner than the chip.

4. The chip fan-out packaging structure according to claim 1, characterized in that, The substrate is made of silicon or glass.

5. The chip fan-out packaging structure according to claim 1, characterized in that, It also includes solder joints, which connect the chip pads and the substrate pads through the metal wiring, and the solder joints are located where the metal wiring is exposed outside the molding compound.

6. A method for fabricating a chip fan-out package structure, characterized in that, Includes the following steps: S1: Provide a substrate, prepare substrate pads and a passivation layer on the surface of the substrate, the passivation layer covers the substrate pads, remove the passivation layer in the chip mounting area and open a window at the position of the substrate pads, mount the chip on the surface of the substrate, chip pads are provided on the surface of the chip away from the substrate, and the material of the passivation layer is photolithographic polyimide or dry film. S2: Prepare a molding compound layer, which covers the chip, substrate pads, chip pads and passivation layer. A window is made at the position of the substrate pads and the chip pads by laser, and metal is filled to connect the chip pads and the substrate pads through metal wiring. The material of the molding compound layer is one of non-photolithographic resin, non-photosensitive polyimide and glass fiber prepreg.

7. The manufacturing method according to claim 6, characterized in that, It also includes step S3: creating solder joints, which are exposed outside the molding layer and connected to the metal wiring.

8. The manufacturing method according to claim 7, characterized in that, It also includes step S4: thinning the substrate.

9. The manufacturing method according to claim 6, characterized in that, The substrate is made of silicon or glass; the passivation layer is thinner than the chip.

10. The manufacturing method according to claim 6, characterized in that, The metal wiring includes vertically arranged metal vias, the diameter of which gradually increases from bottom to top, and the bottom of the metal vias is connected to the chip pads or the substrate pads.

Images