Chip fan-out packaging method and packaging structure thereof
By using laser windowing and hybrid materials, the fan-out packaging process has been simplified, the heat dissipation problem of high-power chips has been solved, and ultra-thin and high-density integration has been achieved, meeting the miniaturization needs of electronic products.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-10
- Publication Date
- 2026-03-24
AI Technical Summary
Existing fan-out packaging technology relies on complex photolithography processes, resulting in high costs. Traditional molding layers have poor thermal conductivity, which cannot meet the heat dissipation requirements of high-power chips, and it is difficult to balance the compatibility of ultra-thin and high-density integration.
Laser windowing technology is used to replace photolithography, and a hybrid material encapsulation layer and diamond heat sink are used to simplify the process and improve heat dissipation performance.
It significantly reduces process complexity and cost, improves heat dissipation performance, and enables ultra-thin packaging and high-density integration, meeting the miniaturization needs of electronic products.
Smart Images
Figure CN121729115A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor packaging, and particularly relates to a chip fan-out packaging method and a packaging structure thereof. BACKGROUND
[0002] With the continuous upgrading of product performance requirements in the fields of consumer electronics, Internet of Things, communication, etc., electronic products are rapidly iterating towards miniaturization, multifunctionalization and environmental protection. The market has put forward higher requirements for the integration, functional density and performance of electronic systems. Fan-out packaging technology has become a key technology direction in the field of high-density and fine packaging due to its advantages of not requiring traditional lead frames and being able to realize chip "expansion" wiring.
[0003] However, the traditional fan-out packaging structure still faces many challenges when dealing with high-power and high-integration chips. The existing technology generally relies on complex photolithography processes for pad windowing, which is tedious and costly, becoming a bottleneck for reducing the overall cost of packaging. At the same time, the thermal conductivity of conventional plastic encapsulation materials is limited, making it difficult to meet the heat dissipation needs of high-power chips, which can easily lead to overheating of the device, increasing the risk of thermal failure, and thus affecting the yield and long-term reliability of the packaging. Although the industry has emerged a variety of new fan-out packaging solutions aimed at simplifying the process and improving integration, these solutions have explored structure design or material application, but it is often difficult to balance high heat dissipation performance and process simplification. Many existing solutions either sacrifice cost advantages due to complex structures or cannot completely solve the heat dissipation problem of high-power chips due to material limitations, and their potential in three-dimensional integration flexibility and ultrathinization still needs to be further explored.
[0004] In summary, developing a new fan-out packaging structure based on a hybrid material plastic encapsulation layer, combined with laser windowing and diamond heat dissipation mounting, has important technical value for breaking through the current bottlenecks of heat dissipation and process complexity faced by high-power chips. SUMMARY
[0005] In view of the technical problems that the existing fan-out packaging technology relies on complex photolithography windowing for process, resulting in high cost, and the traditional plastic encapsulation material has poor thermal conductivity, which cannot meet the heat dissipation needs of high-power chips, and it is difficult to simultaneously consider the compatibility of ultrathinization and high-density integration in structure, the present application proposes a chip fan-out packaging method and a packaging structure thereof.
[0006] According to an aspect of the present application, a packaging method of a chip fan-out packaging structure is provided, comprising the following steps:
[0007] S1, providing a silicon substrate having opposite first and second surfaces, and a chip having opposite functional and non-functional surfaces;
[0008] S2. Bond the non-functional surface of the chip to the first surface of the silicon substrate;
[0009] S3. A molding compound layer encapsulating the chip is formed on the first surface of the silicon substrate, and the pads of the functional surface of the chip are exposed by laser windowing;
[0010] S4. Perform metal wiring on one side of the functional surface of the chip to form a rewiring structure;
[0011] S5. The first surface of the silicon substrate is bonded to a temporary substrate through a temporary bonding layer, and the second surface of the silicon substrate is thinned.
[0012] S6. A diamond heat sink is attached to the second surface of the silicon substrate.
[0013] S7. Remove the temporary substrate and the temporary bonding layer.
[0014] This packaging process uses laser windowing technology to replace the traditional photolithography process, which significantly simplifies the pad exposure process and greatly reduces process complexity and manufacturing costs. At the same time, a diamond heat sink is integrated on the back of the silicon substrate, which effectively improves the heat dissipation performance of high-power chips and overcomes the defect of poor thermal conductivity in traditional plastic packaging structures.
[0015] Preferably, the specific steps of S4 are as follows: First, metal wiring is performed on one side of the functional surface of the chip; then, a passivation layer is fabricated on the molding compound; and second, metal wiring and solder joint fabrication are performed. Refining the metal wiring steps and fabricating the passivation layer and solder joints can improve the reliability of metal interconnects and the stability of signal transmission, meeting the requirements of high-density wiring.
[0016] More preferably, both the molding layer and the passivation layer are made of a mixture of resin and inorganic materials.
[0017] More preferably, the resin includes one or more of epoxy resin, phenolic resin, and non-photosensitive polyimide resin, and the inorganic material includes one or more of silicon dioxide, barium sulfate, silicate, titanium dioxide, aluminum oxide, calcium carbonate, antimony trioxide, and glass fiber.
[0018] Preferably, in step S3, the aperture obtained by laser windowing continuously increases in diameter from bottom to top, reaching its maximum diameter at the surface of the molding compound. This design optimizes subsequent metallization filling and coverage effects, reduces the risk of wiring breakage, and improves interconnect yield.
[0019] Preferably, in step S3, the laser used for laser window opening is a carbon dioxide laser or an ultraviolet laser, the laser spot diameter is 5μm-45μm, the number of single-hole pulses is 1800-20000, and the single-hole pulse energy is 0.5uJ-28uJ.
[0020] Preferably, the first surface of the silicon substrate is provided with pads, and in step S3, the pads on the first surface of the silicon substrate are exposed by laser windowing. Adding the steps of setting the silicon substrate pads and opening the window provides an interface for interconnection between the chip and the silicon substrate, expands 3D integration capabilities, and improves the overall packaging flexibility.
[0021] More preferably, in step S4, while performing metal wiring on one side of the functional surface of the chip, metal pillars interconnecting with the chip are formed on the pads on the first surface of the silicon substrate. Simultaneous fabrication of these interconnect metal pillars enables direct electrical connection between the chip and the silicon substrate pads, simplifying the three-dimensional interconnect process and improving signal transmission efficiency.
[0022] More preferably, the diameter of the metal pillar continuously increases from the bottom upwards, reaching its maximum at the surface of the molding compound. This bottom-to-top diameter design is adapted to laser-cut window patterns, enhancing the adhesion between the metal pillar and the molding compound and preventing detachment.
[0023] According to a second aspect of the present invention, a chip fan-out package structure is provided, comprising the silicon substrate, the chip, the molding compound, the redistribution structure, and the diamond heat sink; the functional surface of the chip is bonded to a first surface of the silicon substrate; the molding compound is disposed on the first surface of the silicon substrate, covering the chip and exposing the pads of the chip; the redistribution structure is disposed on one side of the functional surface of the chip; and the diamond heat sink is disposed on a second surface of the silicon substrate.
[0024] Compared with the prior art, this application has the following beneficial effects:
[0025] (1) The chip fan-out packaging structure of this application uses a mixture of resin or glue and inorganic materials as the molding layer and passivation layer to replace the traditional high-cost special packaging materials; at the same time, laser windowing is used instead of photolithography windowing, saving consumables such as photoresist and etchant and complex process steps, significantly reducing raw material and processing costs.
[0026] (2) The chip fan-out packaging structure of this application directly mounts a diamond heat sink with high thermal conductivity on the back of an ultra-thin silicon substrate, which establishes an efficient thermal management path for the chip and solves the heat dissipation bottleneck of high power consumption chips caused by the poor thermal conductivity of traditional plastic encapsulation materials. While ensuring excellent heat dissipation capabilities, it realizes the ultra-thinness and miniaturization of the package, which meets the development needs of electronic products for high-density integration and lightness and thinness.
[0027] (3) The chip fan-out packaging structure of this application supports the opening of silicon substrate pads and three-dimensional interconnection of the chip, which can expand the packaging function according to the needs and adapt to diverse chip integration scenarios. Attached Figure Description
[0028] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of this application. Other embodiments and many anticipated advantages of these embodiments will be readily recognized as they become better understood through reference to the following detailed description. Elements in the drawings are not necessarily to scale. The same reference numerals refer to corresponding similar parts.
[0029] Figure 1 A flowchart illustrating a packaging method for a chip fan-out package structure according to an embodiment of this application is shown.
[0030] Figures 2a-2g A schematic diagram of the manufacturing process of a chip fan-out package structure according to an embodiment of this application is shown;
[0031] Figure 3 A cross-sectional view of a chip fan-out package structure according to another embodiment of this application is shown;
[0032] The attached figures are labeled as follows:
[0033] 1-Silicon substrate, 101-First surface, 102-Second surface, 103-Silicon substrate pad, 2-Chip, 201-Chip pad, 202-Functional surface, 203-Non-functional surface, 3 Molding layer, 4-Rewiring structure, 401-Solder ball, 402-Metal pillar, 5-Passivation layer, 6-Diamond heat sink, 7-Temporary bonding layer, 8-Temporary substrate. Detailed Implementation
[0034] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention. Furthermore, it should be noted that, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.
[0035] Where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.
[0036] Figure 1 A flowchart of a packaging method for a chip fan-out package structure is shown. Figures 2a-2g The detailed fabrication process of the chip's fan-out package structure is shown, in conjunction with the reference. Figure 1 and Figures 2a-2gThe packaging method for this chip fan-out package structure specifically includes the following steps:
[0037] like Figure 2a As shown, a silicon substrate 1 with opposing first surfaces 101 and second surfaces 102 is provided, along with a plurality of chips 2 with opposing functional surfaces 202 and non-functional surfaces 203. The non-functional surfaces 203 of the chips 2 are bonded to the first surface 101 of the silicon substrate 1. This bonding process requires ensuring precise alignment between the chips 2 and the silicon substrate 1 to guarantee the accuracy and stability of subsequent packaging. High-precision bonding equipment can be used, and a firm connection between the chips 2 and the silicon substrate 1 can be achieved by controlling parameters such as bonding temperature, pressure, and time.
[0038] like Figure 2b As shown, a molding compound 3 is formed on the first surface 101 of the silicon substrate 1 to encapsulate the chip 2, and the chip pads 201 of the functional surface 202 of the chip 2 are exposed by laser windowing.
[0039] Specifically, the material of the molding layer 3 can be a resin-based organic-inorganic composite material. The resin includes one or more of epoxy resin, phenolic resin, and non-photosensitive polyimide resin. The inorganic material includes one or more of silicon dioxide, barium sulfate, silicate, titanium dioxide, aluminum oxide, calcium carbonate, antimony trioxide, and glass fiber. The mixing ratio, by weight, is 15%–45% resin and 55%–85% inorganic material. The above materials should possess good insulation, thermal stability, and mechanical properties to protect the chip 2 from external environmental influences. During the formation of the molding layer 3, a precise injection molding process must be used to ensure that the molding material uniformly encapsulates the chip 2, avoiding defects such as bubbles or voids.
[0040] In a specific embodiment, the material of the molding layer 3 is glass fiber pre-impregnated with a mixture of epoxy resin and silica.
[0041] Specifically, laser windowing uses a carbon dioxide laser or an ultraviolet laser, with the laser spot diameter strictly controlled between 5μm and 45μm, the number of pulses per aperture between 1800 and 20000, and the pulse energy per aperture between 0.5uJ and 28uJ. By using laser windowing, the cumbersome steps and high costs of traditional photolithography processes can be avoided, improving production efficiency and reducing costs. At the same time, the sidewall morphology formed by laser windowing is smooth, and the aperture of the window continuously increases from the bottom to the top, reaching its maximum at the surface of the molding layer 3. Compared with the relatively vertical via morphology produced by conventional photosensitive polyimide or dry film passivation layers, this design can optimize the subsequent metallization filling and coverage effects, reduce the risk of wiring breakage, and improve interconnect yield.
[0042] In other embodiments, such as Figure 3As shown, silicon substrate pads 103 can be provided on the first surface 101 of the silicon substrate 1. These pads are exposed during laser windowing, providing an interface for interconnection between the chip 2 and the silicon substrate 1, expanding the three-dimensional integration function, and improving the overall packaging flexibility. Similarly, the window on the silicon substrate pad 103 continuously increases in diameter from bottom to top, reaching its maximum diameter at the surface of the molding layer 3, to ensure the quality of subsequent metallization filling and interconnection.
[0043] like Figure 2c As shown, on one side of the functional surface 202 of chip 2, the first metal wiring, dielectric material laying, second metal wiring, and solder ball 401 fabrication are performed sequentially to form the redistribution structure 4 and passivation layer 5. During the first metal wiring, the deposition thickness of the metal material and the wiring width must be precisely controlled to ensure good conductivity and signal transmission performance. Metal deposition can be performed using methods such as physical vapor deposition or chemical vapor deposition, followed by photolithography and etching processes to form the desired wiring pattern.
[0044] Specifically, the material of passivation layer 5 is the same as that of molding layer 3. Passivation layer 5 protects the metal wiring from external environmental corrosion and improves the reliability of metal interconnects. During the manufacturing process, it is essential to ensure that passivation layer 5 is uniformly applied to the metal wiring and has good adhesion and insulation properties.
[0045] The second metal wiring and solder joint fabrication must be precisely aligned with the first metal wiring to achieve a reliable electrical connection. The size and shape of the solder ball 401 should be designed according to specific application requirements to ensure a good connection with external circuits. At the same time, the formation process of the solder ball 401 must be controlled to avoid problems such as cold solder joints and short circuits.
[0046] In other embodiments, when metal wiring is performed on one side of the functional surface 202 of chip 2, metal pillars 402 interconnecting with chip 2 are simultaneously formed on the silicon substrate pads 103 of the first surface 101 of silicon substrate 1. The diameter of the metal pillars 402 increases continuously from the bottom upwards, reaching its maximum diameter at the surface of the molding compound 3. The formation of the metal pillars 402 can be achieved using processes such as electroplating, with precise control over their growth rate and dimensional accuracy to ensure good electrical connection with chip 2 and silicon substrate pads 103.
[0047] like Figure 2d As shown, one side of the first surface 101 of the silicon substrate 1 is bonded to the temporary substrate 7 via a temporary bonding layer 6, and then the second surface 102 of the silicon substrate 1 is thinned. The bonding process requires high-precision bonding equipment, with strict control over parameters such as bonding temperature, pressure, and time. The temporary bonding layer 6 must possess good bonding strength and thermal stability to ensure a strong connection between the silicon substrate 1 and the temporary substrate 7 during subsequent thinning. Simultaneously, it must be ensured that the temporary bonding layer 6 will not damage the packaging structure during subsequent removal.
[0048] In specific embodiments, the thinning process can employ techniques such as mechanical grinding and chemical polishing to obtain a smooth and flat surface. During the thinning process, the thickness must be precisely controlled to avoid excessive thinning that could damage the silicon substrate 1. Simultaneously, the flatness and roughness of the second surface 102 of the silicon substrate 1 must meet design requirements to prepare for the subsequent mounting of the diamond heat sink 5. The thinned silicon substrate 1 can further reduce the thickness of the package, achieving ultra-thin and miniaturized packaging.
[0049] like Figure 2e As shown, a diamond heat sink 5 is mounted on the second surface 102 of the silicon substrate 1. The diamond heat sink 5 has high thermal conductivity, enabling the establishment of an efficient thermal management path for the chip 2. During the mounting process, it is crucial to ensure a tight fit between the diamond heat sink 5 and the second surface 102 of the silicon substrate 1. Thermally conductive adhesives or similar materials can be used for bonding to improve heat dissipation efficiency. Simultaneously, cleanliness must be maintained during the mounting process to prevent impurities from affecting heat dissipation performance.
[0050] like Figure 2f As shown, the temporary substrate 7 and temporary bonding layer 6 are removed. The removal process must be gentle and precise to avoid damaging the package structure. After removing the temporary substrate 7 and temporary bonding layer 6, the chip fan-out package structure is basically complete. After laser or mechanical cutting, a single packaged device can be formed, such as... Figure 2g As shown.
[0051] Example 1
[0052] A chip fan-out package structure, reference Figure 2g The system includes a silicon substrate 1, a chip 2, a molding compound 3, a redistribution structure 4, a passivation layer 5, and a diamond heat sink 6. The functional surface 202 of the chip 2 is bonded to the first surface 101 of the silicon substrate 1; the molding compound 3 is disposed on the first surface 101 of the silicon substrate 1, covering the chip 2 and exposing the pads 201 of the chip 2; the redistribution structure 4 is disposed on one side of the functional surface 202 of the chip 2; and the diamond heat sink 6 is disposed on the second surface 102 of the silicon substrate 1.
[0053] The specific encapsulation method is as follows:
[0054] S101, a silicon substrate 1 having opposing first surfaces 101 and second surfaces 102, and a plurality of chips 2 having opposing functional surfaces 202 and non-functional surfaces 203 are provided;
[0055] S102, The non-functional surface 203 of the chip 2 is bonded to the first surface 101 of the silicon substrate 1;
[0056] S103. A molding layer 3 encapsulating the chip 2 is formed on the first surface 101 of the silicon substrate 1, and the chip pads 201 of the functional surface 202 of the chip 2 are exposed by laser windowing.
[0057] S104. On one side of the functional surface 202 of chip 2, the first metal wiring, the laying of dielectric material, the second metal wiring and the fabrication of solder balls 401 are performed sequentially to form the rewiring structure 4 and the passivation layer 5.
[0058] S105. The first surface 101 of the silicon substrate 1 is bonded to the temporary substrate 7 through the temporary bonding layer 6, and then the second surface 102 of the silicon substrate 1 is thinned.
[0059] S106. A diamond heat sink 5 is attached to the second surface 102 of the silicon substrate 1.
[0060] S107, Remove the temporary substrate 7 and the temporary bonding layer 6;
[0061] S108. The package is cut to form a single packaged device.
[0062] Example 2
[0063] A chip fan-out package structure, reference Figure 3 The system includes a silicon substrate 1, a chip 2, a molding compound 3, a redistribution structure 4, metal pillars 402, a passivation layer 5, and a diamond heat sink 6. The functional surface 202 of the chip 2 is bonded to the first surface 101 of the silicon substrate 1; the molding compound 3 is disposed on the first surface 101 of the silicon substrate 1, covering the chip 2 and exposing the pads 201 of the chip 2; the redistribution structure 4 is disposed on one side of the functional surface 202 of the chip 2; the metal pillars 402 are disposed on the silicon substrate pads 103 of the first surface 101 of the silicon substrate 1 and interconnected with the chip 2; and the diamond heat sink 6 is disposed on the second surface 102 of the silicon substrate 1.
[0064] The specific encapsulation method is as follows:
[0065] S201, a silicon substrate 1 having a first surface 101 and a second surface 102 with opposite sides is provided, and a plurality of chips 2 having a functional surface 202 and a non-functional surface 203 with opposite sides are provided, and silicon substrate pads 103 are provided on the first surface 101 of the silicon substrate 1.
[0066] S202, The non-functional surface 203 of the chip 2 is bonded to the first surface 101 of the silicon substrate 1;
[0067] S203. A molding layer 3 is formed on the first surface 101 of the silicon substrate 1 to encapsulate the chip 2, and the chip pads 201 of the functional surface 202 of the chip 2 and the silicon substrate pads 103 of the first surface 101 of the silicon substrate 1 are exposed by laser windowing.
[0068] S204. On one side of the functional surface 202 of the chip 2, the first metal wiring, the laying of dielectric material, the second metal wiring and the fabrication of solder balls 401 are performed in sequence to form a redistribution structure 4 and a passivation layer 5. At the same time, a number of metal pillars 402 interconnecting with the chip 2 are formed on the silicon substrate pads 103 of the first surface 101 of the silicon substrate 1.
[0069] S205. The first surface 101 of the silicon substrate 1 is bonded to the temporary substrate 7 through the temporary bonding layer 6, and then the second surface 102 of the silicon substrate 1 is thinned.
[0070] S206. A diamond heat sink 5 is attached to the second surface 102 of the silicon substrate 1.
[0071] S207, Remove the temporary substrate 7 and the temporary bonding layer 6;
[0072] S208, The package is cut to form a single packaged device.
[0073] The specific embodiments of this application have been described above, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
[0074] In the description of this application, it should be understood that the terms "upper," "lower," "inner," "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing this application and for simplification, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The simple fact that certain measures are recited in mutually different dependent claims does not indicate that combinations of these measures cannot be used for improvement. Any reference signs in the claims should not be construed as limiting the scope.
Claims
1. A packaging method for a chip fan-out package structure, characterized in that, Includes the following steps: S1. A silicon substrate having opposing first and second surfaces, and a chip having opposing functional and non-functional surfaces are provided. S2. Bond the non-functional surface of the chip to the first surface of the silicon substrate; S3. A molding compound layer encapsulating the chip is formed on the first surface of the silicon substrate, and the pads of the functional surface of the chip are exposed by laser windowing; S4. Perform metal wiring on one side of the functional surface of the chip to form a rewiring structure; S5. The first surface of the silicon substrate is bonded to a temporary substrate through a temporary bonding layer, and the second surface of the silicon substrate is thinned. S6. A diamond heat sink is attached to the second surface of the silicon substrate. S7. Remove the temporary substrate and the temporary bonding layer.
2. The packaging method for the chip fan-out package structure according to claim 1, characterized in that, The specific steps of S4 are as follows: perform the first metal wiring on one side of the functional surface of the chip, then make a passivation layer on the molding layer, and perform the second metal wiring and solder joint fabrication.
3. The packaging method for the chip fan-out package structure according to claim 2, characterized in that, Both the molding layer and the passivation layer are made of a mixture of resin and inorganic materials.
4. The packaging method for the chip fan-out package structure according to claim 3, characterized in that, The resin includes one or more of epoxy resin, phenolic resin, and non-photosensitive polyimide resin, and the inorganic material includes one or more of silicon dioxide, barium sulfate, silicate, titanium dioxide, aluminum oxide, calcium carbonate, antimony trioxide, and glass fiber.
5. The packaging method for the chip fan-out package structure according to claim 1, characterized in that, In step S3, the aperture obtained by laser windowing continuously increases in diameter from bottom to top, reaching its maximum at the surface of the encapsulation layer.
6. The packaging method for the chip fan-out package structure according to claim 1, characterized in that, In S3, the laser used for laser windowing is a carbon dioxide laser or an ultraviolet laser, with a laser spot diameter of 5μm-45μm, a single-hole pulse number of 1800-20000, and a single-hole pulse energy of 0.5uJ-28uJ.
7. The packaging method for the chip fan-out package structure according to claim 1, characterized in that, The first surface of the silicon substrate is provided with pads, and in step S3, the pads on the first surface of the silicon substrate are exposed by laser windowing.
8. The packaging method for the chip fan-out package structure according to claim 7, characterized in that, In step S4, while performing metal wiring on one side of the functional surface of the chip, metal pillars interconnecting with the chip are formed on the pads of the first surface of the silicon substrate.
9. The packaging method for the chip fan-out package structure according to claim 8, characterized in that, The diameter of the metal column increases continuously from the bottom upwards, reaching its maximum at the surface of the plastic sealant layer.
10. A chip fan-out package structure as described in any one of claims 1-9, characterized in that, The device includes a silicon substrate, a chip, a molding compound, a redistribution structure, and a diamond heat sink. The functional surface of the chip is bonded to a first surface of the silicon substrate. The molding compound is disposed on the first surface of the silicon substrate, covering the chip and exposing the chip's pads. The redistribution structure is disposed on one side of the functional surface of the chip. The diamond heat sink is disposed on a second surface of the silicon substrate.