Signal processing system, laser radar chip and laser radar
By employing latching, multiplexing, and differential processing techniques in the signal processing system, the problem of accuracy degradation caused by laser emission enable signal noise was solved, achieving higher precision laser ranging and improving the safety of the vehicle system.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-20
- Publication Date
- 2026-03-27
AI Technical Summary
In existing technologies, the laser emission enable signal contains noise, which leads to a decrease in laser ranging accuracy and affects the safety of the vehicle system.
A signal processing system, including digital and analog circuits, is employed. Noise is isolated by latches and multiplexers, clock phase is adjusted by setting up phase-locked loops and delay chains, noise is suppressed by differential control units, and the processing path is selected by the controller according to the signal quality, thereby improving the accuracy of signal processing.
Effective isolation and noise reduction improve the accuracy of laser ranging, ensuring the safety and reliability of the vehicle system.
Smart Images
Figure CN121741689A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the technical field of signal processing, in particular to a signal processing system, a laser radar chip and a laser radar. BACKGROUND
[0002] The laser radar chip is the core component of the laser radar, responsible for the collection, processing and transmission of all laser radar information. In particular in a vehicle-mounted system, the laser radar chip undertakes an important object sensing function, so the accuracy of laser ranging will directly affect the life safety of the driver and passengers. The control of laser emission is a key parameter of laser ranging, and the emission enable signal used to control the emission module will cause the accuracy of laser ranging to decrease if there is noise. SUMMARY
[0003] Embodiments of the present application provide a signal processing system, a laser radar chip and a laser radar, which can reduce the influence of noise and improve the accuracy of laser ranging.
[0004] In a first aspect, embodiments of the present application provide a signal processing system, comprising: a digital circuit comprising a first register, configured to receive a first signal and output a second signal after latching the first signal; and an analog circuit comprising a second register and a first multiplexer, the second register being configured to receive the second signal and output a third signal after latching the second signal, the first multiplexer comprising a first input end, a second input end and a first output end, the first multiplexer being configured to select one of the first input end and the second input end and the first output end, the first input end being configured to receive the second signal, and the second input end being configured to receive the third signal.
[0005] By outputting the second signal after latching the first signal, data instability caused by fluctuations in the input signal can be avoided, and the system can perform operations according to a predetermined time sequence to facilitate subsequent algorithm processes. By latching the second signal in the second register in the analog circuit, noise carried in the process of transmitting the second signal from the digital circuit into the analog circuit can be isolated.
[0006] In one or more embodiments, the signal processing system is a transmission control system, and the first signal is a transmission enable signal.
[0007] By setting the analog circuit, noise carried in the process of transmitting the transmission enable signal from the digital circuit into the analog circuit can be isolated, which is conducive to improving the accuracy of laser ranging.
[0008] In one or more embodiments, the analog circuit comprises: a phase-locked loop configured to output a first clock signal, and a clock input terminal of the first register configured to receive the first clock signal; a second multiplexer comprising a third input terminal, a fourth input terminal and a second output terminal, the second multiplexer configured to select one of the third input terminal and the fourth input terminal to the second output terminal, the third input terminal configured to receive the first clock signal, the fourth input terminal configured to receive a second clock signal, and the second output terminal connected to a clock input terminal of the second register, wherein the second clock signal is a clock signal transmitted from the digital circuit to the analog circuit and looped back from the digital circuit to the analog circuit.
[0009] The phase-locked loop and the second multiplexer are configured to select a corresponding clock signal according to a requirement. If a clock signal with better quality is required, the first clock signal directly output by the phase-locked loop is selected. If a phase that is easier to adjust is required, the second clock signal looped back from the digital circuit to the analog circuit is selected.
[0010] In one or more embodiments, the analog circuit further comprises: a delay chain comprising a plurality of delay units, each of the delay units being configured with a tap, an input terminal of the delay chain being connected to the second output terminal, and the delay chain being configured to delay a signal output by the second multiplexer; an inverter connected to an output terminal of the delay chain and configured to invert the signal output by the delay chain; and a third multiplexer comprising a fifth input terminal, a sixth input terminal and a third output terminal, the third multiplexer configured to select one of the fifth input terminal and the sixth input terminal to the third output terminal, the fifth input terminal connected to an output terminal of the inverter, the sixth input terminal connected to the output terminal of the delay chain, and the third output terminal connected to the clock input terminal of the second register.
[0011] The delay chain, the inverter and the third multiplexer are introduced to configure a full-phase clock, so that the phase of the clock used to sample the first signal can be adjusted, and the first signal can be reliably sampled in the register in the analog circuit, meeting the setup time and hold time requirements.
[0012] In one or more embodiments, the analog circuit further comprises: a differential control unit connected to the first output terminal and configured to differentially process a signal output by the first multiplexer.
[0013] The differential control unit is configured to differentially process the signal output by the first multiplexer, so that the noise in the signal output by the first multiplexer can be suppressed, i.e., the noise of the signal output by the differential control unit is low, which is conducive to improving the accuracy of laser ranging.
[0014] In one or more embodiments, the analog circuit further comprises a fourth multiplexer comprising a seventh input end, an eighth input end and a fourth output end, the fourth multiplexer being configured to select one of the seventh input end and the eighth input end and the fourth output end, the seventh input end being connected with the first output end for receiving one of the second signal and the third signal, the eighth input end being used for receiving the first signal; the differential control unit being connected with the fourth output end, the differential control unit being used for differentially processing the signal output by the fourth multiplexer.
[0015] The fourth multiplexer is provided to select the first signal directly from the digital circuit or the signal after being latched by the second register in the analog circuit according to requirements.
[0016] In one or more embodiments, the signal processing system further comprises a controller connected with the control end of the first multiplexer, and used for: when the signal-to-noise ratio of the second signal is greater than or equal to a first preset threshold and the jitter of the second signal is less than or equal to a second preset threshold, controlling the first input end and the first output end of the first multiplexer to be selected; when the signal-to-noise ratio of the second signal is less than the first preset threshold and / or the jitter of the second signal is greater than the second preset threshold, controlling the second input end and the first output end of the first multiplexer to be selected.
[0017] The controller is provided to control the first multiplexer, so that the second signal is directly output when the second signal meets the product parameter requirements of the current application scenario, thereby improving the efficiency; and the third signal obtained after the second signal is latched by the second register is output when the second signal does not meet the product parameter requirements of the current application scenario, thereby reducing the noise and improving the precision.
[0018] In one or more embodiments, the controller is further connected with a second multiplexer in the analog circuit; and the controller is further used for controlling the third input end and the second output end of the second multiplexer to be selected when the second input end and the first output end of the first multiplexer are controlled to be selected.
[0019] The controller is provided to control the second multiplexer, so that the clock signal used by the second register is the first clock signal closest to the clock source (i.e. the phase-locked loop) when the second signal does not meet the product parameter requirements of the current application scenario, thereby improving the quality of the clock signal to further reduce the noise and improve the precision.
[0020] In a second aspect, the embodiments of the present application provide a laser radar chip, comprising: the signal processing system as described above, the signal processing system being a transmission control system, the first signal being a transmission enable signal, and the signal processing system being configured to process the transmission enable signal and output; and a transmission module configured to transmit laser light in response to the transmission enable signal output by the signal processing system.
[0021] In a third aspect, the embodiments of the present application provide a laser radar, comprising the laser radar chip as described above. BRIEF DESCRIPTION OF DRAWINGS
[0022] One or more embodiments are illustrated by way of example in the figures that form a part of this disclosure and which do not limit the scope of the application that is described in the claims. Like reference numerals can be used to refer to like elements throughout the accompanying drawings.
[0023] Figure 1 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 1 ; Figure 2 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 2 ; Figure 3 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 3 ; Figure 4 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 4 ; Figure 5 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 5 ; Figure 6 is a schematic diagram of a constituent block diagram of the signal processing system provided by the embodiments of the present application Figure 6 . DETAILED DESCRIPTION
[0024] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are some but not all of the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the present application and not used to limit the present application.
[0025] It should be noted that when an element is described as being "connected" to another element, it can be directly connected to the other element or one or more intermediate elements can be present therebetween.
[0026] In addition, the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0027] Please refer to Figure 1 , Figure 1 The schematic diagram of the composition block diagram of the signal processing system provided by the embodiments of the present application is shown in FIG. 1. As shown in FIG. 1, the signal processing system 1000 includes a digital circuit 100 and an analog circuit 200. Figure 1
[0028] The digital circuit 100 is a circuit that processes binary data (0 and 1) by representing information through discrete signals (usually high and low levels). The digital circuit 100 includes a first register 110, which is used to receive a first signal S1 and latch the first signal S1 to output a second signal S2. It can be understood that the first signal S1 and the second signal S2 are the same signal. By latching the first signal S1 to output the second signal S2, the data instability caused by the fluctuation of the input signal (i.e., the first signal S1) can be avoided, and the system can perform operations according to a predetermined time sequence to facilitate the implementation of subsequent algorithm processes.
[0029] The analog circuit 200 includes a second register 210 and a first multiplexer 220. The second register 210 is used to receive the second signal S2 and latch the second signal S2 to output a third signal S3. It can be understood that the second signal S2 and the third signal S3 are the same signal. By latching the second signal S2 in the second register 210 in the analog circuit 200, the noise carried in the process of transmitting the second signal S2 from the digital circuit 100 into the analog circuit 200 can be isolated.
[0030] In some embodiments, the above-mentioned signal processing system is a transmission control system, and accordingly, the first signal S1 is a transmission enable signal. In the related art, because the transmission enable signal is not optimized, the noise and jitter of the transmission enable signal are too large, which may result in low accuracy of laser ranging. By setting the analog circuit 200, the embodiments of the present application can isolate the noise carried in the process of transmitting the transmission enable signal from the digital circuit 100 into the analog circuit 200, thereby facilitating the improvement of the accuracy of laser ranging.
[0031] A multiplexer (MUX) is used to select one signal from multiple input signals as an output, which determines which input channel is connected to the output according to a control signal (selection signal). The first multiplexer 220 includes a first input end IN1, a second input end IN2 and a first output end OU1, and is configured to select one of the first input end IN1 and the second input end IN2 and the first output end OU1. The first input end IN1 is used to receive the second signal S2, and the second input end IN2 is used to receive the third signal S3. When the first input end IN1 and the first output end OU1 are selected, the first multiplexer 220 outputs the second signal S2; when the second input end IN2 and the first output end OU1 are selected, the first multiplexer 220 outputs the third signal S3. By setting the first multiplexer 220, the corresponding signal can be obtained according to the demand; for example, in a specific embodiment, the noise of the second signal S2 meets the product parameter requirement, and the first input end IN1 and the first output end OU1 of the first multiplexer 220 are configured to be selected to improve the working efficiency; for another example, in another specific embodiment, the noise of the second signal S2 exceeds the product parameter requirement, and the noise of the third signal S3 obtained by latching the second register 210 to isolate the noise in the digital circuit meets the product parameter requirement, so the second signal S2 cannot be directly output to the downstream, but the third signal S3 can be selected to be output to the downstream for use.
[0032] In some embodiments, as shown in FIG. 2, the analog circuit 200 further includes a phase-locked loop 230 and a second multiplexer 240. Figure 2
[0033] The phase-locked loop (PLL) 230 is a feedback control system used to generate stable frequency signals, recover synchronization signals, etc. The PLL adjusts the output frequency by comparing the phase difference between the input signal and the internally generated signal, so that the two are kept in synchronization. In this embodiment, the phase-locked loop 230 is used to output a first clock signal, and the clock input end (i.e., the CLK end) of the first register 110 is used to receive the first clock signal.
[0034] The second multiplexer 240 includes a third input end IN3, a fourth input end IN4 and a second output end OU2, and is configured to select one of the third input end IN3 and the fourth input end IN4 and the second output end OU2. The third input end IN3 is used to receive the first clock signal, the fourth input end IN4 is used to receive the second clock signal, and the second output end OU2 is connected to the clock input end of the second register 210; wherein the second clock signal is the clock signal transmitted from the digital circuit 100 to the analog circuit 200 and looped back from the digital circuit 100 to the analog circuit 200.
[0035] By setting the phase-locked loop 230 and the second multiplexer 240, the corresponding clock signal can be selected to be transmitted to the second register 210 according to the requirement. For example, if the quality of the clock signal needs to be better, the first clock signal directly output by the phase-locked loop 230 is selected because the first clock signal is closest to the clock source (i.e., the phase-locked loop 230); if the phase needs to be more easily adjusted, the clock signal looped back from the digital circuit 100 to the analog circuit 200, i.e., the second clock signal, is selected because the second clock signal is closer to the first register 110 in the digital circuit 100.
[0036] In some embodiments, as shown in FIG. 2, the analog circuit 200 further includes a delay chain 250 and an inverter 260. Figure 3
[0037] The delay chain 250 includes a plurality of delay units, and each delay unit is configured to introduce a fixed delay time. Each delay unit is provided with a tap, specifically, a tap is led out at the output end of each delay unit. The tap is an interface of the delay chain and is used to obtain different delay times. The input end of the delay chain 250 is connected to the output end (i.e., the second output end OU2) of the second multiplexer 240, and the delay chain 250 is used to delay the signal output by the second multiplexer 240, and the delay time is determined by the connected tap. The delay chain 250 can realize a configurable delay time of zero to half a clock period.
[0038] The inverter 260 is connected to the output end of the delay chain 250 and is used to perform inversion processing on the signal output by the delay chain 250. The inverter 260 can realize a 180-degree phase change of the clock of the signal output by the delay chain 250.
[0039] The third multiplexer 240 includes a fifth input end IN5, a sixth input end IN6, and a third output end OU3. The fifth input end IN5 is connected to the output end of the inverter 260, the sixth input end IN6 is connected to the output end of the delay chain 250, and the third output end OU3 is connected to the clock input end of the second register 210.
[0040] It can be understood that a tool (such as PrimeTime) is usually used in the digital circuit 100 for static timing analysis (STA) to verify whether all paths meet the setup time and hold time requirements. The analog circuit 200 is a continuous signal processing inside, which is not applicable to the standard digital timing model, and therefore cannot be included in the STA process. The first signal S1 is generated in the digital domain and needs to be latched by the register in the analog circuit 200, but because the register in the analog circuit 200 is not within the STA analysis range, it cannot be guaranteed that it can correctly sample the first signal S1, and may fail to sample. Based on this, the embodiment introduces the delay chain 250, the inverter 260 and the third multiplexer 240, which can realize the configuration of the full-phase clock, so as to adjust the clock phase for sampling the first signal S1, so that the first signal S1 can be reliably sampled in the register in the analog circuit 200, and meet the setup time and hold time requirements.
[0041] In some embodiments, as shown in Figure 4 The analog circuit 200 further includes a differential control unit 270.
[0042] The differential control unit 270 is connected with the first output end OU1, and the differential control unit 270 is configured to perform differential processing on the signal output by the first multiplexer 220. By performing differential processing on the signal output by the first multiplexer 220, the noise in the signal output by the first multiplexer 220 can be suppressed, that is, the noise of the signal output by the differential control unit 270 is low, which is beneficial to improve the accuracy of laser ranging. In some embodiments, the differential control unit 270 is configured as a signal conversion circuit structure of single-ended input (that is, only one input end changes with respect to the reference ground) and differential output (that is, the output is composed of two signals with equal amplitude and opposite phase), so as to improve the anti-interference ability, common mode rejection and transmission quality.
[0043] In some embodiments, as shown in Figure 5 The analog circuit 200 further includes a fourth multiplexer 280.
[0044] The fourth multiplexer 280 includes a seventh input end IN7, an eighth input end IN8 and a fourth output end OU4. The seventh input end IN7 is connected with the first output end OU1 to receive one of the second signal S1 and the third signal S3, and the eighth input end IN8 is configured to receive the first signal S1. The differential control unit 270 is connected with the fourth output end OU4, and the differential control unit 270 is configured to perform differential processing on the signal output by the fourth multiplexer 280.
[0045] By configuring the fourth multiplexer 280, it is possible to select, as needed, either the first signal S1 directly from the digital circuit 100 or the signal latched by the second register 210 in the analog circuit 200 (i.e., either the second signal S1 or the third signal S3). For example, when the signal quality of the first signal S1 itself is high, and its noise meets the product parameter requirements, or when the noise meets the product parameter requirements after differential processing, the fourth multiplexer 280 can be configured to select the eighth input terminal IN8 and the fourth output terminal OU4 to directly output the first signal S1 for use by downstream circuits. When the signal-to-noise ratio of the first signal S1 is low, and the noise still exceeds the product parameter requirements even after differential processing, the seventh input terminal IN7 and the fourth output terminal OU4 of the fourth multiplexer 280 can be selected. At this time, it can be further determined whether the second signal S2 can meet the product parameter requirements. If so, the first input terminal IN1 and the first output terminal OU1 of the first multiplexer 220 are selected. If not, the second input terminal IN2 and the first output terminal OU1 of the first multiplexer 220 are selected.
[0046] It should be understood that even though the signal processing system 1000 in the above embodiments includes both the differential control unit 270 and the fourth multiplexer 280, this application is not limited to this. In other embodiments of this application, the differential control unit 270 can also be omitted. In this case, the output signal of the signal processing system 1000 is one of the first signal S1, the second signal S2 and the third signal S3 output by the fourth multiplexer 280.
[0047] It is worth noting that the aforementioned signal processing system 1000 provides multiple signal processing methods, such as directly inputting the first signal S1, directly outputting the second signal S2, outputting the third signal S3 latched by the second register 210 triggered by the first clock signal, outputting the third signal S3 latched by the second register 210 triggered by the second clock signal, and outputting the first signal S1 / S2 / S3 after differential processing. Since even similar products may have individual differences, or when this signal processing system is applied to different products, product manufacturers can weigh the specific product parameter requirements with signal processing efficiency and choose the appropriate signal processing method. Therefore, the signal processing system 1000 has excellent product compatibility.
[0048] In some embodiments, such as Figure 6 As shown, the signal processing system 1000 also includes a controller 300.
[0049] The controller 300 is connected with a control end of the first multiplexer 220 to control the first multiplexer 220 to select one of a first input end IN1 and a second input end IN2 and a first output end OU1. The controller 300 is specifically configured to: when a signal-to-noise ratio of the second signal S2 is greater than or equal to a first preset threshold and jitter of the second signal S2 is less than or equal to a second preset threshold, control the first multiplexer 220 to select the first input end IN1 and the first output end OU1; and when the signal-to-noise ratio of the second signal S2 is less than the first preset threshold and / or the jitter of the second signal S2 is greater than the second preset threshold, control the first multiplexer 220 to select the second input end IN2 and the first output end OU1. The first preset threshold and the second preset threshold are both preset thresholds, and the two thresholds can be set based on an actual application scenario, and the embodiments of the present application do not make specific limitations thereto.
[0050] When the signal-to-noise ratio of the second signal S2 is greater than or equal to the first preset threshold and the jitter of the second signal S2 is less than or equal to the second preset threshold, it indicates that the second signal S2 can already meet the product parameter requirements of the current application scenario, and then the controller 300 controls the first multiplexer 220 to select the first input end IN1 and the first output end OU1 to directly output the second signal S2, which is beneficial to improve the signal processing efficiency. When the signal-to-noise ratio of the second signal S2 is less than the first preset threshold and / or the jitter of the second signal S2 is greater than the second preset threshold, it indicates that the second signal S2 does not meet the product parameter requirements of the current application scenario, and then the third signal S3 obtained by latching the second signal S2 through the second register 210 is outputted to reduce noise and improve accuracy.
[0051] In some embodiments, please continue to refer to Figure 6 The controller 300 is also connected with a second multiplexer 240 in the analog circuit 200.
[0052] The controller 300 is also configured to: when the second input end IN2 and the first output end OU1 of the first multiplexer 220 are selected, the third input end IN3 and the second output end OU2 of the second multiplexer 240 are selected. That is, when the second signal S2 does not meet the product parameter requirements of the current application scenario, not only the third signal S3 obtained by latching the second signal S2 through the second register 210 is outputted, but also the clock signal adopted by the second register 210 is the first clock signal closest to the clock source (i.e., the phase-locked loop 230), and the quality of the clock signal is the best, which is beneficial to reduce noise and improve accuracy.
[0053] In the embodiments of this application, firstly, by setting a second register 210 in the analog circuit 200 to latch the second signal S2, noise carried during the transmission from the digital circuit 100 to the analog circuit 200 can be isolated. Especially when the first signal S1 is a transmit enable signal, the second register 210 can isolate the noise carried during the transmission of the transmit enable signal from the digital circuit 100 to the analog circuit 200, which is beneficial for improving the accuracy of laser ranging. Secondly, a phase-locked loop 230 and a second multiplexer 240 are set to allow selection of the corresponding clock signal as needed. If a better quality clock signal is required, the first clock signal is directly output from the phase-locked loop 230; if easier phase adjustment is required, the second clock signal looping back from the digital circuit 100 to the analog circuit 200 is selected. Furthermore, a delay chain 250, an inverter 260, and a third multiplexer 240 are introduced to achieve a full-phase clock configuration, thereby adjusting the clock phase used for sampling the first signal S1. This ensures that the first signal S1 can be reliably sampled in the register of the analog circuit 200, meeting the setup and hold time requirements. Additionally, a differential control unit 270 is employed to suppress noise in the signal output by the first multiplexer 220, thereby improving anti-interference capability, common-mode rejection, and transmission quality. In addition, a controller 300 is configured to control the first multiplexer 220 and the second multiplexer 240. When the second signal S2 meets the product parameter requirements of the current application scenario, the second signal S2 is directly output to improve efficiency. When the second signal S2 does not meet the product parameter requirements of the current application scenario, the third signal S3 obtained by latching the second signal S2 through the second register 210 is output to reduce noise and improve accuracy. When the second signal S2 does not meet the product parameter requirements of the current application scenario, the clock signal used by the second register 210 is configured to be the first clock signal closest to the clock source (i.e., the phase-locked loop 230) to improve the quality of the clock signal, thereby further reducing noise and improving accuracy.
[0054] This application also provides a lidar chip. The lidar chip includes a transmitting module and a signal processing system 1000 as described in any embodiment of this application.
[0055] The first signal S1 received by the signal processing system 1000 is a transmit enable signal, which the signal processing system 1000 processes and outputs.
[0056] The transmitting module is configured to transmit laser light in response to a transmit enable signal output by the signal processing system. In some embodiments, the transmitting module includes a transmitting array including at least one transmitting element. In some embodiments, the transmitting array is a VCSEL (Vertical-Cavity Surface-Emitting Laser) array and the transmitting element is a VCSEL. In some embodiments, the transmitting array is an EEL (Edge-Emitting Laser) array and the transmitting element is an EEL.
[0057] The embodiments of the present application also provide a laser radar including the laser radar chip 1000 in any of the embodiments of the present application.
[0058] The laser radar can be a mechanical laser radar, a solid-state laser radar, a semi-solid laser radar, etc., and the present application is not limited thereto. The laser radar can be applied to any device requiring laser detection, such as a mobile robot, a ship, or a vehicle, etc. When the laser radar is applied to a vehicle, the laser radar can detect the distance and speed between the vehicle and an obstacle, etc., and the vehicle can detect nearby moving or approaching obstacles, such as a taller vehicle, a roadside static object, a suddenly approaching flying object, etc., so that the vehicle can plan a path to avoid the obstacle according to the detected information, so as to avoid collision with the obstacle. The vehicle can be an autonomous vehicle or a common vehicle, and the present application is not limited thereto.
[0059] The above only describes the embodiments of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation, or direct or indirect application in other related technical fields, is also included in the patent protection scope of the present application.
[0060] The above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; the technical features of the above embodiments or different embodiments can also be combined, and the steps can be implemented in any order. Those skilled in the art should understand that the technical solutions recorded in the above embodiments can still be modified, or some technical features can be replaced by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A signal processing system, characterized in that, include: A digital circuit includes a first register for receiving a first signal, latching the first signal, and then outputting a second signal. as well as An analog circuit includes a second register and a first multiplexer. The second register is used to receive the second signal, latch the second signal, and output a third signal. The first multiplexer includes a first input terminal, a second input terminal, and a first output terminal. The first multiplexer is configured to select one of the first input terminal and the second input terminal to the first output terminal. The first input terminal is used to receive the second signal, and the second input terminal is used to receive the third signal.
2. The signal processing system according to claim 1, characterized in that, The signal processing system is a transmission control system, and the first signal is a transmission enable signal.
3. The signal processing system according to claim 1, characterized in that, The analog circuit includes: A phase-locked loop (PLL) is used to output a first clock signal, and the clock input of the first register is used to receive the first clock signal; and The second multiplexer includes a third input terminal, a fourth input terminal, and a second output terminal. The second multiplexer is configured to select one of the third input terminal and the fourth input terminal to the second output terminal. The third input terminal is used to receive the first clock signal, the fourth input terminal is used to receive the second clock signal, and the second output terminal is connected to the clock input terminal of the second register. The second clock signal is the clock signal that is transmitted from the first clock signal to the digital circuit and looped back from the digital circuit to the analog circuit.
4. The signal processing system according to claim 3, characterized in that, The analog circuit also includes: A delay chain includes multiple delay units, each of which is configured with a tap. The input of the delay chain is connected to the second output. The delay chain is used to delay the signal output by the second multiplexer. An inverter, connected to the output of the delay chain, is used to invert the signal output by the delay chain; and The third multiplexer includes a fifth input, a sixth input, and a third output. The third multiplexer is configured to select one of the fifth input and the sixth input to the third output. The fifth input is connected to the output of the inverter, the sixth input is connected to the output of the delay chain, and the third output is connected to the clock input of the second register.
5. The signal processing system according to claim 1, characterized in that, The analog circuit also includes: A differential control unit, connected to the first output terminal, is used to perform differential processing on the signal output by the first multiplexer.
6. The signal processing system according to claim 1, characterized in that, The analog circuit also includes: A fourth multiplexer includes a seventh input, an eighth input, and a fourth output. The fourth multiplexer is configured to select one of the seventh input and the eighth input to the fourth output. The seventh input is connected to the first output to receive one of the second signal and the third signal, and the eighth input is used to receive the first signal. A differential control unit is connected to the fourth output terminal. The differential control unit is used to perform differential processing on the signal output by the fourth multiplexer.
7. The signal processing system according to any one of claims 1-6, characterized in that, The signal processing system also includes: The controller, connected to the control terminal of the first multiplexer, is used for: When the signal-to-noise ratio of the second signal is greater than or equal to the first preset threshold and the jitter of the second signal is less than or equal to the second preset threshold, the first input terminal and the first output terminal of the first multiplexer are selected. When the signal-to-noise ratio of the second signal is less than the first preset threshold, and / or the jitter of the second signal is greater than the second preset threshold, the second input terminal of the first multiplexer is controlled to be selected from the first output terminal.
8. The signal processing system according to claim 7, characterized in that, The controller is also connected to a second multiplexer in the analog circuit; The controller is also configured to, when controlling the second input terminal of the first multiplexer to be selected from the first output terminal, control the third input terminal of the second multiplexer to be selected from the second output terminal.
9. A lidar chip, characterized in that, include: The signal processing system according to any one of claims 1-8, wherein the signal processing system is a transmission control system, the first signal is a transmission enable signal, and the signal processing system is used to process and output the transmission enable signal; The transmitting module is used to emit laser light in response to a transmit enable signal output by the signal processing system.
10. A lidar, characterized in that, Includes the lidar chip as described in claim 9.