Npu processor architecture-based integrated circuit memory fault management method and system

Abstract

The application belongs to the technical field of integrated circuit design and manufacturing, and particularly relates to an integrated circuit memory fault management method and system based on an NPU processor architecture. First, multi-dimensional detection is carried out specially for the memory size, storage area and handshake protocol effectiveness of a physical address, which changes the status of passive transmission of abnormal signals in the traditional scheme. Then, according to the fault detection result, a control signal is reversely output to intervene in the mapping logic, so as to effectively avoid fault diffusion caused by continuous transmission of abnormal addresses, and when an address abnormality is detected, subsequent physical addresses can be forcibly relocated to a preset safe address area, reliable safety backup is provided, and the running stability is improved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit design and manufacturing technology, specifically relating to a method and system for memory fault management of integrated circuits based on NPU processor architecture. Background Technology

[0002] With the rapid development of artificial intelligence and deep learning, neural network processors (NPUs), as dedicated computing cores for AI chips, need to handle complex scenarios such as large-scale tensor operations and multi-task concurrent inference, placing extremely high demands on the bandwidth, latency, and memory capacity of on-chip data transmission. Network-on-chip (NoC), with its advantages of distributed interconnection, scalable bandwidth, and low-latency transmission, has become the core architecture for interconnecting functional modules such as the NPU's internal computing core cluster, storage units, and interface modules. The AXI (Advanced eXtensible Interface) bus, due to its standardized interface and support for burst transmission and out-of-order access, has become the mainstream interconnection bus protocol between the NPU's NoC and various functional modules.

[0003] In the memory access process of the monolithic NPU NoC architecture, the core link is Virtual Address (VA) → Segment Memory Management Unit (SMMU) → Physical Address (PA) → Target Storage Area. The hardware system includes NoC Core (including AXI Master), SMMU (including smmu_core core submodule and smmu_in_order sorting submodule), target storage area (such as DDR, Local Memory, on-chip cache, etc.) and corresponding Slave devices. Among them, SMMU is the core component for implementing VA to PA address translation. The specific process of traditional memory management is as follows: The NoC Core Master initiates a memory access request and outputs VA, inputting the VA to PA mapping control signals limit_size and base_address into smmu_core; smmu_core determines the address area of ​​VA and completes the VA to PA mapping conversion; the converted PA is processed by a two-to-one data selector, sorted by smmu_in_order according to the receiving order, and finally transmitted to the NoCCluster Slave device to complete data read and write.

[0004] However, the aforementioned traditional NPU memory management methods have significant technical flaws. They cannot actively detect the size, region, and validity of the AXI handshake protocol of the PA, nor can they output fault identifiers. They can only passively receive and transmit abnormal signals. Furthermore, they lack an active fault control mechanism. Even if problems such as address size exceeding limits or region mapping errors occur, they cannot intervene in the mapping logic of smmu_core to adjust limit_size or correct the region identifier of the PA. They can only continuously output abnormal addresses without any active remediation measures. At the same time, since there is no design for safe region switching logic in fault scenarios, when an address becomes abnormal, subsequent PAs cannot be actively redirected to safe address regions. The system lacks a safety fallback capability in fault states and has insufficient risk resistance. Summary of the Invention

[0005] To address the problems in the background technology, this invention provides a method and system for memory fault management based on an NPU processor architecture integrated circuit.

[0006] The technical solution of the present invention is as follows:

[0007] This invention provides a memory fault management method for integrated circuits based on an NPU processor architecture, comprising:

[0008] S1: After outputting the virtual address according to the memory access request, the storage area of ​​the virtual address is determined by combining the memory size limit parameter and base address parameter of the address mapping, and the conversion from virtual address to physical address is completed according to the preset mapping rule; the converted physical address or the original virtual address is selected to be output according to the enable signal, and the address access operation is sorted according to the receiving order.

[0009] S2: Based on the sorted physical address or original virtual address and the corresponding bus signals, perform fault detection as follows:

[0010] If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked.

[0011] If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously.

[0012] S3: Generate corresponding control signals based on fault identification data, transmit them in reverse to S1, adjust the memory size limit parameters of address mapping, and replace the storage area identifier bits of physical addresses.

[0013] Based on the aforementioned NPU processor architecture-based integrated circuit memory fault management method, step S2, which involves detecting and sorting the physical address memory size and the storage area mapped to the physical address, identifying the fault type, and synchronously outputting fault identification data, specifically includes:

[0014] Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag.

[0015] Determine whether the mapped physical address conforms to the preset zone rules. If it does not conform, output a zone access error fault flag.

[0016] Furthermore, S3, specifically, involves adjusting the memory size limit parameters of the address mapping and replacing the storage region identifier bits of the physical address:

[0017] In response to the address size exceeding fault flag, the memory size limit parameter value of the address mapping is adjusted through the memory size limit signal;

[0018] For the fault flag indicating an area access error, the storage area flag of the physical address is directly replaced with the identifier of the preset secure address area.

[0019] Based on the above-described NPU processor architecture integrated circuit memory fault management method, S2 further includes, after detecting a fault signal, using the physical address corresponding to the fault signal as a node, forcibly relocating all physical addresses after the sorting of the physical addresses to a preset safe address region.

[0020] Based on the above-described NPU processor architecture-based integrated circuit memory fault management method, the validity of the bus handshake protocol in step S2 is determined by the fact that if both the valid signal value and the ready signal value corresponding to the protocol are 1, then the protocol is valid.

[0021] Based on the above-described NPU processor architecture integrated circuit memory fault management method, S2 further includes that if the fault detection switch signal value is 0, the sorted physical address or original virtual address and the corresponding bus signal are buffered and then transmitted to the target storage end.

[0022] Based on the above-described NPU processor architecture integrated circuit memory fault management method, S3 further includes: when no fault signal is detected, stopping the reverse transmission of control signals and restoring the original memory size limit parameters and storage area determination results of the address mapping.

[0023] This invention also provides a memory fault management system based on an NPU processor architecture integrated circuit, comprising:

[0024] Address mapping module: After outputting the virtual address according to the memory access request, it determines the storage area of ​​the virtual address by combining the memory size limit parameter and the base address parameter of the address mapping, and completes the conversion from virtual address to physical address according to the preset mapping rules; it selects to output the converted physical address or the original virtual address according to the enable signal, and sorts the address access operations according to the receiving order;

[0025] Fault detection module: Based on the sorted physical address or original virtual address and the corresponding bus signals, fault detection is performed as follows:

[0026] If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked.

[0027] If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously.

[0028] Control module: Generates corresponding control signals based on fault identification data, transmits them in reverse to the address mapping module, adjusts the memory size limit parameters of the address mapping, and replaces the storage area identifier bits of the physical address.

[0029] Based on the aforementioned NPU processor architecture-based integrated circuit memory fault management system, the fault detection module identifies the fault type by detecting and sorting the physical address memory size and the storage area mapped to the physical address, and synchronously outputs fault identification data. Specifically:

[0030] Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag.

[0031] Determine whether the mapped physical address conforms to the preset zone rules. If it does not conform, output a zone access error fault flag.

[0032] Based on the NPU processor architecture-based integrated circuit memory fault management system described above, the fault detection module also includes a safe region orientation module, which, after detecting a fault signal, uses the physical address corresponding to the fault signal as a node, and forces all physical addresses after the sorting of the physical addresses to be relocated to a preset safe address region.

[0033] Beneficial effects

[0034] The memory fault management method provided by this invention first conducts multi-dimensional detection specifically targeting the memory size, storage area, and handshake protocol validity of physical addresses, changing the traditional approach of passively transmitting abnormal signals. Then, based on the fault detection results, it outputs control signals to intervene in the mapping logic, effectively preventing the spread of faults caused by the continuous transmission of abnormal addresses. Furthermore, when an address anomaly is detected, it can forcibly relocate subsequent physical addresses to a preset safe address region, providing a reliable safety net and improving operational stability. Detailed Implementation

[0035] The following examples are intended to illustrate the present invention, and not to further limit the invention.

[0036] Example 1

[0037] This embodiment provides a memory fault management method for integrated circuits based on NPU processor architecture, including:

[0038] S1: After outputting the virtual address according to the memory access request, the storage area of ​​the virtual address is determined by combining the memory size limit parameter and base address parameter of the address mapping, and the conversion from virtual address to physical address is completed according to the preset mapping rule; the converted physical address or the original virtual address is selected to be output according to the enable signal, and the address access operation is sorted according to the receiving order.

[0039] The control signals for mapping virtual addresses to physical addresses are the memory size limit parameter (limit_size) and the base address parameter (base_address). The limit_size allows the virtual address to be divided into two independent address segments at different locations, achieving address space isolation. In subsequent operations, when a virtual address larger than the limit_size is remapped, the limit_size will be subtracted from the corresponding address size. By adjusting the size of the base_address, the entire virtual address segment can be "relocated" in the physical address space.

[0040] During the virtual address to physical address translation phase, the virtual address is first identified by its address region. Based on preset region division rules, the storage region to which the virtual address belongs is determined. Then, the mapping translation from virtual address to corresponding physical address is completed according to preset mapping rules. The translated physical address undergoes a two-way data selection process. If the enable signal value is 1, the translated physical address participates in the sorting; otherwise, the original virtual address participates in the sorting. Access operations are sorted according to the order in which requests are received, and the processed signal is output.

[0041] S2: Based on the sorted physical address or original virtual address and the corresponding bus signals, perform fault detection as follows:

[0042] If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked.

[0043] If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously.

[0044] During the fault detection phase, the fault detection switch signal value is used to make a judgment. If the fault detection switch signal value is 0, the sorted physical address or original virtual address and the corresponding bus signal are buffered and then transmitted to the target storage end.

[0045] If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked.

[0046] Furthermore, the validity of the bus handshake protocol is determined by the condition that if both the valid signal value and the ready signal value corresponding to the protocol are 1, then the protocol is valid.

[0047] Since there are many transaction signals on the AXI (Advanced eXtensible Interface) bus, the transmission of address, data and other signals only takes effect when the valid signal and the ready signal are pulled high at the same time. Therefore, this invention adopts a layered design of first screening valid signals and then carrying out fault detection, which not only ensures the accuracy of fault detection, but also reduces the amount of invalid computation in the fault detection stage, thereby improving the overall performance of NPU memory address transmission and access.

[0048] If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address will be detected, the fault type will be identified, and fault identification data will be output synchronously. The fault identification data will be transmitted synchronously with the input signal.

[0049] Specifically:

[0050] Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size overlimit (size_overlimit) fault flag.

[0051] Determine whether the mapped physical address conforms to the preset region rules. If it does not conform, output a region access fault (region_access_fault) flag.

[0052] In addition, after a fault signal is detected, all physical addresses that are sorted after the physical address corresponding to the fault signal are forcibly relocated to a preset safe address area, using the physical address corresponding to the fault signal as the node.

[0053] The preset secure address region is specifically used to store emergency data for fault handling. When an address anomaly is detected, subsequent physical addresses are directed to this secure address region to prevent abnormal addresses from accessing the computing core cluster of the neural network processor (NPU) and to protect the hardware security of the integrated circuit.

[0054] This invention designs a safe zone orientation mechanism for fault scenarios. When an address anomaly is detected, it can forcibly relocate subsequent physical addresses to a preset safe address zone, providing a reliable safety fallback and improving operational stability.

[0055] In the fault detection phase, this invention performs multi-dimensional detection on the memory size, storage area, and handshake protocol validity of the physical address. It can accurately identify abnormal scenarios such as address overrun, region mapping error, and protocol handshake failure, and output clear fault identifiers, making fault detection more accurate and facilitating error discovery and debugging.

[0056] S3: Generate corresponding control signals based on fault identification data, transmit them in reverse to S1, adjust the memory size limit parameters of address mapping, and replace the storage area identifier bits of physical addresses.

[0057] During the control phase, in response to the address size exceeding the limit fault, the memory size limit parameter value of the address mapping is adjusted through the memory size limit signal to control the size of subsequent physical addresses.

[0058] For fault indicators related to area access errors, the storage area identifier of the physical address is directly replaced with the identifier of a preset secure address area, thereby enabling fallback recovery after a fault.

[0059] In addition, it also includes: when no fault signal is detected, stopping the reverse transmission control signal and restoring the original memory size limit parameters and storage area determination results of the address mapping.

[0060] During the control phase, this invention uses the fault detection results to output a reverse control signal to intervene in the mapping logic. By adjusting the memory size limit parameter, it controls the subsequent physical address size and switches the replacement region identifier to a safe region, effectively preventing the spread of faults caused by the continuous transmission of abnormal addresses.

[0061] Example 2

[0062] Based on Embodiment 1, this embodiment provides a memory fault management system based on an NPU processor architecture integrated circuit. This system is compatible with a unified Network on Chip (NoC) architecture and the AXI (Advanced eXtensible Interface) bus protocol, and includes:

[0063] Address mapping module: After outputting the virtual address according to the memory access request, it determines the storage area of ​​the virtual address by combining the memory size limit parameter and the base address parameter of the address mapping, and completes the conversion from virtual address to physical address according to the preset mapping rules; it selects to output the converted physical address or the original virtual address according to the enable signal, and sorts the address access operations according to the receiving order.

[0064] Specifically, during the operation of the address mapping module, the following steps are taken: the master device in the NoC core module initiates a memory access request and outputs a virtual address. Control signals for the virtual-to-physical address mapping, namely the memory size limit parameter (limit_size) and base address parameter (base_address) for each address segment, are input to the fragment memory management unit core module. The fragment memory management unit core module first determines the address region of the virtual address based on preset region division rules, then completes the mapping conversion from virtual address to the corresponding physical address according to preset mapping rules. The converted physical address passes through a two-to-one data selector. If the corresponding fragment memory management unit core module's enable signal value is 1, the converted physical address is sent to the fragment memory management unit sorting module; otherwise, the original virtual address enters the fragment memory management unit sorting module. The fragment memory management unit sorting module sorts the access operations according to the order in which the requests are received, and the processed signal is output from the fragment memory management unit.

[0065] Fault detection module: Based on the sorted physical address or original virtual address and the corresponding bus signals, fault detection is performed as follows:

[0066] If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked.

[0067] If the protocol is valid, the sorted physical address memory size and the storage area mapped by the physical address are detected, the fault type is identified, and fault identification data is output synchronously.

[0068] In practical implementation, the fault detection module is equipped with a fault detection switch, which, together with the selector within the module, enables two operating modes:

[0069] If the fault detection switch signal value is 0, the sorted physical address or original virtual address and the corresponding bus signal will pass directly through the fault detection module and enter the first-in-first-out (FIFO) module buffer to avoid timing errors, and finally be transmitted to the target storage end.

[0070] If the fault detection switch signal value is 1, the validity of the AXI bus handshake protocol is checked first. If the protocol is valid, the memory size and storage region information of the input physical address are further checked. If the physical address memory size exceeds the memory size limit parameter, an address size overlimit (size_overlimit) fault flag is output; if the mapped physical address is in the wrong region, a region access fault (region_access_fault) fault flag is output, and these two types of fault flags are transmitted synchronously with the input signal.

[0071] The fault detection module also includes a safe area orientation module, which, after detecting a fault signal, uses the physical address corresponding to the fault signal as a node and forces all physical addresses after the sorted physical address to be relocated to a preset safe address area.

[0072] The preset secure address region is the on-chip static random access memory (SRAM) within the NPU integrated circuit, which is specifically used to store emergency data for fault handling. When an address anomaly is detected, the fault detection module uses hardware circuitry to redirect the physical address to this SRAM region, preventing the abnormal address from accessing the NPU's computing core cluster and protecting the hardware security of the integrated circuit.

[0073] Control module: Generates corresponding control signals based on fault identification data, transmits them in reverse to the address mapping module, adjusts the memory size limit parameters of the address mapping, and replaces the storage area identifier bits of the physical address.

[0074] The output signal from the fault detection module enters the control module. The control module generates a corresponding control signal based on the fault identification data, and transmits it in reverse to the core module of the segment memory management unit through a dedicated 2-to-1 multiplexer.

[0075] Among them, size_overlimit modulates the limit_size signal of the fragment memory management unit core module, dynamically adjusting its value to control the size of subsequent physical addresses; region_access_fault replaces the region identifier bit of the physical address in the fragment memory management unit core module with the identifier of the preset safe address region, thereby realizing a fallback recovery after a failure.

[0076] The memory fault management system provided by this invention consists of a fault detection logic circuit, a secure area switching circuit, a FIFO module, and a control signal driving circuit. The fault detection logic circuit uses combinational logic circuits to implement AXI protocol validity detection, and the secure area switching circuit uses timing logic circuits to generate control signals for the core module of the segment memory management unit. Together with the FIFO module, it avoids timing errors. While achieving fault management, it ensures low latency in address transmission and can be directly integrated into the on-chip storage control area of ​​the NPU chip.

[0077] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should be included within the scope of protection of the present invention.

Claims

1. A memory fault management method based on an NPU processor architecture integrated circuit, characterized in that, include: S1: After outputting the virtual address according to the memory access request, the storage area of ​​the virtual address is determined by combining the memory size limit parameter and base address parameter of the address mapping, and the conversion from virtual address to physical address is completed according to the preset mapping rule; the converted physical address or the original virtual address is selected to be output according to the enable signal, and the address access operation is sorted according to the receiving order. S2: Based on the sorted physical address or original virtual address and the corresponding bus signals, perform fault detection as follows: If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked. If the protocol is valid, the sorted physical address memory size and the storage area mapped to the physical address are checked, the fault type is identified, and fault identification data is output synchronously, specifically: Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag. Determine whether the mapped physical address conforms to the preset zone rules. If it violates the rules, output a zone access error fault flag. S2 also includes, after a fault signal is detected, using the physical address corresponding to the fault signal as a node, all physical addresses after the sorting of the physical address are forcibly relocated to a preset safe address area; S3: Generates corresponding control signals based on the fault identification data, transmits them in reverse to S1, adjusts the memory size limit parameters of the address mapping, and replaces the storage area identifier bits of the physical address, specifically: In response to the address size exceeding fault flag, the memory size limit parameter value of the address mapping is adjusted through the memory size limit signal; For the fault flag indicating an area access error, the storage area flag of the physical address is directly replaced with the identifier of the preset secure address area.

2. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, The validity of the bus handshake protocol described in S2 is determined by the fact that if both the valid signal value and the ready signal value corresponding to the protocol are 1, then the protocol is valid.

3. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S2 also includes that if the fault detection switch signal value is 0, the sorted physical address or original virtual address and the associated bus signal are buffered and then transmitted to the target storage end.

4. The method for memory fault management based on NPU processor architecture integrated circuits according to claim 1, characterized in that, S3 also includes: when no fault signal is detected, stopping the reverse transmission of control signals and restoring the original memory size limit parameters and storage area determination results of the address mapping.

5. A memory fault management system based on an NPU processor architecture integrated circuit, characterized in that, include: Address mapping module: After outputting the virtual address according to the memory access request, it determines the storage area of ​​the virtual address by combining the memory size limit parameter and the base address parameter of the address mapping, and completes the conversion from virtual address to physical address according to the preset mapping rules; it selects to output the converted physical address or the original virtual address according to the enable signal, and sorts the address access operations according to the receiving order; Fault detection module: Based on the sorted physical address or original virtual address and the corresponding bus signals, fault detection is performed as follows: If the fault detection switch signal value is 1, then the validity of the bus handshake protocol is checked. If the protocol is valid, the sorted physical address memory size and the storage area mapped to the physical address are checked, the fault type is identified, and fault identification data is output synchronously, specifically: Determine whether the size of the sorted physical addresses exceeds the memory size limit parameter. If it does, output an address size exceedance fault flag. Determine whether the mapped physical address conforms to the preset zone rules. If it violates the rules, output a zone access error fault flag. The fault detection module also includes a safe area orientation module, which, after detecting a fault signal, uses the physical address corresponding to the fault signal as a node and forces all physical addresses after the sorted physical address to be relocated to a preset safe address area. Control module: Generates corresponding control signals based on fault identification data, transmits them in reverse to the address mapping module, adjusts the memory size limit parameters of the address mapping, and replaces the storage area identifier bits of the physical address. Specifically: In response to the address size exceeding fault flag, the memory size limit parameter value of the address mapping is adjusted through the memory size limit signal; For the fault flag indicating an area access error, the storage area flag of the physical address is directly replaced with the identifier of the preset secure address area.