Chip and one-time information storage method thereof

Abstract

The invention provides a chip and a primary information storage method thereof, which can store a second function and a first function corresponding to secondary information of primary information by using an execution-only area of the chip, thereby utilizing the characteristic that the execution-only area cannot be read and written and can only fetch execution codes. Special primary information such as a key and a watermark of the chip cannot be changed or directly read, so that the storage of the primary information becomes safer and more reliable. Furthermore, the complete primary information is processed into multiple pieces of secondary information, the secondary information is dispersedly stored in the execution-only area through the first functions in one-to-one correspondence with the secondary information, the second functions can be called only through the calling interface, and then after all the first functions are called and all the corresponding secondary information is analyzed, the secondary information is stored in the execution-only area in a scattered mode. Therefore, the security of the primary information is further improved.

Description

Technical Field

[0001] This invention relates to the field of one-time information storage technology, and in particular to a chip and a method for one-time information storage. Background Technology

[0002] Currently, MCU (Microcontroller Unit) chips are finding increasingly wider applications, making secure boot of MCU chips even more crucial. Secure boot of an MCU chip is a multi-layered process designed to ensure the security of the system startup process and prevent malware and unauthorized code execution.

[0003] Currently, secure boot schemes for MCU chips all require public key verification, and the protection level of the public key during secure boot is required to be high. It is necessary to ensure that the public key (or the public key hash value calculated based on the public key) cannot be changed. Therefore, the public key is often stored in a one-time write area such as EFUSE (electronic fuse) or OTP (One-Time Programmable) area.

[0004] However, not all MCU chips have such a region. Therefore, in MCU chips that do not have an EFUSE or OTP region, how to reliably store the public key becomes a problem that must be taken seriously.

[0005] The aforementioned problems also exist in the storage of other important primary information of the chip (such as other keys or the need to add special watermarks to specific libraries and code segments). Summary of the Invention

[0006] The purpose of this invention is to provide a chip and a method for storing primary information thereof, which can safely and reliably store primary information requiring a high level of protection.

[0007] To achieve the above objectives, the present invention provides a chip comprising:

[0008] The execution-only region stores a first function and a second function. The first function, after being called, returns an execution address associated with secondary information of primary information. The second function is used to call the first function and parse the secondary information from the execution address returned by the first function. Then, the primary information is obtained based on the parsed secondary information. The execution-only region cannot be read or written after the execution-only function is enabled. Only instruction fetching and code execution are allowed.

[0009] The calling interface is used to call the second function from outside the execution-only region, in order to further call the first function.

[0010] Optionally, the primary information includes at least one of a key and a watermark.

[0011] Optionally, the key is a public key required for secure boot of the chip. The chip also includes a secure boot code area, which stores the image header, image, image hash value, digital signature, and hash value of the public key of the secure boot code file. The digital signature is generated by signing the secure boot code file with a private key, and the private key and the public key form a key pair.

[0012] Optionally, the execution-only region can be set with the start and end addresses by the corresponding fields in the option byte of the chip; or, the execution-only region can be set by configuring the corresponding registers in the EFUSE or OTP of the chip; or, the execution-only region can be set by a programming tool.

[0013] Optionally, the first function and the second function are stored in the execution-only region as binary files.

[0014] Optionally, the information of the calling interface includes the execution address and declaration information of the second function.

[0015] Optionally, the second function is also used to verify the identity of the caller after it is invoked.

[0016] Optionally, the calling interface further includes a link register, and the second function verifies the caller's identity by checking the value of the link register.

[0017] Optionally, the primary information is processed into multiple secondary information. The execution-only region stores the primary information in a distributed manner by storing the first function that corresponds one-to-one with each of the secondary information. The second function is used to call all the first functions to combine all the parsed secondary information to obtain the complete primary information.

[0018] Optionally, the length of the primary information is at least two bytes, and the primary information is extracted byte by byte into multiple secondary information.

[0019] Based on the same inventive concept, the present invention also provides a method for one-time information storage of a chip as described in the present invention, which includes the following steps:

[0020] Obtain secondary information corresponding to primary information;

[0021] The execution address of the first function is determined based on the secondary information, and the execution address is associated with the secondary information. The first function is used to return the execution address after being called.

[0022] A second function is generated, which is used to call the first function and parse the secondary information from the execution address of the first function;

[0023] Load the first function and the second function into the chip's execution-only region;

[0024] Enable the execute-only function for the execute-only region, so that the execute-only region cannot be read or written, and can only fetch and execute code;

[0025] The information of the calling interface of the second function is retained externally. The calling interface is used to call the second function from outside the execution-only region in order to further call the first function and parse out the secondary information, and finally obtain the primary information.

[0026] Optionally, the length of the primary information is at least two bytes, and in the step of obtaining the secondary information corresponding to the primary information, multiple pieces of the secondary information of the primary information are obtained according to the bytes; then, when the second function is called through the calling interface, the second function calls all the first functions to obtain all the secondary information, thereby obtaining the complete primary information.

[0027] Optionally, in the step of loading the first function and the second function into the executable-only region of the chip, the first function and the second function are first compiled into binary files, and then the binary files are loaded into the executable-only region.

[0028] Optionally, when the second function is called through the calling interface, the second function first verifies the caller's identity by checking the value of the link register.

[0029] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0030] 1. By using an execution-only region to store the first function corresponding to the secondary information of the second function and the primary information, the characteristics of the execution-only region, which cannot be read or written but can only fetch and execute code, are utilized to ensure that the chip's key, watermark, and other special primary information requiring a high level of protection cannot be modified or directly read, thereby making the storage of this primary information more secure and reliable.

[0031] 2. Complete primary information is processed into multiple secondary information. These secondary information are stored in a distributed manner in the execution-only area through corresponding first functions. The second functions can only be called through the interface. Only after calling all the first functions and parsing all the corresponding secondary information can the complete primary information be combined, thereby further improving the security and reliability of primary information storage. Attached Figure Description

[0032] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0033] Figure 1 This is a schematic diagram of the chip architecture according to an embodiment of the present invention.

[0034] Figure 2 This is a schematic diagram of an application example architecture of a chip according to an embodiment of the present invention.

[0035] Figure 3 yes Figure 2 The diagram shows the chip's one-time information storage method and secure boot process. Detailed Implementation

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0037] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0038] Please refer to Figure 1One embodiment of the present invention provides a chip, which can be an MCU chip or any other suitable chip, including an execute-only dedicated code read protection (DCRP). This DCRP, once enabled for execute-only functionality, cannot be read or written; it only allows instruction fetching and code execution. The DCRP can be a specific area of ​​any memory within the chip, such as EFUSE (electronic fuse), OTP (One-Time Programmable Memory), SRAM (Static Random Access Memory), ROM (Read-Only Memory), or flash memory (e.g., embedded flash memory EFASH or SOI flash).

[0039] In one example, the executable-only region is a specific area of ​​flash memory in an MCU chip (which can be a system-on-a-chip). The start and end addresses of this specific region are set by the corresponding fields (e.g., DCRP_AREA_START and DCRP_AREA_END) in the MCU chip's option byte opt. Furthermore, the executable-only region can be read-write protected by configuring the corresponding bits in the option byte. When the read-write protection function is enabled, the executable-only region cannot be read or written, and only instruction fetching and code execution are allowed.

[0040] In another example, the execution-only region is a specific area of ​​the EFUSE (electronic fuse) within the chip, which is set via the EFUSE_MCU_RSV register in EFUSE. The EFUSE setting has a higher priority than the option byte setting.

[0041] In yet another example, the execution-only region is set in the chip using a programming tool.

[0042] It should be understood that in other embodiments of the present invention, better protection can be achieved by further utilizing other protection functions of the chip, such as write protection, MPU (Memory Protect Unit) protection, security protection, etc.

[0043] In this embodiment, the execution-only region DCRP stores the first function SF and the second function GF. Optionally, the first function SF and the second function GF are stored in the execution-only region DCRP in the form of binary files.

[0044] The first function, SF, is a special executable function that, upon being called, returns an execution address associated with secondary information related to the primary information. The second function, GF, is an interface function that calls the first function SF and parses the corresponding secondary information from the execution address returned by SF, thereby obtaining the primary information based on the parsed secondary information. The primary information may include at least one of special information such as a key and a watermark.

[0045] The calling interface is used to call the second function GF from outside the execution-only region DCRP, which in turn calls the first function SF, ultimately obtaining information. The information from the calling interface includes the execution address and declaration information of the second function GF, thus eliminating the need for the calling interface of the first function SF to be exposed outside the execution-only region DCRP.

[0046] Clearly, by calling the second function GF through the interface, the user can obtain information once. During this process, the user cannot write to or read the execution-only region DCRP, thus ensuring the security of the information once.

[0047] Optionally, the second function GF is also used to verify the identity of the caller after it is called. For example, the calling interface also includes a link register (LR, not shown). The link register LR stores the return address of the second function GF, that is, the execution address of the second function GF. After the second function GF is called, it can verify the identity of the caller by checking the value of the link register, that is, use the value of the link register to check the compliance of calling the second function GF.

[0048] Alternatively, please refer to Figure 1 The primary information that the chip needs to store is processed, analyzed, adapted, segmented, recombined, or comprehensively summarized using any suitable means, resulting in n+1 secondary information pieces, where n ≥ 1 and is an integer. These n+1 secondary information pieces must be combined to obtain the complete primary information. The Execution Region Requested (DCRP) stores the primary information in a distributed manner by storing the first function SF (i.e., SF0~SFn) corresponding one-to-one with each secondary information piece of the primary information. When the second function GF is called through the interface, the second function GF calls the first function SF (i.e., all first functions SF0~SFn) corresponding to all the secondary information of the primary information, thereby parsing out all the secondary information. Only by combining all the parsed secondary information can the complete primary information be obtained.

[0049] As an example, please refer to Figure 2 and Figure 3The length of a primary message is at least two bytes. This primary message is extracted byte by byte into n+1 secondary messages K[0]~K[n], which in turn generate n+1 schematic functions SF0~SFn. For example, if the primary message (which can be a key) is 0XAABBCCDDEE, it has a total of 5 bytes. Extracting the primary message byte by byte, we can obtain the following secondary messages: K[0]=0XEE, K[1]=0XDD, K[2]=0XCC, K[3]=0XBB, K[4]=0XAA. Therefore, based on the obtained K[0]~K[4] values, the execution addresses of the five first functions SF1~SF4 can be determined. For example, the execution address of the first first function SF0 can be 0x0800K[0]00 (i.e. 0x0800EE00), the execution address of the second second function SF1 can be 0x0801K[1]00 (i.e. 0x0801DD00), and the execution address of the third second function SF2 can be 0x0802K[2]00 (i.e. 0x0802CC00), and so on. In this way, the address of each special function will contain secondary information. The execution address of the second function GF has no special requirements. When it calls the first first function SF0, it can parse the secondary information K[0] as 0XEE from the execution address 0x0800EE00 of the first first function SF0. ​​In this way, K[0]~K[4] can be obtained, and K[0]~K[4] can be combined to obtain the primary information 0XAABBCCDDEE.

[0050] In addition, please combine Figure 1 This embodiment also provides a method for storing information in a chip once, which includes the following steps:

[0051] First, obtain the secondary information corresponding to the primary information;

[0052] Next, the execution address of the first function SF is determined based on the obtained secondary information. The execution address of the first function SF is associated with the corresponding secondary information. The first function SF is used to return the corresponding execution address after being called.

[0053] Then, a second function GF is generated, which is used to call the first function SF and parse the corresponding secondary information from the execution address of the first function SF;

[0054] Then, the first function SF and the second function GF are loaded into the chip's execution-only region DCRP;

[0055] Next, enable the execute-only function for the execute-only region DCRP, so that the execute-only region DCRP cannot be read or written, and can only fetch and execute code;

[0056] Then, the information of the calling interface of the second function GF is retained externally. This calling interface is used to call the second function GF from outside the execution region DCRP to further call the first function SF and parse out the secondary information, and finally obtain the required primary information.

[0057] In summary, the chip and its method for storing primary information in this embodiment can use an execution-only region to store the second function and the first function corresponding to the secondary information of the primary information. By leveraging the characteristic that the execution-only region cannot be read or written, but can only fetch and execute code, special primary information such as the chip's key and watermark cannot be altered or directly read, thus making the storage of this primary information more secure and reliable. Furthermore, the complete primary information is processed into multiple secondary information pieces. These secondary information pieces are distributed and stored in the execution-only region through corresponding first functions. The second functions can only be invoked through an interface. Only after calling all the first functions and parsing all the corresponding secondary information can the complete primary information be reconstructed, thereby further improving the security and reliability of storing primary information requiring a high level of protection, such as keys.

[0058] The following is combined Figure 2 and Figure 3 The invention uses an MCU chip as a specific application example and a primary information key required for the secure startup of the MCU chip as an example to illustrate the chip and its primary information protection method in detail.

[0059] The public key required for secure boot of an MCU chip is typically at least 2 bytes long, for example, n bytes. Additionally, please refer to... Figure 3 The MCU chip also includes a Main Bootloader (MBL) for secure boot. The MBL stores the image header, image, image hash, digital signature, and public key hash of the secure boot code file. The secure boot code file (or code) can support ECDSA (e.g., asymmetric encryption algorithm) for signature verification and can be user-defined secure boot code. The digital signature is generated using a private key through any suitable tool, such as the GigaDevice tool or a user-developed signature tool, and can support ECDSA. This private key and the public key required for secure boot of the MCU chip form a key pair. This private key and public key can be a root of trust (RoT) key pair generated by the developer using the GigaDevice tool. Optionally, the MBL also stores the MBL public key, which is required for the startup or operation of applications other than the secure bootloader within the chip.

[0060] It should be understood that the MCU chip contains not only the Security Boot Record (MBL), Execution-Only Region (DCRP), and Call Interface (interface) mentioned above, but also any other required hardware and software, such as a CPU core, ROM, SRAM, EFUSE, TRNG engine, CAU engine, HASH engine, and the data registers required by these engines, etc., which will not be elaborated here.

[0061] Please refer to Figure 2 and Figure 3 This application example provides a method for storing the public key of an MCU chip, which includes the following steps:

[0062] S1. Obtain the n+1 values ​​K[x] = K[0] ~ K[n] (i.e. n+1 secondary information) corresponding to the public key (i.e., primary information) according to the bytes. For example, the public key is 0XAABBCCDDEE, which has a total of 5 bytes, i.e., n = 4. The value range of x in K[x] is 0 to 4. One way to obtain the n+1 K[x] results is as follows: K[0] = 0XEE, K[1] = 0XDD, K[2] = 0XCC, K[3] = 0XBB, K[4] = 0XAA.

[0063] S2. Based on the obtained K[x] values ​​(i.e., K[0]~K[n]), determine the execution address of the first function SF. For example, the execution address of the first function SF0 can be 0x0800K[0]00 (i.e., x=0, 0x0800K[0]00=0x0800EE00), and the execution address of the second function SF1 can be 0x0801K[1]00 (i.e., x=1, 0x0801K[1]00=0x0801K[1]00=0x0801K[1]00). 0801DD00), the execution address of the third first function SF2 can be 0x0802K[2]00 (i.e., x = 2, 0x0802K[2]00 = 0x0802CC00), and so on, the execution address of the (n+1)th first function SFn can be 0x080nK[n]00 (i.e., x = n), so that the execution address of each first function SF0~SFn will contain the public key information (i.e., the corresponding K[x]).

[0064] S3. Generate the code of the first function SF based on the execution address of each first function SF. The function of each first function SF is to return the execution address of the first function SF after it is called. The execution address will include the public key information.

[0065] S4. Generate the code of the second function GF based on the execution address of the second function GF. There are no special requirements for the execution address of the second function GF. The function of the second function GF is to call all the first functions SF0 to SFn and parse the public key information K[x] from the execution addresses of each first function SF0 to SFn. For example, if the execution address of the first first function SF0 is 0x0800EE00, then the parsed public key information K[0] is 0XEE. Thus, by combining the parsed K[0] to K[n], the complete information of the public key is obtained.

[0066] S5 compiles each of the first functions SF and the second function GF into binary files and loads them into the chip's execution-only region DCRP.

[0067] S6 enables the execution-only function for the execution-only region DCRP, so that the regions where the first function SF and the second function GF are located will be neither read nor written, and can only execute the code in that region;

[0068] S7 only retains the information of the calling interface of the second function GF to the outside world. The information of the calling interface includes the execution address of the second function GF and the declaration information of the second function GF. The calling interfaces of each first function SF will not be exposed to the outside world.

[0069] This completes the secure storage of the MCU chip's public key.

[0070] Please refer to further information. Figure 2 and Figure 3 After the public key is saved according to the above public key saving method, when the MCU chip enters the secure boot process, it includes the following steps:

[0071] S8, the user calls the second function GF through the interface to call all the first functions SF, thereby resolving all values ​​K[0] to K[n] of the public key. During this process, the user cannot write or read the execution-only region DCRP. In this step, after the second function GF is called and before the second function GF calls the first first function SF, the second function GF first verifies the caller's identity by checking the value of the link register. Only after the caller's identity is verified as valid will the first first function SF be called.

[0072] S9. Parse all the combinations of public key values ​​K[0]~K[n] to obtain the complete public key. Then, calculate the hash value of the public key based on the complete public key. Compare the calculated public key hash value with the public key hash value stored in the secure boot code area MBL to verify the correctness of the obtained public key.

[0073] S10, if the public key verification is successful, it can be used to decrypt the file information in the Secure Boot Code Block (MBL) to verify the integrity and authenticity of the secure boot code in the MBL, thereby completing the secure boot of the MCU chip. This process includes, for example, decrypting the digital signature stored in the MBL using the public key and comparing the decrypted digital signature with the digital signature stored in the MBL to verify the correctness of the digital signature.

[0074] Obviously, in this application example, the value of the public key is stored in the execution-only region of the MCU chip, and the public key is converted into multiple values ​​K[0]~K[n] and stored in the execution address of the first function in the execution-only region. The execution-only region can be read and written during runtime, and information can only be obtained by calling the interface, thus making the storage of the public key very secure.

[0075] It should be understood that while the above application example describes public key storage, in other application examples, the public key can be replaced with other important primary information to achieve secure storage of that primary information. For example, the public key in the above application example could be replaced with watermark information, which needs to be added to a specific library and / or code segment. This watermark information can be a string of characters composed of numbers and letters, thereby achieving secure storage of the watermark information. Further details will not be elaborated upon here.

[0076] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A chip, characterized in that, include: The execution-only region stores a first function and a second function. The first function, after being called, returns an execution address associated with secondary information of primary information. The second function is used to call the first function and parse the secondary information from the execution address returned by the first function. Then, the primary information is obtained based on the parsed secondary information. The execution-only region cannot be read or written after the execution-only function is enabled. Only instruction fetching and code execution are allowed. The calling interface is used to call the second function from outside the execution-only region, in order to further call the first function.

2. The chip as described in claim 1, characterized in that, The information includes at least one of a key and a watermark.

3. The chip as described in claim 2, characterized in that, The key is the public key required for secure boot of the chip. The chip also includes a secure boot code area, which stores the image header, image, image hash value, digital signature, and hash value of the public key of the secure boot code file. The digital signature is generated by signing the secure boot code file with a private key, and the private key and the public key form a key pair.

4. The chip as described in claim 1, characterized in that, The executable region is configured with its start and end addresses by setting the corresponding fields in the chip's option byte; or, the executable region is configured by configuring the corresponding registers in the chip's EFUSE or OTP; or, the executable region is configured by a programming tool.

5. The chip as described in claim 1, characterized in that, The first function and the second function are stored in the execution-only region as binary files.

6. The chip as described in claim 1, characterized in that, The information of the calling interface includes the execution address and declaration information of the second function.

7. The chip as described in claim 1, characterized in that, The second function is also used to verify the identity of the caller after it is invoked.

8. The chip as described in claim 7, characterized in that, The calling interface also includes a link register, and the second function verifies the caller's identity by checking the value of the link register.

9. The chip as described in any one of claims 1-8, characterized in that, The primary information is processed into multiple secondary information. The execution-only region stores the primary information in a distributed manner by storing the first function that corresponds one-to-one with each of the secondary information. The second function is used to call all the first functions to combine all the parsed secondary information to obtain the complete primary information.

10. The chip as described in claim 9, characterized in that, The length of the primary information is at least two bytes, and the primary information is extracted into multiple secondary information by bytes.

11. A method for storing information in a chip as described in any one of claims 1-10, characterized in that, Includes the following steps: Obtain secondary information corresponding to primary information; The execution address of the first function is determined based on the secondary information, and the execution address is associated with the secondary information. The first function is used to return the execution address after being called. A second function is generated, which is used to call the first function and parse the secondary information from the execution address of the first function; Load the first function and the second function into the chip's execution-only region; Enable the execute-only function for the execute-only region, so that the execute-only region cannot be read or written, and can only fetch and execute code; The information of the calling interface of the second function is retained externally. The calling interface is used to call the second function from outside the execution-only region in order to further call the first function and parse out the secondary information, and finally obtain the primary information.

12. The one-time information storage method as described in claim 11, characterized in that, The length of the primary information is at least two bytes, and in the step of obtaining the secondary information corresponding to the primary information, multiple pieces of the secondary information of the primary information are obtained according to the bytes; then, when the second function is called through the calling interface, the second function calls all the first functions to obtain all the secondary information, thereby obtaining the complete primary information.

13. The one-time information storage method as described in claim 11, characterized in that, In the step of loading the first function and the second function into the executable-only region of the chip, the first function and the second function are first compiled into binary files, and then the binary files are loaded into the executable-only region.

14. The one-time information storage method as described in claim 11, characterized in that, When the second function is called through the aforementioned calling interface, the second function first verifies the caller's identity by checking the value of the link register.

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