Display device

Abstract

A display device according to an embodiment is disclosed. The display device includes: a pixel array in which a plurality of data lines, a plurality of gate lines, and a plurality of pixel circuits are arranged; a data driver configured to output a data voltage to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate a common gate signal.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2024-0129862, filed on September 25, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to display devices. Background Technology

[0004] As the market for future vehicles, such as electric vehicles and autonomous vehicles, expands, the demand for vehicle display devices is rapidly increasing. Among vehicle display devices, display panels for organic light-emitting diode (OLED) displays are attracting attention.

[0005] Organic light-emitting display devices include self-emissive organic light-emitting diodes (hereinafter referred to as "OLEDs"), and have advantages such as fast response speed, good luminous efficiency and brightness, and wide viewing angle. OLEDs have a fast response speed, are excellent in terms of luminous efficiency, brightness and viewing angle, and provide excellent contrast and color reproduction because they can represent black grayscale with perfect black.

[0006] Because the display panels of organic light-emitting diode (OLED) displays can be flexibly bent, curved surfaces can be easily achieved. Due to these advantages, the market share of OLED displays in the automotive display market is rapidly increasing. Summary of the Invention

[0007] The vehicle display device includes a display panel comprising multiple pixels and a driver configured to output drive signals for driving the display panel. The driver includes a gate driver configured to supply gate signals such as scan signals and light emission control signals to the display panel, and a data driver configured to supply data signals to the display panel.

[0008] When the gate driver circuitry is located in the non-display area, the bezel of the display panel increases. In contrast, when the gate driver circuitry is located between pixels in the display area, the bezel decreases, but the pixel design margin decreases. Therefore, a solution is needed that can ensure pixel design margin while achieving a narrow bezel for the display panel.

[0009] This disclosure aims to address all the necessities and problems described above.

[0010] This disclosure provides a display device capable of achieving a narrow bezel.

[0011] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0012] A display device according to embodiments of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged; a data driver configured to output data voltages to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a timing controller configured to generate the common gate signal.

[0013] A display device according to embodiments of the present disclosure may include: a pixel array in which a plurality of data lines, a plurality of gate lines and a plurality of pixel circuits are arranged; a data driver configured to output data voltages to the plurality of data lines; a gate driver configured to sequentially output gate signals to the plurality of gate lines; a common line configured to simultaneously apply a common gate signal to the plurality of gate lines; and a power supply configured to generate the common gate signal.

[0014] This disclosure achieves a narrow bezel for the display panel and ensures pixel design margin by omitting at least one of a plurality of gate drivers that generate gate signals and by simultaneously applying a predetermined common gate signal to all pixels via a common line.

[0015] This disclosure can improve image quality degradation that may be caused by changes in pixel drive voltage by simultaneously applying a predetermined common gate signal to all pixels via a common line.

[0016] This disclosure enables low-power driving because it reduces power consumption.

[0017] The effects of this specification are not limited to those mentioned above, and those skilled in the art will clearly understand from the following description and the appended claims other effects not mentioned. Attached Figure Description

[0018] The above and other objects, features and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0019] Figures 1A to 1C This is a block diagram illustrating a display device according to an embodiment of the present disclosure;

[0020] Figures 2A to 2B This is a diagram illustrating the configuration of a gate driver according to an embodiment of the present disclosure;

[0021] Figures 3A to 3B This is a diagram illustrating a first gate driver according to an embodiment of the present disclosure;

[0022] Figures 4A to 4B This is a diagram showing the wiring arranged in a gate driver according to an embodiment;

[0023] Figure 5 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure;

[0024] Figure 6 It shows that it is applied to Figure 5 A diagram showing the timing of the gate signal drive in the pixel circuit;

[0025] Figure 7 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure;

[0026] Figures 8A to 8B It shows that it is applied to Figure 7 A diagram showing the timing of the gate signal drive in the pixel circuit;

[0027] Figures 9A to 9G This is a diagram illustrating the output principle of the gate signal according to an embodiment of the present disclosure;

[0028] Figures 10 to 15 This is a diagram illustrating the principle of gate signal application according to an embodiment; and

[0029] Figures 16 to 17 This is a diagram illustrating the improvement in FFR performance according to an embodiment of the present disclosure. Detailed Implementation

[0030] The advantages and features of this specification, as well as methods of implementing them, will become apparent from the preferred embodiments described in detail with reference to the accompanying drawings. However, this specification is not limited to the embodiments described below, and may be implemented in different forms. The embodiments are provided only to fully disclose this disclosure and to fully convey its scope to those skilled in the art, and this specification is defined by the disclosed claims.

[0031] Since the shapes, dimensions, scales, angles, numbers, etc., disclosed in the drawings used to describe embodiments of this disclosure are merely exemplary, this disclosure is not limited to the items shown. Throughout the specification, the same reference numerals indicate the same parts. Furthermore, in describing this disclosure, detailed descriptions of relevant known technologies will be omitted where it is determined that such detailed descriptions might unnecessarily obscure the essential points of this disclosure.

[0032] When using terms such as "comprising," "having," or "consisting of" in this specification, additional parts may be added unless "only" is used. Unless otherwise expressly stated, the singular form of a component includes the plural form.

[0033] When explaining components, it should be understood that the margin of error is included, even when there is no separate explicit description.

[0034] When describing positional relationships, such as when the positional relationship between two parts is described as "on top of", "above", "below", "adjacent to", etc., one or more other parts may be located between the two parts unless "immediately following" or "directly" is used.

[0035] Although terms like "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical spirit of this disclosure, the "first component" mentioned below can also be the "second component."

[0036] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0037] The following implementations can be combined or integrated with each other in part or in whole, and can be linked and operated in various technical ways. The implementations can be performed independently or in conjunction with each other.

[0038] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0039] In the display device disclosed herein, the pixel circuit and gate driving circuit may include multiple transistors. The transistors may be implemented as oxide thin-film transistors (oxide TFTs) including oxide semiconductors, low-temperature polycrystalline silicon (LTPS) TFTs, etc.

[0040] A transistor is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that supplies charge carriers to the transistor. In a transistor, charge carriers begin to flow from the source. The drain is the electrode through which charge carriers leave the transistor. In a transistor, charge carriers flow from the source to the drain. In the case of an n-channel transistor, since the charge carriers are electrons, the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. An n-channel transistor has a current direction from the drain to the source. In the case of a p-channel transistor (p-channel metal-oxide-semiconductor (PMOS)), since the charge carriers are holes, the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-channel transistor, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can be changed depending on the applied voltage. Therefore, this disclosure is not limited to the source and drain of a transistor. In the following description, the source and drain of a transistor will be referred to as the first electrode and the second electrode.

[0041] The gate signal oscillates between the gate on-voltage and the gate off-voltage. The gate on-voltage is set to a voltage higher than the transistor's threshold voltage, and the gate off-voltage is set to a voltage lower than the transistor's threshold voltage.

[0042] A transistor turns on in response to a gate on-voltage and turns off in response to a gate off-voltage. In the case of an n-channel transistor, the gate on-voltage can be a high gate voltage, and the gate off-voltage can be a low gate voltage. In the case of a p-channel transistor, the gate on-voltage can be a low gate voltage, and the gate off-voltage can be a high gate voltage.

[0043] Figures 1A to 1C This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0044] Reference Figures 1A to 1C The display device according to embodiments of the present disclosure includes a display panel 100 and a display panel driving circuit for writing pixel data to pixels of the display panel 100. Additionally, the display device includes a power supply 150.

[0045] The display panel 100 may be, but is not limited to, a panel with a rectangular structure, having a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. For example, the display panel 100 may be a non-homogeneous panel in which at least a portion is curved or elliptical.

[0046] The display area AA of the display panel 100 includes a pixel array for displaying an input image. The pixel array includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix. The display panel 100 may also include power lines commonly connected to the pixels. These power lines may be commonly connected to pixel circuitry to supply the voltage required to drive the pixels 101.

[0047] Each of pixel 101 can be divided into red, green, and blue sub-pixels for color implementation. Each pixel may also include a white sub-pixel. Each sub-pixel includes pixel circuitry for driving a light-emitting element. The light-emitting element may include an OLED or an inorganic light-emitting diode (LED). Each pixel circuitry is connected to data lines, gate lines, and power lines. In the following description, a pixel may be interpreted as a sub-pixel.

[0048] The display area AA includes multiple pixel lines L1 to Ln. Each of the pixel lines L1 to Ln comprises a row of pixels arranged along the row direction (X-axis direction) in the pixel array of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Sub-pixels arranged along the data line direction in the column direction Y share the same data line 102. A horizontal time period is obtained by dividing a frame time period by the total number of pixel lines L1 to Ln.

[0049] The display panel 100 can be implemented using a non-transmissive display panel or a transmissive display panel. A transmissive display panel can be used in a transparent display device in which an image is displayed on the screen while actual objects in the background are visible. The display panel 100 can be made of a flexible display panel.

[0050] Power supply 150 receives an input voltage applied from host system 300 and outputs the voltage required to drive pixels 101 of display panel 100 and display panel driving circuitry. For this purpose, power supply 150 may include a DC-DC converter. The DC-DC converter may include a charge pump, regulator, buck converter, boost converter, etc. Power supply 150 can output a constant voltage (or DC voltage) via the DC-DC converter, such as gate on-state voltage, gate off-state voltage, pixel drive voltage, cathode voltage, reference voltage, and IC drive voltage of the display panel driving circuitry. Gate on-state voltage and gate off-state voltage can be supplied to level shifter 140 and gate driver 120. Voltages such as pixel drive voltage, cathode voltage, and reference voltage can be supplied to pixel 101 via a power line commonly connected to pixel 101.

[0051] The power supply 150 may also include a gamma voltage generator. The gamma voltage generator receives a high-level reference voltage and a low-level reference voltage and outputs multiple gamma reference voltages divided at specific intervals on a preset gamma curve (e.g., a 2.2 gamma curve). The gamma reference voltages are supplied to a data driver 110. In the data driver 110, the gamma reference voltages are further subdivided into grayscale voltages by a voltage divider circuit. The gamma voltage generator can be implemented using a programmable gamma circuit that can adjust the voltage of each of the gamma reference voltages according to digital data. A timing controller 130, a host system 300, or a separate external device can update the digital data stored in the registers of the programmable gamma circuit via a communication interface.

[0052] The display panel driving circuit, under the control of the timing controller 130, writes the pixel data of the input image into the pixels 101 of the display panel 100. The display panel driving circuit includes a data driver 110 and a gate driver 120.

[0053] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. The touch sensor driver is not shown in Figure 1. The data driver 110 and the touch sensor driver may be integrated into a single source driver IC.

[0054] The data driver 110 receives pixel data of the input image as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 can receive a gamma reference voltage and generate a gamma compensation voltage for each grayscale using a voltage divider circuit. The gamma compensation voltage for each grayscale is supplied to a digital-to-analog converter (hereinafter referred to as "DAC") disposed in each channel of the data driver 110.

[0055] The data driver 110 samples and latches the digital data received from the timing controller 130, and then inputs the digital data to the DAC. Here, the digital data includes pixel data of the input image. Additionally, the digital data may include mode selection data for selecting a first mode and a second mode. The DAC converts the pixel data into a gamma-compensated voltage and outputs a data voltage of the pixel data.

[0056] The gate driver 120 may be formed on the display panel 100 together with the circuit elements and wiring of the display area AA. The gate driver 120 may be disposed in at least one of the left non-display area NA and the right non-display area NA outside the display area AA in the display panel 100, or at least a portion thereof may be disposed within the display area AA.

[0057] Under the control of the timing controller 130, the gate driver 120 sequentially outputs pulses of the gate signal to the gate line 103. The gate driver 120 can sequentially supply the gate signal to the gate line 103 by shifting the pulses of the gate signal using a shift register. When multiple gate signals are applied to each pixel, the gate driver 120 may include multiple shift registers. The gate signals may include an emission control signal (or EM signal) and a scan signal input to the pixel circuitry through multiple gate lines.

[0058] The gate driver 120 can be arranged as an in-panel gate (GIP) in the non-display area, or as an in-display gate (GIA) between sub-pixels SP in the display area AA. For example, Figure 1B As shown, the circuitry of the gate driver 120 can be arranged in the non-display area NA, or as... Figure 1C As shown, the circuitry of the gate driver 120 can be arranged between pixels in the display area AA.

[0059] The timing controller 130 receives digital video data of the input image and timing signals synchronized with the data from the host system 300. The timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The horizontal synchronization signal Hsync and the data enable signal DE have a periodicity of one horizontal time period (1H).

[0060] The timing controller 130 can control the display panel driving circuit by generating a data timing control signal for controlling the operation timing of the data driver 110 and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system 300. The timing controller 130 can synchronize the data driver 110 and the gate driver 120 by controlling the operation timing of the display panel driving circuit.

[0061] The gate timing control signal output from the timing controller 130 can be input to the shift register of the gate driver 120 through the level shifter 140. The level shifter 140 can convert the voltage of the gate timing control signal received from the timing controller 130 into the swing width between the gate turn-on voltage and the gate turn-off voltage, and supply it to the gate driver 120.

[0062] The timing controller 130 can analyze the input image for each frame and generate a control signal for selectively outputting gate signals based on the analysis results. The generated control signal can be provided to the shift register of the gate driver 120 via the level shifter 140.

[0063] The host system 300 may include a motherboard from one of a television system, set-top box, navigation system, personal computer (PC), vehicle system, mobile terminal, and wearable terminal. The host system 300 can scale the image signal from the video source according to the resolution of the display panel 100 and can send it to the timing controller 130 along with a timing signal.

[0064] In this implementation, it is desirable to apply a common gate signal to all pixels simultaneously via a common line, excluding at least one of the multiple gate drivers that generate the gate signal.

[0065] Figures 2A to 2B This is a diagram illustrating the configuration of a gate driver according to an embodiment of the present disclosure. Figures 3A to 3B This is a diagram illustrating a first gate driver according to an embodiment of the present disclosure, and Figures 4A to 4B This is a diagram showing the wiring arranged in a gate driver according to an embodiment.

[0066] Reference Figures 2A to 2B According to embodiments of the present disclosure, a gate driver may include a first gate driver that outputs a first gate signal, a first common line CML1 that commonly applies a second gate signal or a first common gate signal, and a second common line CML2 that commonly applies a third gate signal or a second common gate signal.

[0067] A first gate signal can be sequentially output for each pixel line via a first gate driver. A first common gate signal can be simultaneously applied to all pixels via a first common line CML1, and a second common gate signal can be simultaneously applied to all pixels via a second common line CML2.

[0068] Here, the first gate signal can be the first scan signal SCAN1, the first common gate signal can be the second scan signal SCAN2, and the second common gate signal can be the EM signal EM, but is not limited to these.

[0069] As described above, in the implementation, since each of the first common gate signal and the second common gate signal is applied simultaneously through a single common line, therefore, in situations such as Figure 2A In structures like these, the bezel size of the display panel can be reduced, and in situations such as Figure 2B In structures like these, pixel design margins can be ensured.

[0070] Reference Figure 3AAccording to embodiments of the present disclosure, a first gate driver may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor or pull-up transistor T9, a tenth transistor or pull-down transistor T10, a first capacitor C1, and a second capacitor C2.

[0071] The first transistor T1 is turned on by a start signal GVST or a previous carry signal C(n-1) and connects the first node Qh to the second power line PL2, which is subjected to a low potential voltage. The first transistor T1 includes a gate electrode to which the previous carry signal C(n-1) is applied, a first electrode connected to the first node Qh, and a second electrode connected to the second power line PL2.

[0072] The second transistor T2 is turned on by the voltage of the reset signal RST and connects the first node Qh to the first power line PL1, which is subjected to a high potential voltage VGH. The second transistor T2 includes a gate electrode to which the reset signal RST is applied, a first electrode connected to the first node Qh, and a second electrode connected to the first power line PL1.

[0073] The third transistor T3 is turned on by the voltage of the second control node Qb, and connects the second control node Qb to the first power line PL1, which is subjected to a high potential voltage VGH. The third transistor T3 includes a gate electrode connected to the second control node Qb, a first electrode connected to the first node Qh, and a second electrode connected to the first power line PL1.

[0074] The fourth transistor T4 is turned on by the voltage of the next clock signal GCLK(N+2) and connects the second control node Qb to the second power line PL2. The fourth transistor T4 includes a gate electrode to which the next clock signal GCLK(N+2) is applied, a first electrode connected to the second power line PL2, and a second electrode connected to the second control node Qb.

[0075] The fifth transistor T5 is turned on by a low potential voltage VGL and connects the first node Qh to the first control node Q. The fifth transistor T5 includes a gate electrode connected to the second power line PL2, a first electrode connected to the first node Qh, and a second electrode connected to the first control node Q.

[0076] The sixth transistor T6 is turned on by the voltage of the reset signal RST and connects the second control node Qb to the second power line PL2. The sixth transistor T6 includes a gate electrode to which the reset signal RST is applied, a first electrode connected to the second power line PL2, and a second electrode connected to the second control node Qb.

[0077] The seventh transistor T7 is turned on by a start signal GVST or a previous carry signal C(n-1) and connects the second control node Qb to the first power line PL1. The seventh transistor T7 includes a gate electrode to which the previous carry signal C(n-1) is applied, a first electrode connected to the first node Qh, and a second electrode connected to the first power line PL1.

[0078] The eighth transistor T8 is turned on by the voltage of the first node Qh and connects the second control node Qb to the first power line PL1. The eighth transistor T8 includes a gate electrode connected to the first node Qh, a first electrode connected to the second control node Qb, and a second electrode connected to the first power line PL1.

[0079] The ninth transistor T9 is turned on by the voltage of the first control node Q and outputs the clock signal GCLK(N) to the output node OUT. The ninth transistor T9 includes a gate electrode connected to the first control node Q, a first electrode connected to the clock line CL to which the clock signal GCLK(N) is applied, and a second electrode connected to the output node OUT.

[0080] The tenth transistor T10 is turned on by the voltage of the second control node Qb and outputs a high potential voltage VGH to the output node OUT. The tenth transistor T10 includes a gate electrode connected to the second control node Qb, a first electrode connected to the output node OUT, and a second electrode connected to the first power line PL1.

[0081] The first capacitor C1 is connected between the gate electrode and the second electrode of the ninth transistor T9. The second capacitor C2 is connected between the gate electrode and the second electrode of the tenth transistor T10.

[0082] like Figure 3B As shown, the gate driver can output the gate signal synchronously with the clock signal. For example, when using four-phase clock signals GCLK1, GCLK2, GCLK3, and GCLK4, the gate driver outputs the gate signal synchronously with the clock signal GCLK1.

[0083] Reference Figures 4A to 4B In the region where the gate driver according to an embodiment of the present disclosure is arranged, the wiring for the first gate driver SCAN1 that outputs the first gate signal SCAN1(N), the wiring for applying the start signal GVST, the four-phase clock signals GCLK1, GCLK2, GCLK3 and GCLK4 and the reset signal RST to each signal transmission portion of the first gate driver SCAN1, the first common line CML1 that applies the first common gate signal SCAN2 to the common ground, and the second common line CML2 that applies the second common gate signal EM to the common ground can be arranged.

[0084] The first gate signal output from the first gate driver SCAN1, the first common gate signal applied through the first common line CML1, and the second common gate signal applied through the second common line CML2 can be provided to the pixel through multiple gate lines GL1, GL2, and GL3.

[0085] Therefore, since the first common gate signal and the second common gate signal are applied through a common line, it is not necessary to provide a signal transmission section for generating the first common gate signal and the second common gate signal, or wiring for applying start signal, clock signal and reset signal to the signal transmission section.

[0086] In this example, the first common gate signal and the second common gate signal are applied as a common gate signal through a common line, but it is not necessary to be limited to this.

[0087] Figure 5 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure.

[0088] Reference Figure 5 The pixel circuit according to a first embodiment of the present disclosure includes a light-emitting element EL, a driving element DT that supplies current to the light-emitting element EL, a plurality of switching elements T1, T2, T3, T4 and T5 that switch the current path connected to the driving element DT, and a capacitor Cst that stores the gate-source voltage of the driving element DT. The driving element DT and the switching elements T1, T2, T3, T4 and T5 can be implemented as a P-channel TFT.

[0089] The pixel circuitry is connected to power lines that are subjected to a direct current (DC) voltage or a constant voltage, such as the pixel drive voltage line or first power line PL1 that is subjected to the pixel drive voltage ELVDD, the pixel base voltage line or second power line PL2 that is subjected to the pixel base voltage ELVSS, and the third power line PL3 that is subjected to the reference voltage Vref. These power lines can be connected to all pixels on the display panel.

[0090] The light-emitting element (EL) can be implemented as an organic light-emitting diode (OLED). The EL includes an anode, a cathode, and an organic compound layer formed between the anode and cathode. The anode of the EL is connected to a fourth node n4, and its cathode is connected to a second electric field line PL2 to which the pixel base voltage ELVSS is applied. The organic compound layer may include a hole injection layer HIL, a hole transport layer HTL, an emissive layer EML, an electron transport layer ETL, and an electron injection layer EIL, but this disclosure is not limited thereto. The EL can be implemented in a series structure of multiple emissive layers stacked together. A series structure of the EL can improve pixel brightness and lifetime.

[0091] The driving element DT generates current based on the gate-source voltage Vgs and drives the light-emitting element EL. The driving element DT includes a first electrode connected to a first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0092] A first switching element T1 is connected between the data line DL and the first node n1. The first switching element T1 is turned on according to the gate on-state voltage VGL of the first gate signal SCAN1(N), and applies the data voltage Vdata of the pixel data to the first node n1. The first switching element T1 includes a first electrode connected to the data line DL, a gate electrode to which the first gate signal SCAN1(N) is applied, and a second electrode connected to the first node n1.

[0093] The second switching element T2 is connected between the second node n2 and the third node n3. The second switching element T2 is turned on according to the gate turn-on voltage VGL of the first common gate signal SCAN2, and is connected to the gate electrode and the second electrode of the driving element DT. The second switching element T2 includes a first electrode connected to the second node n2, a gate electrode to which the first common gate signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0094] A third switching element T3 is connected between the fourth node n4 and the third power line PL3. The third switching element T3 is turned on according to the gate on-state voltage VGL of the first common gate signal SCAN2, and connects the fourth node n4 to the third power line PL3, which is subject to an applied reference voltage Vref. The third switching element T3 includes a first electrode connected to the third power line PL3, a gate electrode to which the first common gate signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0095] A fourth switching element T4 is connected between the first node n1 and the third power line PL3. The fourth switching element T4 is turned on according to the gate on-voltage VGL of the second common gate signal EM, and connects the first node n1 to the third power line PL3. The fourth switching element T4 includes a first electrode connected to the first node n1, a gate electrode to which the second common gate signal EM is applied, and a second electrode connected to the third power line PL3.

[0096] A fifth switching element T5 is connected between the third node n3 and the fourth node n4. The fifth switching element T5 is turned on according to the gate on-state voltage VGL of the second common gate signal EM, and connects the third node n3 to the fourth node n4. The fifth switching element T5 includes a first electrode connected to the third node n3, a gate electrode to which the second common gate signal EM is applied, and a second electrode connected to the fourth node n4.

[0097] Capacitor Cst is connected between the first node n1 and the second node n2. Capacitor Cst maintains the gate-source voltage Vgs of the driving element DT during the light-emitting period.

[0098] The gate signals applied to the pixel circuit of the first embodiment include a first gate signal SCAN1(N), a first common gate signal SCAN2, and a second common gate signal EM. In the pixel circuit of the first embodiment, in addition to the first gate signal SCAN1(N), the first common gate signal SCAN2 and the second common gate signal EM can be applied through a common line.

[0099] Figure 6 It shows that it is applied to Figure 5 The diagram shows the timing of the gate signal drive for the pixel circuit.

[0100] Reference Figure 5 and Figure 6 The pixel circuit according to the embodiments of the present disclosure can be driven in the order of initialization step Ti, data writing and sensing step Tw / s, and light emission step Tem.

[0101] In the initialization step Ti, a first common gate signal SCAN2 with a gate on-state voltage is simultaneously applied to all pixels through the first common line, and a second common gate signal EM with a gate on-state voltage can be simultaneously applied to all pixels through the second common line.

[0102] In the data writing and sensing step Tw / s, first gate signals SCAN1(1) to SCAN1(N) with gate turn-on voltage are sequentially applied to each pixel line, and the threshold voltage of the driving element can be sensed.

[0103] In the light-emitting step Tem, a second common gate signal EM with a gate turn-on voltage is simultaneously applied to all pixels through the second common line, and therefore all pixels can emit light at the same time.

[0104] Thus, in the implementation, in addition to the first gate signal SCAN1(N) for applying the data voltage Vdata to each pixel line, the first common gate signal SCAN2 for applying the initialization voltage Vref and the second common gate signal EM for making the light-emitting element emit light can be applied to all pixels simultaneously through the first common line and the second common line.

[0105] Figure 7 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure.

[0106] Reference Figure 7The pixel circuit according to this embodiment includes a first light-emitting element EL1 that emits light in a first mode SMODE, a second light-emitting element EL2 that emits light in a second mode PMODE, a driving element DT that drives the first light-emitting element EL1 and the second light-emitting element EL2, a plurality of switching elements T1 to T7 that switch the current path connected to the driving element DT, and a capacitor Cst. The driving element DT and the plurality of switching elements T1 to T7 can be implemented as p-channel transistors, but are not limited thereto.

[0107] The pixel circuitry is connected to power lines that are subject to DC or constant voltage, such as the pixel drive voltage line or first power line PL1 subject to pixel drive voltage ELVDD, the pixel base voltage line or second power line PL2 subject to pixel base voltage ELVSS, and the reference voltage line or third power line PL3 subject to reference voltage Vref. On the display panel, these power lines can be commonly connected to all pixels.

[0108] The driving element DT generates current based on the gate-source voltage Vgs and drives the first light-emitting element EL1 and the second light-emitting element EL2. The driving element DT includes a first electrode connected to a first power line PL1 to which the pixel driving voltage ELVDD is applied, a gate electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0109] The first light-emitting element EL1 and the second light-emitting element EL2 can be implemented as an OLED. Light-emitting elements EL1 and EL2 include an anode electrode, a cathode electrode, and an organic compound layer formed between the electrodes. The anode electrode of the first light-emitting element EL1 is connected to a fourth node n4, and the cathode electrode is connected to a second electric field line PL2 to which the pixel base voltage ELVSS is applied. The anode electrode of the second light-emitting element EL2 is connected to a fifth node n5, and the cathode electrode is connected to the second electric field line PL2. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). Light-emitting elements EL1 and EL2 can be implemented in a series structure of multiple stacked emissive layers. The series structure of light-emitting elements EL1 and EL2 can improve the brightness and lifetime of the pixel.

[0110] In this configuration, a first lens can be arranged on the first light-emitting element EL1, and a second lens can be arranged on the second light-emitting element EL2. The first lens limits the vertical viewing angle of the first light-emitting element EL1 emitting light in the first mode, and the second lens can narrow both the vertical and horizontal viewing angles of the second light-emitting element EL2. The first light-emitting element EL1 emits light in the first mode but is emitted at a first viewing angle due to the first lens, and the second light-emitting element EL2 emits light in the second mode but is emitted at a second viewing angle smaller than the first viewing angle due to the second lens.

[0111] A first switching element T1 is connected between the data line DL and the first node n1. The first switching element T1 is turned on according to the gate on-state voltage VGL of the first gate signal SCAN1, and applies the data voltage Vdata of the pixel data to the first node n1. The first switching element T1 includes a first electrode connected to the data line DL, a gate electrode to which the first gate signal SCAN1(N) is applied, and a second electrode connected to the first node n1.

[0112] The second switching element T2 is connected between the second node n2 and the third node n3. The second switching element T2 is turned on according to the gate turn-on voltage VGL of the first common gate signal SCAN2, and is connected to the gate electrode and the second electrode of the driving element DT. The second switching element T2 includes a first electrode connected to the second node n2, a gate electrode to which the first common gate signal SCAN2 is applied, and a second electrode connected to the third node n3.

[0113] A third switching element T3 is connected between the fourth node n4 and the third power line PL3. The third switching element T3 is turned on according to the gate on-state voltage VGL of the first common gate signal SCAN2, and connects the fourth node n4 to the third power line PL3, which is subject to an applied reference voltage Vref. The third switching element T3 includes a first electrode connected to the third power line PL3, a gate electrode to which the first common gate signal SCAN2 is applied, and a second electrode connected to the fourth node n4.

[0114] A fourth switching element T4 is connected between the fifth node n5 and the third power line PL3. The fourth switching element T4 is turned on according to the gate on-state voltage VGL of the first common gate signal SCAN2, and connects the fifth node n5 to the third power line PL3, which is subject to an applied reference voltage Vref. The fourth switching element T4 includes a first electrode connected to the third power line PL3, a gate electrode to which the first common gate signal SCAN2 is applied, and a second electrode connected to the fifth node n5.

[0115] A fifth switching element T5 is connected between the first node n1 and the third power line PL3. The fifth switching element T5 is turned on according to the gate on-voltage VGL of the second-first common gate signal EM1, and connects the first node n1 to the third power line PL3. The fifth switching element T5 includes a first electrode connected to the first node n1, a gate electrode to which the second-first common gate signal EM1 is applied, and a second electrode connected to the third power line PL3.

[0116] A sixth switching element T6 is connected between the third node n3 and the fourth node n4. The sixth switching element T6 is turned on according to the gate on-state voltage VGL of the second-second common gate signal EM2, and connects the third node n3 to the fourth node n4. The sixth switching element T6 includes a first electrode connected to the third node n3, a gate electrode to which the second-second common gate signal EM2 is applied, and a second electrode connected to the fourth node n4.

[0117] A seventh switching element T7 is connected between the third node n3 and the fifth node n5. The seventh switching element T7 is turned on according to the gate on-state voltage VGL of the second-third common gate signal EM3, and connects the third node n3 to the fifth node n5. The seventh switching element T7 includes a first electrode connected to the third node n3, a gate electrode to which the second-third common gate signal EM3 is applied, and a second electrode connected to the fifth node n5.

[0118] Capacitor Cst is connected between the first node n1 and the second node n2. Capacitor Cst maintains the gate-source voltage Vgs of the driving element DT during the light-emitting period.

[0119] The gate signals applied to the pixel circuit of the second embodiment include a first gate signal SCAN1(N), a first common gate signal SCAN2, a second-first common gate signal EM1, a second-second common gate signal EM2, and a second-third common gate signal EM3. In the pixel circuit of the second embodiment, except for the first gate signal SCAN1(N), the first common gate signal SCAN2, the second-first common gate signal EM1, the second-second common gate signal EM2, and the second-third common gate signal EM3 can be applied through a common line.

[0120] Figures 8A to 8B It shows that it is applied to Figure 7 The diagram shows the timing of the gate signal drive for the pixel circuit.

[0121] Reference Figure 7 and Figures 8A to 8B The pixel circuit according to the embodiments of the present disclosure can be driven in the order of initialization step Ti, data writing and sensing step Tw / s, and light emission step Tem.

[0122] In initialization step Ti, a first common gate signal SCAN2 with a gate on-state voltage is simultaneously applied to all pixels via a first common line, and a second-first common gate signal EM1 with a gate on-state voltage is simultaneously applied to all pixels via a second common line. In the first mode, a second-second common gate signal EM2 with a gate on-state voltage is simultaneously applied to all pixels via a third common line, and in the second mode, a second-third common gate signal EM3 with a gate on-state voltage is simultaneously applied to all pixels via a fourth common line.

[0123] In the data writing and sensing step Tw / s, the first gate signals SCAN1(1) to SCAN1(N) with gate turn-on voltage can be applied sequentially to each pixel line.

[0124] In the light-emitting step Tem, the second-to-first common gate signal EM1, which has a gate on-state voltage, can be simultaneously applied to all pixels through the second common line. In the first mode, with Figure 8A Together, the second-to-second common gate signal EM2, with a gate on-state voltage, is simultaneously applied to all pixels through the third common line, enabling the first light-emitting elements of all pixels to emit light simultaneously. In the second mode, as... Figure 8B As shown, the second-third common gate signal EM3 with gate turn-on voltage is simultaneously applied to all pixels through the fourth common line, so that the second light-emitting elements of all pixels can emit light at the same time.

[0125] Thus, in the implementation, in addition to the first gate signal SCAN1(N) used to apply the data voltage Vdata to each pixel line, the first common gate signal SCAN2, the second-1st common gate signal EM1, the second-2nd common gate signal EM2, and the second-3rd common gate signal EM3 can be applied to all pixels simultaneously through the first common line, the second common line, the third common line, and the fourth common line, respectively.

[0126] Therefore, in the implementation, the entire display panel can switch between the first mode and the second mode simultaneously.

[0127] In this implementation, since all pixels emit light simultaneously, rather than sequentially line-by-line, the segment for applying the gate turn-off voltage of the EM signal becomes longer, and thus flicker may occur. Therefore, in this implementation, the aim is to reduce the segment for applying the gate turn-off voltage of the EM signal by dispersing the time period of applying the gate turn-off voltage of the EM signal.

[0128] Figures 9A to 9G This is a diagram illustrating the output principle of the gate signal according to an embodiment of the present disclosure.

[0129] Reference Figures 9A to 9C In one implementation, the display area is divided into multiple regions, and a gate signal can be modulated and applied so that each divided region emits light simultaneously.

[0130] For example, 100 pixel lines can be divided into four regions AA1, AA2, AA3 and AA4, and a second common gate signal EM can be applied to cause each region AA1, AA2, AA3 and AA4, which each includes 25 pixel lines, to emit light simultaneously.

[0131] For each region AA1, AA2, AA3 and AA4, the first gate signal SCAN1(N) can be applied sequentially on a pixel-line basis.

[0132] The first common gate signals SCAN2(1) to SCAN2(4) can be simultaneously applied to each region AA1, AA2, AA3 and AA4 through different first common lines CML1. That is, the first common gate signal SCAN2(1) is applied to region AA1 through the first-a common line CML1a, the first common gate signal SCAN2(2) is applied to region AA2 through the first-b common line CML1b, the first common gate signal SCAN2(3) is applied to region AA3 through the first-c common line CML1c, and the first common gate signal SCAN2(4) is applied to region AA4 through the first-d common line CML1d.

[0133] The second common gate signal EM can be applied through a single common line CML2 with modulated gate turn-on voltage pulses, so that each region AA1, AA2, AA3 and AA4 emits light simultaneously.

[0134] For example, when pixels in the entire display area emit light simultaneously without dividing the area into regions, the segment for which the gate turn-off voltage of the second common gate signal EM is applied during a frame is held for a time t×4; however, when the area is divided and pixels emit light simultaneously by region, the segment for which the gate turn-off voltage of the second common gate signal EM is applied during a frame is held for only time t for each region, making flicker imperceptible.

[0135] This example describes the case where the second common gate signal EM is applied via a single common line, but it is not limited to this and multiple common lines can be applied.

[0136] Reference Figures 9D to 9E In this implementation, the second common gate signal EM can be applied by region through two second common lines CML2 (i.e., the second-a common line CML2a and the second-b common line CML2b).

[0137] For example, the second common gate signal EM(1) is applied simultaneously to the odd-numbered regions AA1 and AA3, and the second common gate signal EM(2) is applied simultaneously to the even-numbered regions AA2 and AA4.

[0138] When the second common gate signal EM is applied simultaneously by region through the two second common lines in this manner, the emission time of the pixel in each region within a frame can be increased.

[0139] Reference Figures 9F to 9G In this embodiment, the second common gate signal EM can be applied by region through four second common lines CML2 (i.e., the second-a common line CML2a, the second-b common line CML2b, the second-c common line CML2c, and the second-d common line CML2d).

[0140] For example, the second common gate signal EM(1) is applied to region AA1 through the 2-a common line CML2a, the second common gate signal EM(2) is applied to region AA2 through the 2-b common line CML2b, the second common gate signal EM(3) is applied to region AA3 through the 2-c common line CML2c, and the second common gate signal EM(4) is applied to region AA4 through the 2-d common line CML2d.

[0141] When the second common gate signal EM is applied simultaneously by region through the four second common lines in this manner, the emission time of the pixel in each region within a frame can be increased.

[0142] Furthermore, in the implementation, at least one second common line to which the second common gate signal EM is applied can be used, and the maximum number of second common lines can be equal to the number of regions. Therefore, in the implementation, when the display area is divided into n regions (where n is a natural number), the number of first common lines to which the second gate signal for initializing the pixels in each region is applied can be n, and the number of second common lines to which the third gate signal for causing the light-emitting elements in the pixels of each region to emit light can be set in the range of 1 to n.

[0143] Figures 10 to 15 This is a diagram used to illustrate the principle of gate signal application according to an embodiment.

[0144] Reference Figures 10 to 12According to the embodiment, the timing controller 130 can generate a start signal GVST', clock signals GCLK1', GCLK2', GCLK3' and GCLK4', and a reset signal RST' for generating a first gate signal SCAN1(N), and also generates a first common gate signal SCAN2' and a second common gate signal EM', and provides them to the level shifter 140.

[0145] The level shifter 140 can amplify the voltage levels of the start signal GVST', clock signals GCLK1', GCLK2', GCLK3' and GCLK4', reset signal RST', first common gate signal SCAN2' and second common gate signal EM' provided from the timing controller 130. It can supply the amplified start signal GVST, clock signals GCLK1, GCLK2, GCLK3 and GCLK4 and reset signal RST to the first gate driver 120, supply the first common gate signal SCAN2 to the first common line CML1, and supply the second common gate signal EM to the second common line CML2.

[0146] like Figure 12 As shown, power supply 150 can supply high potential voltage VGH and low potential voltage VGL to level shifter 140 for amplifying the voltage level of the signal in level shifter 140.

[0147] In other words, in the implementation, the timing controller can generate a first common gate signal and a second common gate signal, and can apply them to pixels in the display area through the first common line and the second common line.

[0148] Reference Figures 13 to 15 According to the embodiment, the timing controller 130 can generate a start signal GVST', clock signals GCLK1', GCLK2', GCLK3' and GCLK4', and a reset signal RST' for generating a first gate signal SCAN1(N), and can provide them to the level shifter 140.

[0149] The level shifter 140 can amplify the voltage levels of the start signal GVST', clock signals GCLK1', GCLK2', GCLK3' and GCLK4' and reset signal RST' provided from the timing controller 130, and can supply the amplified start signal GVST, clock signals GCLK1, GCLK2, GCLK3 and GCLK4 and reset signal RST to the first gate driver 120.

[0150] Additionally, the timing controller 130 according to the embodiment can provide a first control signal CS1 and a second control signal CS2 to the power supply 150, and the power supply 150 can generate a first common gate signal SCAN2 based on the first control signal CS1 and supply the generated first common gate signal SCAN2 to the first common line CML1, and can generate a second common gate signal EM based on the second control signal CS2 and supply the generated second common gate signal EM to the second common line CML2.

[0151] In other words, in the implementation, the power supply can generate a first common gate signal and a second common gate signal, and can apply them to pixels in the display area through the first common line and the second common line.

[0152] Additionally, in this implementation, the TFTs of the pixel circuit, where all components are implemented as p-channel LTPS TFTs, may exhibit hysteresis characteristics. Due to this hysteresis, the threshold voltage Vth may decrease when the data voltage changes from black grayscale to white grayscale, and therefore, the brightness may decrease more significantly compared to when the voltage changes from white grayscale to another white grayscale without a change in the threshold voltage, leading to a deterioration in first frame response (FFR) performance.

[0153] Figures 16 to 17 This is a diagram illustrating the improvement in FFR performance according to an embodiment of the present disclosure.

[0154] Reference Figure 16 In the comparative example where simultaneous emission was not performed, the voltage drop in the pixel driving voltage may not occur when the grayscale changes from white to black; however, when the grayscale changes from black to white, the voltage drop in the pixel driving voltage may increase, resulting in a decrease in the brightness of the emitting pixel and thus degrading the FFR performance.

[0155] In contrast, in the implementation of simultaneous emission, since all pixels emit light after the data voltage is applied to all pixels within a frame, the voltage drop in the pixel driving voltage may not occur, thereby improving FFR performance.

[0156] Reference Figure 17 When the grayscale area is fixed and the area around it changes from black grayscale to white grayscale, in the comparative example where simultaneous emission is not performed, the voltage drop in the pixel driving voltage may decrease, resulting in an increase in the brightness of the emitting pixel, thereby generating a bright flicker.

[0157] Additionally, when the grayscale area is fixed and the area around it changes from white grayscale to black grayscale, in the comparative example where simultaneous emission is not performed, the voltage drop in the pixel driving voltage may increase, resulting in a decrease in the brightness of the emitting pixel, thereby generating dark flicker.

[0158] In contrast, in the implementation of simultaneous illumination, since all pixels emit light after the data voltage is applied to all pixels within a frame, voltage drop in the pixel driving voltage may not occur, and flicker may not be generated during screen transitions.

[0159] Therefore, in the implementation, since data voltages are applied to all pixels within a frame and then emission is performed simultaneously, image quality degradation such as FFR performance deterioration or flickering can be improved.

[0160] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the embodiments described above are illustrative in all respects and do not limit the present disclosure.

Claims

1. A display device, comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixel circuits are arranged in the pixel array; A data driver configured to output a data voltage to the plurality of data lines; A gate driver configured to sequentially output gate signals to the plurality of gate lines; A common line, which is configured to simultaneously apply a common gate signal to the plurality of gate lines; as well as A timing controller configured to generate the common gate signal.

2. The display device according to claim 1, wherein, The gate signal includes a first scan signal for supplying the data voltage to the pixel circuit.

3. The display device according to claim 2, wherein, The common gate signal includes: A second scan signal used to initialize the pixel circuit; and Light emission control signals used to drive the light-emitting elements of the pixel circuit.

4. The display device according to claim 3, wherein, The pixel array is divided into n regions, where n is a natural number, and The common line includes: n first common lines, each of which is configured to apply the second scanning signal to a corresponding region in the n regions, and A second common line for applying the light emission control signal to the n regions.

5. The display device according to claim 4, wherein, The number of common lines used to apply the light emission control signal is less than or equal to n.

6. The display device according to claim 1, wherein, The gate driver and the common line are arranged in the non-display area or the display area and are connected to the plurality of gate lines.

7. The display device according to claim 1, wherein, The pixel circuit includes a driving element, a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a light-emitting element, and a capacitor. The driving element includes a gate electrode connected to the second node, a first electrode connected to a first electric field line to which a pixel driving voltage is applied, and a second electrode connected to the third node. The first switching element includes a gate electrode to which a first scan signal is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to a first node. The second switching element includes a gate electrode to which a second scan signal is applied, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element includes a gate electrode to which the second scan signal is applied, a first electrode connected to a third electric field line to which a reference voltage is applied, and a second electrode connected to a fourth node. The fourth switching element includes a gate electrode to which a light-emitting control signal is applied, a first electrode connected to the first node, and a second electrode connected to the third electric field line. The fifth switching element includes a gate electrode to which the light emission control signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The light-emitting element is connected between the fourth node and the second electric field line to which the pixel base voltage is applied, and The capacitor is connected between the first node and the second node.

8. The display device according to claim 1, wherein, The pixel circuit includes a driving element, a first switching element, a second switching element, a third switching element, a fourth switching element, a fifth switching element, a sixth switching element, a seventh switching element, a first light-emitting element, a second light-emitting element, and a capacitor. The driving element includes a gate electrode connected to the second node, a first electrode connected to a first electric field line to which a pixel driving voltage is applied, and a second electrode connected to the third node. The first switching element includes a gate electrode to which a first scan signal is applied, a first electrode connected to a data line to which a data voltage is applied, and a second electrode connected to a first node. The second switching element includes a gate electrode to which a second scan signal is applied, a first electrode connected to the second node, and a second electrode connected to the third node. The third switching element includes a gate electrode to which the second scan signal is applied, a first electrode connected to a third electric field line to which a reference voltage is applied, and a second electrode connected to a fourth node. The fourth switching element includes a gate electrode to which the second scan signal is applied, a first electrode connected to the third electric field line, and a second electrode connected to the fifth node. The fifth switching element includes a gate electrode to which a first light-emitting control signal is applied, a first electrode connected to the first node, and a second electrode connected to the third electric field line. The sixth switching element includes a gate electrode to which a second light-emitting control signal is applied, a first electrode connected to the third node, and a second electrode connected to the fourth node. The seventh switching element includes a gate electrode to which a third light-emitting control signal is applied, a first electrode connected to the third node, and a second electrode connected to the fifth node. The first light-emitting element is connected between the fourth node and the second electric field line to which the pixel base voltage is applied. The second light-emitting element is connected between the fifth node and the second electric field line, and The capacitor is connected between the first node and the second node.

9. The display device according to claim 1, wherein, The pixel circuit is driven in the order of initialization, data writing and sensing, and light emission. In the initialization step, the pixel circuit is simultaneously initialized via the common gate signal. In the data writing and sensing steps, data voltages are sequentially applied to the pixel circuit based on pixel lines via the gate signal, and In the light-emitting step, the pixel circuit emits light simultaneously through the common gate signal.

10. A display device, comprising: A pixel array, wherein multiple data lines, multiple gate lines and multiple pixel circuits are arranged in the pixel array; A data driver configured to output a data voltage to the plurality of data lines; A gate driver configured to sequentially output gate signals to the plurality of gate lines; A common line, which is configured to simultaneously apply a common gate signal to the plurality of gate lines; as well as A power supply configured to generate the common gate signal.

11. The display device according to claim 10, wherein, The gate signal includes: A first scan signal is used to supply the data voltage to the pixel circuit.

12. The display device according to claim 11, wherein, The common gate signal includes: A second scan signal used to initialize the pixel circuit; and Light emission control signals used to drive the light-emitting elements of the pixel circuit.

13. The display device according to claim 12, wherein, The pixel array is divided into n regions, where n is a natural number, and The common line includes: n first common lines, each of which is configured to apply the second scanning signal to a corresponding region in the n regions, and A second common line for applying the light emission control signal to the n regions.

14. The display device according to claim 13, wherein, The number of common lines used to apply the light emission control signal is less than or equal to n.

15. The display device according to claim 10, further comprising: A timing controller configured to generate control signals for generating the common gate signal. The power supply generates the common gate signal based on the control signal.

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