Display control circuit for detecting noise interference and control method thereof

Abstract

The invention discloses a display control circuit for detecting noise interference and a control method thereof, the display control circuit comprises a display driver and a time schedule controller, and the time schedule controller is coupled with the display driver. In the control method, the display driver sets an asynchronous signal indicating that the timing controller and the display driver are asynchronous. When the display driver or the time schedule controller judges that the time interval of the asynchronous signal is smaller than the preset time interval, the display driver executes a noise interference mode. When the display driver or the time schedule controller judges that the time interval of the asynchronous signal is equal to or larger than the preset time interval, and after the noise interference mode is executed, the display driver executes a crash reset mode.

Description

TECHNICAL FIELD

[0001] The present invention relates to a display technology, in particular, a display control circuit for detecting noise interference and a control method thereof. BACKGROUND

[0002] Each pixel of a liquid crystal display (LCD) is usually composed of a layer of molecules arranged between two transparent electrodes, usually made of indium tin oxide (ITO), and two polarizing filters, whose polarization directions are perpendicular to each other in most cases. If there is no liquid crystal between the polarizing filters, the light passing through the first polarizing filter will be blocked by the second polarizing filter. Before an electric field is applied, the orientation of the liquid crystal molecules is determined by the alignment of the electrode surfaces. In a twisted nematic (TN) device, the surface alignment directions at the two electrodes are perpendicular to each other, so the molecules are arranged in a helical structure or twisted manner. This causes the rotation of the polarization of the incident light, making the display screen appear gray. If the applied voltage is large enough, the liquid crystal molecules in the center of the molecule layer are almost not twisted, and the polarization of the incident light will not rotate when passing through the liquid crystal layer. Then, this incident light will be polarized in a direction mainly perpendicular to the second polarizing filter, and thus be blocked, making the pixel appear black. By controlling the voltage applied to the liquid crystal layer of each pixel, light can be allowed to pass through in different amounts, thereby presenting different gray scales. As mentioned above, the twist and transmittance of the liquid crystal are controlled by the voltage across the liquid crystal, which is the voltage difference between the pixel voltage and the common electrode voltage. If the voltage across the liquid crystal remains a direct current voltage of a single polarity for a long time, the movable ions in the liquid crystal will move in the same direction. This movement generates an electric field with opposite polarity charges on the electrodes, which in turn affects the alignment and transmittance of the liquid crystal and causes polarization. SUMMARY

[0003] The present invention provides a display control circuit for detecting noise interference and a control method thereof, which avoids abnormal screen and residual image imprint.

[0004] In an embodiment of the present invention, a control method of a display control circuit is provided, the display control circuit comprising a timing controller and a display driver, the control method comprising the steps of: setting an asynchronous signal, which indicates that the timing controller and the display driver are not synchronized; executing a noise interference mode when a time interval of the asynchronous signal is less than a preset time interval; and executing a crash reset mode when the noise interference mode is executed and when it is judged that the time interval of the asynchronous signal is equal to or greater than the preset time interval.

[0005] In an embodiment of the present application, a display control circuit is provided, which includes a timing controller and a display driver. The display driver is coupled to the timing controller and is configured to set an out-of-sync signal, which indicates that the timing controller is out of sync with the display driver. When the timing controller determines that a time interval of the out-of-sync signal is less than a preset time interval, the display driver executes a noise disturbance mode. After executing the noise disturbance mode, and when the timing controller determines that the time interval of the out-of-sync signal is equal to or greater than the preset time interval, the display driver executes a hang reset mode.

[0006] In an embodiment of the present application, a display control circuit is provided, which includes a timing controller and a display driver. The display driver is coupled to the timing controller and is configured to set an out-of-sync signal, which indicates that the timing controller is out of sync with the display driver. When the timing controller determines that a time interval of the out-of-sync signal is less than a preset time interval, the display driver executes a noise disturbance mode. After executing the noise disturbance mode, and when the timing controller determines that the time interval of the out-of-sync signal is equal to or greater than the preset time interval, the display driver executes a hang reset mode.

[0007] Based on the above, the display control circuit and the control method thereof for detecting noise disturbance execute a noise disturbance mode or a hang reset mode according to a preset time interval and a time interval of an out-of-sync signal, which indicates that the timing controller is out of sync with the display driver, thereby avoiding abnormal screen and residual image burn-in. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 FIG. 1 is a schematic diagram of a display control circuit according to a first embodiment of the present application.

[0009] Figure 2 FIG. 3 is a schematic diagram of a pixel equivalent circuit according to an embodiment of the present application.

[0010] Figure 3 FIG. 4 is a schematic diagram of a state of a driving voltage and waveforms of a sync signal, an out-of-sync signal, a wake-up signal, a pixel voltage, and a common voltage according to an embodiment of the present application.

[0011] Figure 4 FIG. 5 is a flowchart of a control method of the display control circuit according to the first embodiment of the present application.

[0012] Figure 5 FIG. 6 is a schematic diagram of a screen presentation of a display panel corresponding to the display control circuit according to the first embodiment of the present application. Figure 3

[0013] Figure 6 FIG. 7 is a schematic diagram of a display control circuit according to a second embodiment of the present application.

[0014] Figure 7 ​A waveform diagram of the states of a driving voltage, a synchronization signal, an asynchronous signal, a wake-up signal, a pixel voltage, and a common voltage according to another embodiment of the present application.

[0015] Figure 8 A flowchart of a control method of a display control circuit according to a second embodiment of the present application.

[0016] Figure 9 A waveform diagram of the states of a driving voltage, a synchronization signal, an asynchronous signal, a wake-up signal, a pixel voltage, and a common voltage according to another embodiment of the present application. Figure 7 A screen presentation of a display panel corresponding to

[0017] Figure 10 A waveform diagram of the states of a driving voltage, a synchronization signal, an asynchronous signal, a wake-up signal, a pixel voltage, and a common voltage according to another embodiment of the present application.

[0018] Figure 11 A screen presentation of a display panel corresponding to Figure 10 A screen presentation of a display panel corresponding to

[0019] Figure 12 A schematic diagram of a display control circuit according to a third embodiment of the present application.

[0020] Figure 13 A waveform diagram of the states of a driving voltage, a synchronization signal, an asynchronous signal, a polarity signal, a pixel voltage, and a common voltage according to an embodiment of the present application.

[0021] Figure 14 A schematic diagram of a pixel of a display panel performing dot inversion according to an embodiment of the present application.

[0022] Figure 15 A screen presentation of a display panel corresponding to Figure 13 A screen presentation of a display panel corresponding to

[0023] Figure 16 A schematic diagram of a display control circuit according to a fourth embodiment of the present application.

[0024]

SYMBOL DESCRIPTION

[0025] 1: display control circuit

[0026] 10: timing controller

[0027] 100: timing control unit

[0028] 101: time detector

[0029] 11: display driver

[0030] 110, 110': data detection circuit

[0031] 111, 111': amplification circuit

[0032] 112, 112': output switching circuit

[0033] 113, 113': display controller

[0034] 114: counter

[0035] 115: time detector

[0036] DL: data line

[0037] SL: scan line

[0038] SW: transistor switch

[0039] CPIX: pixel liquid crystal capacitor

[0040] VCOM: common voltage

[0041] D: input data

[0042] VOUT: driving voltage

[0043] VPIX: pixel voltage

[0044] LOCK: synchronization signal

[0045] UNLOCK: non-synchronization signal

[0046] VW: wake-up signal

[0047] T1, T2, T3, T2': time period

[0048] S10, S12, S14, S16: step

[0049] P: display panel

[0050] U1: display driving unit

[0051] U2: time detecting unit

[0052] CV: count value

[0053] POL: polarity signal DETAILED DESCRIPTION

[0054] Embodiments of the present application will be described further with reference to the following drawings. In the drawings and specification, identical reference numerals have been used to designate identical elements. In the drawings, the shapes and thicknesses can be exaggerated for the sake of convenience and simplicity in explanation. It is to be understood that the elements illustrated in the drawings and described in the specification are intended to exemplify the form of the present application and that many other modifications can be made within the scope of the present application.

[0055] Unless specifically stated otherwise, some of the conditions or words, such as "can," "could," "might," or "may," generally occurred in the context of an embodiment of the present application. These conditions or words, however, are not intended to mean that a particular feature, element, or step is required or necessary in every embodiment or that a particular embodiment can not utilize alternative or optional features, elements, or steps. In other embodiments, these features, elements, or steps can be optional.

[0056] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular structures, materials, or features being described in one or more embodiments can be combined in any suitable manner in other embodiments. It is intended that the specification and examples be considered as exemplary only, with the true scope of the application being indicated by the following claims.

[0057] Certain terms are used throughout the description and claims to refer to particular elements. However, the terms as used in the specification and claims should not be construed as specific to one or the other. Rather, the terms are used only in their broadest and most general sense to refer to the function of the element to which the terms are used. The specification and claims should not be construed as indicating any special significance to the use of particular terms.

[0058] The disclosure is specifically described by the following examples, which are merely illustrative. Various modifications and refinements can be made by those skilled in the art without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure is determined by the appended claims. Throughout the specification and claims, unless explicitly specified, the words “a” and “described” mean that such a statement includes “a or at least one” of the stated elements or components. Furthermore, as used in this disclosure, the singular article also includes a statement of multiple elements or components unless clearly excluded from the specific context. Moreover, when applied in this description and all the following claims, unless explicitly specified, “in which” means both “in which” and “therein”. The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meaning in the art, in the content of this disclosure, and in the specific context. Certain terms used to describe this disclosure will be discussed below or elsewhere in this specification to provide additional guidance to a practitioner in describing this disclosure. Examples throughout this specification, including examples of any terms discussed herein, are for illustrative purposes only and do not limit the scope or meaning of this disclosure or any of the illustrative terms. Similarly, this disclosure is not limited to the various embodiments set forth in this specification.

[0059] The following description describes a display control circuit and its control method for detecting noise interference. The circuit executes a noise interference mode or a crash reset mode based on a preset time interval and a time interval of an asynchronous signal, thereby avoiding screen abnormalities and image burn-in. The asynchronous signal indicates that the timing controller and the display driver are out of sync.

[0060] Figure 1 This is a schematic diagram of a display control circuit according to a first embodiment of the present invention. Figure 2 This is a schematic diagram of a pixel equivalent circuit according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1 and Figure 2 The first embodiment of the display control circuit 1 is described below. The display control circuit 1 includes a timing controller 10 and a display driver 11. The display driver 11 is coupled to the timing controller 10 and a data line DL. The data line DL and the scan line SL are coupled to a transistor switch SW. The transistor switch SW is coupled to a common voltage VCOM through a pixel liquid crystal capacitor CPIX having a common electrode. The pixel liquid crystal capacitor CPIX includes a liquid crystal capacitor and a storage capacitor coupled in parallel.

[0061] The display driver 11 receives the input data D from the timing controller 10 to generate the driving voltage VOUT. The driving voltage VOUT is applied to the data line DL to generate the pixel voltage VPIX between the transistor switch SW and the pixel liquid crystal capacitor CPIX. The display driver 11 can set the synchronization signal LOCK, which indicates that the timing controller 10 is synchronized with the display driver 11 in the normal state. Alternatively, when the display driver 11 detects the noise disturbance, the display driver 11 can set the unsynchronization signal UNLOCK, which indicates that the timing controller 10 is not synchronized with the display driver 11. The display driver 11 transmits the synchronization signal LOCK or the unsynchronization signal UNLOCK to the timing controller 10. The timing controller 10 provides the wake-up signal VW to the display driver 11 according to the preset time interval and the time interval of the unsynchronization signal UNLOCK. The preset time interval can be, but is not limited to, the time interval of enabling at least one scan line SL, the time interval of sequentially enabling a plurality of scan lines SL, or the time interval of displaying at least one image frame.

[0062] Figure 3 Fig. 1 is a schematic diagram of the waveforms of the state of the driving voltage, the synchronization signal, the unsynchronization signal, the wake-up signal, the pixel voltage, and the common voltage according to an embodiment of the present application. Please refer to Figs. 1, 2, 3, and 4. Figure 1 Figure 2 Figure 3 Figs. 2, 3, and 4 are schematic diagrams of the waveforms of the state of the driving voltage, the synchronization signal, the unsynchronization signal, the wake-up signal, the pixel voltage, and the common voltage according to different embodiments of the present application. Please refer to Figs. 1, 2, 3, and 4. The time periods Tl, T2, and T3 occur sequentially. In the time period Tl, the display driver 11 sets the synchronization signal LOCK to the high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the wake-up signal VW is at the high voltage level, and the driving voltage VOUT is from the normal data. In the time period T2, the display driver 11 sets the unsynchronization signal UNLOCK to the low voltage level. In the time period T2, the timing controller 10 judges that the time interval of the unsynchronization signal UNLOCK is less than the preset time interval, so that the display driver 11 performs the noise disturbance mode, and the wake-up signal VW is still at the high voltage level. In the noise disturbance mode, the display driver 11 can maintain the last driving voltage VOUT before the unsynchronization signal UNLOCK occurs for the time interval of the unsynchronization signal UNLOCK. The last driving voltage VOUT corresponds to the last data. The pixel voltage VPIX and the common voltage VCOM are represented by the solid line and the dashed line, respectively. In the time period T3, the display driver 11 sets the synchronization signal LOCK to the high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the wake-up signal VW is still at the high voltage level, and the display driver 11 receives the input data D from the timing controller 10 to generate the new driving voltage VOUT from the normal data.

[0063] ​​In an embodiment of the present application, the timing controller 10 can include, but is not limited to, a timing control unit 100 and a time detector 101. The timing control unit 100 is coupled to the display driver 11, and the time detector 101 is coupled to the timing control unit 100 and the display driver 11. The timing control unit 100 generates input data D. The time detector 101 receives a synchronization signal LOCK or an unsynchronization signal UNLOCK, stores a preset time interval, and determines a time interval of the unsynchronization signal UNLOCK. The time detector 101 provides a wake-up signal VW to the display driver 11 according to the preset time interval and the time interval of the unsynchronization signal UNLOCK.

[0064] In an embodiment of the present application, the display driver 11 can include, but is not limited to, a data detection circuit 110, an amplification circuit 111, an output switching circuit 112, and a display controller 113. The amplification circuit 111 is coupled to the data detection circuit 110, the output switching circuit 112, and the display controller 113. The display controller 113 is coupled to the output switching circuit 112 and the time detector 101. The data detection circuit 110 is coupled to the timing control unit 100 and the time detector 101. The output switching circuit 112 is coupled to a data line DL. The data detection circuit 110 receives the input data D to set the synchronization signal LOCK or the unsynchronization signal UNLOCK, and transmits the synchronization signal LOCK or the unsynchronization signal UNLOCK to the time detector 101. The data detection circuit 110, the amplification circuit 111, and the output switching circuit 112 receive the input data D to generate a driving voltage VOUT. The display controller 113 receives the wake-up signal VW to control the amplification circuit 111 and the output switching circuit 112.

[0065] Figure 4 A flow chart of a control method of a display control circuit according to a first embodiment of the present application is shown in FIG. 10. Referring to FIGS. 10 and 11, Figure 1 、 Figure 3 and Figure 4 The first embodiment of the control method is described as follows. In step S10, the display driver 11 sets the synchronization signal LOCK or the unsynchronization signal UNLOCK. When the display driver 11 sets the synchronization signal LOCK, step S12 is performed. In step S12, the display driver 11 outputs the driving voltage VOUT from normal data. After step S12, the process returns to step S10. When the display driver 11 sets the unsynchronization signal UNLOCK, step S14 is performed. In step S14, when the time interval of the unsynchronization signal UNLOCK is less than the preset time interval, the display driver 11 performs a noise interference mode. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT for the time interval of the unsynchronization signal UNLOCK. After step S14, the process returns to step S10. As long as substantially the same results can be achieved,Figure 4 The steps of the flowchart shown do not have to be followed in the order shown, nor do they have to be continuous, that is, other steps can be interposed.

[0066] Figure 5 For corresponding Figure 3 schematic diagram of screen presentation of display panel. Please refer to Figure 3 and Figure 5 , the left display panel P displays the window in time periods T1 and T2, and the right display panel P displays the window in time period T3. Therefore, the screen presentation of the left display panel P is the same as that of the right display panel P. Thus, this control method can avoid the situation of screen abnormality after detecting noise interference in a short time.

[0067] Figure 6 For the schematic diagram of the display control circuit according to the second embodiment of the present application. Please refer to Figure 6 and Figure 2 , the second embodiment of the display control circuit 1 is introduced as follows. The display control circuit 1 comprises a timing controller 10 and a display driver 11. The display driver 11 is coupled to the timing controller 10 and the data line DL.

[0068] The display driver 11 receives the input data D from the timing controller 10 to generate the driving voltage VOUT. The driving voltage VOUT is applied to the data line DL to generate the pixel voltage VPIX between the transistor switch SW and the pixel liquid crystal capacitor CPIX. The display driver 11 can set the synchronization signal LOCK to indicate that the timing controller 10 and the display driver 11 are synchronized in the normal state. Alternatively, when the display driver 11 detects noise interference, the display driver 11 can set the non-synchronization signal UNLOCK to indicate that the timing controller 10 and the display driver 11 are not synchronized. The display driver 11 transmits the synchronization signal LOCK or the non-synchronization signal UNLOCK to the timing controller 10. The display driver 11 judges the time interval of the non-synchronization signal UNLOCK by itself. The display driver 11 generates the wake-up signal VW in itself according to the preset time interval and the time interval of the non-synchronization signal UNLOCK. The preset time interval can be, but is not limited to, the time interval of enabling at least one scan line SL, the time interval of sequentially enabling a plurality of scan lines SL, or the time length of displaying at least one image frame.

[0069] Please refer to Figure 6 , Figure 2 and Figure 3, time periods Tl, T2 and T3 occur sequentially. In time period Tl, the display driver 11 sets the synchronization signal LOCK to a high voltage and transmits the synchronization signal LOCK to the timing controller 10. At the same time, the wake-up signal VW is at a high voltage and the driving voltage VOUT is from normal data. In time period T2, the display driver 11 sets the non-synchronization signal UNLOCK to a low voltage. In time period T2, the display driver 11 determines that the time interval of the non-synchronization signal UNLOCK is less than a preset time interval, so that the display driver 11 executes a noise interference mode, and the wake-up signal VW is still at a high voltage. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT for the time interval of the non-synchronization signal UNLOCK. In time period T3, the display driver 11 sets the synchronization signal LOCK to a high voltage and transmits the synchronization signal LOCK to the timing controller 10. At the same time, the wake-up signal VW is still at a high voltage, and the display driver receives the input data D from the timing controller 10 to generate a new driving voltage VOUT from normal data.

[0070] In an embodiment of the present application, the display driver 11 can include, but is not limited to, a display driving unit U1 and a time detection unit U2. The display driving unit U1 is coupled to the timing controller 10 and the time detection unit U2. The display driving unit U1 receives the input data D to set the synchronization signal LOCK or the non-synchronization signal UNLOCK and transmits the synchronization signal LOCK or the non-synchronization signal UNLOCK to the timing controller 10 and the time detection unit U2. The time detection unit U2 has an independent power supply. The time detection unit U2 determines the time interval of the non-synchronization signal UNLOCK and provides the wake-up signal VW to the display driving unit U1 according to the time interval of the non-synchronization signal UNLOCK and the preset time interval. When the display driving unit U1 sets the non-synchronization signal UNLOCK, the display driving unit U1 does not affect the time detection unit U2 to determine the time interval of the non-synchronization signal UNLOCK because the time detection unit U2 has an independent power supply.

[0071] In an embodiment of the present application, the display driving unit U1 can include, but is not limited to, a data detection circuit 110', an amplification circuit 111', an output switching circuit 112', and a display controller 113'. The amplification circuit 111' is coupled to the data detection circuit 110', the output switching circuit 112', and the display controller 113'. The display controller 113' is coupled to the output switching circuit 112' and the time detection unit U2. The data detection circuit 110' is coupled to the time sequence controller 10 and the time detection unit U2. The output switching circuit 112' is coupled to the data line DL. The data detection circuit 110' receives the input data D to set the synchronization signal LOCK or the non-synchronization signal UNLOCK, and transmits the synchronization signal LOCK or the non-synchronization signal UNLOCK to the time sequence controller 10 and the time detection unit U2. The data detection circuit 110', the amplification circuit 111', and the output switching circuit 112' receive the input data D to generate the driving voltage VOUT. The display controller 113' receives the wake-up signal VW to control the amplification circuit 111' and the output switching circuit 112'.

[0072] In an embodiment of the present application, the time detection unit U2 can include, but is not limited to, a counter 114 and a time detector 115. The time detector 115 is coupled to the counter 114 and the data detection circuit 110'. Since the counter 114 has an independent power supply, the counter 114 can provide the count value CV. The time detector 115 receives the synchronization signal LOCK and the non-synchronization signal UNLOCK and the count value CV, and determines the time interval of the non-synchronization signal UNLOCK according to the count value CV, and provides the wake-up signal VW to the display controller 113' according to the preset time interval and the time interval of the non-synchronization signal UNLOCK.

[0073] Figure 7 The waveforms of the state of the driving voltage, the synchronization signal, the non-synchronization signal, the wake-up signal, the pixel voltage, and the common voltage according to another embodiment of the present application are shown in FIG. 4. Please refer to Figure 1 、 Figure 2 and Figure 7, the time periods Tl, T2 and T2' occur sequentially. In the time period Tl, the display driver 11 sets the synchronization signal LOCK to a high voltage and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the wake-up signal VW is at a high voltage and the driving voltage VOUT is from normal data. In the time period T2, the display driver 11 sets the non-synchronization signal UNLOCK to a low voltage. In the time period T2, the timing controller 10 judges that the time interval of the non-synchronization signal UNLOCK is less than the preset time interval, so that the display driver 11 executes the noise interference mode and the wake-up signal VW is still at a high voltage. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT for the time interval of the non-synchronization signal UNLOCK. In the time period T2', and after the noise interference mode, the timing controller 10 judges that the time interval of the non-synchronization signal UNLOCK is greater than or equal to the preset time interval, so that the display driver 11 executes the crash reset mode and the wake-up signal VW has a negative pulse. In the crash reset mode, the display driver 11 can adjust the output driving voltage VOUT to be equal to the common voltage VCOM applied to the common electrode of the pixel liquid crystal capacitor CPIX. Therefore, the pixel voltage VPIX is finally equal to the common voltage VCOM.

[0074] In some embodiments of the present application, the display controller 113 receives the negative pulse of the wake-up signal VW to control the amplification circuit 111 and the output switching circuit 112, so as to adjust the output driving voltage VOUT to be equal to the common voltage VCOM applied to the common electrode of the pixel liquid crystal capacitor, and display a black screen.

[0075] Figure 8 A flow chart of a control method for the display control circuit according to the second embodiment of the present application. Please refer to Figure 1 、 Figure 7 and Figure 8 The second embodiment of the control method is introduced as follows. The steps S10, S12 and S14 have been described above, so they will not be described again here. After the step S14, the step S16 is executed. In the step S16, when the time interval of the non-synchronization signal UNLOCK is greater than or equal to the preset time interval, the display driver 11 executes the crash reset mode. In the crash reset mode, the display driver 11 can adjust the output driving voltage VOUT to be equal to the common voltage VCOM. After the step S16, return to the step S10. As long as basically the same results can be achieved, Figure 8 The steps of the flow chart shown in the figure do not have to follow the order shown strictly, nor have to be continuous, that is, there can be other steps in between.

[0076] Figure 9 A schematic diagram of the screen presentation of the display panel corresponding to Figure 7 Please refer toFigure 7 With Figure 9 The left display panel P displays a window in time periods Tl and T2, and the right display panel P displays a black screen in time period T2'. Thus, this control method can continuously display a black screen to avoid the afterimage imprint and polarization phenomenon when noise interference is detected for a long time.

[0077] Figure 10 Fig. 6 is a waveform diagram of the driving voltage, the synchronization signal, the unsynchronization signal, the wake-up signal, the pixel voltage and the common voltage according to another embodiment of the present application. Please refer to Figure 1 , Figure 2 With Figure 10 The time periods Tl, T2, T2' and T3 occur in sequence. In time period Tl, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the wake-up signal VW is at a high voltage level, and the driving voltage VOUT is from normal data. In time period T2, the display driver 11 sets the unsynchronization signal UNLOCK to a low voltage level. In time period T2, the timing controller 10 determines that the time interval of the unsynchronization signal UNLOCK is less than a preset time interval, so that the display driver 11 executes the noise interference mode, and the wake-up signal VW is still at a high voltage level. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT in time period T2. In time period T2' and after the noise interference mode, the timing controller 10 determines that the time interval of the unsynchronization signal UNLOCK is greater than or equal to the preset time interval, so that the display driver 11 executes the crash reset mode, and the wake-up signal VW has a negative pulse. In the crash reset mode, the display driver 11 can adjust the output driving voltage VOUT to be equal to the common voltage VCOM applied to the common electrode of the pixel liquid crystal capacitor CPIX until the end of the time interval of the unsynchronization signal UNLOCK. In time period T3, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the wake-up signal VW is still at a high voltage level, and the display driver receives the input data D from the timing controller 10 to generate a new driving voltage VOUT from normal data.

[0078] In some embodiments of the present application, the display controller 113 receives the negative pulse of the wake-up signal VW to control the amplification circuit 111 and the output switching circuit 112 to adjust the output driving voltage VOUT to be equal to the common voltage VCOM applied to the common electrode of the pixel liquid crystal capacitor CPIX until the end of the time interval of the unsynchronization signal UNLOCK.

[0079] Figure 11 Fig. 7 is a waveform diagram of the driving voltage, the synchronization signal, the unsynchronization signal, the wake-up signal, the pixel voltage and the common voltage according to another embodiment of the present application. Please refer to Figure 10a schematic diagram of a screen presented by a display panel of the display device. Please refer to Figure 10 With reference to Figure 11 , the left display panel P displays a view window in time periods T1 and T2, the middle display panel P displays a black picture in time period T2', and the right display panel P displays a view window in time period T3. Therefore, this control method can avoid the afterimage imprint and polarization phenomenon after detecting noise interference for a long time.

[0080] Figure 12 a schematic diagram of a display control circuit according to a third embodiment of the present application. Please refer to Figure 12 With reference to Figure 1 , the third embodiment of the display control circuit will be introduced as follows. Figure 12 The third embodiment of the present application is different from the first embodiment of the present application in that Figure 1 The third embodiment of the present application uses a polarity signal POL to replace the wake-up signal VW of the first embodiment of the present application. Figure 12 The remaining features of the third embodiment of the present application have been described above, and thus will not be described here again. Figure 1 Figure 12

[0081] Figure 13 ​​Fig. 1 is a schematic diagram of waveforms of a driving voltage, a synchronization signal, an unsynchronization signal, a polarity signal, a pixel voltage and a common voltage according to an embodiment of the present application. Time periods Tl, T2, T2' and T3 occur sequentially. In time period Tl, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the polarity signal POL can be, but is not limited to, an alternating normal square wave signal, and the driving voltage VOUT outputted from normal data. In time period T2, the display driver 11 sets the unsynchronization signal UNLOCK to a low voltage level. In time period T2, the display driver 11 sets the unsynchronization signal UNLOCK to a low voltage level. In time period T2, the timing controller 10 judges that the time interval of the unsynchronization signal UNLOCK is less than a preset time interval, so that the display driver 11 performs a noise interference mode, and the polarity signal POL can still be an alternating normal square wave signal. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT in time period T2. In time period T2', and after the noise interference mode, the timing controller 10 judges that the time interval of the unsynchronization signal UNLOCK is greater than or equal to the preset time interval, so that the display driver 11 performs a crash reset mode, and the polarity signal POL is an alternating control square wave signal. In the crash reset mode, the display driver 11 can repeatedly change the polarity of the driving voltage VOUT outputted at the time when the unsynchronization signal UNLOCK occurs until the time interval of the unsynchronization signal UNLOCK ends. When the polarity of the driving voltage VOUT changes, the polarity of the pixel voltage VPIX also changes. Therefore, the average value of the pixel voltage VPIX is almost zero to avoid the polarization phenomenon in time period T2'. In time period T3, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the polarity signal POL is still an alternating normal square wave signal, and the display driver 11 receives the input data D from the timing controller 10 to generate a new driving voltage VOUT from normal data.

[0082] In some embodiments of the present application, the display controller 113 receives the polarity signal POL as an alternating control square wave signal to control the amplification circuit 111 and the output switching circuit 112 to repeatedly change the polarity of the driving voltage VOUT outputted until the time interval of the unsynchronization signal UNLOCKL ends.

[0083] Figure 14 Fig. 2 is a schematic diagram of a pixel of a display panel performing dot inversion according to an embodiment of the present application. Please refer to Figure 14The display panel P has 42 pixels, each with a positive or negative polarity. The display panel P can perform row inversion, column inversion, frame inversion, or dot inversion, but the invention is not limited thereto. For example, when the display panel P performs dot inversion to display at least one image frame, the positive and negative polarities of the pixels are changed to negative and positive polarities respectively in the next image frame. The time interval for displaying one image frame is equal to the time interval for sequentially enabling all scan lines of the display panel P.

[0084] Figure 15 For the corresponding Figure 13 This is a schematic diagram of the display panel screen. Please refer to [link / reference]. Figure 13 and Figure 15 The left display panel P shows windows during time periods T1 and T2, the middle display panel P shows the image with polarity changes during time period T2', and the right display panel P shows windows during time period T3. Therefore, this control method can avoid image retention and polarization phenomena after prolonged detection of noise interference.

[0085] Figure 16 This is a schematic diagram of a display control circuit according to a fourth embodiment of the present invention. Please refer to [link / reference]. Figure 16 and Figure 6 The following describes a fourth embodiment of the display control circuit. Figure 16 The fourth embodiment and Figure 6 The difference in the second embodiment is that Figure 16 The fourth embodiment uses a polarity signal POL to replace Figure 6 The wake-up signal VW in the second embodiment. Figure 16 The remaining features have been described above, so they will not be repeated here.

[0086] Please see Figure 13 , Figure 2 and Figure 16, time periods Tl, T2, T2' and T3 occur sequentially. In time period Tl, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the polarity signal POL can be, but is not limited to, an alternating normal square wave signal, and the driving voltage VOUT comes from normal data. In time period T2, the display driver 11 sets the unsynchronized signal UNLOCK to a low voltage level. In time period T2, the display driver 11 judges that the time interval of the unsynchronized signal UNLOCK is less than a preset time interval, so that the display driver 11 executes a noise interference mode, and the polarity signal POL can still be an alternating normal square wave signal. In the noise interference mode, the display driver 11 can maintain the last driving voltage VOUT in time period T2. In time period T2', and after the noise interference mode, the display driver 11 judges that the time interval of the unsynchronized signal UNLOCK is greater than or equal to the preset time interval, so that the display driver 11 executes a crash reset mode, and the polarity signal POL is an alternating control square wave signal. In the crash reset mode, the display driver 11 can repeatedly change the polarity of the output driving voltage VOUT until the time interval of the unsynchronized signal UNLOCK ends. Therefore, the average value of the pixel voltage VPIX is almost zero to avoid the polarization phenomenon in time period T2'. In time period T3, the display driver 11 sets the synchronization signal LOCK to a high voltage level and transmits the synchronization signal LOCK to the timing controller 10. Meanwhile, the polarity signal POL is still an alternating normal square wave signal, and the display driver 11 receives the input data D from the timing controller 10 to generate a new driving voltage VOUT from normal data.

[0087] In some embodiments of the present application, the display controller 113' receives the polarity signal POL as an alternating control square wave signal to control the amplification circuit 111' and the output switching circuit 112', thereby repeatedly changing the polarity of the output driving voltage VOUT until the time interval of the unsynchronized signal UNLOCK ends.

[0088] According to the above-provided embodiments, the display control circuit for detecting noise interference and the control method thereof execute a noise interference mode or a crash reset mode according to the preset time interval and the time interval of the unsynchronized signal, which indicates that the timing controller and the display driver are not synchronized, thereby avoiding abnormal screen and residual image imprinting.

[0089] The above descriptions are only some preferred embodiments of the present application and are not intended to limit the scope of the present application. Any equivalent changes and modifications made according to the shapes, structures, features and spirits described in the claims of the present application should be included in the scope of protection of the present application.

Claims

1. A control method for a display control circuit, the display control circuit comprising a timing controller and a display driver, characterized in that, The control method includes the following steps: A desynchronization signal is set, which indicates that the timing controller and the display driver are not synchronized; When the time interval of the asynchronous signal is shorter than a preset time interval, a noise interference mode is executed; and After executing the noise interference mode, and when it is determined that the time interval of the asynchronous signal is equal to or greater than the preset time interval, the crash reset mode is executed.

2. The control method as described in claim 1, characterized in that, In the noise interference mode, the last drive voltage prior to the occurrence of the asynchronous signal is maintained for the duration of the asynchronous signal.

3. The control method as described in claim 1, characterized in that, In the crash reset mode, the output drive voltage is adjusted to be equal to the common voltage applied to the common electrode until the time interval of the asynchronous signal ends.

4. The control method as described in claim 1, characterized in that, In the crash reset mode, the polarity of the output drive voltage changes repeatedly until the time interval of the asynchronous signal ends.

5. The control method as described in claim 1, characterized in that, The preset time interval is the time interval during which at least one scan line is enabled or at least one image frame is displayed.

6. A display control circuit, characterized in that, The display control circuit includes: Timing controller; and The display driver is coupled to the timing controller and is used to set an asynchronous signal, which indicates that the timing controller and the display driver are out of sync; When the timing controller determines that the time interval of the asynchronous signal is less than a preset time interval, the display driver executes a noise interference mode. After executing the noise interference mode, and when the timing controller determines that the time interval of the asynchronous signal is equal to or greater than the preset time interval, the display driver executes the crash reset mode.

7. The display control circuit as described in claim 6, characterized in that, In the noise interference mode, the display driver maintains the last drive voltage prior to the occurrence of the asynchronous signal for the duration of the asynchronous signal.

8. The display control circuit as described in claim 6, characterized in that, In the crash reset mode, the display driver adjusts the output drive voltage to be equal to the common voltage applied to the common electrode until the time interval of the asynchronous signal ends.

9. The display control circuit as described in claim 6, characterized in that, In the crash reset mode, the display driver repeatedly changes the polarity of the output drive voltage until the time interval of the asynchronous signal ends.

10. The display control circuit as described in claim 6, characterized in that, The preset time interval is the time interval during which at least one scan line is enabled or at least one image frame is displayed.

11. The display control circuit as described in claim 6, characterized in that, The timing controller includes: A timing control unit, coupled to the display driver; and A time detector, coupled to the timing control unit and the display driver, is used to determine the time interval of the asynchronous signal.

12. A display control circuit, characterized in that, The display control circuit includes: Timing controller; and The display driver is coupled to the timing controller and is used to set an asynchronous signal, which indicates that the timing controller and the display driver are out of sync; When the display driver determines that the time interval of the asynchronous signal is less than a preset time interval, the display driver executes a noise interference mode; After executing the noise interference mode, and when the display driver determines that the time interval of the asynchronous signal is equal to or greater than the preset time interval, the display driver executes the crash reset mode.

13. The display control circuit as described in claim 12, characterized in that, In the noise interference mode, the display driver maintains the last drive voltage prior to the occurrence of the asynchronous signal for the duration of the asynchronous signal.

14. The display control circuit as described in claim 12, characterized in that, In the crash reset mode, the display driver adjusts the output drive voltage to be equal to the common voltage applied to the common electrode until the time interval of the asynchronous signal ends.

15. The display control circuit as described in claim 12, characterized in that, In the crash reset mode, the display driver repeatedly changes the polarity of the output drive voltage until the time interval of the asynchronous signal ends.

16. The display control circuit as described in claim 12, characterized in that, The preset time interval is the time interval during which at least one scan line is enabled or at least one image frame is displayed.

17. The display control circuit as described in claim 12, characterized in that, The display driver includes: A display driving unit, coupled to the timing controller, is used to set the asynchronous signal; and A time detection unit is coupled to the display driving unit and is used to determine the time interval of the asynchronous signal.

18. The display control circuit as described in claim 17, characterized in that, The time detection unit includes: A counter, used to provide a count value; and A time detector is coupled to the counter and the display driving unit, and is used to determine the time interval of the asynchronous signal based on the count value.

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