Method of operating memory device and related apparatus

Abstract

The invention relates to a method of operating a memory device and a related apparatus. A method of operating a memory device includes: reading a first logic page with a first set of read voltage levels to obtain a first read result; reading the first logic page with a second set of read voltage levels having a first offset relative to the first set of read voltage levels to obtain a second read result; reading the first logic page with a third set of read voltage levels having a second offset different from the first offset relative to the first set of read voltage levels to obtain a third read result; reading a second logical page different from the first logical page with a fourth set of read voltage levels to obtain a fourth read result; a set of optimal read voltage levels is determined for the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and more specifically, to a method of operating a memory device, a memory device, a memory controller and a memory system. BACKGROUND

[0002] Memory devices, such as NAND flash memory, are low cost, high density, nonvolatile solid-state storage media that can be electrically erased and reprogrammed. A memory device includes an array of memory cells. A memory cell is read by comparing the voltage stored by the memory cell to a read voltage used. For example, a memory cell whose voltage is below the read voltage can be considered to store a bit (or, bit) "1", while a memory cell whose voltage is above the read voltage can be considered to store a bit "0". SUMMARY

[0003] A brief summary of the present disclosure is presented in the following for the purpose of providing a basic understanding of some aspects of the present disclosure. However, this summary is not an extensive overview of the present disclosure. It is not intended to identify key or critical elements of the present disclosure or to delineate the scope of the present disclosure. Its sole purpose is to present some concepts of the present disclosure in a simplified form as a prelude to the more detailed description that is presented later.

[0004] According to a first aspect of the present disclosure, there is provided a method of operating a memory device, comprising:

[0005] performing a read operation on a first logical page in the memory device using a first set of read voltage levels for respective read voltages corresponding to the first logical page to obtain a first read result for the first logical page;

[0006] performing a read operation on the first logical page using a second set of read voltage levels for respective read voltages corresponding to the first logical page to obtain a second read result for the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;

[0007] performing a read operation on the first logical page using a third set of read voltage levels for respective read voltages corresponding to the first logical page to obtain a third read result for the first logical page, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset;

[0008] performing a read operation on the first logical page with a second set of read voltage levels corresponding to the respective order of read voltages for the first logical page to obtain a second read result of the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;

[0009] determining a set of optimal read voltage levels for the respective order of read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

[0010] According to a second aspect of the present disclosure, there is provided a memory device, comprising:

[0011] a memory cell array; and

[0012] a peripheral circuit coupled to the memory cell array and configured to perform the method according to the first aspect of the present disclosure.

[0013] According to a third aspect of the present disclosure, there is provided a memory system, comprising:

[0014] a memory controller; and

[0015] a memory device coupled to the memory controller and comprising a memory cell array and a peripheral circuit coupled to the memory cell array and configured to perform the following operations:

[0016] performing a read operation on a first logical page in the memory cell array with a first set of read voltage levels corresponding to the respective order of read voltages for the first logical page to obtain a first read result of the first logical page;

[0017] performing a read operation on the first logical page with a second set of read voltage levels corresponding to the respective order of read voltages for the first logical page to obtain a second read result of the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;

[0018] performing a read operation on the first logical page with a third set of read voltage levels corresponding to the respective order of read voltages for the first logical page to obtain a third read result of the first logical page, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset;

[0019] performing a read operation on a second logical page in the memory cell array with a fourth set of read voltage levels corresponding to the respective order of read voltages for the second logical page to obtain a fourth read result of the second logical page, the second logical page being different from the first logical page; and

[0020] Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

[0021] According to a fourth aspect of this disclosure, a memory controller is provided for controlling a memory device, the memory controller comprising:

[0022] A memory interface for connecting the memory controller to the memory device;

[0023] Processor; and

[0024] A memory coupled to the processor and storing instructions, which, when executed by the processor, cause the processor to perform the following operations:

[0025] The memory interface is instructed to send a first read command to the memory device to perform a read operation on the first logic page using a first set of read voltage levels for each level of read voltage corresponding to the first logic page in the memory device, and to receive a first read result of the first logic page from the memory device;

[0026] The memory interface is instructed to send a second read command to the memory device to perform a read operation on the first logic page using a second set of read voltage levels for each level of read voltage corresponding to the first logic page, and to receive a second read result of the first logic page from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;

[0027] The memory interface is instructed to send a third read command to the memory device to perform a read operation on the first logic page using a third set of read voltage levels for each level of read voltage corresponding to the first logic page, and to receive a third read result of the first logic page from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset;

[0028] The memory interface is instructed to send a fourth read command to the memory device to perform a read operation on the second logic page using a fourth set of read voltage levels for each read voltage level corresponding to the second logic page in the memory device, and to receive the fourth read result of the second logic page from the memory device, wherein the second logic page is different from the first logic page; and

[0029] determine a set of optimal read voltage levels for the step read voltages corresponding to the first logical page based on the first read results, the second read results, the third read results, and the fourth read results.

[0030] According to a fifth aspect of the present disclosure, a memory system is provided, comprising:

[0031] a memory device; and

[0032] a memory controller coupled to the memory device and configured to perform the following operations:

[0033] send a first read command to the memory device to perform a read operation on a first logical page in the memory device with a first set of read voltage levels for step read voltages corresponding to the first logical page, and receive first read results of the first logical page from the memory device;

[0034] send a second read command to the memory device to perform a read operation on the first logical page with a second set of read voltage levels for the step read voltages corresponding to the first logical page, and receive second read results of the first logical page from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels;

[0035] send a third read command to the memory device to perform a read operation on the first logical page with a third set of read voltage levels for the step read voltages corresponding to the first logical page, and receive third read results of the first logical page from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset;

[0036] send a fourth read command to the memory device to perform a read operation on a second logical page in the memory device with a fourth set of read voltage levels for step read voltages corresponding to the second logical page, and receive fourth read results of the second logical page from the memory device, the second logical page being different from the first logical page; and

[0037] determine a set of optimal read voltage levels for the step read voltages corresponding to the first logical page based on the first read results, the second read results, the third read results, and the fourth read results.

[0038] According to a sixth aspect of the present disclosure, an electronic device is provided, comprising:

[0039] one or more processors; and

[0040] a memory coupled to the one or more processors and storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform the method according to the first aspect of the present disclosure.

[0041] According to a seventh aspect of the present disclosure, there is provided a non-transitory storage medium having stored thereon computer-executable instructions that, when executed by one or more processors, cause the one or more processors to perform the method according to the first aspect of the present disclosure.

[0042] According to an eighth aspect of the present disclosure, there is provided a computer program product comprising instructions that, when executed by a processor, implement the method according to the first aspect of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0043] The foregoing and other features and advantages of the present disclosure will become apparent to those skilled in the art from the following description of embodiments of the present disclosure, taken in conjunction with the accompanying drawings. The drawings are incorporated in and constitute a part of this specification, and are included for explanatory purposes. In the drawings:

[0044] Figure 1 A schematic block diagram of an exemplary system according to some embodiments of the present disclosure is shown;

[0045] Figure 2 A schematic diagram of an exemplary memory card and an exemplary solid state drive (SSD) according to some embodiments of the present disclosure is shown;

[0046] Figure 3 A schematic diagram of an exemplary memory device including a peripheral circuit according to some embodiments of the present disclosure is shown;

[0047] Figure 4 A schematic diagram of a cross-section of an exemplary memory cell array including a memory string according to some embodiments of the present disclosure is shown;

[0048] Figure 5 A schematic block diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to some embodiments of the present disclosure is shown;

[0049] Figure 6 A schematic block diagram of a memory controller according to some embodiments of the present disclosure is shown;

[0050] Figure 7 A distribution of threshold voltages of memory cells in a memory device according to some embodiments of the present disclosure is shown;

[0051] Figure 8A flowchart of a method for operating a memory device according to some embodiments of the present disclosure is shown;

[0052] Figure 9 A flowchart illustrating an exemplary process in which a method for operating a memory device according to an embodiment of the present disclosure is applied;

[0053] Figure 10 It shows in Figure 9 A diagram illustrating how the offset reading voltage level causes bit flipping during the process;

[0054] Figure 11 A flowchart is shown of another exemplary process in which a method for operating a memory device according to an embodiment of the present disclosure is applied;

[0055] Figure 12 It shows in Figure 11 A diagram illustrating how the offset reading voltage level causes bit flipping during the process;

[0056] Figure 13 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0057] Note that in the embodiments described below, the same reference numerals are sometimes used across different figures to denote the same parts or parts with the same function, and repeated descriptions are omitted. In some cases, similar reference numerals and letters are used to denote similar items, so once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0058] For ease of understanding, the positions, dimensions, and extents of the structures shown in the accompanying drawings and other materials may not represent actual positions, dimensions, and extents. Therefore, this disclosure is not limited to the positions, dimensions, and extents disclosed in the accompanying drawings and other materials. Detailed Implementation

[0059] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0060] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this disclosure or its application or use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in this disclosure. However, those skilled in the art will understand that they merely illustrate exemplary ways that can be used to implement this disclosure, and not exhaustive ways. Furthermore, the drawings are not necessarily drawn to scale, and some features may be enlarged to show details of specific components.

[0061] In addition, techniques, methods and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods and equipment should be considered part of the specification.

[0062] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0063] refer to Figure 1 , Figure 1 A schematic block diagram of an exemplary system 100 according to some embodiments of the present disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality device, augmented reality device, or any other suitable electronic device having a memory device therein. Figure 1 As shown, system 100 may include host 108 and memory system 102, which has one or more memory devices 104 and memory controller 106. Host 108 may be a processor (e.g., central processing unit (CPU)) or system-on-a-chip (SoC) (e.g., application processor (AP)). Host 108 may be configured to send data to or receive data from memory device 104.

[0064] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as an SSD or embedded multimedia card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) with respect to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0065] The memory controller 106 and the memory device(s) 104 can be integrated into various types of memory systems, such as included in the same package (e.g., a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In the case of a UFS package, the memory system 102 can be implemented and packaged into a smartphone, a tablet computer, a laptop computer, a digital camera, a digital camcorder, a digital audio player, a digital video player, a digital radio, a digital TV, a digital signage, a digital media player, a digital media adapter, a digital video recorder, a set-top box, a game console, a personal computer, a server, a network appliance, a network router, a network switch, a network bridge, a network hub, a network modem, a network interface controller, a network adapter, a network card, a network hub, a network switch, a network bridge, a network router, a network appliance, a network server, a network storage device, a network printer, a network fax machine, a network telephone, a network security appliance, a network firewall, a network intrusion prevention system, a network intrusion detection system, a network load balancer, a network load Figure 2In the example shown in part (A), the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in Figure 1 FIG. 1A). Figure 2 In another example shown in part (B), the memory controller 106 and the multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in Figure 1 FIG. 1A). In some embodiments, the SSD 206 has a larger storage capacity and / or a faster operating speed than the memory card 202.

[0066] Figure 3 A schematic diagram of an exemplary memory device 300 including a peripheral circuit is shown in accordance with some embodiments of the present disclosure. The memory device 300 can be an example of the memory device 104 in Figure 1 FIG. 1A. The memory device 300 can include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. The memory cell array 301 can be a NAND flash cell array in which memory cells 306 are provided in the form of an array of NAND storage strings 308 each extending vertically above a substrate (not shown). In some embodiments, each NAND storage string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, such as a voltage or a charge, that depends on the number of electrons trapped within a region of the memory cell 306. Each memory cell 306 can be a floating-gate type memory cell including a floating gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0067] Each memory cell 306 has any one of a plurality of storage states. Specifically, each memory cell 306 can be configured to store N bits of data in one of 2 N storage states, where N is an integer greater than 1. The 2 N storage states include an erased state and 2 N- 1 non-erased state. In some embodiments, each memory cell 306 can comprise a single-level cell (SLC) having two possible storage states (levels) and thus can store one bit of data. For example, a first storage state "0" can correspond to a first threshold voltage range, while a second storage state "1" can correspond to a second threshold voltage range. In some embodiments, each memory cell 306 can comprise an xLC capable of storing more than a single bit of data in equal to or more than four storage states (levels), such as, but not limited to, a dual-level cell (MLC) having four possible storage states (levels) and thus can store two bits of data, a triple-level cell (TLC) having eight possible storage states (levels) and thus can store three bits of data, a quad-level cell (QLC) having sixteen possible storage states (levels) and thus can store four bits of data, and the like. In some examples, a program operation is performed by writing one of three possible nominal storage values to an MLC memory cell to program the MLC memory cell from an erased state to one of three possible program levels (e.g., 01, 10, and 11). A fourth nominal storage value can be used to represent an erased state (e.g., 00).

[0068] As Figure 3 As shown in FIG. 1, each NAND memory string 308 can also include a source select gate (SSG) transistor 310 at its source end and a drain select gate (DSG) transistor 312 at its drain end. The SSG transistor 310 and the DSG transistor 312 can be configured to activate a selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some implementations, all NAND memory strings 308 in the same memory block 304 have array common source (ACS). In some embodiments, the drains of each NAND memory string 308 are coupled to a respective bit line 316 from which data can be read or written via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage or a deselect voltage to the gate of the respective DSG transistor 312 via one or more DSG lines 313 and / or by applying a select voltage or a deselect voltage to the gate of the respective SSG transistor 310 via one or more SSG lines 315.

[0069] As Figure 3As shown in FIG. 3, the NAND memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have, for example, a common source line 314 coupled to the ACS. In some embodiments, each memory block 304 can be a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (EV) (e.g., a high positive bias (e.g., 20V or greater)). The memory cells 306 adjacent to the NAND memory strings 308 can be coupled through word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a physical page(s) 320 of memory cells 306. For example, in the same memory block 304, the memory cells 306 coupled to the same word line 318 can constitute a plurality of physical pages 320. A physical page can be a basic unit of data for read and program operations. The size of one physical page 320 in bits can be related to the number of NAND memory strings 308 coupled by a word line 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in the corresponding physical page 320 and a gate line coupling the control gates.

[0070] A physical page refers to a physical organization structure of actual memory cells in a NAND flash memory, which usually includes a plurality of memory cells. A logical page is an abstraction layer seen by a user or a system or an application, which does not represent a physical unit of storing data, but a logical organization structure for managing data. In the management process of a NAND flash memory, a logical page is usually corresponding to a physical page through a mapping table. A logical page can be a basic unit of data for read and program operations.

[0071] As Figure 3 shown, the memory cell array 301 can include an array of memory cells 306 in a plurality of rows and a plurality of columns in each memory block 304. In some embodiments, a row of memory cells 306 corresponds to one or more physical pages 320, and a column of memory cells corresponds to one NAND memory string 308. The plurality of rows of memory cells 306 can be respectively coupled to a plurality of word lines 318, and the plurality of columns of memory cells 306 can be respectively coupled to a plurality of bit lines 316. The peripheral circuit 302 can be coupled to the memory cell array 301 through the bit lines 316 and the word lines 318.

[0072] Figure 4 A schematic diagram showing a cross-section of an exemplary memory cell array 301 including NAND memory strings 308 is shown in accordance with some embodiments of the present disclosure. AsFigure 4 As shown, the NAND memory string 308 can include a stack structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and the memory string 308 vertically penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be alternately stacked, and two adjacent gate layers 411 are separated by one insulating layer 412. The number of memory cells included in the memory cell array 301 can be determined based on the number of pairs of the gate layers 411 and the insulating layers 412 in the stack structure 410.

[0073] The constituent material of the gate layer 411 can include a conductive material. The conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate surrounding a memory cell. The gate layers 411 at the top of the stack structure 410 can laterally extend as upper select gate lines 413, the gate layers 411 at the bottom of the stack structure 410 can laterally extend as lower select gate lines 414, and the gate layers 411 laterally extending between the upper select gate lines and the lower select gate lines can serve as word line layers 403.

[0074] In some embodiments, the stack structure 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0075] Referring back to Figure 3 , the peripheral circuit 302 can be coupled to the memory cell array 301 through the bit lines 316, the word lines 318, the source lines 314, the SSG lines 315, and the DSG lines 313. The peripheral circuit 302 can include any suitable analog signal circuitry, digital signal circuitry, and mixed signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the SSG lines 315, and the DSG lines 313. The peripheral circuit 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5Some example peripheral circuitry is shown, including page buffer / sense amplifier 504, column decoder / bit line driver 506, row decoder / word line driver 508, voltage generator 510, control logic unit 512, registers 514, input / output circuitry 516, and data bus 518. It should be understood that additional peripheral circuitry not shown in FIG. 3 can also be included in some examples. Figure 5 Additional peripheral circuitry not shown in FIG. 3 can also be included.

[0076] Page buffer / sense amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic unit 512. In some examples, page buffer / sense amplifier 504 can store a page of program data (write data) to be programmed into one physical page 320 of memory cell array 301. In other examples, page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into memory cells 306 coupled to a selected word line 318. In yet other examples, page buffer / sense amplifier 504 can also sense low power signals from bit lines 316 representing data bits stored in memory cells 306 and amplify small voltage swings to identifiable logic levels in read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying bit line voltages generated from voltage generator 510.

[0077] Row decoder / word line driver 508 can be configured to be controlled by control logic unit 512 and select / deselect memory blocks 304 of memory cell array 301 and select / deselect word lines 318 of memory blocks 304. Row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, row decoder / word line driver 508 can also select / deselect and drive SSG lines 315 and DSG lines 313. Row decoder / word line driver 508 can be configured to perform erase operations on memory cells 306 coupled to selected word line(s) 318. Voltage generator 510 can be configured to be controlled by control logic unit 512 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0078] The control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic unit 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The input / output circuit 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic unit 512 and to buffer and relay status information received from the control logic unit 512 to the host. The input / output circuit 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data input / output interface and data buffer to buffer and relay data to or from the memory cell array 301.

[0079] Reference is made to Figure 6 FIG. 1 shows a schematic block diagram of a memory controller according to some embodiments of the present disclosure. As shown, the memory controller 106 (which can be the memory controller 106 of FIG. 1) includes a control logic unit 512, registers 514, and an input / output circuit 516. The control logic unit 512 can be coupled to each of the peripheral circuits described above and configured to control the operation of each of the peripheral circuits. The registers 514 can be coupled to the control logic unit 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuits. The input / output circuit 516 can be coupled to the control logic unit 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to the control logic unit 512 and to buffer and relay status information received from the control logic unit 512 to the host. The input / output circuit 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data input / output interface and data buffer to buffer and relay data to or from the memory cell array 301. Figure 6 Figure 1 ​The memory controller 106) can include a processor 1063 (such as, but not limited to, a central processing unit (CPU), a microprocessor (MPU), and the like) for controlling the general operation of the memory system 102. The memory controller 106 can include a memory 1065 (such as, but not limited to, a read-only memory (ROM)). The processor 1063 can be configured to execute program instructions stored in the memory 1065. The memory controller 106 can include a random access memory (RAM) 1066 in which the processor 1063 can store a work area and memory management information. The memory controller 106 can include a host interface (I / F) 1061 and a memory I / F 1062. The host I / F 1061 can include a data exchange protocol between the memory system 102 and the host 108. The memory I / F 1062 can connect the memory controller 106 with the memory device 104 and can communicate with the memory device 104 in compliance with an interface protocol. For example, the ONFI (Open NAND Flash Interface) protocol is an open interface standard for NAND flash memory. The memory controller 106 can instruct the memory I / F 1062 to transmit a command (e.g., a read command, and the like) to the memory device 104, the command being in a form compliant with the interface protocol specification and can include one or more command sequences. Further, the memory controller 106 can include an error correction module 1064 (such as, but not limited to, an error correction circuit (ECC)). The error correction module 1064 can detect an error of data read from the memory device 104 and correct the error. The processor 1063, the memory 1065, the RAM 1066, the host I / F 1061, the memory I / F 1062, and the error correction module 1064 of the memory controller 106 can be coupled together via a bus 1060.

[0080] Figure 7 A distribution of threshold voltages of exemplary memory cells in a memory device according to some embodiments of the disclosure is shown. While the following refers to Figure 7 An example where the memory cells are TLC is described, but embodiments of the disclosure are not limited thereto. For example, the memory cells can be various xLCs, such as MLC, QLC, and the like, or can be implemented in various other configurations. For example, when each of the memory cells stores N bits of data, the memory cells have 2 N states, and the states of the memory cells need to be determined using 2 N -1 order read voltages.

[0081] Referring to Figure 7 (A), the plurality of memory cells have an erase state E and first to seventh program states P1, P2, P3, P4, P5, P6, and P7. The seven (for TLC, N=3, 2 N-1=7) to determine the states of the plurality of memory cells. The first order read voltages RV can have a read voltage level RVL between two states. For example, the read voltage RV1 can have a read voltage level RVL1 between the erase state E and the first program state P1, and so on for the read voltages RV2 to RV7, which can have read voltage levels RVL2 to RVL7, respectively.

[0082] Under the control of a memory controller (such as the memory controller 106 in Figure 1 a memory device (such as the memory device 104 in Figure 1 Under the control of a memory controller (such as the memory controller 106 in

[0083] In TLC NAND flash, one physical page usually corresponds to three logical pages, i.e., a low page (LP), a middle page (MP), and a high page (UP). In Figure 7 In the non-limiting example of (A), the LP corresponds to the read voltages RV1, RV5, the MP corresponds to the read voltages RV2, RV4, RV6, and the UP corresponds to the read voltages RV3, RV7, of course other suitable configurations are possible. For example, when reading data of the low page from a memory cell, the read voltage RV1 is first applied to the word line where the memory cell is located for distinguishing the erase state E from the program states P1 to P7. Illustratively, the data in the memory cell whose threshold voltage level is less than the level RVL1 of the read voltage RV1 is read as 1, and the data in the memory cell whose threshold voltage level is greater than the level RVL1 of the read voltage RV1 is read as 0. Then, the read voltage RV5 is applied to the word line where the memory cell is located for distinguishing the erase state E, the program states P1 to P4, and the program states P5 to P7. Similarly, when reading data of the middle page and the high page from a memory cell, the data of the corresponding physical page can be obtained from the data of the low page, the middle page, and the high page.

[0084] Compared to Figure 7 The memory cells in the erase state E and the program states P1 to P7 in (A) have different threshold voltages. As shown in (B), the distribution of the threshold voltages of the memory cells can change over time after the memory cells are programmed due to physical characteristics of the memory cells or external factors such as stress, wear, temperature, etc. For example, the memory cells have different erase state E' and different program states P1', P2', P3', P4', P5', P6', and P7'. Figure 7

[0085] The read voltage levels RVL1 to RVL7 of the read voltages RV1 to RV7 are generally determined based on the distribution of the threshold voltages immediately after the memory cells are programmed. Thus, when the data read operation is performed using the read voltage levels RVL1 to RVL7 as they are for the respective read voltages RV1 to RV7 after the distribution of the threshold voltages has changed, the read data obtained by the data read operation can include errors, and the reliability of the memory device can decrease or deteriorate. For example, read errors can occur on the memory cells corresponding to the hatched area. For example, when the data read operation is performed using the read voltage RV1 having the read voltage level RVL1, the memory cells within the hatched area can be erroneously determined to be in the erase state E' due to the decrease in the threshold voltage even though the memory cells within the hatched area are programmed in the first program state P1'.

[0086] Thus, the distribution of the threshold voltages of the memory cells can shift due to various factors during the lifetime of the memory device. For example, the distribution of the threshold voltages can change due to increased usage time, changes in external environment (e.g., changes in temperature), and presence of manufacturing defects, etc. Finding the optimal read voltage is important to reduce the raw bit error rate. Especially after the distribution of the threshold voltages has changed, the optimal read voltage levels need to be re-determined for the respective read voltages in order to reduce the raw bit error rate.

[0087] ​According to the characteristic that the distribution of threshold voltage is similar to normal distribution, for example, for SLC NAND corresponding to a single reading voltage, the reading voltage level of the single reading voltage can be shifted left or right (in this document, the shift is along the threshold voltage axis, left shift means to decrease the level, right shift means to increase the level) and the number of bit flips caused by each step of shift can be recorded, and a curve with the number of bit flips on the vertical axis relative to the reading voltage level on the horizontal axis can be drawn. The number of bit flips can be considered as the number of memory cells whose reading values are flipped. For example, for the single reading voltage, left shift will cause the reading values of some memory cells to flip from "1" to "0", and right shift will cause the reading values of some memory cells to flip from "0" to "1". The number of bit flips caused by each step can be simply determined by the change of the number of "0" (or "1") in the reading result of each step compared to the number of "0" (or "1") in the reading result of the previous step. For example, originally A "0"s are read, after left shift by one step, (A+B) "0"s are read, then the number of bit flips caused by this step is B. As a result, the level corresponding to the trough of the drawn curve (i.e. the place where the number of bit flips is the smallest) can be determined as the optimal reading voltage level of the single reading voltage.

[0088] With the development of technology, xLC NAND, such as TLC / QLC NAND, which can store more and more bits of data per memory cell, appears, and at the same time, the threshold voltage window of these xLC NANDs becomes smaller and smaller, which makes it particularly important to find the optimal reading voltage level for each reading voltage.

[0089] The above method of shifting the reading voltage level to find the trough of the number of bit flips for SLC NAND corresponding to a single reading voltage can be performed for each reading voltage of the multiple reading voltages corresponding to xLC NAND to determine the optimal reading voltage level thereof. However, the more the possible storage states of memory cells, the more the number of reading voltage levels required, which makes the above method more and more time-consuming and laborious.

[0090] The levels of multiple reading voltages can be simultaneously shifted to find the optimal reading voltage level. For example, for LP, the reading voltage level RVL1 of reading voltage RV1 and the reading voltage level RVL5 of reading voltage RV5 can be simultaneously shifted at each step. It should be noted that for reading voltage RV1, left shift of reading voltage level RVL1 will cause bit flips from "1" to "0", and right shift of reading voltage level RVL1 will cause bit flips from "0" to "1"; on the contrary, for reading voltage RV5, right shift of reading voltage level RVL5 will cause bit flips from "1" to "0", and left shift of reading voltage level RVL5 will cause bit flips from "0" to "1".

[0091] The number of bits "0" (or "1") in the read result of LP at each step cannot be used to determine the bit flips associated with the read voltage level RVL1 offset and the bit flips associated with the read voltage level RVL5 offset, respectively. This is because: if the read voltage level RVL1 and the read voltage level RVL5 are simultaneously shifted in the same direction (e.g., both left or both right) at each step, the bit flips caused by the two are just opposite, and it is possible that each causes a large number of bit flips but the overall number of bits "0" (or "1") does not change much; if the read voltage level RVL1 and the read voltage level RVL5 are simultaneously shifted in opposite directions (e.g., one left and the other right) at each step, the bit flips caused by the two are the same, and it is impossible to distinguish the number of bits "0" (or "1") changes contributed by each.

[0092] One solution is to simultaneously shift the read voltage level RVL1 and the read voltage level RVL5 in the same direction at each step, and then identify whether a single memory cell is flipped from "1" to "0" or from "0" to "1" by data comparison for the memory cell, so as to determine whether the bit flip of the memory cell is due to the shift of the read voltage level RVL1 or the read voltage level RVL5. For example, when simultaneously left shifted, the number of bits flipped from "1" to "0" belongs to the read voltage level RVL1, and the number of bits flipped from "0" to "1" belongs to the read voltage level RVL5; when simultaneously right shifted, the number of bits flipped from "0" to "1" belongs to the read voltage level RVL1, and the number of bits flipped from "1" to "0" belongs to the read voltage level RVL5. Then, a curve with the number of bits flipped belonging to the read voltage level RVL1 on the vertical axis relative to the read voltage level RVL1 on the horizontal axis is drawn, and the trough level of the curve is determined as the optimal read voltage level RVL1, and a curve with the number of bits flipped belonging to the read voltage level RVL5 on the vertical axis relative to the read voltage level RVL5 on the horizontal axis is drawn, and the trough level of the curve is determined as the optimal read voltage level RVL5. This solution requires hardware support for data comparison for each single memory cell, and needs to cache more data.

[0093] The present disclosure provides a method of operating a memory device, which analyzes the read results of a target page by means of the read results of another page (as an indicator page) when finding the optimal read level of each order read voltage corresponding to the target page. Specifically, the method obtains the read results of the indicator page with a set of read voltage levels corresponding to the indicator page, and obtains multiple read results of the target page with multiple sets of read voltage levels corresponding to the target page respectively, which have offsets from each other. The method is able to derive the bit flipping information associated with each order read voltage corresponding to the target page from the multiple read results of the target page based on the read results of the indicator page, and further determine its optimal read level. Note that when referring to the read results of a page herein, it should be understood as the full page read results, not the read values of some memory cells therein. Therefore, the method does not rely on the hardware support of data comparison of each individual memory cell, nor requires caching more data.

[0094] The method of operating a memory device according to various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that there can be other steps in the actual method, but in order to avoid obscuring the points of the present disclosure, these other steps are not discussed herein and the accompanying drawings also do not show them. It should also be understood that the present disclosure will be mainly exemplarily illustrated for TLC, but this does not mean any limitation, and the present disclosure is equally applicable to any other xLC.

[0095] Figure 8 A flowchart of a method 600 of operating a memory device (such as the memory device 104 in Figure 1 ) according to some embodiments of the present disclosure is shown. As shown in Figure 8 , the method 600 includes steps S602 to S610.

[0096] At step S602, a read operation is performed on a first logical page corresponding to each order read voltage of the first logical page with a first set of read voltage levels to obtain a first read result of the first logical page.

[0097] At step S604, a read operation is performed on the first logical page corresponding to each order read voltage of the first logical page with a second set of read voltage levels to obtain a second read result of the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels.

[0098] At step S606, a read operation is performed on the first logical page corresponding to each order read voltage of the first logical page with a third set of read voltage levels to obtain a third read result of the first logical page, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset.

[0099] At step S608, a read operation is performed on the second logical page with a fourth set of read voltage levels for the respective order of read voltages corresponding to the second logical page in the memory device to obtain a fourth read result of the second logical page, the second logical page being different from the first logical page.

[0100] At step S610, based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for the respective order of read voltages corresponding to the first logical page.

[0101] Here, the first logical page is a target page, and the second logical page is an indicator page. The first logical page and the second logical page can be different types of logical pages. In some examples, the first logical page is a low page, and the second logical page is a high page. In some examples, the first logical page is a high page, and the second logical page is a low page. In some examples, the first logical page is a middle page, and the second logical page is a high page. In some examples, the first logical page is a middle page, and the second logical page is a low page. In some embodiments, the respective order of read voltages corresponding to the first logical page includes a first order read voltage and a second order read voltage, and the respective order of read voltages corresponding to the second logical page includes a third order read voltage, which can be located between the first order read voltage and the second order read voltage. In some embodiments, the respective order of read voltages corresponding to the second logical page includes only one order of read voltage between the first order read voltage and the second order read voltage corresponding to the first logical page.

[0102] In particular, it can be desirable that the respective memory cells of the target page and the indicator page have similar threshold voltage distributions, which can facilitate improving the accuracy and reliability of using the indicator page to assist the target page in determining the optimal read voltage. In some embodiments, the first logical page and the second logical page can correspond to the same physical page in the memory device, such as the physical page 320 in Figure 3 In some embodiments, a first physical page in the memory device corresponding to the first logical page and a second physical page in the memory device corresponding to the second logical page can be coupled to the same word line in the memory device, such as the word line 318 in Figure 3 For example, the first physical page can be the same as the second physical page, or can be different from the second physical page. In some embodiments, a first word line to which the first physical page corresponding to the first logical page is coupled and a second word line to which the second physical page corresponding to the second logical page is coupled can be included in the same group of word lines in the memory device. For example, the first word line can be the same as the second word line, or can be different from the second word line. Reference is made to Figure 3The plurality of memory cells 306 in the NAND memory string 308 are respectively coupled to a corresponding one of the plurality of word lines 318. The plurality of word lines 318 to which the plurality of memory cells 306 are coupled can be divided into a plurality of word line groups according to position, each word line group including at least one word line 318. When performing an operation, the memory device can apply a corresponding word line voltage to the word lines 318 in a word line group to improve performance of the memory device.

[0103] In some cases, such as when the first and second logical pages correspond to the same physical page in the memory device, step S602 and step S608 can be combined into one step. Specifically, a read operation can be performed on the physical page using a set of read voltage levels (RVL1-RVL7) for each of the read voltages (e.g., RV1-RV7) of the physical page to obtain read results for the physical page. The read results for each of the logical pages corresponding to the physical page can then be determined from the read results for the physical page. It can be appreciated that the set of read voltage levels (RVL1-RVL7) includes a first set of read voltage levels for the first logical page (e.g., (RVL10, RVL50) when the first logical page is a low page) and a fourth set of read voltage levels for the second logical page (e.g., (RVL30, RVL70) when the second logical page is a high page), and the read results for the physical page include a first read result for the first logical page and a fourth read result for the second logical page. This can be convenient, such as when the method 600 is re-run with a third logical page (e.g., a middle page) as a target page and the first or second logical page (e.g., a low page / high page) as an indicator page. A read operation for the target page can be omitted because the original read results for the third logical page (obtainable using a set of read voltage levels (RVL20, RVL40, RVL60)) are already included in the read results for the physical page.

[0104] At each of steps S604 and S606, the read voltage levels of the read voltages of the first logical page can be offset simultaneously, which facilitates fast finding the optimal read voltage levels. Specifically, the first logical page can correspond to the first order read voltage and the second order read voltage. In some embodiments, the first offset in step S604 is configured such that the offset of the read voltage level for the first order read voltage in the second set of read voltage levels relative to the read voltage level for the first order read voltage in the first set of read voltage levels has the same offset direction as the offset of the read voltage level for the second order read voltage in the second set of read voltage levels relative to the read voltage level for the second order read voltage in the first set of read voltage levels, and the second offset in step S606 is configured such that the offset of the read voltage level for the first order read voltage in the third set of read voltage levels relative to the read voltage level for the first order read voltage in the first set of read voltage levels has the same offset direction as the offset of the read voltage level for the second order read voltage in the third set of read voltage levels relative to the read voltage level for the second order read voltage in the first set of read voltage levels. In other words, for each of the first order read voltage and the second order read voltage, the offset direction of the read voltage level used at step S604 relative to the read voltage level used at step S602 is the same as that of the other, and the offset direction of the read voltage level used at step S606 relative to the read voltage level used at step S602 is also the same as that of the other.

[0105] For example, when the first logical page is a low page, it corresponds to the first order read voltage RV1 and the second order read voltage RV5. The first set of read voltage levels is denoted as (RVL10, RVL50), the second set of read voltage levels is denoted as (RVL11, RVL51), and the third set of read voltage levels is denoted as (RVL12, RVL52). Then, in the above embodiments, the first offset can be configured such that the offset of RVL11 relative to RVL10 has the same offset direction as the offset of RVL51 relative to RVL50, and the second offset can be configured such that the offset of RVL12 relative to RVL10 has the same offset direction as the offset of RVL52 relative to RVL50. For example, one of the first offset and the second offset can be left shifting RVL1 and RVL5 simultaneously, and the other can be right shifting RVL1 and RVL5 simultaneously. Details will be given later in connection with Figure 9 and Figure 10 A more detailed non-limiting example illustration is given in this regard.

[0106] In some embodiments, the first offset in step S604 is configured such that the shift of the read voltage level in the second set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage has an opposite shift direction as the shift of the read voltage level in the second set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage, and the second offset in step S606 is configured such that the shift of the read voltage level in the third set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage has an opposite shift direction as the shift of the read voltage level in the third set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage. In other words, for each of the first order read voltage and the second order read voltage, the shift direction of the read voltage level used at step S604 relative to the read voltage level used at step S602 is opposite to that of the other, and the shift direction of the read voltage level used at step S606 relative to the read voltage level used at step S602 is also opposite to that of the other.

[0107] For example, in the above embodiments, the first offset can be configured such that the shift of RVL11 relative to RVL10 has an opposite shift direction as the shift of RVL51 relative to RVL50, and the second offset can be configured such that the shift of RVL12 relative to RVL10 has an opposite shift direction as the shift of RVL52 relative to RVL50. For instance, one of the first offset and the second offset can be shifting RVL1 left and RVL5 right at the same time, and the other can be shifting RVL1 right and RVL5 left at the same time. More details will be given later in connection with Figure 11 and Figure 12 Non-limiting examples are given below for further illustration.

[0108] In some cases, the first logical page can correspond to a third or more order read voltage. Specifically, the third or more order read voltage includes the first order read voltage and the second order read voltage. In such cases, the read voltage levels of the other order read voltages can be maintained while the read voltage levels of the two order read voltages of the first logical page are simultaneously offset. Specifically, in some embodiments, the first offset in step S604 is configured such that the offset of the read voltage level for the first order read voltage in the second set of read voltage levels relative to the read voltage level for the first order read voltage in the first set of read voltage levels has a non-zero offset amount from the offset of the read voltage level for the second order read voltage in the second set of read voltage levels relative to the read voltage level for the second order read voltage in the first set of read voltage levels, the offset of the read voltage level for each order read voltage in the third or more order read voltage other than the first order read voltage and the second order read voltage in the second set of read voltage levels relative to the read voltage level for the each order read voltage in the first set of read voltage levels has a zero offset amount, the second offset in step S606 is configured such that the offset of the read voltage level for the first order read voltage in the third set of read voltage levels relative to the read voltage level for the first order read voltage in the first set of read voltage levels has a non-zero offset amount from the offset of the read voltage level for the second order read voltage in the third set of read voltage levels relative to the read voltage level for the second order read voltage in the first set of read voltage levels, the offset of the read voltage level for each order read voltage in the third or more order read voltage other than the first order read voltage and the second order read voltage in the third set of read voltage levels relative to the read voltage level for the each order read voltage in the first set of read voltage levels has a zero offset amount. In other words, for each of the first order read voltage and the second order read voltage, the read voltage level used at step S604 is offset from the read voltage level used at step S602, the read voltage level used at step S606 is also offset from the read voltage level used at step S602; while for the third order read voltage, the read voltage level used at step S604 is not offset from the read voltage level used at step S602, the read voltage level used at step S606 is also not offset from the read voltage level used at step S602.

[0109] For example, when the first logical page is a middle page, it corresponds to the first order read voltage RV2, the second order read voltage RV4, the third order read voltage RV6. The first set of read voltage levels are denoted as (RVL20, RVL40, RVL60), the second set of read voltage levels are denoted as (RVL21, RVL41, RVL61), and the third set of read voltage levels are denoted as (RVL22, RVL42, RVL62). Then, in the above embodiment, the first offset can be configured such that the offset of RVL21 relative to RVL20 has a non-zero offset amount from the offset of RVL41 relative to RVL40 and the offset of RVL61 relative to RVL60 has a zero offset amount (i.e., RVL21 is not equal to RVL20, RVL41 is not equal to RVL40, RVL61 is equal to RVL60), and the second offset can be configured such that the offset of RVL22 relative to RVL20 has a non-zero offset amount from the offset of RVL42 relative to RVL40 and the offset of RVL62 relative to RVL60 has a zero offset amount (i.e., RVL22 is not equal to RVL20, RVL42 is not equal to RVL40, RVL62 is equal to RVL60). It can be appreciated that similar to the foregoing embodiment, the offset of RVL21 relative to RVL20 and the offset of RVL41 relative to RVL40 can have the same or opposite offset directions, and the offset of RVL22 relative to RVL20 and the offset of RVL42 relative to RVL40 can correspondingly have the same or opposite offset directions. Thus, the optimal read voltage levels of the first order read voltage RV2 and the second order read voltage RV4 can be determined first using the method 600.

[0110] For the third order read voltage RV6, its optimal read voltage level can be determined using the aforementioned method for SLC or using the method 600. For example, the method 600 can be re-run with the first offset configured such that the offset of RVL41 relative to RVL40 and the offset of RVL61 relative to RVL60 have a non-zero offset amount and the offset of RVL21 relative to RVL20 has a zero offset amount (i.e., RVL41 is not equal to RVL40, RVL61 is not equal to RVL60, and RVL21 is equal to RVL20), and the second offset configured such that the offset of RVL42 relative to RVL40 and the offset of RVL62 relative to RVL60 have a non-zero offset amount and the offset of RVL22 relative to RVL20 has a zero offset amount (i.e., RVL42 is not equal to RVL40, RVL62 is not equal to RVL60, and RVL22 is equal to RVL20). It can be appreciated that similar to the aforementioned embodiments, the offset of RVL41 relative to RVL40 and the offset of RVL61 relative to RVL60 can have the same or opposite offset directions, and the offset of RVL42 relative to RVL40 and the offset of RVL62 relative to RVL60 can correspondingly have the same or opposite offset directions. Thus, the optimal read voltage levels of the second order read voltage RV4 and the third order read voltage RV6 can again be determined using the method 600.

[0111] In some embodiments, the first offset and the second offset can have the same offset amount.

[0112] In some examples, the first offset and the second offset are configured such that the offset of the read voltage level in the second set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage is the same offset as the offset of the read voltage level in the third set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage. Additionally or alternatively, in some examples, the offset of the read voltage level in the second set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage is the same offset as the offset of the read voltage level in the third set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage. For example, when the first logical page is a low page, which corresponds to the first order read voltage RV1 and the second order read voltage RV5. The first set of read voltage levels is denoted as (RVL10, RVL50), the second set of read voltage levels is denoted as (RVL11, RVL51), and the third set of read voltage levels is denoted as (RVL12, RVL52). Then, in the above example, the offset of RVL11 relative to RVL10 can have the same offset as the offset of RVL12 relative to RVL10, and the offset of RVL51 relative to RVL50 can have the same offset as the offset of RVL52 relative to RVL50. In this way, the first offset and the second offset occur symmetrically for each order of read voltage, which can facilitate finding the optimal read voltage level for each order of read voltage quickly.

[0113] In other embodiments, the first offset and the second offset can also have different offsets. In some examples, the first offset and the second offset are configured such that the offset of the read voltage level in the second set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage is different from the offset of the read voltage level in the third set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage. Additionally or alternatively, in some examples, the offset of the read voltage level in the second set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage is different from the offset of the read voltage level in the third set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage.

[0114] The offset amount of the first offset and the offset amount of the second offset can be individually configured according to their specific needs for each order of read voltage. That is, the first offset can be configured such that the offset of the read voltage level in the second set of read voltage levels for the first order of read voltage with respect to the read voltage level in the first set of read voltage levels for the first order of read voltage has the same or different offset amount as the offset of the read voltage level in the third set of read voltage levels for the second order of read voltage with respect to the read voltage level in the first set of read voltage levels for the second order of read voltage. Similarly, the second offset can be configured such that the offset of the read voltage level in the third set of read voltage levels for the first order of read voltage with respect to the read voltage level in the first set of read voltage levels for the first order of read voltage has the same or different offset amount as the offset of the read voltage level in the third set of read voltage levels for the second order of read voltage with respect to the read voltage level in the first set of read voltage levels for the second order of read voltage.

[0115] Step S610 can include determining, based on the first read result, the second read result, the third read result, and the fourth read result, whether to offset the first set of read voltage levels to obtain a set of optimal read voltage levels. In some embodiments, in response to determining, based on the first read result, the second read result, the third read result, and the fourth read result, not to offset the first set of read voltage levels to obtain a set of optimal read voltage levels, the first set of read voltage levels is determined as the set of optimal read voltage levels. In some embodiments, in response to determining, based on the first read result, the second read result, the third read result, and the fourth read result, to offset the first set of read voltage levels to obtain a set of optimal read voltage levels, a direction of offset and an offset value for offsetting the first set of read voltage levels are determined based on the first read result, the second read result, the third read result, and the fourth read result; based on the determined direction of offset, a first offset amount to be applied to the first offset and a second offset amount to be applied to the second offset are determined.

[0116] For example, a bit 1 count and / or a bit 0 count in each of the first data to the third data can be determined. Then, for each step read voltage corresponding to the first logical page, a difference between a number of bit flips caused by the first offset and a number of bit flips caused by the second offset is determined based on the bit 1 count and / or the bit 0 count. The one set of optimal read voltage levels for the step read voltages corresponding to the first logical page can be determined based on the difference. In some embodiments, in response to determining that an absolute value of the difference does not exceed a preset difference threshold, the first set of read voltage levels is determined as the one set of optimal read voltage levels. In some embodiments, in response to determining that the absolute value of the difference exceeds the preset difference threshold, a direction of offset and an offset value for offsetting the first set of read voltage levels are determined based on a positive or negative of the difference. The preset difference threshold can be set according to actual conditions. In particular, the preset difference threshold can be configured individually for each step read voltage according to its specific needs.

[0117] For example, a bit 1 count and / or a bit 0 count in each of the first data to the third data can be determined. Then, for each step read voltage corresponding to the first logical page, a difference between a number of bit flips caused by the first offset and a number of bit flips caused by the second offset is determined based on the bit 1 count and / or the bit 0 count. The one set of optimal read voltage levels for the step read voltages corresponding to the first logical page can be determined based on the difference. In some embodiments, in response to determining that an absolute value of the difference does not exceed a preset difference threshold, the first set of read voltage levels is determined as the one set of optimal read voltage levels. In some embodiments, in response to determining that the absolute value of the difference exceeds the preset difference threshold, a direction of offset and an offset value for offsetting the first set of read voltage levels are determined based on a positive or negative of the difference. The preset difference threshold can be set according to actual conditions. In particular, the preset difference threshold can be configured individually for each step read voltage according to its specific needs.

[0118] For example, if the difference is positive, it can indicate that the offset direction of the first offset should be taken as the offset direction for offsetting the first set of read voltage levels, and accordingly, the offset value can be determined as the value between the first set of read voltage levels and the second set of read voltage levels (e.g., but not limited to, half of the sum of the two, such a bisection is advantageous for quickly finding the optimal read voltage levels); if the difference is negative, it can indicate that the offset direction of the second offset should be taken as the offset direction for offsetting the first set of read voltage levels, and accordingly, the offset value can be determined as the value between the first set of read voltage levels and the third set of read voltage levels (e.g., but not limited to, half of the sum of the two, such a bisection is advantageous for quickly finding the optimal read voltage levels). It can be appreciated that when the difference is defined oppositely as the difference between the number of bit flips caused by the second offset and the number of bit flips caused by the first offset, the meaning indicated by the positive or negative of the difference is also reversed accordingly.

[0119] For example, the first offset amount to be applied to the first offset and the second offset amount to be applied to the second offset can be determined based on the determined offset direction. When the determined offset direction is the same as the offset direction adopted to obtain the current first set of read voltage levels, the offset amounts currently used for the first offset and the second offset can be continued to be adopted. When the determined offset direction is opposite to the offset direction adopted to obtain the current first set of read voltage levels, the first offset amount and the second offset amount can be reduced relative to the offset amounts currently used for the first offset and the second offset, e.g., but not limited to, reduced to half of the original (such a bisection is advantageous for quickly finding the optimal read voltage levels).

[0120] In some embodiments, in response to determining that the first offset amount and the second offset amount do not exceed a preset offset amount threshold, the first set of read voltage levels is determined as the set of optimal read voltage levels. The preset offset amount threshold can be set according to actual conditions, and the preset offset amount threshold can also be set for the first offset amount and the second offset amount respectively (which can be the same or different). In particular, the preset offset amount threshold can be configured separately for each order of read voltage according to its specific needs. As a non-limiting example, the preset offset amount threshold can take a smallest level variable unit of a digital-to-analog converter (1 DAC). It can be determined that when the first offset amount and the second offset amount are equal to 1 DAC, the optimal read voltage levels have been found accurately enough.

[0121] In some embodiments, in response to determining that the first offset and the second offset exceed the preset offset threshold: performing read operations on the first logical page with a first set of read voltage levels updated based on the offset values for the steps of read voltages corresponding to the first logical page to re-obtain a first read result of the first logical page; performing read operations on the first logical page with a second set of read voltage levels updated based on the offset values and the first offset for the steps of read voltages corresponding to the first logical page to re-obtain a second read result of the first logical page; performing read operations on the first logical page with a third set of read voltage levels updated based on the offset values and the second offset for the steps of read voltages corresponding to the first logical page to re-obtain a third read result of the first logical page; and determining a set of optimal read voltage levels for the steps of read voltages corresponding to the first logical page based on the re-obtained first read result, the re-obtained second read result, the re-obtained third read result, and the fourth read result (obtained in step S608). Specifically, the process of determining a set of optimal read voltage levels based on the re-obtained first read result, the re-obtained second read result, the re-obtained third read result, and the fourth read result can be similar to the process of determining a set of optimal read voltage levels based on the first read result, the second read result, the third read result, and the fourth read result, which is not repeated here. Through such iteration, the updated first set of read voltage levels can be made to continuously approach until reaching the optimal read voltage levels.

[0122] For non-limiting illustration purposes, the following is combined with Figure 9 to Figure 12 Various exemplary processes are described in which the method 600 of operating a memory device according to embodiments of the present disclosure is applied.

[0123] Figure 9 A flowchart of an exemplary process 700 in which the method 600 of operating a memory device according to embodiments of the present disclosure is applied is shown. Figure 10 A schematic diagram showing bit flips resulting from offsetting read voltage levels in the process of Figure 9 A schematic diagram showing bit flips resulting from offsetting read voltage levels in the process of Figure 10 In the middle, the memory cells in the gray area have a read value of "1" and the memory cells in the white area have a read value of "0".

[0124] As Figure 9As shown, the UP (as the indicator page) is read with a first set of read voltage levels (RVL10, RVL50) to obtain a read result D0 of the UP (S704). For example, the read voltage levels RVL10, RVL30, RVL50, RVL70 can be default values obtained by looking up a table, or values determined in a previous run of the method 600, etc. A data D0' is generated by Boolean operation of D0 and D00, and a bit 1 count and / or a bit 0 count in the data D0' is determined (S706).

[0125] The LP is read with a second set of read voltage levels (RVL11 = RVL10 - δ1, RVL51 = RVL50 - δ5) to obtain a read result D1 of the LP (S708). Each read voltage level in the second set of read voltage levels is left-shifted relative to a corresponding read voltage level in the first set of read voltage levels. δ1 is the shift δ for RVL1, and δ5 is the shift δ for RVL5. A data D1' is generated by Boolean operation of D1 and D00, and a bit 1 count and / or a bit 0 count in the data D1' is determined (S710).

[0126] The LP is read with a third set of read voltage levels (RVL12 = RVL10 + δ1, RVL52 = RVL50 + δ5) to obtain a read result D2 of the LP (S712). Each read voltage level in the third set of read voltage levels is right-shifted relative to a corresponding read voltage level in the first set of read voltage levels. The right-shifts here for RV1 and RV5 are symmetric to the left-shifts before, in other words, they have the same shift δ. A data D2' is generated by Boolean operation of D2 and D00, and a bit 1 count and / or a bit 0 count in the data D2' is determined (S714).

[0127] Based on the bit 1 count and / or the bit 0 count in each of the data D0', D1', D2', a difference Δ (Δ RV1 , Δ RV5 ) of the number of left-shift bit flips and the number of right-shift bit flips is determined for each read voltage (RV1, RV5) of the LP (S716).

[0128] It is respectively determined whether the absolute value of Δ RV1 , Δ RV5 exceeds a corresponding threshold value Δ limit (Δ limit1 , Δ limit5 ) (S718). If Δ does not exceed Δ limitRV1, RV5) of the LP are determined as a set of optimal read voltage levels (S726). Specifically, if Δ RV1 RV1 is not greater than Δ limit1 RV1 is not greater than Δ RV5 RV1 is not greater than Δ limit5 RV1 is not greater than Δ limit It can be understood that if one of RV1 and RV5 finds the optimal read voltage level first, the one can be fixed at the optimal read voltage level, and only the level of the other is adjusted in the subsequent iteration until the other also finds the optimal read voltage level.

[0129] If Δ limit , the shift direction and the shifted value for shifting the first set of read voltage levels in this round can be determined according to the positive and negative of Δ (S720). Specifically, if Δ RV1 > 0, it is determined that the shift direction for shifting RVL10 in this round is left shift, and RVL10 = (RVL11 + RVL10) / 2; if Δ RV1 < 0, it is determined that the shift direction for shifting RVL10 in this round is right shift, and RVL10 = (RVL12 + RVL10) / 2. In addition, if Δ RV5 > 0, it is determined that the shift direction for shifting RVL50 in this round is left shift, and RVL50 = (RVL51 + RVL50) / 2; if Δ RV5 < 0, it is determined that the shift direction for shifting RVL50 in this round is right shift, and RVL50 = (RVL52 + RVL50) / 2.

[0130] Based on the determined shift direction, the value of the shift amount δ in the next round can be determined (S722). Specifically, if it is determined that the shift direction for shifting RVL10 in this round is the same as the shift direction for shifting RVL10 in the last round, then δ1 = δ1; if it is determined that the shift direction for shifting RVL10 in this round is different from the shift direction for shifting RVL10 in the last round, then δ1 = δ1 / 2. In addition, if it is determined that the shift direction for shifting RVL50 in this round is the same as the shift direction for shifting RVL50 in the last round, then δ5 = δ5; if it is determined that the shift direction for shifting RVL50 in this round is different from the shift direction for shifting RVL50 in the last round, then δ5 = δ5 / 2.

[0131] It is determined whether δ1 and δ5 are equal to 1 DAC, respectively (S724). If δ is equal to 1 DAC, the first set of read voltage levels (RVL10, RVL50) is determined as the set of optimal read voltage levels for the respective orders of LP's voltages (RV1, RV5) (S726). Specifically, RVL10 is determined as the optimal read voltage level for RV1 if δ1 is equal to 1 DAC, and RVL50 is determined as the optimal read voltage level for RV5 if δ5 is equal to 1 DAC. It is appreciated that if one of RV1 and RV5 finds the optimal read voltage level first, the one can be fixed at the optimal read voltage level, and only the level of the other is adjusted in the subsequent iteration until the other also finds the optimal read voltage level.

[0132] If δ is not equal to 1 DAC, it can return to S704 for the next round of iteration.

[0133] Reference Figure 10 , (A) corresponds to D0 and D00, (B) corresponds to D1 and D00, (C) corresponds to D2 and D00.

[0134] In an example embodiment, it is determined that the bit 1 count in (D00 AND D0) is a, the bit 1 count in (D00 AND D1) is b, the bit 1 count in (D00 AND D2) is c, the bit 0 count in (D00 OR D0) is d, the bit 0 count in (D00 OR D1) is e, the bit 0 count in (D00 OR D2) is f, and it is further determined that the number of 1→0 bit flips caused by left shifting RVL1 is ① = a - b, the number of 0→1 bit flips caused by right shifting RVL1 is ② = c - a, the number of 0→1 bit flips caused by left shifting RVL5 is ③ = d - e, and the number of 1→0 bit flips caused by right shifting RVL5 is ④ = f - d, and it is determined that Δ RV1 = ① - ②, Δ RV5 = ③ - ④.

[0135] In another example embodiment, it is determined that the bit 1 count in D0 is a, the bit 1 count in D1 is b, the bit 1 count in D2 is c, the bit 1 count in (D00 XOR D0) is d, the bit 1 count in (D00 XOR D1) is e, the bit 1 count in (D00 XOR D2) is f, and it is further determined that the number of 1→0 bit flips caused by left shifting RVL1 is ① = (a - b + d - e) / 2, the number of 0→1 bit flips caused by right shifting RVL1 is ② = (f - d - a + c) / 2, the number of 0→1 bit flips caused by left shifting RVL5 is ③ = (d - e - a + b) / 2, and the number of 1→0 bit flips caused by right shifting RVL5 is ④ = (a - c + f - d) / 2, and it is determined that Δ RV1 = ① - ②, ΔRV5 = 1 - 2.

[0136] The bit 1 count in the foregoing example embodiments can be replaced with bit 0 count using NOT operation, or vice versa.

[0137] In an example embodiment, the bit 0 count in [NOT (D00 AND D0)] is determined as a, the bit 0 count in [NOT (D00 AND D1)] is determined as b, the bit 0 count in [NOT (D00 AND D2)] is determined as c, the bit 0 count in (D00 OR D0) is determined as d, the bit 0 count in (D00 OR D1) is determined as e, the bit 0 count in (D00 OR D2) is determined as f, and then the number of 1→0 bit flips 1 caused by left shift RVL1 is determined as 1 = a - b, the number of 0→1 bit flips 2 caused by right shift RVL1 is determined as 2 = c - a, the number of 0→1 bit flips 3 caused by left shift RVL5 is determined as 3 = d - e, the number of 1→0 bit flips 4 caused by right shift RVL5 is determined as 4 = f - d, and then the Δ is determined as RV1 = 1 - 2. RV5 = 3 - 4.

[0138] In another example embodiment, the bit 1 count in (D00 AND D0) is determined as a, the bit 1 count in (D00 AND D1) is determined as b, the bit 1 count in (D00 AND D2) is determined as c, the bit 1 count in [NOT (D00 OR D0)] is determined as d, the bit 1 count in [NOT (D00 OR D1)] is determined as e, the bit 1 count in [NOT (D00 OR D2)] is determined as f, and then the number of 1→0 bit flips 1 caused by left shift RVL1 is determined as 1 = a - b, the number of 0→1 bit flips 2 caused by right shift RVL1 is determined as 2 = c - a, the number of 0→1 bit flips 3 caused by left shift RVL5 is determined as 3 = d - e, the number of 1→0 bit flips 4 caused by right shift RVL5 is determined as 4 = f - d, and then the Δ is determined as RV1 = 1 - 2. RV5 = 3 - 4.

[0139] In yet another example embodiment, the bit 1 count in D0 is determined to be a, the bit 1 count in D1 is determined to be b, the bit 1 count in D2 is determined to be c, the bit 0 count in [NOT (D00 XOR D0)] is determined to be d, the bit 0 count in [NOT (D00 XOR D1)] is determined to be e, the bit 0 count in [NOT (D00 XOR D2)] is determined to be f, and then the number of 1→0 bit flips caused by left shift RVL1 is determined to be ①=(a-b+d-e) / 2, the number of 0→1 bit flips caused by right shift RVL1 is determined to be ②=(f-d-a+c) / 2, the number of 0→1 bit flips caused by left shift RVL5 is determined to be ③=(d-e-a+b) / 2, the number of 1→0 bit flips caused by right shift RVL5 is determined to be ④=(a-c+f-d) / 2, and then Δ RV1 = ①-②, Δ RV5 = ③-④.

[0140] Figure 11 A flowchart of another example procedure 700' in which the method 600 of operating a memory device according to an embodiment of the present disclosure is applied is shown. Figure 12 A schematic diagram showing bit flips caused by offset read voltage levels during Figure 11 Figure 12 In the diagram, the memory cells in the gray area have a read value of "1", and the memory cells in the white area have a read value of "0".

[0141] The procedure 700' differs from the procedure 700 in steps S708' and S712', i.e. step S708' left shifts RVL1 while right shifting RVL5, and step S712' right shifts RVL1 while left shifting RVL5.

[0142] Referring to Figure 12 , (A) corresponds to D0 and D00, (B) corresponds to D1 and D00, and (C) corresponds to D2 and D00.

[0143] ​Since process 700' performs level shifting in a different way from process 700, the calculation process of its Δ also changes accordingly. For example, in an example embodiment, it is determined that the bit 1 count in D0 is a, the bit 1 count in D1 is b, the bit 1 count in D2 is c, the bit 1 count in (D00 XOR D0) is d, the bit 1 count in (D00 XOR D1) is e, the bit 1 count in (D00 XOR D2) is f, and then it is determined that the number of 1→0 bit flips caused by left shift RVL1 is (a-b+d-e) / 2, the number of 0→1 bit flips caused by right shift RVL1 is (f-d-a+c) / 2, the number of 0→1 bit flips caused by left shift RVL5 is (c-a-f+d) / 2, and the number of 1→0 bit flips caused by right shift RVL5 is (a-b+e-d) / 2, and thus Δ RV1 = ①-②, Δ RV5 = ③-④. Other example embodiments can also be adaptively modified, which will not be described here in detail.

[0144] As can be seen from the above, the method according to the present disclosure can quickly find a set of optimal read voltage levels for each level of read voltage corresponding to a target page by simultaneously shifting the levels of the read voltage corresponding to the target page, and can accurately and simply determine the bit flip information associated with each level of read voltage corresponding to the target page from the bit '0' count and / or the bit '1' count in the resulting data respectively by processing each read result of the target page with the read result of the page, and then determine the read voltage levels of each level of read voltage corresponding to the target page, without relying on hardware to support data comparison of each individual memory cell, which significantly reduces the requirements on hardware and greatly reduces the amount of data cache.

[0145] In addition, in the processes shown in Figure 9 and Figure 11 , in addition to leaving the iterative loop from step S718 "No" and step S724 "Yes", in some embodiments, the following condition for leaving the iterative loop can also be applied: judging whether the read result D0 obtained by reading LP with the first set of read voltage levels (RVL10, RVL50) is consistent with the data previously written into LP, if consistent (meaning that the data stored in LP can be successfully read at this time with the first set of read voltage levels (RVL10, RVL50)), then the first set of read voltage levels (RVL10, RVL50) is determined as a set of optimal read voltage levels for each level of read voltage (RV1, RV5) of LP (S726). For example, this judgment step can be located between step S704 and step S706, and in the case of inconsistency (meaning that the read fails), proceed to step S706.

[0146] The methods of operating a memory device taught by the present disclosure can be implemented in a variety of ways, such as by a memory controller or firmware software, or developed into the memory device. For example, the methods of operating a memory device taught by the present disclosure can be run when a memory device (such as memory device 104 in Figure 1 ), a memory system (such as memory system 102 in Figure 1 ) containing the memory device, or a system (such as system 100 in Figure 1 ) containing the memory system is shipped or enabled, can be run every preset time period (e.g., in a patrol of the status of the target page), and can be run in response to a read failure (i.e., the read result is inconsistent with the data written previously) or an error correction command. Specifically, in some embodiments, the method 600 can include performing steps S602-S610 in response to a failure to read data stored in the first logical page. For example, the failure to read data stored in the first logical page includes that the data in the read first logical page contains an error (e.g., an error detected by an error correction module 1064 in Figure 6 ). In some embodiments, the method 600 can include performing steps S602-S610 in a patrol of the status of the first logical page.

[0147] The methods of operating a memory device taught by the present disclosure can read or re-read data in a target page after determining or re-determining the optimal read voltage level. Specifically, in some embodiments, the method 600 can include performing a read operation on the first logical page with the determined set of optimal read voltage levels (e.g., at step S610) for each step read voltage corresponding to the first logical page to read data stored in the first logical page.

[0148] According to some aspects of the present disclosure, the present disclosure provides a memory device (such as memory device 300 in Figure 3 ) comprising a memory cell array (such as memory cell array 301 in Figure 3 ) and a peripheral circuit (such as peripheral circuit 302 in Figure 3 ) coupled to the memory cell array. The peripheral circuit can be configured to perform the method of operating a memory device according to any embodiment of the present disclosure.

[0149] For example, referring to Figure 5The peripheral circuit can include a control logic unit 512 and registers 514 coupled to the control logic unit 512. The registers 514 can store instructions that, when executed by the control logic unit 512, cause the control logic unit 512 to perform a method of operating a memory device according to any embodiment of the disclosure. Specifically, the control logic unit 512 can send control signals to the page buffer / sense amplifier 504 to read data from the memory cell array 301. The control logic unit 512 can control the voltage generator 510 to generate a read voltage to be supplied to the memory cell array 301 at a desired level (e.g., the various read voltage levels described with respect to the method 600).

[0150] According to some aspects of the disclosure, the disclosure provides a memory system (such as the memory system 102 in Figure 1 ) including a memory controller (such as the memory controller 106 in Figure 1 ) and a memory device (such as the memory device 104 in Figure 1 ) coupled to the memory controller. The memory device (such as the memory device 300 in Figure 3 ) includes a memory cell array (such as the memory cell array 301 in Figure 3 ) and a peripheral circuit (such as the peripheral circuit 302 in Figure 3 ) coupled to the memory cell array. The peripheral circuit can be configured to perform a method of operating a memory device according to any embodiment of the disclosure. Specifically, the peripheral circuit can be configured to perform the following operations: performing a read operation on a first logical page of the memory cell array with a first set of read voltage levels for respective read voltages corresponding to the first logical page to obtain a first read result for the first logical page; performing a read operation on the first logical page with a second set of read voltage levels for the respective read voltages corresponding to the first logical page to obtain a second read result for the first logical page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; performing a read operation on the first logical page with a third set of read voltage levels for the respective read voltages corresponding to the first logical page to obtain a third read result for the first logical page, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset; performing a read operation on a second logical page of the memory cell array with a fourth set of read voltage levels for respective read voltages corresponding to the second logical page to obtain a fourth read result for the second logical page, the second logical page being different from the first logical page; and determining a set of optimal read voltage levels for the respective read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

[0151] In some embodiments, the peripheral circuitry is configured to perform the operation in response to a failure to read data stored in the first logical page. For example, a failure to read data stored in the first logical page may include an error in the data being read from the first logical page. In some embodiments, the peripheral circuitry is configured to perform the operation during a routine inspection of the state of the first logical page.

[0152] The memory device taught in this disclosure can read or reread data in a target page after an optimal read voltage level has been determined or redefined. Specifically, in some embodiments, the peripheral circuitry is configured to perform a read operation on the first logic page using the set of optimal read voltage levels for each level of read voltage corresponding to the first logic page, in order to read the data stored in the first logic page.

[0153] In some exemplary embodiments, the peripheral circuitry can be configured to: receive signals from the memory controller (e.g., via input / output circuitry in the peripheral circuitry (such as...) Figure 5 The input / output circuit 516) is connected to the memory interface of the memory controller (such as, Figure 6 The memory I / F 1062 receives a read command to read data stored in the first logical page using a set of read voltage levels stored in the memory controller for the first logical page; in response to determining that reading the data stored in the first logical page has failed, the operation is performed; the data stored in the first logical page is reread using a determined set of optimal read voltage levels; and the data stored in the first logical page is sent to the memory controller. For example, the peripheral circuitry can also be configured to send the determined set of optimal read voltage levels for the first logical page to the memory controller. Thus, the memory controller can update the set of read voltage levels for the first logical page stored therein for use when subsequently sending read commands for the first logical page.

[0154] In this exemplary embodiment, the process of the memory controller re-determining the optimal read voltage level for the memory device can be imperceptible. For the memory controller, it sends a read command to the memory device regarding a first logical page, and then receives the data stored in the first logical page from the memory device.

[0155] In other exemplary embodiments, the peripheral circuitry may be configured to receive signals from the memory controller (e.g., via input / output circuitry in the peripheral circuitry, such as...). Figure 5 The input / output circuit 516) is connected to the memory interface of the memory controller (such as, Figure 6receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 5 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 6 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 6 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 5 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 6 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller. Figure 5 receiving, by the memory I / F 1062 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page; responsive to determining that reading the data stored in the first logical page fails, notifying the memory controller of the read failure; responsive to receiving, by the input / output circuit 516 of the memory device, a read command from the memory controller to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, reading the data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page; and sending, by the memory I / F 1062 of the memory device, the data stored in the first logical page to the memory controller.

[0156] In comparison with the foregoing exemplary embodiments, in the present exemplary embodiments, the process of the memory device to re-determine the optimal read voltage levels can be done under the error correction command of the memory controller.

[0157] In some other exemplary embodiments, the process of the memory device to re-determine the optimal read voltage levels can also be done automatically by the memory device without necessarily responding to a specific instruction from the memory controller.

[0158] In some embodiments, the determination that reading the data stored in the first logical page fails can be performed by the memory device (specifically, its peripheral circuitry), for example, by comparing the data currently read from the first logical page with the data previously programmed (written) to the first logical page.

[0159] In other embodiments, the determination that reading the data stored in the first logical page failed can also be performed by the memory controller (specifically, its error correction module). In such embodiments, the aforementioned "in response to determining that reading the data stored in the first logical page failed, notifying the memory controller of the read failure" step can be removed, the peripheral circuit instead being configured to send the read data of the first logical page to the memory controller and perform the process of re-determining the optimal read voltage level upon receiving an error correction command issued by the memory controller based on determining that reading the data stored in the first logical page failed.

[0160] In some embodiments, the memory device can include an input / output circuit coupled to the peripheral circuit and coupled to the memory controller. In some examples, the peripheral circuit is configured to perform the operations in response to receiving the error correction command from the memory controller via the input / output circuit. In some examples, the peripheral circuit is configured to perform the operations in response to receiving the read command from the memory controller via the input / output circuit and perform the read operations on the first logical page with the set of optimal read voltage levels for the respective order read voltages corresponding to the first logical page to read the data stored in the first logical page. In some examples, the peripheral circuit is configured to perform the operations in response to receiving the read command from the memory controller via the input / output circuit and perform the read operations on the first logical page with the set of optimal read voltage levels for the respective order read voltages corresponding to the first logical page to read the data stored in the first logical page. In some examples, the peripheral circuit is configured to perform the operations in response to receiving the patrol command from the memory controller via the input / output circuit.

[0161] According to some aspects of the present disclosure, the present disclosure provides a memory controller (such as memory controller 106 in Figure 1 and Figure 6 ) for controlling a memory device (such as memory device 104 in Figure 1 and Figure 6 ). The memory controller includes a memory interface (such as memory I / F 1062 in Figure 6 ) for connecting the memory controller with the memory device. The memory controller includes a processor (such as processor 1063 in Figure 6 ) and a memory coupled to the processor and storing instructions (such as memory 1064 in Figure 6the memory 1065 in the computer system 1000). The instructions, when executed by the processor, cause the processor to perform a method of operating a memory device in accordance with any of the embodiments of the present disclosure. Specifically, the instructions, when executed by the processor, cause the processor to perform the following operations: instruct the memory interface to send a first read command to the memory device to perform a read operation on a first logical page of the memory device with a first set of read voltage levels for a respective tier of read voltages corresponding to the first logical page, and receive a first read result of the first logical page from the memory device; instruct the memory interface to send a second read command to the memory device to perform a read operation on the first logical page with a second set of read voltage levels for the respective tier of read voltages corresponding to the first logical page, and receive a second read result of the first logical page from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; instruct the memory interface to send a third read command to the memory device to perform a read operation on the first logical page with a third set of read voltage levels for the respective tier of read voltages corresponding to the first logical page, and receive a third read result of the first logical page from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, the second offset being different from the first offset; instruct the memory interface to send a fourth read command to the memory device to perform a read operation on a second logical page of the memory device with a fourth set of read voltage levels for a respective tier of read voltages corresponding to the second logical page, and receive a fourth read result of the second logical page from the memory device, the second logical page being different from the first logical page; and determine a set of optimal read voltage levels for the respective tier of read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

[0162] In some embodiments, the instructions, when executed by the processor, cause the processor to perform the operations in response to a failure to read data stored in the first logical page. For example, the failure to read data stored in the first logical page can include the read data in the first logical page containing an error. In some embodiments, the instructions, when executed by the processor, cause the processor to perform the operations during a patrol of a status of the first logical page.

[0163] In some embodiments, the instructions, when executed by the processor, cause the processor to instruct the memory to adjust read voltage levels stored in the memory for the respective tier of read voltages corresponding to the first logical page to the set of optimal read voltage levels.

[0164] In some embodiments, the instructions, when executed by the processor, cause the processor to instruct the memory interface to send a fifth read command to the memory device to perform a read operation on the first logical page with the set of optimal read voltage levels for the respective tier of read voltages corresponding to the first logical page, and receive data stored in the first logical page from the memory device.

[0165] In some example embodiments, the processor can instruct the memory interface to send a read command to the memory device to read data stored in a first logical page with a set of read voltage levels stored in the memory for the first logical page, and receive the data stored in the first logical page from the memory device; in response to determining that reading the data stored in the first logical page fails (e.g., an error is detected via an error correction module (such as error correction module 1064 in Figure 6 ), perform the operations to update the set of read voltage levels stored in the memory for the first logical page to a determined set of optimal read voltage levels for the first logical page (e.g., the processor can send an instruction to the memory to adjust the read voltage levels to the determined optimal read voltage levels); instruct the memory interface to resend the read command to the memory device to read the data stored in the first logical page with the set of optimal read voltage levels stored in the memory for the first logical page, and receive the data stored in the first logical page from the memory device.

[0166] In such example embodiments, the process of the memory device re-determining optimal read voltage levels for the memory controller can be transparent. To the memory device, it receives a read command from the memory controller (specifically, its memory interface) regarding a first logical page, and then sends the data stored in the first logical page to the memory controller (specifically, its memory interface).

[0167] According to some aspects of the disclosure, the disclosure provides a memory system (such as memory system 102 in Figure 1 and Figure 6 ), which includes a memory device (such as memory device 104 in Figure 1 and Figure 6 ) and a memory controller coupled to the memory device (such as memory controller 102 in Figure 1 and Figure 6The memory controller can be configured to perform the method of operating a memory device as described in accordance with any embodiment of the present disclosure. In particular, the memory controller can be configured to perform the following operations: send a first read command to the memory device to perform a read operation on a first logical page of the memory device with a first set of read voltage levels for respective tiers of read voltages corresponding to the first logical page, and receive a first read result for the first logical page from the memory device; send a second read command to the memory device to perform a read operation on the first logical page with a second set of read voltage levels for the respective tiers of read voltages, the second set of read voltage levels having a first offset relative to the first set of read voltage levels, and receive a second read result for the first logical page from the memory device; send a third read command to the memory device to perform a read operation on the first logical page with a third set of read voltage levels for the respective tiers of read voltages, the third set of read voltage levels having a second offset relative to the first set of read voltage levels, the second offset being different than the first offset, and receive a third read result for the first logical page from the memory device; send a fourth read command to the memory device to perform a read operation on a second logical page of the memory device with a fourth set of read voltage levels for the respective tiers of read voltages corresponding to the second logical page, the second logical page being different than the first logical page, and receive a fourth read result for the second logical page from the memory device; and determine a set of optimal read voltage levels for the respective tiers of read voltages corresponding to the first logical page based on the first read result, the second read result, the third read result, and the fourth read result.

[0168] In some embodiments, the memory controller is configured to perform the operations in response to a failure to read data stored in the first logical page. For example, the failure to read data stored in the first logical page can include the read data in the first logical page containing an error. In some embodiments, the memory controller is configured to perform the operations during a patrol of a status of the first logical page.

[0169] In some embodiments, the memory controller is configured to adjust read voltage levels stored by the memory controller for the respective tiers of read voltages corresponding to the first logical page to the set of optimal read voltage levels.

[0170] In some embodiments, the memory controller is configured to send a fifth read command to the memory device to perform a read operation on the first logical page with the set of optimal read voltage levels for the respective tiers of read voltages corresponding to the first logical page, and receive data stored in the first logical page from the memory device.

[0171] In some example embodiments, the memory controller is configured to perform the operations via a memory interface (such as a memory interface 106 in FIG. 1) to the memory device. Figure 6the memory controller) to the memory device to read data stored in the first logical page with the set of read voltage levels stored in the memory controller for the first logical page, and receive the data stored in the first logical page from the memory device; in response to determining that reading the data stored in the first logical page fails (e.g., via an error correction module (such as Figure 6 the error correction module 1064 in the memory controller) detects an error), performing the operations to update the set of read voltage levels stored by the memory controller for the first logical page to the determined set of optimal read voltage levels for the first logical page (e.g., via a processor (such as Figure 6 the processor 1063 in the memory controller) can send an indication to the memory (such as Figure 6 the memory 1065 in the memory controller) to adjust the read voltage levels to the determined optimal read voltage levels); (e.g., via a memory interface (such as Figure 6 the memory I / F 1062 in the memory controller) to the memory device to read data stored in the first logical page with the set of optimal read voltage levels stored in the memory controller for the first logical page, and receive the data stored in the first logical page from the memory device.

[0172] In such example embodiments, the process of the memory device re-determining optimal read voltage levels for the memory controller can be transparent to the memory device. To the memory device, it receives a read command from the memory controller regarding the first logical page, and then sends the read data to the memory controller.

[0173] The present disclosure also provides an electronic device, which can include one or more processors, and memory storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform the method of operating a memory device according to any of the preceding embodiments of the present disclosure. As Figure 13As shown, the electronic device 900 includes a processor(s) 902 and a memory 904 storing computer-executable instructions that, when executed by the processor(s) 902, cause the processor(s) 902 to perform a method of operating a memory device according to any of the preceding embodiments of the disclosure. The processor(s) 902 can be, for example, a central processing unit (CPU) of the electronic device 900. The processor(s) 902 can be any type of general purpose processor, or can be a processor specifically designed for operating a memory device, such as an application-specific integrated circuit (“ASIC”). The memory 904 can include various computer-readable media that are accessible by the processor(s) 902. In various embodiments, the memory 904 described herein can include volatile and non-volatile media, removable and non-removable media. For example, the memory 904 can include any combination of random access memory (“RAM”), dynamic RAM (“DRAM”), static RAM (“SRAM”), read only memory (“ROM”), flash memory, cache memory, and / or any other type of non-transitory computer readable media. The memory 904 can store instructions that, when executed by the processor 902, cause the processor 902 to perform a method of operating a memory device according to any of the preceding embodiments of the disclosure.

[0174] The present disclosure also provides a non-transitory storage medium having stored thereon computer-executable instructions that, when executed by one or more processors, cause the one or more processors to perform a method of operating a memory device according to any of the preceding embodiments of the disclosure.

[0175] The present disclosure also provides a computer program product that can include instructions that, when executed by a processor, can implement a method of operating a memory device according to any of the preceding embodiments of the disclosure. The instructions can be any set of instructions that are directly executable by the one or more processors, such as machine code, or indirectly executable, such as scripts. The instructions can be stored in an object code format for direct processing by the one or more processors, or in any other computer languages, including scripts or collections of independent source code modules that are interpreted or compiled on demand.

[0176] The above-described one or more exemplary embodiments of the present disclosure are described. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims can be performed in a different order and still accomplish desirable results. Additionally, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In certain implementations, multitasking and parallel processing can be advantageous.

[0177] The systems, apparatuses, modules or units illustrated by the above-described embodiments can be specifically implemented by a computer chip or entity, or a product with some functions. A typical implementation device is a server system. Of course, the present disclosure does not exclude that with the development of computer technology, the computer for implementing the functions of the above-described embodiments may be a personal computer, a laptop computer, a vehicle-mounted human-computer interaction device, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0178] Although one or more embodiments of the present disclosure provide method operation steps as described in the embodiments or flowcharts, more or fewer operation steps can be included based on conventional or non-inventive means. The order of steps listed in the embodiments is only one of the many step execution orders, and does not represent the only execution order. When the device or terminal product is executed in practice, it can be executed in sequence or in parallel (for example, in a parallel processor or multi-thread processing environment, or even in a distributed data processing environment) according to the method order shown in the embodiments or the accompanying drawings.

[0179] The terms "comprise", "contain", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, products or devices that include a series of elements not only include those elements, but also include other elements not explicitly listed, or further include elements inherent to such processes, methods, products or devices. Without more limitations, it does not exclude the presence of other same or equivalent elements in the processes, methods, products or devices that include the elements. For example, if the words "first", "second" and the like are used to indicate names, they do not mean any particular order.

[0180] For ease of description, the above apparatus is described in various modules with different functions respectively. Of course, functions of the modules can be implemented in one or more software and / or hardware in implementing one or more embodiments of the present disclosure, and the modules with the same function can be implemented by a combination of a plurality of sub-modules or sub-units, etc. The above-described apparatus embodiments are merely illustrative. For example, the division of the units is merely a logical function division, and there can be another division manner in actual implementation. For example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or other forms.

[0181] The present disclosure is described with reference to flowcharts and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and a combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus generate a means for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0182] These computer program instructions can also be stored in a computer readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction means, which implements the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams. These computer program instructions can also be loaded into a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to generate a computer implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide steps for implementing the functions specified in one or more flows of the flowcharts and / or one or more blocks of the block diagrams.

[0183] Those skilled in the art should understand that one or more embodiments of the present disclosure can take the form of entirely hardware embodiments, entirely software embodiments or embodiments combining software and hardware aspects. Moreover, one or more embodiments of the present disclosure can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0184] One or more embodiments of the disclosure can be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types. One or more embodiments of the disclosure can also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules can be located in both local and remote computer storage media including memory storage devices.

[0185] Identical or similar parts among various embodiments of the disclosure can be mutually referred to each other, and each embodiment focuses on the difference from other embodiments. Especially, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the method embodiments. In the description of the disclosure, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the disclosure. In the disclosure, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, the person skilled in the art can combine and combine the different embodiments or examples described in the disclosure and the features of the different embodiments or examples, without contradiction.

[0186] In addition, when used in the disclosure, the words "herein", "above", "below", "hereunder", "the preceding", and words of similar meaning should refer to the entire disclosure rather than any particular part of the disclosure. In addition, unless explicitly stated otherwise or understood in the context used, the conditional language used herein, such as "may", "could", "for example", "such as", and the like, generally aims to express that some embodiments include, while other embodiments do not include, certain features, elements and / or states. Therefore, such conditional language generally does not aim to imply that one or more embodiments require features, elements and / or states in any way, or whether to include these features, elements and / or states or perform these features, elements and / or states in any particular embodiment.

[0187] The above merely provides an example of one or more embodiments of the present disclosure but is not intended to limit one or more embodiments of the present disclosure. One or more embodiments of the present disclosure can have various changes and modifications for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of the present disclosure shall be included in the scope of claims.

Claims

1. A method for operating a memory device, comprising: A first set of read voltage levels is used to perform a read operation on the first logic page for each read voltage level corresponding to the first logic page in the memory device, so as to obtain the first read result of the first logic page; A second set of read voltage levels is used to perform a read operation on the first logic page for each level of read voltage corresponding to the first logic page, so as to obtain a second read result of the first logic page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; A third set of read voltage levels is used to perform a read operation on the first logic page for each level of read voltage corresponding to the first logic page, so as to obtain a third read result of the first logic page. The third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset. A fourth set of read voltage levels is used to perform read operations on the second logic page for each read voltage level corresponding to the second logic page in the memory device, to obtain a fourth read result of the second logic page, wherein the second logic page is different from the first logic page; and Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

2. The method according to claim 1, wherein, The first logic page corresponds to the first-order read voltage and the second-order read voltage. The first offset is configured such that the offset of the read voltage level in the second set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage has the same offset direction as the offset of the read voltage level in the second set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage. The second offset is configured such that the offset of the read voltage level in the third set of read voltage levels for the first read voltage relative to the read voltage level in the first set of read voltage levels for the first read voltage has the same offset direction as the offset of the read voltage level in the third set of read voltage levels for the second read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage.

3. The method according to claim 1, wherein, The first logic page corresponds to the first-order read voltage and the second-order read voltage. The first offset is configured such that the offset of the read voltage level in the second set of read voltage levels for the first order read voltage relative to the read voltage level in the first set of read voltage levels for the first order read voltage has an offset direction opposite to the offset of the read voltage level in the second set of read voltage levels for the second order read voltage relative to the read voltage level in the first set of read voltage levels for the second order read voltage. The second offset is configured such that the offset of the read voltage level in the third set of read voltage levels for the first read voltage relative to the read voltage level in the first set of read voltage levels for the first read voltage has an offset direction opposite to that of the offset of the read voltage level in the third set of read voltage levels for the second read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage.

4. The method according to claim 1, wherein, The first logic page corresponds to a third or more read voltage, wherein the third or more read voltage includes a first read voltage and a second read voltage, and wherein, The first offset is configured such that the offset of the read voltage level in the second group of read voltage levels for the first read voltage relative to the read voltage level in the first group of read voltage levels for the first read voltage relative to the read voltage level in the first group of read voltage levels for the second read voltage relative to the read voltage level in the first group of read voltage levels for the second read voltage relative to the read voltage level in the first group of read voltage levels for the second read voltage relative to the read voltage level in the second group of read voltage levels for the second read voltage relative to the read voltage level in the first ... The second offset is configured such that the offset of the read voltage level in the third set of read voltage levels for the first read voltage relative to the read voltage level in the first set of read voltage levels for the first read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage relative to the read voltage level in the first set of read voltage levels for the second read voltage relative to the read voltage level in the third set of read voltage levels for each read voltage other than the first read voltage and the second read voltage relative to the read voltage level in the first set of read voltage levels for each read voltage relative to the read voltage level in the first set of read voltage levels for each read voltage relative to the first read voltage.

5. The method according to claim 1, wherein, The first offset and the second offset have the same offset amount.

6. The method according to claim 1, comprising: In response to determining, based on the first read result, the second read result, the third read result, and the fourth read result, that the first set of read voltage levels should not be deviated to obtain the set of optimal read voltage levels, the first set of read voltage levels is determined as the set of optimal read voltage levels.

7. The method according to claim 1, comprising: In response to determining, based on the first read result, the second read result, the third read result, and the fourth read result, to offset the first set of read voltage levels to obtain the set of optimal read voltage levels, the offset direction and the offset value for offsetting the first set of read voltage levels are determined based on the first read result, the second read result, the third read result, and the fourth read result; Based on the determined offset direction, a first offset amount to be applied to the first offset and a second offset amount to be applied to the second offset are determined.

8. The method of claim 7, comprising: In response to determining that the first offset and the second offset do not exceed a preset offset threshold, the first set of read voltage levels is determined as the set of optimal read voltage levels.

9. The method of claim 7, further comprising responding to determining that the first offset and the second offset exceed a preset offset threshold: For each read voltage corresponding to the first logic page, a read operation is performed on the first logic page using the first set of read voltage levels updated based on the offset value, so as to obtain the first read result of the first logic page again; For each read voltage corresponding to the first logical page, a read operation is performed on the first logical page using the second set of read voltage levels updated based on the offset value and the first offset, so as to obtain the second read result of the first logical page again; For each read voltage corresponding to the first logical page, a read operation is performed on the first logical page using the third set of read voltage levels updated based on the offset value and the second offset, so as to obtain the third read result of the first logical page again; as well as Based on the re-obtained first read result, the re-obtained second read result, the re-obtained third read result, and the fourth read result, the set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

10. The method according to claim 1, wherein, Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page, including: Based on the first data generated from the first read result and the fourth read result, the second data generated from the second read result and the fourth read result, and the third data generated from the third read result and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

11. The method according to claim 10, wherein, The first data, the second data, and the third data are generated by performing Boolean operations on the first read result, the second read result, the third read result, and the fourth read result, respectively.

12. The method of claim 11, comprising: Determine the bit 1 count and / or bit 0 count in each of the first data to the third data; For each read voltage corresponding to the first logic page, the difference between the number of bit flips caused by the first offset and the number of bit flips caused by the second offset is determined based on the bit 1 count and / or bit 0 count. Specifically, determining a set of optimal read voltage levels for each read voltage level corresponding to the first logic page, based on the first read result, the second read result, the third read result, and the fourth read result, includes: Based on the difference, a set of optimal read voltage levels is determined for each read voltage level corresponding to the first logic page.

13. The method of claim 12, comprising: In response to determining that the absolute value of the difference does not exceed a preset difference threshold, the first set of read voltage levels is determined as the optimal set of read voltage levels.

14. The method of claim 12, comprising: In response to determining that the absolute value of the difference exceeds a preset difference threshold, the offset direction and the offset value for offsetting the first set of read voltage levels are determined based on the sign of the difference.

15. The method according to claim 1, wherein, The first logical page and the second logical page satisfy at least one of the following: The first logical page and the second logical page correspond to the same physical page in the memory device; The first physical page corresponding to the first logical page and the second physical page corresponding to the second logical page in the memory device are coupled to the same word line in the memory device; The first word line coupled to the first physical page corresponding to the first logical page and the second word line coupled to the second physical page corresponding to the second logical page in the memory device are included in the same set of word lines in the memory device.

16. The method according to claim 1, wherein, The read voltages corresponding to the first logic page include a first read voltage and a second read voltage, and the read voltages corresponding to the second logic page include a third read voltage, which is located between the first read voltage and the second read voltage.

17. The method according to claim 16, wherein, The read voltages corresponding to the second logic page include only one read voltage between the first read voltage and the second read voltage.

18. The method according to claim 1, further comprising: In response to a failure to read data stored in the first logical page, the method according to claim 1 is executed.

19. The method according to claim 18, wherein, Failure to read data stored in the first logical page includes data containing errors in the first logical page being read.

20. The method according to claim 1, 18, or 19, comprising: A read operation is performed on the first logic page using the set of optimal read voltage levels for each read voltage level corresponding to the first logic page, so as to read the data stored in the first logic page.

21. The method according to claim 1, further comprising: During the inspection of the state of the first logical page, the method according to claim 1 is executed.

22. A memory device, comprising: Memory cell array; as well as The peripheral circuitry is coupled to the memory cell array and configured to perform the method according to any one of claims 1 to 21.

23. A memory system, comprising: Memory controller; as well as A memory device, coupled to the memory controller, includes a memory cell array and peripheral circuitry, the peripheral circuitry being coupled to the memory cell array and configured to perform the following operations: A first set of read voltage levels is used to perform a read operation on the first logic page for each level of read voltage corresponding to the first logic page in the memory cell array, so as to obtain the first read result of the first logic page; A second set of read voltage levels is used to perform a read operation on the first logic page for each level of read voltage corresponding to the first logic page, so as to obtain a second read result of the first logic page, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; A third set of read voltage levels is used to perform a read operation on the first logic page for each level of read voltage corresponding to the first logic page, so as to obtain a third read result of the first logic page. The third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset. A fourth set of read voltage levels is used to perform read operations on the second logic page for each read voltage level corresponding to the second logic page in the memory cell array, to obtain a fourth read result for the second logic page, wherein the second logic page is different from the first logic page; and Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

24. The memory system according to claim 23, wherein, The memory device includes input / output circuitry coupled to the peripheral circuitry and the memory controller, the peripheral circuitry being configured as follows: The operation is performed in response to receiving an error correction command from the memory controller via the input / output circuitry.

25. The memory system according to claim 23 or 24, wherein, The memory device includes input / output circuitry coupled to the peripheral circuitry and the memory controller, the peripheral circuitry being configured as follows: In response to receiving a read command from the memory controller via the input / output circuit, a read operation is performed on the first logic page using the set of optimal read voltage levels for each level of read voltage corresponding to the first logic page, so as to read the data stored in the first logic page.

26. The memory system according to claim 23, wherein, The memory device includes input / output circuitry coupled to the peripheral circuitry and the memory controller, the peripheral circuitry being configured as follows: In response to receiving a read command from the memory controller via the input / output circuit, the operation is performed, and a read operation is performed on the first logic page with the set of optimal read voltage levels for each level of read voltage corresponding to the first logic page, so as to read the data stored in the first logic page.

27. The memory system according to claim 23, wherein, The memory device includes input / output circuitry coupled to the peripheral circuitry and the memory controller, the peripheral circuitry being configured as follows: The operation is performed in response to receiving a patrol command from the memory controller via the input / output circuit.

28. A memory controller for controlling a memory device, the memory controller comprising: A memory interface for connecting the memory controller to the memory device; processor; as well as A memory coupled to the processor and storing instructions, which, when executed by the processor, cause the processor to perform the following operations: The memory interface is instructed to send a first read command to the memory device to perform a read operation on the first logic page using a first set of read voltage levels for each level of read voltage corresponding to the first logic page in the memory device, and to receive a first read result of the first logic page from the memory device; The memory interface is instructed to send a second read command to the memory device to perform a read operation on the first logic page using a second set of read voltage levels for each level of read voltage corresponding to the first logic page, and to receive a second read result of the first logic page from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; The memory interface is instructed to send a third read command to the memory device to perform a read operation on the first logic page using a third set of read voltage levels for each level of read voltage corresponding to the first logic page, and to receive a third read result of the first logic page from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset; The memory interface is instructed to send a fourth read command to the memory device to perform a read operation on the second logic page using a fourth set of read voltage levels for each read voltage level corresponding to the second logic page in the memory device, and to receive the fourth read result of the second logic page from the memory device, wherein the second logic page is different from the first logic page; and Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

29. The memory controller according to claim 28, wherein, When the instruction is executed by the processor, the processor: The operation is performed in response to a failure to read data stored in the first logical page.

30. The memory controller according to claim 29, wherein, Failure to read data stored in the first logical page includes data containing errors in the first logical page being read.

31. The memory controller according to any one of claims 28 to 30, wherein, When the instruction is executed by the processor, the processor: The memory is instructed to adjust the read voltage levels stored in the memory for each read voltage level corresponding to the first logic page to the set of optimal read voltage levels.

32. The memory controller according to any one of claims 28 to 30, wherein, When the instruction is executed by the processor, the processor: The memory interface is instructed to send a fifth read command to the memory device to perform a read operation on the first logic page using the set of optimal read voltage levels for each level of read voltage corresponding to the first logic page, and to receive the data stored in the first logic page from the memory device.

33. The memory controller according to claim 28, wherein, When the instruction is executed by the processor, the processor: The operation is performed during the inspection of the state of the first logical page.

34. A memory system, comprising: Memory devices; as well as A memory controller, coupled to the memory device and configured to perform the following operations: Send a first read command to the memory device to perform a read operation on the first logic page using a first set of read voltage levels for each level of read voltage corresponding to the first logic page in the memory device, and receive a first read result of the first logic page from the memory device; A second read command is sent to the memory device to perform a read operation on the first logic page using a second set of read voltage levels for each level of read voltage corresponding to the first logic page, and a second read result of the first logic page is received from the memory device, wherein the second set of read voltage levels has a first offset relative to the first set of read voltage levels; A third read command is sent to the memory device to perform a read operation on the first logic page using a third set of read voltage levels for each level of read voltage corresponding to the first logic page, and a third read result of the first logic page is received from the memory device, wherein the third set of read voltage levels has a second offset relative to the first set of read voltage levels, and the second offset is different from the first offset; Sending a fourth read command to the memory device to perform a read operation on the second logic page using a fourth set of read voltage levels for each read voltage level corresponding to the second logic page in the memory device, and receiving a fourth read result of the second logic page from the memory device, wherein the second logic page is different from the first logic page; and Based on the first read result, the second read result, the third read result, and the fourth read result, a set of optimal read voltage levels is determined for each level of read voltage corresponding to the first logic page.

35. The memory system according to claim 34, wherein, The memory controller is configured to: The operation is performed in response to a failure to read data stored in the first logical page.

36. The memory system according to claim 35, wherein, Failure to read data stored in the first logical page includes data containing errors in the first logical page being read.

37. The memory system according to any one of claims 34 to 36, wherein, The memory controller is configured to: The read voltage levels stored in the memory controller for each level of read voltage corresponding to the first logic page are adjusted to the set of optimal read voltage levels.

38. The memory system according to any one of claims 34 to 36, wherein, The memory controller is configured to: A fifth read command is sent to the memory device to perform a read operation on the first logic page using the set of optimal read voltage levels for each read voltage level corresponding to the first logic page, and to receive the data stored in the first logic page from the memory device.

39. The memory system according to claim 34, wherein, The memory controller is configured to: The operation is performed during the inspection of the state of the first logical page.

40. An electronic device comprising: One or more processors; as well as A memory coupled to the one or more processors and storing computer-executable instructions that, when executed by the one or more processors, cause the one or more processors to perform the method according to any one of claims 1 to 21.

41. A non-transient storage medium having stored thereon computer-executable instructions, which, when executed by one or more processors, cause the one or more processors to perform the method according to any one of claims 1 to 21.

42. A computer program product comprising instructions that, when executed by a processor, implement the method according to any one of claims 1 to 21.

Images