Memory device for performing erase operation in subblock unit and

Abstract

The present disclosure relates to a memory device performing an erase operation in sub-block units and an operating method thereof, the memory device including a plurality of memory blocks each including a first sub-block and a second sub-block, and a control circuit. The control circuit may apply a first erase permission voltage and a first erase voltage among the plurality of erase voltages to a first sub-block of the selected memory block, and check a level of the applied first erase voltage when verification of an erase state of the first sub-block is successful; applying a second erase permission voltage and a second erase voltage among the plurality of erase voltages to a second sub-block of the selected memory block, and checking a level of the applied second erase voltage when verification of an erase state of the second sub-block is successful; and adjusting a level of the first erase permission voltage and a level of the second erase permission voltage based on a result of comparison between the level of the first erase voltage and the level of the second erase voltage.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0130027, filed on September 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to a semiconductor design technique, and more specifically, to a memory device and a method of operating the memory device. Background Technology

[0004] Memory systems are storage devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Memory systems are divided into volatile memory devices and non-volatile memory devices. Volatile memory devices are memory devices whose stored data is lost when power is interrupted. Representative examples of volatile memory devices include static RAM (SRAM), dynamic RAM (DRAM), and synchronous DRAM (SDRAM). Non-volatile memory devices are memory devices whose stored data is retained even when power is interrupted. Representative examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM). Flash memory is mainly divided into NOR type memory and NAND type memory.

[0005] To improve the integration density of semiconductor memory devices, a semiconductor memory device with a three-dimensional array structure was investigated. To efficiently manage the larger memory blocks compared to traditional memory blocks with two-dimensional array structures, a technique for managing memory operations on a sub-block basis was proposed. In other words, a semiconductor memory device was proposed that supports partial erase operations performed on a sub-block basis.

[0006] Although partial erasure operations are performed on a sub-block basis as described above, in general, erasure operations are performed on at least two sub-blocks with different stacking positions from the substrate under the same conditions.

[0007] For this reason, there is concern about reduced data reliability, because in at least two sub-blocks with different stacking positions from the substrate, the data of the sub-block not selected as the erase target will be degraded due to the erase operation performed on the sub-block selected as the erase target. Summary of the Invention

[0008] Various embodiments of this disclosure relate to a memory device and a method of operating the memory device, which can be erased in sub-block units and can improve memory efficiency and the reliability of the erasure operation.

[0009] The technical objectives to be achieved by the embodiments of this disclosure are not limited to those described above, and other objectives not described above can be clearly understood by those skilled in the art from the following description.

[0010] According to embodiments of this disclosure, a memory device may include a plurality of memory blocks and control circuitry. Each memory block includes a first sub-block and a second sub-block. The control circuitry is configured to: apply a first erase enable voltage and a first erase voltage (one of a plurality of erase voltages) to a first sub-block of a selected memory block; and check the level of the applied first erase voltage when the erase state of the first sub-block is successfully verified; apply a second erase enable voltage and a second erase voltage (one of a plurality of erase voltages) to the second sub-block of the selected memory block; and check the level of the applied second erase voltage when the erase state of the second sub-block is successfully verified; and adjust the level of the first erase enable voltage and the level of the second erase enable voltage based on a comparison between the levels of the first erase voltage and the second erase voltage.

[0011] According to embodiments of this disclosure, an operation method for a memory device includes a plurality of memory blocks, each memory block including a first sub-block and a second sub-block. The operation method may include: applying a first erase enable voltage and a first erase voltage (one of a plurality of erase voltages) to a first sub-block of a selected memory block among the plurality of memory blocks, and checking the level of the applied first erase voltage when the erase state of the first sub-block is successfully verified; applying a second erase enable voltage and a second erase voltage (one of a plurality of erase voltages) to the second sub-block of the selected memory block, and then checking the level of the applied second erase voltage when the erase state of the second sub-block is successfully verified; and adjusting the level of the first erase enable voltage and the level of the second erase enable voltage based on a comparison result between the level of the first erase voltage and the level of the second erase voltage.

[0012] According to embodiments of this disclosure, a memory device capable of performing erase operations on a sub-block basis can appropriately adjust the difference between the erase allow voltage and the erase voltage supplied to the sub-blocks based on the position of the sub-blocks stacked on the substrate.

[0013] Therefore, memory efficiency and the reliability of erase operations can be improved. Attached Figure Description

[0014] Figure 1This is a diagram illustrating an example of a memory system including a memory device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a diagram illustrating a memory device connected to an external device for test operations according to an embodiment of the present disclosure.

[0016] Figure 3 This is a diagram illustrating detailed components of a memory device according to embodiments of the present disclosure.

[0017] Figure 4A and Figure 4B This is a flowchart describing an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0018] Figure 5 This is a diagram illustrating the detailed components of a memory block included in a memory device according to embodiments of the present disclosure.

[0019] Figures 6A to 6D This is a diagram illustrating an erase operation performed on a sub-block basis in a memory device according to an embodiment of the present disclosure.

[0020] Figures 7A to 7C This is a timing diagram describing an erase operation performed in a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0021] Various embodiments of the present disclosure are described below with reference to the accompanying drawings. However, the elements and features of the present disclosure may be configured or arranged differently to form other embodiments, which may be variations of any of the disclosed embodiments.

[0022] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as "one embodiment," "example embodiment," "embodiment," "another embodiment," "some embodiments," "multiple embodiments," "other embodiments," "optional embodiments," etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may or may not be combined in the same embodiment.

[0023] In this disclosure, the terms “comprising,” “including,” “containing,” and “comprising” are open-ended. As used in the appended claims, these terms specify the presence of the said element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the device from including other components (e.g., interface units, circuitry, etc.).

[0024] In this disclosure, various units, circuits, or other components may be described or claimed to be "configured to" perform one or more tasks. In this context, "configured to" is used to indicate a structure (e.g., a circuit) that includes a block / unit / circuit / component that performs one or more tasks during operation. Therefore, even if a specified block / unit / circuit / component is not currently operational (e.g., not turned on or activated), it can be said that the block / unit / circuit / component is configured to perform a task. Blocks / units / circuits / components used with the expression "configured to" include hardware, such as circuits, memory storing program instructions executable to perform operations, etc. Additionally, "configured to" may include general-purpose structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., FPGAs or general-purpose processors running software) in a manner capable of performing the relevant tasks. "Configured to" may also include means (e.g., integrated circuits) that adjust manufacturing processes (e.g., semiconductor manufacturing equipment) to manufacture means for performing or implementing one or more tasks.

[0025] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) a purely hardware circuit implementation (e.g., an implementation of purely analog and / or digital circuitry) and (b) a combination of circuitry and software (and / or firmware), such as (if applicable): (i) a combination of processors or (ii) a processor / software (including digital signal processors), software, and memory portions that work together to enable a device such as a mobile phone or server to perform various functions; and (c) circuitry, such as a microprocessor or a portion of a microprocessor, which requires software or firmware for operation even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of the term in this application, including all uses in any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations consisting solely of one or more processors or a portion of a processor and accompanying software and / or firmware of one or more processors. For example, if the terms “circuit” or “logic” apply to a particular claim element, they also cover integrated circuits of a memory device.

[0026] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for nouns following these terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second. Furthermore, while these terms may be used herein to distinguish various elements, these elements are not limited by these terms. These terms are used to differentiate one element from another element with the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0027] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on those factors, or at least partially on those factors. For example, the phrase "A is determined based on B." While B is a factor influencing the determination of A in this case, this phrase does not exclude the possibility that A is also determined based on C. In other cases, A may be determined solely based on B.

[0028] In this document, a data item, data entry, or data term can be a bit sequence. For example, a data item may include the contents of a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or any other entity that can be represented by a bit sequence. According to an embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a data packet transmitted between two different components.

[0029] Figure 1 This is a diagram illustrating a memory system including a memory device according to an embodiment of the present disclosure.

[0030] Figure 2 This is a diagram illustrating a memory device connected to an external device for test operations according to an embodiment of the present disclosure.

[0031] Reference Figure 1 The data processing system 100 may include a host 102 that is coupled to or connected to a memory system such as memory system 110. For example, the host 102 and memory system 110 may be interconnected via a data bus, host cable, etc. to perform data communication.

[0032] Memory system 110 may include memory device 150 and controller 130. Memory device 150 and controller 130 in memory system 110 can be considered as physically separate components or elements. Memory device 150 and controller 130 may be connected via at least one data path. For example, a data path may include a channel and / or a way.

[0033] According to embodiments, the memory device 150 and the controller 130 may be functionally separated components or elements. Further, according to embodiments, the memory device 150 and the controller 130 may be implemented using a single chip or multiple chips. The controller 130 may perform data input / output operations in response to a request input from an external device. For example, when the controller 130 performs a read operation in response to a read request input from an external device, data stored in a plurality of non-volatile memory cells included in the memory device 150 is transferred to the controller 130.

[0034] For example, depending on the host interface protocol, the memory system 110 can be implemented using any of a variety of storage devices that can be electrically connected to the host 102. Non-limiting examples of suitable storage devices include solid-state drives (SSDs), multimedia cards (MMCs), embedded MMCs (eMMCs), miniature MMCs (RS-MMCs), micro MMCs, secure digital cards (SDs), mini SDs, micro SDs, universal serial bus (USB) storage devices, universal flash memory (UFS) devices, compact flash memory (CF) cards, smart media (SM) cards, memory sticks, etc.

[0035] The controller 130 can control the memory device 150 to perform read operations, program operations, and erase operations corresponding to commands input from the host 102, and the memory system 110 can perform these operations independently, regardless of commands input from external devices such as the host 102.

[0036] In this embodiment, the controller 130 can autonomously generate commands, addresses, and data regardless of requests from the host 102, and can send these commands, addresses, and data to the memory device 150. For example, the controller 130 can provide commands, addresses, and data to the memory device 150 to perform background operations, such as read operations and programming operations for wear leveling, garbage collection, read recycling, and media scanning.

[0037] In embodiments, the memory device 150 may take many alternative forms, such as double data rate synchronous dynamic random access memory (DDR SDRAM), fourth generation low power double data rate (LPDDR4) SDRAM, graphics double data rate (GDDR) SDRAM, low power DDR (LPDDR) SDRAM, Rambus dynamic random access memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory device, resistive RAM (RRAM), phase change memory (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), or spin-transfer torque RAM (STT-RAM).

[0038] More specifically, the memory device 150 may include a memory cell array 151 for storing data and a control circuit 152 for controlling the operation of the memory cell array 151.

[0039] The memory cell array 151 may include multiple memory blocks <1, 2, ...>. Furthermore, each of the multiple memory blocks <1, 2, ...> may include multiple pages (not shown).

[0040] A memory block can be understood as a group of non-volatile memory cells whose data is removed together during an erase operation. Each cell in a memory block may include pages (not shown). Logically, non-volatile memory cells are grouped by pages, for example, storing data together during a programming operation or outputting data together during a read operation. For example, a memory block may include multiple pages. A page may include multiple non-volatile memory cells.

[0041] From a physical perspective, which differs from logical operations such as programming or reading, a memory block can include multiple word lines (not shown). A word line can include multiple non-volatile memory cells.

[0042] In this context, depending on the number of bits that can be stored or represented in a non-volatile memory cell, one word line can correspond to at least one page. For example, when a non-volatile memory cell is a single-level cell (SLC) storing one data bit, one word line can correspond to one page. When a non-volatile memory cell is a double-level cell (DLC) storing two data bits, one word line can correspond to two pages. When a non-volatile memory cell is a triple-level cell (TLC) storing three data bits, one word line can correspond to three pages. When a non-volatile memory cell is a quad-level cell (QLC) storing four data bits, one word line can correspond to four pages. Similarly, when a non-volatile memory cell is a multi-level cell storing five or more data bits, one word line can correspond to five or more pages.

[0043] Each of the multiple memory blocks <1, 2, ...> may include two or more sub-blocks that can be erased independently. That is, typically, a memory block is configured as a group of memory cells that can be erased in one erase operation. However, in embodiments of this disclosure, each of the multiple memory blocks may include two or more sub-blocks configured as a group of memory cells that can be erased in one erase operation. In this case, each of the two or more sub-blocks may include multiple cell strings. Each of the multiple cell strings may include multiple memory cells stacked on a substrate.

[0044] Reference Figure 5 as well as Figure 1 Each of the multiple memory blocks <1, 2, ...> can include multiple cell strings CSTR11 to CSTR24 connected between multiple bit lines BL and a common source line CSL. The multiple cell strings CSTR11 to CSTR24 can be constructed identically.

[0045] Each of the multiple cell strings CSTR11 to CSTR24 can be connected between the bit line BL associated with each cell string and the common source line CSL.

[0046] Each of the multiple cell strings CSTR11 to CSTR24 may include multiple drain selection transistors DST<1:2>, multiple memory cells MC<1:8>, multiple dummy memory cells DSC<1:2>, and multiple source selection transistors SST<1:2> connected in series between the bit line BL associated with each cell string and the common source line CSL. The multiple memory cells MC<1:8> represent memory cells used to store valid data. The multiple dummy memory cells DSC<1:2> represent memory cells not used to store valid data.

[0047] Multiple source selection transistors (SST<1:2>), multiple memory cells (MC<1:8>), multiple dummy memory cells (DSC<1:2>), and multiple drain selection transistors (DST<1:2>) can be arranged sequentially along the height direction VD. In this case, the multiple dummy memory cells (DSC<1:2>) can be positioned in the middle of the multiple memory cells (MC<1:8>). For example, as... Figure 5 As shown, multiple virtual memory cells DSC<1:2> can be set between the first to fourth memory cells MC<1:4> and the fifth to eighth memory cells MC<5:8>.

[0048] The gates of multiple source select transistors (SST<1:2>) can be connected to multiple source select lines (SSL<1:2>). The gates of multiple memory cells (MC<1:8>) can be connected to multiple word lines (WL<1:8>). The gates of multiple dummy memory cells (DSC<1:2>) can be connected to multiple dummy word lines (DWL<1:2>). The gates of multiple drain select transistors (DST<1:2>) can be connected to multiple drain select lines (DSL<1:2>).

[0049] A common source line (CSL) can be formed in a substrate (not shown). The substrate can have a main surface extending along a first direction (FD) and a second direction (SD). The common source line (CSL) can extend along the second direction (SD). The first direction (FD) and the second direction (SD) can be orthogonal to each other.

[0050] Bit line BL can extend along the first direction FD and can be set along the second direction SD. Multiple source select lines SSL<1:2>, multiple word lines WL<1:8>, multiple dummy word lines DWL<1:2>, and multiple drain select lines DSL<1:2> can extend along the second direction SD.

[0051] Multiple cell strings CSTR11 to CSTR24 can extend along the height direction VD perpendicular to the main surface of the substrate, and can be arranged along the first direction FD and the second direction SD. In each of the multiple cell strings CSTR11 to CSTR24, the memory cell MC closest to the multiple source selection transistors SST<1:2> is... <1> The height can be the lowest, and it should be the memory cell MC closest to the multiple drain-select transistors DST<1:2>. <8> The height can be the highest.

[0052] Figure 5 The diagram shows two drain-select transistors (DST<1:2>) and two source-select transistors (SST<1:2>) in each of the multiple cell strings CSTR11 to CSTR24. However, at least one drain-select transistor or at least one source-select transistor can be provided in each of the multiple cell strings CSTR11 to CSTR24.

[0053] Figure 5 Each of the multiple cell strings CSTR11 to CSTR24 is shown to include eight main memory cells MC<1:8>. However, at least two memory cells may be provided in each of the multiple cell strings CSTR11 to CSTR24.

[0054] Figure 5 Each of the multiple cell strings CSTR11 to CSTR24 is shown to include two dummy memory cells DSC<1:2>, which are positioned between four main memory cells MC<1:4> and the remaining four memory cells MC<5:8>. However, each of the multiple cell strings CSTR11 to CSTR24 may include one or more dummy memory cells.

[0055] Each of the multiple memory blocks <1, 2, ...> may include a first sub-block 1 and a second sub-block 2. The first sub-block 1 may include first to fourth word lines WL<1:4>. The second sub-block 2 may include fifth to eighth word lines WL<5:8>. In this case, the first sub-block 1 and the second sub-block 2 can be configured along the height direction VD. That is, the first to fourth word lines WL<1:4> stacked on one side of the two dummy word lines DWL<1:2> used as reference word lines can be configured as the first sub-block 1. The fifth to eighth word lines WL<5:8> stacked on the other side of the two dummy word lines DWL<1:2> used as reference word lines can be configured as the second sub-block 2.

[0056] Sub-block 1 and Sub-block 2 can be erased independently. That is, either Sub-block 1 or Sub-block 2 can be selected, and an erase operation can be performed on the selected sub-block, while the unselected sub-block can remain un-erased. In this case, erase prevention voltages can be driven in the two dummy word lines DWL<1:2> set between the first to fourth word lines WL<1:4> and the fifth to eighth word lines WL<5:8> to independently erase Sub-block 1 and Sub-block 2. Furthermore, the levels of the erase prevention voltages driven in the two dummy word lines DWL<1:2> can be different from each other.

[0057] As an example, a method for partitioning the sub-blocks defined in each of a plurality of memory blocks <1, 2, ...> has been described. However, the criteria used for partitioning sub-blocks are not limited to this example. That is, an example has been described in which each of the plurality of memory blocks <1, 2, ...> includes two sub-blocks, Sub-block 1 and Sub-block 2, but each of the plurality of memory blocks <1, 2, ...> may include three or more sub-blocks. Furthermore, an example has been described in which four word lines are included in a sub-block (i.e., Sub-block 1 or Sub-block 2), but it is well understood that a sub-block (i.e., Sub-block 1 or Sub-block 2) may include three or fewer word lines, or five or more word lines. Furthermore, an example has been described in which two dummy word lines DWL<1:2> are included for partitioning two sub-blocks, Sub-block 1 and Sub-block 2, but it is well understood that one or three or more dummy word lines may be included.

[0058] The control circuit 152, under the control of the controller 130, controls the programming operation that stores data in the memory cell array 151, the reading operation that outputs the data stored in the memory cell array 151, and the erasure operation that erases the data stored in the memory cell array 151.

[0059] The control circuit 152 can divide the first to fourth word lines WL<1:4>, which are stacked on one side of the multiple dummy word lines DWL<1:2> positioned in the middle, among the multiple word lines WL<1:8> included in each of the multiple memory blocks <1, 2, ...>, into a first sub-block 1, and can divide the fifth to eighth word lines WL<5:8>, which are stacked on the other side of the multiple dummy word lines DWL<1:2>, into a second sub-block 2. That is, the reason why each of the multiple memory blocks <1, 2, ...> can include at least two sub-blocks is that the control circuit 152 controls the operation by dividing each of the multiple memory blocks <1, 2, ...> into at least two sub-blocks.

[0060] The control circuit 152 can perform an erase operation by applying an erase voltage to the substrate corresponding to a selected memory block among a plurality of memory blocks <1, 2, ...>. That is, the control circuit 152 can perform an erase operation by applying an erase voltage to the common source line (CSL) of the selected memory block. In this case, when performing an erase operation by applying an erase voltage to the substrate corresponding to the selected memory block, the control circuit 152 can select one of the first sub-block 1 and the second sub-block 2 included in the memory block, and then can perform an independent erase operation only on the selected sub-block. For example, when the first sub-block 1 is selected as the erase target and the second sub-block 2 is not selected as the erase target, the control circuit 152 can perform an erase operation only on the first sub-block 1 and may not perform an erase operation on the second sub-block 2.

[0061] For reference, the operation of erasing a memory cell in a programmed state by increasing the voltage level of the channel of the select memory block by applying an erase voltage to the substrate corresponding to the select memory block can be defined as an erase operation using the gate-induced drain leakage (GIDL) method. That is, in an erase operation using the GIDL method, electrons stored in the charge storage layer of a programmed memory cell among multiple memory cells included in the select memory block can be detrapped by the high voltage level of the channel and the low voltage level of the word line. Therefore, the state of the programmed memory cell can be transitioned to the erased state.

[0062] More specifically, in order to perform a first erase process operation on the first sub-block 1 of a selected memory block among a plurality of memory blocks <1, 2, ...>, the control circuit 152 may apply a first erase enable voltage and any one of a plurality of erase voltages to the first sub-block 1 of the selected memory block in a set order (E10). According to an embodiment, with the first erase enable voltage already applied to the first to fourth word lines WL<1:4> corresponding to the first sub-block 1 of the selected memory block, the control circuit 152 may perform the first erase process operation by applying any one of a plurality of erase voltages to the substrate corresponding to the selected memory block and applying an erase prevent voltage to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the selected memory block in a set order.

[0063] Furthermore, after performing the first erase process operation on the first sub-block 1 of the selected memory block, the control circuit 152 can check whether the verification of the erase status of the first sub-block 1 was successful (E10) by performing a first erase verification operation. According to an embodiment, the control circuit 152 can perform the first erase verification operation by applying an erase verification voltage to the first word lines to the fourth word lines WL<1:4> corresponding to the first sub-block 1 of the selected memory block. In this case, the erase verification voltage can be a hard erase verification (HEV) voltage. In this case, the HEV voltage can represent a read voltage that determines the threshold voltage distribution of the memory cells included in the erased memory block.

[0064] In addition, the control circuit 152 can increase the voltage level of the erase voltage according to the incremental step pulse erase (ISPE) method, and simultaneously perform the first erase process operation and the first erase verification operation (E10) alternately on the first sub-block 1 of the selected memory block.

[0065] Furthermore, when the erase state verification is successful in the first erase verification operation, the control circuit 152 can set the erase voltage (i.e., any one of the multiple erase voltages) used in the first erase process operation that was just executed to the first erase voltage (E10).

[0066] Furthermore, if the verification of the erase state in the first erase verification operation fails even after the first erase process operation and the first erase verification operation have been performed alternately a preset number of times, the control circuit 152 can determine that the erase operation on the first sub-block 1 has failed. Additionally, the control circuit 152 can apply the second erase enable voltage and any one of a plurality of erase voltages to the second sub-block 2 of the selected memory block among the plurality of memory blocks MEMORY BLOCK<1, 2, ...> in a set order, so as to perform the second erase process operation (E20) on the second sub-block 2 of the selected memory block. According to an embodiment, when the second erase enable voltage has been applied to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the selected memory block, the control circuit 152 can perform a second erase process operation by applying any one of a plurality of erase voltages to the substrate corresponding to the selected memory block in a set order and applying an erase prevent voltage to the first to fourth word lines WL<1:4> corresponding to the first sub-block 1 of the selected memory block.

[0067] Furthermore, after performing the second erase process operation, i.e., the erase operation for the second sub-block 2 of the selected memory block, the control circuit 152 can check whether the verification of the erase status of the second sub-block 2 was successful (E20) by performing a second erase verification operation. According to an embodiment, the control circuit 152 can perform the second erase verification operation by applying an erase verification voltage to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the selected memory block. In this case, the erase verification voltage can be the HEV voltage. In this case, the HEV voltage can represent the read voltage that determines the threshold voltage distribution of the memory cells included in the erased memory block. That is, the control circuit 152 can use the same erase verification voltage in the first erase verification operation for the first sub-block 1 of the selected memory block and the second erase verification operation for the second sub-block 2 of the selected memory block.

[0068] In addition, the control circuit 152 can increase the voltage level of the erase voltage according to the ISPE method, while alternately performing the second erase process operation and the second erase verification operation (E20) on the second sub-block 2 of the selected memory block.

[0069] Furthermore, when the erasure status verification is successful in the second erasure verification operation, the control circuit 152 can set the erasure voltage (i.e., any one of the multiple erasure voltages) used in the previously executed second erasure process operation as the second erasure voltage (E20).

[0070] Furthermore, if the verification of the erase state in the second erase verification operation is still unsuccessful even after the second erase process operation and the second erase verification operation have been performed alternately a preset number of times, the control circuit 152 can determine that the erase operation on the second sub-block 2 has failed.

[0071] The control circuit 152 can set the level of the first erase voltage by repeatedly performing the first erase process operation and the first erase verification operation on the first sub-block 1 of the selected memory block as in operation E10, and can set the level of the second erase voltage by repeatedly performing the second erase process operation and the second erase verification operation on the second sub-block 2 of the selected memory block as in operation E20.

[0072] Subsequently, the control circuit 152 can compare the levels of the first erase voltage and the second erase voltage, and can adjust the levels of the first erase enable voltage and the second erase enable voltage based on the comparison result (E30).

[0073] In other words, control circuit 152 can perform operation E30 by referencing the level of the first erase voltage used in the first erase process operation included in operation E10 and the level of the second erase voltage used in the second erase process operation included in operation E20, to adjust the levels of the first erase allow voltage and the second erase allow voltage to be used in the subsequently executed operations E10 and E20. Therefore, if control circuit 152 executes operations E10 and E20 after executing operation E30, control circuit 152 can use the first erase allow voltage and the second erase allow voltage with the levels adjusted in the previously executed operation E30.

[0074] According to an embodiment, the control circuit 152 can adjust the levels of the first erase enable voltage and the second erase enable voltage by performing operation E10 on the first sub-block 1 of the first memory block MEMORY BLOCK 1 in a plurality of memory blocks MEMORY BLOCK <1, 2, ...> using a first erase enable voltage with a default level, performing operation E20 on the second sub-block 2 of the first memory block MEMORY BLOCK 1 using a second erase enable voltage with a default level, and then performing operation E30.

[0075] Subsequently, when operation E10 is performed on the first sub-block 1 of the second memory block MEMORY BLOCK 2 out of multiple memory blocks MEMORY BLOCK <1, 2, ...>, the control circuit 152 can use a first erase enable voltage having a level adjusted in the previously performed operation E30. Similarly, when operation E20 is performed on the second sub-block 2 of the second memory block MEMORY BLOCK 2, the control circuit 152 can use a second erase enable voltage having a level adjusted in the previously performed operation E30.

[0076] More specifically, control circuit 152 can perform operation E10 on the first sub-block 1 of a selected memory block among multiple memory blocks MEMORY BLOCK<1, 2, ...> by using a first erase enable voltage with a default level and multiple erase voltages. Next, control circuit 152 can perform operation E20 on the second sub-block 2 of the selected memory block by using a second erase enable voltage with a default level and multiple erase voltages. Next, control circuit 152 can perform operation E30 by using the first erase voltage set in operation E10 and the second erase voltage set in operation E20.

[0077] When the level of the first erase voltage is higher than the level of the second erase voltage, the control circuit 152 can perform operation E30 to set the level of the second erase enable voltage to be higher than the level of the first erase enable voltage.

[0078] When the level of the second erase voltage is higher than the level of the first erase voltage, the control circuit 152 can perform operation E30 to set the level of the first erase allow voltage to be higher than the level of the second erase allow voltage.

[0079] When the levels of the first erase voltage and the second erase voltage are the same, the control circuit 152 can perform operation E30 to set the levels of the first erase enable voltage and the first erase enable voltage to be the same.

[0080] When the level of the first erase voltage and the level of the second erase voltage are both higher than the expected level, the control circuit 152 can perform operation E30 to set the level of the first erase enable voltage and the level of the second erase enable voltage to be higher than the default level.

[0081] When both the level of the first erase voltage and the level of the second erase voltage are higher than the expected level, and the level of the first erase voltage is higher than the level of the second erase voltage, the control circuit 152 can perform operation E30, setting the level of the first erase allowable voltage to be higher than the default level, and setting the level of the second erase allowable voltage to be higher than the level of the first erase allowable voltage. For example, if the default level is 0 V, the control circuit 152 can set the level of the first erase allowable voltage to 0.5 V and set the level of the second erase allowable voltage to 1 V.

[0082] When both the level of the first erase voltage and the level of the second erase voltage are higher than the expected level, and the level of the second erase voltage is higher than the level of the first erase voltage, the control circuit 152 can perform operation E30, setting the level of the second erase enable voltage to be higher than the default level, and setting the level of the first erase enable voltage to be higher than the level of the second erase enable voltage. For example, if the default level is 0 V, the control circuit 152 can set the level of the second erase enable voltage to 0.5 V and set the level of the first erase enable voltage to 1 V.

[0083] When the levels of both the first and second erase voltages are higher than expected and are equal, the control circuit 152 can perform operation E30, setting each of the first and second erase enable voltage levels to be higher than the default level. For example, if the default level is 0 V, the control circuit 152 can set both the first and second erase enable voltage levels to 0.5 V.

[0084] When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level, the control circuit 152 may perform operation E30 to set at least one of the levels of the first erase enable voltage and the second erase enable voltage to the default level.

[0085] When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level and the level of the first erase voltage is higher than the level of the second erase voltage, the control circuit 152 can perform operation E30 to set the level of the first erase allowable voltage to a default level and set the level of the second erase allowable voltage to be higher than the level of the first erase allowable voltage. For example, if the default level is 0 V, the control circuit 152 can set the level of the first erase allowable voltage to 0 V and set the level of the second erase allowable voltage to 0.5 V.

[0086] When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level and the level of the second erase voltage is higher than the level of the first erase voltage, the control circuit 152 can perform operation E30, setting the level of the second erase allowable voltage to a default level and setting the level of the first erase allowable voltage to be higher than the level of the second erase allowable voltage. For example, if the default level is 0 V, the control circuit 152 can set the level of the first erase allowable voltage to 0.5 V and set the level of the second erase allowable voltage to 0 V.

[0087] When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level and the levels of the first erase voltage and the second erase voltage are the same, the control circuit 152 can perform operation E30 to set each of the levels of the first erase enable voltage and the second erase enable voltage to the default level.

[0088] The control circuit 152 can control the operation of the memory device 150 by dividing the operation of the memory device 150 into a first operation mode and a second operation mode.

[0089] Furthermore, the control circuit 152 can enter a second operating mode after entering / exiting the first operating mode. In this case, the exit timing of the first operating mode and the entry timing of the second operating mode can be divided in various ways according to the method of using the memory device 150. For example, the control circuit 152 can enter the second operating mode in response to exiting the first operating mode. As another example, the control circuit 152 can enter the second operating mode when at least one power-off and power-on event occurs after the control circuit 152 exits the first operating mode.

[0090] According to an embodiment, the control circuit 152 can enter a first operation mode when the test operation begins and exit the first operation mode when the test operation is completed.

[0091] According to an embodiment, the control circuit 152 can enter a second operating mode when normal operation begins after a test operation.

[0092] In this context, test operations may include wafer test operations, package test operations, or built-in self-test operations.

[0093] According to the embodiments, such as Figure 1 As shown, the memory device 150 can enter / exit a first operating mode in order to autonomously perform a built-in self-test operation.

[0094] According to another embodiment, such as Figure 2As shown, an external device 170 for wafer testing or package testing operations can be connected to the outside of the memory device 150. In this case, the control circuit 152 can enter a first operating mode and perform test operations under the control of the external device 170.

[0095] Specifically, in the first operating mode, the control circuit 152 can sequentially execute operations E10, E20, and E30 on selected memory blocks among multiple memory blocks <1, 2, ...>. That is, the control circuit 152 can set the level of the first erase voltage by executing operation E10 on the first sub-block 1 of the selected memory block, set the level of the second erase voltage by executing operation E20 on the second sub-block 2 of the selected memory block, and adjust the levels of the first erase allow voltage and the second erase allow voltage by executing operation E30.

[0096] In this scenario, the "selected memory block" chosen as the execution target of operations E10, E20, and E30 in the first operating mode may include at least one memory block from a plurality of memory blocks <1, 2, ...>. According to an embodiment, a desired number of memory blocks belonging to the plurality of memory blocks <1, 2, ...> and located in a specific position can be selected as "selected memory blocks" at which the effects of process, voltage, and temperature (PVT) will be relatively greatest. According to another embodiment, a predetermined number of memory blocks belonging to the plurality of memory blocks <1, 2, ...> and located in a specific position where the PVT effect will be greatest, and a predetermined number of memory blocks belonging to the plurality of memory blocks <1, 2, ...> and located in a specific position where the PVT effect will be least, can be selected as "selected memory blocks".

[0097] After performing operations E10, E20, and E30 sequentially on the selected memory block in the first operating mode as described above, the control circuit 152 can exit the first operating mode. That is, the control circuit 152 can adjust the levels of the first erase enable voltage and the second erase enable voltage by entering / exiting the first operating mode.

[0098] Furthermore, the control circuit 152 can maintain a first erase enable voltage and a second erase enable voltage, having levels adjusted in the first operating mode, in a non-volatile state. For example, the control circuit 152 can store the first erase enable voltage and the second erase enable voltage, having levels adjusted in the first operating mode, in some regions of the memory cell array 151.

[0099] Furthermore, when performing an erase operation on the first sub-block 1 of each of the multiple memory blocks <1, 2, ...> in the second operating mode, the control circuit 152 can use a first erase-allowed voltage having a level adjusted in the first operating mode. Similarly, when performing an erase operation on the second sub-block 2 of each of the multiple memory blocks <1, 2, ...> in the second operating mode, the control circuit 152 can use a second erase-allowed voltage having a level adjusted in the first operating mode.

[0100] After entering / exiting the first operating mode, the control circuit 152 can enter the second operating mode. In this case, the second operating mode can be a mode that the control circuit 152 enters for normal operation, which is different from the test operation. Therefore, as... Figure 1 As shown, the control circuit 152 can enter the second operating mode only in a configuration where the memory device 150 is included in the memory system 110.

[0101] Therefore, as Figure 1 As shown, after entering / exiting a first operating mode in a configuration in which the memory device 150 is included in the memory system 110, the control circuit 152 can enter a second operating mode. In this case, the control circuit 152 can enter the second operating mode in response to exiting the first operating mode.

[0102] In addition, in such Figure 2 After the external device 170 for test operation has been connected to the external structure of the memory device 150 and entered / exited the first operating mode, the structure where the external device 170 is connected to the external structure of the memory device 150 has been changed as follows: Figure 1 With the memory device 150 already included in the memory system 110, the control circuit 152 can enter a second operating mode. In this case, the control circuit 152 can enter the second operating mode when at least one power-off and power-on event occurs after exiting the first operating mode.

[0103] Figure 3 This is a diagram illustrating detailed components of a memory device according to embodiments of the present disclosure.

[0104] Reference Figure 3The memory device 150 may include a memory cell array 151 for storing data. The memory device 150 may include control circuitry 152 configured to perform programming operations that store data in the memory cell array 151, reading operations that output data stored in the memory cell array 151, and erasing operations that erase data stored in the memory cell array 151.

[0105] The memory cell array 151 may include multiple memory blocks <1, 2, ...>. The structure of each of the multiple memory blocks <1, 2, ...> can be referred to... Figure 1 and Figure 5 The structure.

[0106] For reference, it can be seen that Figure 3 This shows that the local line LL and bit line BL are connected to each of multiple memory blocks <1, 2, ...>. If such a structure corresponds to... Figure 5 From the structure, it can be seen that the local line LL has the following form: the local line LL includes multiple source select lines SSL<1:2>, multiple word lines WL<1:8>, multiple dummy word lines DWL<1:2> and multiple drain select lines DSL<1:2>.

[0107] The control circuit 152 may include control logic 300 and peripheral circuitry 200. The peripheral circuitry 200 may be configured to perform programming, reading, and erasing operations on each of the multiple memory blocks <1, 2, ...> under the control of the control logic 300.

[0108] Under the control of the control logic 300, the peripheral circuit 200 can perform operation E10 on the first sub-block 1 of the selected memory block among multiple memory blocks MEMORY BLOCK<1, 2, ...>, or perform operation E20 on the second sub-block 2 of the selected memory block.

[0109] In a first operating mode, control logic 300 can control peripheral circuit 200 by performing operation E10 on the first sub-block 1 of the selected memory block to check the level of the first erase voltage, and by performing operation E20 on the second sub-block 2 of the selected memory block to check the level of the second erase voltage. Furthermore, control logic 300 can execute operation E30 using the level of the first erase voltage checked in operation E10 and the level of the second erase voltage checked in operation E20.

[0110] More specifically, the peripheral circuitry 200 may include a voltage generator 210, a row decoder 220, a page buffer group 230, a column decoder 240, input and output circuitry 250, a pass / fail determiner 260, and a substrate driver 270.

[0111] Voltage generator 210 can generate various operating voltages Vop used in programming, reading, and erasing operations in response to the operation signal OP_CMD. For example, voltage generator 210 can generate programming voltage, read verification voltage, pass voltage, first erase enable voltage, second erase enable voltage, multiple erase voltages, erase verification voltage, and select transistor operating voltage under the control of control logic 300.

[0112] In response to the row decoder control signal AD_signal, the row decoder 220 can transmit the operating voltage Vop to the local line LL of the selected memory block among multiple memory blocks MEMORY BLOCK<1, 2, ...>. For example, in response to the row decoder control signal AD_signal, the row decoder 220 can supply a first erase enable voltage, a second erase enable voltage, an erase verification voltage, and an erase prevention voltage to multiple word lines WL<1:8> included in the local line LL, wherein the first erase enable voltage, the second erase enable voltage, and the erase verification voltage are generated by the voltage generator 210.

[0113] Page buffer group 230 may include multiple page buffers PB1 to PBn connected to bit lines BL1 to BLn. The multiple page buffers PB1 to PBn may operate in response to a page buffer control signal PBSIGNAL. For example, when an operation applying multiple erase voltages is performed during an erase operation, the multiple page buffers PB1 to PBn may control bit lines BL1 to BLn in a floating state and may sense the current or voltage level of each of the bit lines BL1 to BLn after the erase verification operation has begun.

[0114] The column decoder 240 can transfer data between the input and output circuitry 250 and the page buffer group 230 in response to the column address CADD. For example, the column decoder 240 can exchange data with the page buffer 231 via the data line DL, or with the input and output circuitry 250 via the column line CL.

[0115] The input and output circuit 250 can transmit data from the controller (…). Figure 1 The command CMD and address ADD received by 130 are transmitted to control logic 300, or data DATA can be exchanged with column decoder 240.

[0116] After a read operation, read verification operation, or erase verification operation begins, the pass / fail determiner 260 can generate a reference current in response to the enable bit VRY_BIT<#>, and can output a pass signal PASS or a failure signal FAIL by comparing the sensed voltage VPB received from the page buffer group 230 with the reference voltage generated based on the reference current.

[0117] The substrate driver 270 can be connected to the memory cells included in the memory cell array 151 via a common source line CSL, and can control the voltage applied to the common source line CSL. After the erase operation begins, the substrate driver 270 can supply any of a plurality of erase voltages to the substrate via the common source line CSL.

[0118] The substrate driver 270 can receive the source line control signal CTRL_SL from the control logic 300, and can control the source line voltage applied to the common source line CSL based on the source line control signal CTRL_SL.

[0119] Control logic 300 can respond to commands CMD and addresses ADD by controlling peripheral circuitry 200 through outputting operation signals OP_CMD, line decoder control signals AD_signal, page buffer control signals PBSIGNAL, and enable bits VRY_BIT<#>. Furthermore, control logic 300 can determine whether a read verification operation or an erase verification operation has passed or failed by using signals PASS or FAIL.

[0120] Figure 4A and Figure 4B This is a flowchart describing an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0121] Reference Figure 4A and Figure 4B As can be seen, after entering the first operating mode, the memory device 150 according to the embodiments of this disclosure sets the level of the first erase voltage by performing operation E10 on the first sub-block 1 of the selected memory block among a plurality of memory blocks MEMORY BLOCK<1, 2, ...>, sets the level of the second erase voltage by performing operation E20 on the second sub-block 2 of the selected memory block, and then adjusts the levels of the first erase enable voltage and the second erase enable voltage by performing operation E30. For reference, in Figure 4A and Figure 4B In the first operating mode, operations E10, E20, and E30 are executed sequentially; however, this is merely illustrative. Operations E20, E10, and E30 can be executed sequentially according to the designer's choice.

[0122] Reference Figure 4A Operation E10 can be performed in the following order.

[0123] First, the first erase process operation (S10) can be performed by applying the first erase enable voltage and any one of the multiple erase voltages to the first sub-block 1 of the selected memory block among the multiple memory blocks MEMORY BLOCK<1, 2, ...>.

[0124] After S10, in order to check whether each of the threshold voltage levels of the memory cells included in the first sub-block 1 of the selected memory block is lower than the level of the erase verification voltage, a first erase verification operation (S20) can be performed to apply the erase verification voltage to the first sub-block 1 of the selected memory block.

[0125] The success of the verification of the erase status of the first sub-block 1 of the selected storage block can be checked by the first erase verification operation performed in S20 (S30).

[0126] When the verification of the erase state of the first sub-block 1 of the selected memory block fails (No in S30), any one of the multiple erase voltages can be selected again (S35). Furthermore, S10, S20, S30, and S35 can be repeated using the erase voltage selected in S35 until the verification of the erase state of the first sub-block 1 of the selected memory block succeeds (Yes in S30). In this case, the multiple erase voltages selected in S35 can be erase voltages that increase sequentially in proportion to the number of repetitions of S35 according to the ISPE method. For example, multiple erase voltages can be selected sequentially in S35 by using the erase voltage with the lowest level among the multiple erase voltages in the first execution of S10, and the erase voltage with the second lowest level among the multiple erase voltages in the second execution of S10.

[0127] When the verification of the erase status of the first sub-block 1 of the selected storage block is successful (yes in S30), the erase voltage (i.e., any one of the multiple erase voltages) selected in the previously executed S35 and used in S10 can be set as the first erase voltage (S40).

[0128] Reference Figure 4A Operation E20 can be performed in the following order.

[0129] First, the second erase process operation (S50) can be performed by applying the second erase enable voltage and any one of the multiple erase voltages to the second sub-block 2 of the selected memory block among the multiple memory blocks MEMORY BLOCK<1, 2, ...>. In this case, the selected memory block as the target of operation E10 and the selected memory block as the target of operation E20 can be the same memory block.

[0130] After S50, in order to check whether each of the threshold voltage levels of the memory cells included in the second sub-block 2 of the selected memory block is lower than the level of the erase verification voltage, a second erase verification operation (S60) can be performed to apply the erase verification voltage to the second sub-block 2 of the selected memory block.

[0131] The success of the verification of the erase status of the second sub-block 2 of the selected storage block can be checked by the second erase verification operation performed in S60 (S70).

[0132] When the verification of the erase status of the second sub-block 2 of the selected memory block fails (No in S70), any one of the multiple erase voltages can be selected again (S75). Furthermore, S50, S60, S70, and S75 can be repeated using the erase voltage selected in S75 until the verification of the erase status of the second sub-block 2 of the selected memory block succeeds (Yes in S70). In this case, the multiple erase voltages selected in S75 can be erase voltages that increase sequentially in proportion to the number of repetitions of S75 according to the ISPE method. For example, multiple erase voltages can be selected sequentially in S75 by using the erase voltage with the lowest level among the multiple erase voltages in the first execution of S50, and the erase voltage with the second lowest level among the multiple erase voltages in the second execution of S50.

[0133] When the verification of the erase status of the second sub-block 2 of the selected storage block is successful (yes in S70), the erase voltage (i.e., any one of the multiple erase voltages) selected in the previously executed S75 and used in S50 can be set as the second erase voltage (S80).

[0134] Reference Figure 4B Operation E30 can be performed in the following order.

[0135] First, it can be checked whether the level of the first erase voltage set in the previously executed operation E10 and the level of the second erase voltage set in the previously executed operation E20 are greater than the expected level (S91).

[0136] When the level of the first erase voltage and the level of the second erase voltage are both greater than the expected level (yes in S91), it can be checked whether the level of the first erase voltage is higher than the level of the second erase voltage (S92).

[0137] When the level of the first erase voltage is higher than the level of the second erase voltage in S92 (which is true in S92), the level of the first erase enable voltage can be set higher than the default level, and the level of the second erase enable voltage can be set higher than the level of the first erase enable voltage (S94).

[0138] When the level of the first erase voltage in S92 is equal to or lower than the level of the second erase voltage (no in S92), it can be checked whether the levels of the first erase voltage and the second erase voltage are the same (S93).

[0139] When the levels of the first erase voltage and the second erase voltage are the same in S93 (yes in S93), each of the levels of the first erase enable voltage and the second erase enable voltage can be set to be higher than the default level, and the levels of the first erase enable voltage and the second erase enable voltage can be set to be the same as each other (S95).

[0140] When the levels of the first erase voltage and the second erase voltage are not the same in S93 (no in S93), the level of the second erase enable voltage can be set higher than the default level, and the level of the first erase enable voltage can be set higher than the level of the second erase enable voltage (S96).

[0141] If at least one of the levels of the first erase voltage and the second erase voltage is equal to or lower than the expected level (no in S91), it can be checked whether the level of the first erase voltage is higher than the level of the second erase voltage (S97).

[0142] When the level of the first erase voltage is higher than the level of the second erase voltage in S97 (which is true in S97), the level of the first erase enable voltage can be set to the default level, and the level of the second erase enable voltage can be set to be higher than the level of the first erase enable voltage (S99).

[0143] When the level of the first erase voltage in S97 is equal to or lower than the level of the second erase voltage (no in S97), it can be checked whether the levels of the first erase voltage and the second erase voltage are the same (S98).

[0144] When the levels of the first erase voltage and the second erase voltage are the same in S98 (yes in S98), each of the levels of the first erase enable voltage and the second erase enable voltage can be set to the default level (S9A).

[0145] When the levels of the first erase voltage and the second erase voltage are not the same in S98 (no in S98), the level of the second erase enable voltage can be set to the default level, and the level of the first erase enable voltage can be set to a level higher than the level of the second erase enable voltage (S9B).

[0146] Figures 6A to 6D This is a diagram illustrating an erase operation performed on a sub-block basis in a memory device according to an embodiment of the present disclosure.

[0147] first, Figure 6A and Figure 6B This shows the voltage applied to the target memory block when an erase operation is performed on the first sub-block 1 included in each of the multiple memory blocks <1, 2, ...>.

[0148] also, Figure 6C and Figure 6D The voltage applied to the target memory block to be erased is shown when an erase operation is performed on the second sub-block 2 included in each of the multiple memory blocks <1, 2, ...>.

[0149] Specifically, from Figure 6A It can be seen which voltage is applied to the target memory block in order to perform the first erase process operation on the first sub-block 1 of the target memory block.

[0150] First, a first erase-allowed voltage can be applied to the first to fourth word lines WL<1:4> corresponding to the first sub-block 1 of the target memory block. That is, in order to lower the threshold voltage level of the memory cells included in the first sub-block 1 of the target memory block, the first erase-allowed voltage can be applied to the first to fourth word lines WL<1:4>. For example, the level of the first erase-allowed voltage can be set to a voltage level between 0 V and 2 V.

[0151] Furthermore, an erase prevention voltage can be applied to the word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. That is, to ensure that the threshold voltage levels of the memory cells included in the second sub-block 2 of the target memory block remain unchanged, the erase prevention voltage can be applied to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. For example, the erase prevention voltage can be set to a voltage level between 18 V and 20 V.

[0152] Furthermore, one of a plurality of erase voltages can be applied to the common source line CSL connected to the substrate. In this case, as described above, according to the ISPE method, each time the first erase process operation is repeated, one of a plurality of erase voltages can be selected according to a set sequence, and the selected erase voltage can be applied to the common source line CSL. That is, for example, an erase voltage of 18 V can be selected in the first first erase process operation, an erase voltage of 18.5 V can be selected in the second first erase process operation, and an erase voltage of 19 V can be selected in the third first erase process operation.

[0153] In addition, from Figure 6B It can be seen which voltage is applied to the target memory block in order to perform the first erase verification operation on the first sub-block 1 of the target memory block.

[0154] First, an erase verification voltage can be applied to the first to fourth word lines (WL<1:4>) corresponding to the first sub-block 1 of the target memory block. That is, to check whether the threshold voltage levels of each memory cell included in the first sub-block 1 of the target memory block are lower than the erase verification voltage level, the erase verification voltage can be applied to the first to fourth word lines (WL<1:4>) corresponding to the first sub-block 1 of the target memory block. For example, the erase verification voltage level can be set to a voltage level between 4.5 V and 5 V.

[0155] Furthermore, the erase pass voltage can be applied to the word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block to be erased. That is, in order to exclude memory cells included in the second sub-block 2 of the target memory block from the target of the first erase verification operation (i.e., to protect unerased memory cells), the erase pass voltage can be applied to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block to be erased. For example, the erase pass voltage can be set to a voltage level between 10 V and 12 V.

[0156] In addition, a ground voltage VSS can be applied to the common source line CSL connected to the substrate.

[0157] In addition, from Figure 6C It can be seen which voltage is applied to the target memory block in order to perform the second erase process operation on the second sub-block 2 of the target memory block.

[0158] First, a second erase enable voltage can be applied to the word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. That is, to lower the threshold voltage level of the memory cells included in the second sub-block 2 of the target memory block, the second erase enable voltage can be applied to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. For example, the level of the second erase enable voltage can be set to a voltage level between 0 V and 2 V.

[0159] Furthermore, an erase prevention voltage can be applied to the first to fourth word lines (WL<1:4>) corresponding to the first sub-block 1 of the target memory block. That is, to ensure that the threshold voltage levels of the memory cells included in the first sub-block 1 of the target memory block remain unchanged, an erase prevention voltage can be applied to the first to fourth word lines (WL<1:4>) corresponding to the first sub-block 1 of the target memory block. For example, the erase prevention voltage can be set to a voltage level between 18 V and 20 V.

[0160] Furthermore, one of a plurality of erase voltages can be applied to the common source line CSL connected to the substrate. In this case, as described above, according to the ISPE method, each time the second erase process operation is repeated, one of a plurality of erase voltages can be selected according to a set sequence, and the selected erase voltage can be applied to the common source line CSL. That is, for example, an erase voltage of 18 V can be selected in the first second erase process operation, an erase voltage of 18.5 V can be selected in the second second erase process operation, and an erase voltage of 19 V can be selected in the third second erase process operation.

[0161] In addition, from Figure 6D It can be seen which voltage is applied to the target memory block in order to perform the second erase verification operation on the second sub-block 2 of the target memory block.

[0162] First, an erase verification voltage can be applied to the word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. That is, to check whether the threshold voltage levels of each memory cell included in the second sub-block 2 of the target memory block are lower than the erase verification voltage level, the erase verification voltage can be applied to the fifth to eighth word lines WL<5:8> corresponding to the second sub-block 2 of the target memory block. For example, the erase verification voltage level can be set to a voltage level between 4.5 V and 5 V.

[0163] Furthermore, the erase pass voltage can be applied to the first to fourth word lines WL<1:4> corresponding to the first sub-block 1 of the target memory block to be erased. That is, in order to exclude memory cells included in the first sub-block 1 of the target memory block from the target of the second erase verification operation (i.e., to protect unerased memory cells), the erase pass voltage can be applied to the first to fourth word lines WL<1:4> corresponding to the first sub-block 1 of the target memory block to be erased. For example, the level of the erase pass voltage can be set to a voltage level between 10 V and 12 V.

[0164] In addition, a ground voltage VSS can be applied to the common source line CSL connected to the substrate.

[0165] Figures 7A to 7C This is a timing diagram describing an erase operation performed in a memory device according to an embodiment of the present disclosure.

[0166] first, Figure 7AThe erase operation performed on the first sub-block 1 of the selected storage block in the first operating mode can be shown, namely operation E10.

[0167] Specifically, the first erase process operation ERAx can be performed by: applying a first erase enable voltage VPMA to the word line (WLs of Sub-block1) corresponding to the first sub-block 1 of the selected memory block among the plurality of memory blocks MEMORY BLOCK<1, 2, ...>, applying an erase prevent voltage VPHI to the word line (WLs of Sub-block2) corresponding to the second sub-block 2 of the selected memory block, and applying any one of the plurality of erase voltages VERSx to the common source line CSL connected to the substrate.

[0168] In addition, a first erase verification operation VEAx can be performed: an erase verification voltage VEY is applied to the word line (WLsof Sub-block1) corresponding to the first sub-block 1 of the selected memory block among the multiple memory blocks MEMORY BLOCK<1, 2, ...>, an erase pass voltage VPASS is applied to the word line (WLs of Sub-block2) corresponding to the second sub-block 2 of the selected memory block, and a ground voltage VSS is applied to the common source line CSL. In this case, x can be a natural number equal to or greater than 1.

[0169] More specifically, after the erase operation on the first sub-block 1 begins, in the first erase process operation ERA1, the first erase enable voltage VPMA can be applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1, the erase prevent voltage VPHI can be applied to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2, and "VERS1" of the multiple erase voltages VERSx can be applied to the common source line CSL.

[0170] Next, in the first erase verification operation VEA1, the erase verification voltage VEY can be applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1, the erase pass voltage VPASS can be applied to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2, and the ground voltage VSS can be applied to the common source line CSL.

[0171] If the erase status verification of Sub-block 1 is successful in the first erase verification operation VEA1, the second first erase process operation ERA2 can be skipped. However, in Figure 7A In the first erase verification operation VEA1, the verification of the erase status of the first sub-block 1 failed. Therefore, it can be seen that the second first erase process operation ERA2 is executed using "VERS2" among multiple erase voltages VERSx, and then the second first erase verification operation VEA2 is executed.

[0172] Similarly, if the erase status verification of Sub-block 1 is successful in the second first erase verification operation VEA2, the third first erase process operation ERA3 can be omitted. However, in Figure 7A In the second first erase verification operation VEA2, the verification of the erase status of the first sub-block 1 failed. Therefore, it can be seen that the third first erase process operation ERA3 is executed using "VERS3" among multiple erase voltages VERSx, and the third first erase verification operation VEA3 is executed.

[0173] In addition, Figure 7A In the third first erase verification operation (VEA3), the erase status of the first sub-block 1 is successfully verified. Therefore, "VERS3" used in the third first erase process operation (ERA3), which was just executed before the third first erase verification operation (VEA3), can be set as the first erase voltage.

[0174] also, Figure 7B The erase operation performed on the second sub-block 2 of the selected storage block in the first operating mode can be shown, namely operation E20.

[0175] Specifically, the second erase process operation ERBx can be performed by: applying an erase prevention voltage VPHI to the word line (WLs of Sub-block1) corresponding to the first sub-block 1 of the selected memory block among the plurality of memory blocks MEMORY BLOCK<1, 2, ...>, applying a second erase enable voltage VPMB to the word line (WLs of Sub-block2) corresponding to the second sub-block 2 of the selected memory block, and applying any one of the plurality of erase voltages VERSx to the common source line CSL connected to the substrate.

[0176] In addition, a second erase verification operation VEBx can be performed: an erase pass voltage VPASS is applied to the word line (WLsof Sub-block1) corresponding to the first sub-block 1 of the selected memory block among the multiple memory blocks MEMORY BLOCK<1, 2, ...>, an erase verification voltage VEY is applied to the word line (WLs of Sub-block2) corresponding to the second sub-block 2 of the selected memory block, and a ground voltage VSS is applied to the common source line CSL. In this case, x can be a natural number equal to or greater than 1.

[0177] More specifically, after the erase operation on the second sub-block 2 begins, in the first second erase process operation ERB1, the second erase enable voltage VPMB can be applied to the word line (WLs of Sub-block 2) corresponding to the selected memory block, the erase prevent voltage VPHI can be applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1, and the erase voltage "VERS1" among the multiple erase voltages VERSx can be applied to the common source line CSL.

[0178] Next, in the first second erase verification operation VEB1, the erase verification voltage VEY can be applied to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2 of the selected memory block, the erase pass voltage VPASS can be applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1, and the ground voltage VSS can be applied to the common source line CSL.

[0179] If the erase status verification is successful in the first second erase verification operation VEB1, the second erase process operation ERB2 can be skipped. However, in Figure 7B In the first second erase verification operation VEB1, the verification of the erase status of the second sub-block 2 failed. Therefore, it can be seen that the second second erase process operation ERB2 is performed using the erase voltage "VERS2" among multiple erase voltages VERSx, and then the second second erase verification operation VEB2 is performed.

[0180] Similarly, if the erase status verification of Sub-block 2 is successful in the second erase verification operation VEB2, the third erase process operation ERB3 can be omitted. However, in Figure 7BIn the second erase verification operation VEB2, the verification of the erase status of the second sub-block 2 fails. Therefore, it can be seen that the third second erase process operation ERB3 is performed using the erase voltage "VERS3" among the multiple erase voltages VERSx, and then the third second erase verification operation VEB3 is performed.

[0181] It can be seen that, in this way, Figure 7B In the process, the erase voltage “VERS5” among multiple erase voltages VERSx is used to perform the fifth second erase process operation ERB5, and then the fifth second erase verification operation VEB5 is performed.

[0182] In addition, Figure 7B The diagram shows the successful verification of the erase status of the second sub-block 2 in the fifth second erase verification operation VEB5. Therefore, the erase voltage "VERS5" used in the fifth second erase process operation ERB5, which was just executed before the fifth second erase verification operation VEB5, can be set as the second erase voltage.

[0183] It can be seen that it is already Figure 7A The first erase voltage determined in operation E10 in the first operating mode shown is the erase voltage "VERS3" with the third highest level among the multiple erase voltages VERSx, and it has already been... Figure 7B The second erase voltage determined in operation E20 in the first operating mode shown in the figure is erase voltage "VERS5" which has the fifth highest level among a plurality of erase voltages VERSx, and erase voltage "VERS5" has a higher level than erase voltage "VERS3".

[0184] Therefore, although not specifically shown in the accompanying drawings, in operation E30 of the first operating mode, the level of the first erase enable voltage VPMA can be set to be higher than the level of the second erase enable voltage VEYB.

[0185] also, Figure 7C The diagram illustrates the erase operation performed on each of the multiple memory blocks <1, 2, ...> in the second operating mode after setting the level of the first erase enable voltage VPMA to be higher than the level of the second erase enable voltage VEYB in the first operating mode.

[0186] Specifically, in the second operation mode, the erasure operation of the first sub-block 1 of the erase target block among multiple memory blocks MEMORY BLOCK<1, 2, ...> can be performed by repeating the first erasure process operation ERAx and the first erasure verification operation VEAx.

[0187] More specifically, the first erase process operation ERAx can be performed by: applying a first erase enable voltage VPMA with a relatively higher level than the second erase enable voltage VEYB to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1 of the erase target block, applying an erase prevent voltage VPHI to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2, and applying any one of the plurality of erase voltages VERSx to the common source line CSL connected to the substrate.

[0188] Next, the first erase verification operation VEAx can be performed: the erase verification voltage VEY is applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1 of the erase target block, the erase pass voltage VPASS is applied to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2, and the ground voltage VSS is applied to the common source line CSL connected to the substrate. In this case, x can be a natural number equal to or greater than 1.

[0189] Furthermore, in the second operation mode, the erasure operation of the second sub-block 2 of the erase target block among multiple memory blocks MEMORY BLOCK<1, 2, ...> can be performed by repeating the second erase process operation ERBx and the second erase verification operation VEBx.

[0190] More specifically, a second erase process operation ERBx can be performed: applying a second erase enable voltage VPMB, which has a relatively lower level than the first erase enable voltage VEYA, to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2 of the erase target block; applying an erase prevent voltage VPHI to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1; and applying any one of a plurality of erase voltages VERSx to the common source line CSL connected to the substrate.

[0191] Next, a second erase verification operation VEBx can be performed: an erase verification voltage VEY is applied to the word line (WLs of Sub-block 2) corresponding to the second sub-block 2 of the erase target block, an erase pass voltage VPASS is applied to the word line (WLs of Sub-block 1) corresponding to the first sub-block 1, and a ground voltage VSS is applied to the common source line CSL connected to the substrate. In this case, x can be a natural number equal to or greater than 1.

[0192] For reference only. Figures 7A to 7C This illustrates the case where, in operation E30, the level of the first erase enable voltage VPMA is set higher than the level of the second erase enable voltage VEYB, because in the first operating mode, the level of the first erase voltage set in operation E10 is checked to be lower than the level of the second erase voltage set in operation E20. Although in Figures 7A to 7C The timing diagram does not specify this, but as shown in the reference... Figure 4B As described, the levels of the first erase enable voltage VPMA and the second erase enable voltage VEYB can be set in various forms during operation E30, and the results of the settings can be applied to the erase operation performed in the second operating mode.

[0193] Although various embodiments of this disclosure have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A memory device, comprising: Multiple storage blocks, each storage block comprising a first sub-block and a second sub-block; as well as Control circuit: A first erase enable voltage and a first erase voltage from a plurality of erase voltages are applied to a first sub-block of a selected memory block among the plurality of memory blocks, and when the erase status of the first sub-block is successfully verified, the level of the applied first erase voltage is checked. The second erase enable voltage and the second erase voltage from the plurality of erase voltages are applied to the second sub-block of the selected memory block, and when the erase status of the second sub-block is successfully verified, the level of the applied second erase voltage is checked, and Based on the comparison between the levels of the first erase voltage and the second erase voltage, the levels of the first erase allow voltage and the second erase allow voltage are adjusted.

2. The memory device according to claim 1, wherein, The control circuit: In the first operating mode, the operations of checking the level of the first erase voltage, checking the level of the second erase voltage, and adjusting the levels of the first erase allow voltage and the second erase allow voltage are sequentially performed on the selected memory block. and In the second operating mode following the first operating mode, when an erase operation is performed on the first sub-block of each of the plurality of memory blocks, a first erase allow voltage having a level adjusted in the first operating mode is used, and when an erase operation is performed on the second sub-block of each of the plurality of memory blocks, a second erase allow voltage having a level adjusted in the first operating mode is used.

3. The memory device according to claim 2, wherein: Each of the plurality of memory blocks includes a plurality of word lines, which are stacked vertically on a substrate; The first character line stacked on the first side of the reference character line among the multiple character lines is designated as the first sub-block; and The second word line stacked on the second side of the reference word line is set as the second sub-block.

4. The memory device according to claim 3, wherein, The control circuit: The first erase process operation and the first erase verification operation are executed alternately. The first erase process operation applies one of the plurality of erase voltages to the substrate corresponding to the selected memory block in a set order when a first erase enable voltage with a default level is applied to the first word line of the selected memory block. The first erase verification operation applies an erase verification voltage to the first word line of the selected memory block. and The erase voltage applied to the substrate corresponding to the selected memory block during the first erase process operation, which is performed before the successful verification of the erase status of the first sub-block in the first erase verification operation, is set as the first erase voltage.

5. The memory device according to claim 4, wherein, The control circuit: The second erase process operation and the second erase verification operation are executed alternately. The second erase process operation applies one of the plurality of erase voltages to the substrate corresponding to the selected memory block in a set order when the second erase enable voltage with the default level is applied to the second word line of the selected memory block. The second erase verification operation applies the erase verification voltage to the second word line of the selected memory block. and The erase voltage applied to the substrate corresponding to the selected memory block during the second erase process operation, which is performed before the successful verification of the erase status of the second sub-block in the second erase verification operation, is set as the second erase voltage.

6. The memory device according to claim 5, wherein, The control circuit: When the level of the first erase voltage is higher than the level of the second erase voltage, the level of the second erase allow voltage is set to be higher than the level of the first erase allow voltage. When the level of the second erase voltage is higher than the level of the first erase voltage, the level of the first erase allow voltage is set to be higher than the level of the second erase allow voltage. and When the levels of the first erase voltage and the second erase voltage are the same, the levels of the first erase enable voltage and the second erase enable voltage are set to be the same.

7. The memory device according to claim 6, wherein, The control circuit: When each of the levels of the first erase voltage and the second erase voltage is higher than the expected level, each of the levels of the first erase allow voltage and the second erase allow voltage is set to be higher than the default level. and When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level, at least one of the levels of the first erase allow voltage and the second erase allow voltage is set to the default level.

8. The memory device according to claim 5, wherein, The control circuit includes: The peripheral circuitry executes either the first erase process operation or the second erase process operation, as well as either the first erase verification operation or the second erase verification operation. The first erase process operation or the second erase process operation, under the condition that the first erase allow voltage or the second erase allow voltage and the erase prevent voltage are applied to the first word line or the second word line, applies one of the plurality of erase voltages to the substrate. The first erase verification operation or the second erase verification operation checks the erase status of the first sub-block or the second sub-block by applying an erase verification voltage to the first word line or the second word line. Control logic: In the first operating mode, the peripheral circuit is controlled to perform the operation of checking the level of the first erase voltage by alternately executing the first erase process operation and the first erase verification operation on the first sub-block of the selected memory block, and to perform the operation of checking the level of the second erase voltage by alternately executing the second erase process operation and the second erase verification operation on the second sub-block of the selected memory block. Based on the comparison between the levels of the first erase voltage and the second erase voltage, the levels of the first erase allow voltage and the second erase allow voltage are adjusted.

9. The memory device according to claim 8, wherein, The peripheral circuit includes: A voltage generator generates the plurality of erase voltages, the first erase allow voltage and the second erase allow voltage, the erase verification voltage, and the erase prevention voltage; The line decoder selectively supplies the first erase enable voltage, the second erase enable voltage, the erase verification voltage, and the erase prevention voltage to the plurality of word lines; and A substrate driver supplies one of the plurality of erase voltages to the substrate.

10. The memory device according to claim 2, wherein, The first operation mode is the mode that is entered and exited when the test operation begins and ends.

11. The memory device according to claim 3, wherein, The reference character line includes at least one dummy character line disposed in the middle of the plurality of character lines.

12. A method of operating a memory device, the memory device comprising a plurality of memory blocks, each memory block comprising a first sub-block and a second sub-block, the method comprising: The first erase enable voltage and the first erase voltage among a plurality of erase voltages are applied to the first sub-block of the selected memory block among the plurality of memory blocks, and when the verification of the erase status of the first sub-block is successful, the level of the applied first erase voltage is checked. The second erase enable voltage and the second erase voltage among the plurality of erase voltages are applied to the second sub-block of the selected memory block, and then the level of the applied second erase voltage is checked when the erase status of the second sub-block is successfully verified. as well as Based on the comparison between the levels of the first erase voltage and the second erase voltage, the levels of the first erase allow voltage and the second erase allow voltage are adjusted.

13. The operating method according to claim 12, further comprising: In the first operating mode, the following operations are performed sequentially: applying the first erase enable voltage and the first erase voltage, applying the second erase enable voltage and the second erase voltage, and adjusting the level of the first erase enable voltage and the level of the second erase enable voltage. as well as In the second operating mode following the first operating mode, when an erase operation is performed on the first sub-block of each of the plurality of memory blocks, a first erase allow voltage having a level adjusted in the first operating mode is used, and when an erase operation is performed on the second sub-block of each of the plurality of memory blocks, a second erase allow voltage having a level adjusted in the first operating mode is used.

14. The operating method according to claim 13, wherein: Each of the plurality of memory blocks includes a plurality of word lines, which are stacked vertically on a substrate; The first character line stacked on the first side of the reference character line among the multiple character lines is designated as the first sub-block; and The second word line stacked on the second side of the reference word line is set as the second sub-block.

15. The operating method according to claim 14, wherein, Applying the first erase allow voltage and the first erase voltage includes: The first erase process operation is performed, wherein, with a first erase enable voltage having a default level applied to the first word line of the selected memory block, one of the plurality of erase voltages is applied to the substrate in a set order. After the first erase process operation, a first erase verification operation is performed, which verifies the erase status of the first sub-block by applying an erase verification voltage to the first word line; and The first erase process operation and the first erase verification operation are executed alternately, and the voltage applied to the substrate in the first erase process operation, which is executed before the successful verification of the erase state, is set to the first erase voltage.

16. The operating method according to claim 15, wherein, Applying the second erase enable voltage and the second erase voltage includes: A second erase process operation is performed, wherein, with a second erase enable voltage having the default level applied to the second word line of the selected memory block, one of the plurality of erase voltages is applied to the substrate in a set order; Following the second erase process operation, a second erase verification operation is performed, which verifies the erase status of the second sub-block by applying an erase verification voltage to the second word line; and The second erase process operation and the second erase verification operation are executed alternately, and the erase voltage applied to the substrate in the second erase process operation, which is executed before the successful verification of the erase state, is set to the second erase voltage.

17. The operating method according to claim 16, wherein, Adjusting the levels of the first erase enable voltage and the second erase enable voltage includes: When the level of the first erase voltage is higher than the level of the second erase voltage, the level of the second erase allow voltage is set to be higher than the level of the first erase allow voltage. When the level of the second erase voltage is higher than the level of the first erase voltage, the level of the first erase enable voltage is set to be higher than the level of the second erase enable voltage; and When the levels of the first erase voltage and the second erase voltage are the same, the levels of the first erase enable voltage and the second erase enable voltage are set to be the same.

18. The operating method according to claim 17, wherein, Adjusting the levels of the first erase enable voltage and the second erase enable voltage includes: When each of the levels of the first erase voltage and the second erase voltage is higher than the expected level, each of the levels of the first erase enable voltage and the second erase enable voltage is set to be higher than the default level; and When at least one of the levels of the first erase voltage and the second erase voltage is lower than the expected level, at least one of the levels of the first erase allow voltage and the second erase allow voltage is set to the default level.

19. The operating method according to claim 13, wherein, The first operation mode is the mode that is entered and exited when the test operation begins and ends.

20. The operating method according to claim 14, wherein, The reference character line includes at least one dummy character line disposed in the middle of the plurality of character lines.

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